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+-- fifo.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+-- fifo
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+use work.nono_const.all;
+
+entity fifo is
+ port(
+ data_in: in unsigned(7 downto 0);
+ data_out: out unsigned(7 downto 0);
+ ck: in std_logic;
+ ck_in: in std_logic;
+ ck_out: in std_logic;
+ flags: out std_logic_vector(5 downto 0);
+ purge: in std_logic
+ );
+end fifo;
+
+architecture rtl of fifo is
+component fifodriver is
+ port(
+ masterck,reset: in std_logic;
+ readreq,writereq: in std_logic;
+ fifock:out std_logic;
+ fiforead:out std_logic;
+ fifowrite:out std_logic
+ );
+end component;
+
+component fifoctlr_cc is
+ port (clock_in: IN std_logic;
+ read_enable_in: IN std_logic;
+ write_enable_in: IN std_logic;
+ write_data_in: IN std_logic_vector(7 downto 0);
+ fifo_gsr_in: IN std_logic;
+ read_data_out: OUT std_logic_vector(7 downto 0);
+ full_out: OUT std_logic;
+ empty_out: OUT std_logic;
+ fifocount_out: OUT std_logic_vector(3 downto 0));
+end component;
+
+
+-- en std_logic_vector :
+signal data_in_s: std_logic_vector(7 downto 0);
+signal data_out_s: std_logic_vector(7 downto 0);
+
+-- autres signaux
+signal read_enable:std_logic;
+signal write_enable:std_logic;
+signal clock_fifo:std_logic;
+
+
+begin
+-- conversion de types :
+--data_in_s <= TO_STDLOGICVECTOR(std);
+data_in_s <= conv_std_logic_vector(data_in);
+
+data_out <= TO_UNSIGNED(bvtoi(data_out_s));
+
+FIFO1:fifoctlr_cc
+ port map(
+ clock_in=>clock_fifo,
+ read_enable_in=>read_enable,
+ write_enable_in=>write_enable,
+ write_data_in=>data_in_s,
+ fifo_gsr_in=>purge,
+ read_data_out=>data_out_s,
+ full_out=>flags(5),
+ empty_out=>flags(4),
+ fifocount_out=>flags(3 downto 0)
+ );
+
+FD1:fifodriver
+ port map(
+ masterck=>ck,
+ reset=>purge,
+ readreq=>ck_out,
+ writereq=>ck_in,
+ fifock=>clock_fifo,
+ fiforead=>read_enable,
+ fifowrite=>write_enable
+ );
+
+end rtl;
+
+
+