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diff --git a/2004/n/fpga/src/portserie/TEST_REG.VHD b/2004/n/fpga/src/portserie/TEST_REG.VHD
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--- testbench pour le registre
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use work.mypack.all;
-
-entity testreg is
-constant adr_w : integer :=10;
-constant data_w : integer :=8;
-end testreg;
-
-architecture sim1 of testreg is
-component registre
- port(
- adrbus: in std_logic_vector((adr_w - 1) downto 0);
- databus:inout std_logic_vector((data_w - 1) downto 0);
- input: in std_logic_vector((data_w - 1) downto 0);
- output: out std_logic_vector((data_w - 1) downto 0);
- rw: in std_logic;
- load: in std_logic;
- ck: in std_logic;
- rst: in std_logic
- );
-end component;
-
-signal adrbus: std_logic_vector((adr_w - 1) downto 0);
-signal databus: std_logic_vector((data_w - 1) downto 0);
-signal input: std_logic_vector((data_w - 1) downto 0);
-signal put: std_logic_vector((data_w - 1) downto 0);
-signal rw: std_logic;
-signal load: std_logic;
-signal ck: std_logic;
-signal rst: std_logic;
-
-begin
- R0: registre
- generic map(adr => 12)
- port map(
- adrbus=> adrbus,
- databus=> databus,
- input=> input := '00000001',
- output=> output,
- rw=> rw :='0',
- load=> load :='0',
- ck=> ck :='0',
- rst=> rst
- );
-
- adrbus <= '0000001100' ,
- '0100001100' after 40 ns,
- '0000001101' after 60 ns;
- '0000001100' after 100 ns,
-
- databus <= databus + 1 after 2 ns;
- input <= not input after 3 ns;
- rw <= not rw after 11 ns;
- load <= not load after 7 ns;
- ck <= not ck after 5 ns;
- rst <= '1','0' after 2 ns;
-
-end sim1;
-
-
-configuration cf1 of testreg is
- for sim1
- for all : registre use entity work.registre(rtl); end for;
- end for;
-end cf1;
-