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-rw-r--r--2004/n/fpga/src/or/or8.vhd29
1 files changed, 11 insertions, 18 deletions
diff --git a/2004/n/fpga/src/or/or8.vhd b/2004/n/fpga/src/or/or8.vhd
index ae0d159..85f2088 100644
--- a/2004/n/fpga/src/or/or8.vhd
+++ b/2004/n/fpga/src/or/or8.vhd
@@ -15,29 +15,22 @@ use work.nono_const.all;
entity or8 is
port (
- in0 : in std_logic;
- in1 : in std_logic;
- in2 : in std_logic;
- in3 : in std_logic;
- in4 : in std_logic;
- in5 : in std_logic;
- in6 : in std_logic;
- in7 : in std_logic;
- or_out : out std_logic
+ or8_in : in std_logic_vector (7 downto 0);
+ or8_out : out std_logic
);
end entity;
architecture RTL of or8 is
begin
- or_out <= '1' when
- (in0 = '1' or
- in1 = '1' or
- in2 = '1' or
- in3 = '1' or
- in4 = '1' or
- in5 = '1' or
- in6 = '1' or
- in7 = '1'
+ or8_out <= '1' when
+ (or8_in (0) = '1' or
+ or8_in (1) = '1' or
+ or8_in (2) = '1' or
+ or8_in (3) = '1' or
+ or8_in (4) = '1' or
+ or8_in (5) = '1' or
+ or8_in (6) = '1' or
+ or8_in (7) = '1'
) else '0';
end RTL;