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Diffstat (limited to '2004/n/fpga/src/gpio/bch_reg_io.vhd')
-rw-r--r--2004/n/fpga/src/gpio/bch_reg_io.vhd27
1 files changed, 14 insertions, 13 deletions
diff --git a/2004/n/fpga/src/gpio/bch_reg_io.vhd b/2004/n/fpga/src/gpio/bch_reg_io.vhd
index f9fd5c9..a404427 100644
--- a/2004/n/fpga/src/gpio/bch_reg_io.vhd
+++ b/2004/n/fpga/src/gpio/bch_reg_io.vhd
@@ -1,7 +1,7 @@
-- bch_reg_io.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-André Galmes
--- Test de reg_rw.
+-- Test de reg_io.
library ieee;
use ieee.std_logic_1164.all;
@@ -22,8 +22,9 @@ architecture sim1 of bch_reg_io is
rst : in std_logic;
rw : in std_logic;
enable : in std_logic;
- data_in : inout T_DATA;
- data_out : inout T_DATA
+ data_f_in : inout T_DATA; -- forward in = entrée dans le sens direct.
+ data_out : out T_DATA;
+ data_b_in : in T_DATA -- backward in = entrée pour la lecture
);
end component;
@@ -31,16 +32,18 @@ architecture sim1 of bch_reg_io is
signal rst : std_logic;
signal rw : std_logic; -- read / write
signal enable : std_logic;
- signal data_in : T_DATA;
+ signal data_f_in : T_DATA;
signal data_out : T_DATA;
+ signal data_b_in : T_DATA;
begin
U1 : reg_io port map (
rst => rst,
rw => rw,
enable => enable,
- data_in => data_in,
- data_out => data_out
+ data_f_in => data_f_in,
+ data_out => data_out,
+ data_b_in => data_b_in
);
rst <= '1', '0' after CK_PERIOD;
@@ -50,13 +53,11 @@ begin
'1' after 5*CK_PERIOD,
'0' after 6*CK_PERIOD;
rw <= '1', '0' after 3*CK_PERIOD;
- data_in <= x"01",
- x"02" after 3*CK_PERIOD,
- "ZZZZZZZZ" after 5*CK_PERIOD;
- --x"03" after 5*CK_PERIOD;
- data_out <= "ZZZZZZZZ",
- x"07" after 5*CK_PERIOD,
- "ZZZZZZZZ" after 6*CK_PERIOD;
+ data_f_in <= x"01",
+ x"02" after 3*CK_PERIOD,
+ "ZZZZZZZZ" after 5*CK_PERIOD;
+ --x"03" after 5*CK_PERIOD;
+ data_b_in <= x"07";
end sim1;
configuration cf1_bch_reg_io of bch_reg_io is