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Diffstat (limited to '2004/n/fpga/src/fpga/fpga.vhd')
-rw-r--r--2004/n/fpga/src/fpga/fpga.vhd40
1 files changed, 36 insertions, 4 deletions
diff --git a/2004/n/fpga/src/fpga/fpga.vhd b/2004/n/fpga/src/fpga/fpga.vhd
index 95aa898..1973b41 100644
--- a/2004/n/fpga/src/fpga/fpga.vhd
+++ b/2004/n/fpga/src/fpga/fpga.vhd
@@ -22,9 +22,11 @@ port(
bus_adr : in std_logic_vector(23 downto 0);
bus_data : INOUT std_logic_vector(7 downto 0);
irq : OUT std_logic;
+ irqrxFIFO,irqrxRX,irqrxERR,irqtx : OUT std_logic;
-- les entrées-sorties
- rxin1:in std_logic
+ rxin1:in std_logic;
+ txout1:out std_logic
);
end fpga;
@@ -49,6 +51,22 @@ architecture rtl of fpga is
);
END COMPONENT;
+ COMPONENT txserie
+ PORT(
+ rst : IN std_logic;
+ bus_clk : IN std_logic;
+ rw : IN std_logic;
+ clk : IN std_logic;
+ clk_ref : IN std_logic;
+ csData : IN std_logic;
+ csConfig : IN std_logic;
+ csFlag : IN std_logic;
+ bus_data : INOUT std_logic_vector(7 downto 0);
+ txout : OUT std_logic;
+ minIRQ : OUT std_logic
+ );
+ END COMPONENT;
+
COMPONENT decodisa
PORT(
adr_bus : IN std_logic_vector(23 downto 0);
@@ -91,14 +109,28 @@ begin
clk => clk_speed,
clk_ref => clk_ref,
rxin => rxin1,
- irqFIFO => open,
- irqRX => open,
- irqERR => open,
+ irqFIFO => irqrxFIFO,
+ irqRX => irqrxRX,
+ irqERR => irqrxERR,
csData => cs(1),
csConfig => cs(2),
csFlag => cs(3)
);
+ Inst_txserie1: txserie PORT MAP(
+ rst => rst,
+ bus_clk => bus_clk,
+ rw => rw,
+ bus_data => bus_data,
+ clk => clk_speed,
+ clk_ref => clk_ref,
+ txout => txout1,
+ minIRQ => irqtx,
+ csData => cs(4),
+ csConfig => cs(5),
+ csFlag => cs(6)
+ );
+
end rtl;