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+JDF G
+// Created by Project Navigator ver 1.0
+PROJECT fpga
+DESIGN fpga
+DEVFAM spartan2
+DEVFAMTIME 0
+DEVICE xc2s200
+DEVICETIME 0
+DEVPKG pq208
+DEVPKGTIME 1080594971
+DEVSPEED -6
+DEVSPEEDTIME 0
+DEVTOPLEVELMODULETYPE HDL
+TOPLEVELMODULETYPETIME 0
+DEVSYNTHESISTOOL XST (VHDL/Verilog)
+SYNTHESISTOOLTIME 0
+DEVSIMULATOR Modelsim
+SIMULATORTIME 0
+DEVGENERATEDSIMULATIONMODEL VHDL
+GENERATEDSIMULATIONMODELTIME 0
+SOURCE fpga.vhd
+SOURCE isa_const.vhd
+SOURCE ..\decodisa\decodadr.xco
+STIMULUS ..\portserie\rxserie\bch_rxserie.vhd
+SOURCE ..\portserie\rxserie\rxserie.vhd
+SOURCE ..\portserie\clockgene\clockgene.vhd
+SOURCE ..\portserie\fifo\fifodriver.vhd
+SOURCE ..\portserie\fifo\sfifo.xco
+SOURCE ..\registre\registre.vhd
+STIMULUS ..\registre\test_reg.vhd
+SOURCE ..\portserie\uart\rxcver.vhd
+SOURCE ..\decodisa\decodisa.vhd
+STIMULUS ..\decodisa\bch_decodisa.vhd
+STIMULUS fpga-test.vhd
+SOURCE ..\modele\nono_const.vhd
+[STATUS-ALL]
+decodisa.ngcFile=WARNINGS,1080659193
+[STRATEGY-LIST]
+Normal=True