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Diffstat (limited to '2004/n/fpga/src/fpga/fpga-test.vhd')
-rw-r--r--2004/n/fpga/src/fpga/fpga-test.vhd78
1 files changed, 63 insertions, 15 deletions
diff --git a/2004/n/fpga/src/fpga/fpga-test.vhd b/2004/n/fpga/src/fpga/fpga-test.vhd
index 4595ca4..4459bef 100644
--- a/2004/n/fpga/src/fpga/fpga-test.vhd
+++ b/2004/n/fpga/src/fpga/fpga-test.vhd
@@ -31,7 +31,12 @@ ARCHITECTURE behavior OF bch_fpga IS
bus_adr : IN std_logic_vector(23 downto 0);
rxin1 : IN std_logic;
bus_data : INOUT std_logic_vector(7 downto 0);
- irq : OUT std_logic
+ irq : OUT std_logic;
+ irqrxFIFO : OUT std_logic;
+ irqrxRX : OUT std_logic;
+ irqrxERR : OUT std_logic;
+ irqtx : OUT std_logic;
+ txout1 : OUT std_logic
);
END COMPONENT;
@@ -45,8 +50,11 @@ ARCHITECTURE behavior OF bch_fpga IS
SIGNAL bus_adr : std_logic_vector(23 downto 0);
SIGNAL bus_data : std_logic_vector(7 downto 0);
SIGNAL irq : std_logic;
+ SIGNAL irqrxFIFO,irqrxRX,irqrxERR,irqtx : std_logic;
+
SIGNAL rxin1 : std_logic:='0';
-
+ SIGNAL txout1 : std_logic;
+
signal data : integer;
signal data_received : std_logic_vector(7 downto 0);
@@ -62,18 +70,25 @@ BEGIN
bus_adr => bus_adr,
bus_data => bus_data,
irq => irq,
- rxin1 => rxin1
+ irqrxFIFO => irqrxFIFO ,
+ irqrxRX => irqrxRX,
+ irqrxERR => irqrxERR ,
+ irqtx => irqtx ,
+ rxin1 => rxin1,
+ txout1 => txout1
);
+
-- master clock
clk_speed <= (Not clk_speed) after (CK_PERIOD/2);
-- Reset
-rst <= '1','0' after (10*CK_PERIOD);
+rst <= '1','0' after (100 ns);
-- baudrate/(16*2) used to generate half clock cycle;
clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz
+
-- feeding back output from transmitter to the input of receiver
-rxin1 <= (not rxin1) after 15751 ns;
+rxin1 <= txout1;
check:process
@@ -119,23 +134,56 @@ check:process
WAIT FOR 20 ns;
END write_bus;
+
+-- RX
+-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0)
+-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 )
+
+
+-- TX
+-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
+-- Flag : (x ! x ! x ! x ! Empty ! Full ! FLI1 ! FLI0 )
+
begin
- read_bus(259);
- data<=179;
- write_bus(259);
- read_bus(259);
- wait for 100 ns;
- read_bus(258);
+-- RX
+-- data : 257
+-- config : 258
+-- flag : 259
+-- TX
+-- data : 260
+-- config : 261
+-- flag : 262
+
+ wait for 500 ns;
+
+-- configuration du RX (RX_config)
data<=255;
write_bus(258);
read_bus(258);
wait for 100 ns;
- read_bus(257);
- data<=179;
- write_bus(257);
- read_bus(257);
+-- configuration du TX
+ data<=119;
+ write_bus(261);
+ read_bus(261);
+ wait for 5 us;
+
+-- transmission par le TX
+ data<=177;
+ write_bus(260);
+ read_bus(260);
+
+ wait for 100 ns;
+
+
+-- transmission par le TX
+ data<=22;
+ write_bus(260);
+ read_bus(260);
+
+
+ wait for 100 ns;
wait for 100 ns;
end process;