summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/decodisa/decodadr.xco
diff options
context:
space:
mode:
Diffstat (limited to '2004/n/fpga/src/decodisa/decodadr.xco')
-rw-r--r--2004/n/fpga/src/decodisa/decodadr.xco42
1 files changed, 42 insertions, 0 deletions
diff --git a/2004/n/fpga/src/decodisa/decodadr.xco b/2004/n/fpga/src/decodisa/decodadr.xco
new file mode 100644
index 0000000..498e91e
--- /dev/null
+++ b/2004/n/fpga/src/decodisa/decodadr.xco
@@ -0,0 +1,42 @@
+# Xilinx CORE Generator 6.1.03i
+# Username = Administrateur
+# COREGenPath = D:\xilinx\coregen
+# ProjectPath = D:\vhdl\robot\carte_fpga\src\decodisa
+# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\decodisa
+# OverwriteFiles = true
+# Core name: decodadr
+# Number of Primitives in design: 768
+# Number of CLBs used in design: 264
+# Number of Slices used in design: 512
+# Number of LUT sites used in design: 768
+# Number of LUTs used in design: 768
+# Number of REG used in design: 0
+# Number of SRL16s used in design: 0
+# Number of Distributed RAM primitives used in design: 0
+# Number of Block Memories used in design: 0
+# Number of Dedicated Multipliers used in design: 0
+# Number of HU_SETs used: 1
+# Huset "default" = (0, 0) to (17, 16) in CLBs
+#
+SET BusFormat = BusFormatAngleBracketNotRipped
+SET XilinxFamily = Spartan2
+SET OutputOption = OutputProducts
+SET FlowVendor = Foundation_iSE
+SET FormalVerification = None
+SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
+SELECT Binary_Decoder Spartan2 Xilinx,_Inc. 6.0
+CSET output_sense = active_high
+CSET async_init_value = 0
+CSET set_clear_priority = clear_overrides_set
+CSET ce_overrides = sync_controls_override_ce
+CSET number_of_outputs = 256
+CSET output_options = non_registered
+CSET sync_init_value = 0
+CSET clock_enable = false
+CSET create_rpm = true
+CSET decoder_enable = true
+CSET asynchronous_settings = none
+CSET synchronous_settings = none
+CSET component_name = decodadr
+GENERATE
+