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authorschodet2003-05-04 21:56:51 +0000
committerschodet2003-05-04 21:56:51 +0000
commit631d7502c6cdee8aceb95de8bf9526b3b1dd421e (patch)
treeefaa8528a4ea9f74d98e25808f85b1d7934a520e
parent1b94afd8e022967fa63827e686ee4431b0533f2b (diff)
Inversion des bits irq et clk.
Desactivation des interuptions lors d'une interuption.
-rw-r--r--2003/i/buzz/src/kernel/pbus.c21
1 files changed, 12 insertions, 9 deletions
diff --git a/2003/i/buzz/src/kernel/pbus.c b/2003/i/buzz/src/kernel/pbus.c
index b1c7025..7d28fff 100644
--- a/2003/i/buzz/src/kernel/pbus.c
+++ b/2003/i/buzz/src/kernel/pbus.c
@@ -86,7 +86,7 @@ pbusattach(parent, self, aux)
printf("\n");
- PBUS_WRITE_4(0x08,PBUS_RnW|PBUS_CLK);
+ PBUS_WRITE_4(0x08,PBUS_RnW);
PBUS_WRITE_4(0x0,0);
sc->sc_dmasize=DMASIZE;
sc->in_dma=0;
@@ -240,7 +240,10 @@ int pbus_intr(void *p)
unsigned long status=PBUS_READ_4(0);
if (status&0x20000000)
{
+ /* Désactive les interuptions. */
PBUS_WRITE_4(8,PBUS_READ_4(8)&0x3FFF);
+ sc->pbusinten=0;
+ /* Envoie le signal à l'application. */
if (sc->cproc!=NULL) psignal(sc->cproc,sc->csignal);
}
else
@@ -280,31 +283,31 @@ pbusioctl(dev, cmd, addr, flag, proc)
switch (cmd)
{
case PBUS_READ:
- PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_CLK|PBUS_RnW|sc->pbusinten);
PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_RnW|sc->pbusinten);
+ PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_CLK|PBUS_RnW|sc->pbusinten);
PBUS_WAIT;
parm->data=PBUS_READ_4(8)&0xFF;
- PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_CLK|PBUS_RnW|sc->pbusinten);
+ PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_RnW|sc->pbusinten);
PBUS_WAIT;
break;
case PBUS_WRITE:
- PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_CLK|(parm->data)|sc->pbusinten);
PBUS_WRITE_4(8,(parm->addr<<8)|(parm->data)|sc->pbusinten);
- PBUS_WAIT;
PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_CLK|(parm->data)|sc->pbusinten);
PBUS_WAIT;
- PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_CLK|PBUS_RnW|sc->pbusinten);
+ PBUS_WRITE_4(8,(parm->addr<<8)|(parm->data)|sc->pbusinten);
+ PBUS_WAIT;
+ PBUS_WRITE_4(8,(parm->addr<<8)|PBUS_RnW|sc->pbusinten);
break;
case PBUS_INTDISABLE:
sc->pbusinten=0;
- PBUS_WRITE_4(8,0|PBUS_CLK|PBUS_RnW|sc->pbusinten);
+ PBUS_WRITE_4(8,0|PBUS_RnW|sc->pbusinten);
break;
case PBUS_INTENABLE:
sc->pbusinten=PBUS_INTEN;
- PBUS_WRITE_4(8,0|PBUS_CLK|PBUS_RnW|sc->pbusinten);
+ PBUS_WRITE_4(8,0|PBUS_RnW|sc->pbusinten);
break;
case PBUS_INTREAD:
- parm->ints=(~(PBUS_READ_4(8)>>16))&0x1F;
+ parm->ints=(PBUS_READ_4(8)>>16)&0x1F;
break;
}
}