summaryrefslogtreecommitdiff
path: root/2004
diff options
context:
space:
mode:
authorprot2004-02-24 21:54:48 +0000
committerprot2004-02-24 21:54:48 +0000
commite6a9408accc210877fdfbc564d8919f5372fa2ea (patch)
tree2b2d59c559c7aacacac68043c78d653baa8e105a /2004
parent3a46e687fadd28f93b3a67063e535615770a966d (diff)
MAJ phase 1
Diffstat (limited to '2004')
-rw-r--r--2004/n/fpga/src/portserie/rxserie.vhd59
1 files changed, 29 insertions, 30 deletions
diff --git a/2004/n/fpga/src/portserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie.vhd
index 21c8080..2b906d5 100644
--- a/2004/n/fpga/src/portserie/rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie.vhd
@@ -4,8 +4,8 @@
--
-- * Prend 3 adresses mémoire :
-- 0 - Rxdata
--- 1 - Flag : (x ! x ! x ! x ! FNE ! FFull ! FL1 ! FL0 )
--- 2 - Config : (x ! x ! x ! On/Off ! FNEIF ! FFIF ! BdR1 ! BdR0)
+-- 1 - Flag : (x ! x ! FNE ! FFull ! FL3 ! FL2 ! FL1 ! FL0 )
+-- 2 - Config : (x ! x ! x ! On/Off ! FNEIF ! FFIF ! BdR1 ! BdR0)
-- * Mettre le bit On/Off à 1 pour activer la reception
-- * Chaque lecture dans rxdata dépile la donnée de la fifo
-- * Dès que le registre à décalage est plein, il empile la donnée dans la
@@ -53,13 +53,13 @@ end rxserie;
architecture rtl of rxserie is
-component registre
- generic(adr : integer);
+component regIO
+ generic(adr : T_ADDRESS);
port(
- adrbus: in std_logic_vector((adr_w - 1) downto 0);
- databus: inout std_logic_vector(7 downto 0);
- input: in std_logic_vector(7 downto 0);
- output: out std_logic_vector(7 downto 0);
+ bus_address: in T_ADDRESS;
+ bus_data: inout T_DATA;
+ input: in T_DATA;
+ output: out T_DATA;
rw: in std_logic;
load: in std_logic;
ck: in std_logic;
@@ -67,20 +67,18 @@ component registre
);
end component;
-component fifo
+component fifo is
port(
- data_in: in std_logic_vector(7 downto 0);
- data_out: in std_logic_vector(7 downto 0);
- ck_in: in std_logic;
- ck_out: in std_logic;
- f0: out std_logic;
- f1: out std_logic;
- f2: out std_logic;
- f3: out std_logic;
+ data_in: in T_DATA;
+ data_out: out T_DATA;
+ ck: in std_logic;
+ ck_in: in std_logic;
+ ck_out: in std_logic;
+ flags: out std_logic_vector(5 downto 0);
purge: in std_logic
);
end component;
-
+
component receiver
port(
data_in: in std_logic_vector(7 downto 0);
@@ -92,33 +90,34 @@ end component;
component clockgene
port(
- ck_in: in std_logic;
- ck_out: in std_logic;
+ ckin: in std_logic;
+ ckout: out std_logic;
param: in std_logic_vector(1 downto 0)
);
end component;
component decoder
- generic(adr : integer);
+ generic(adr : T_ADDRESS);
port(
- adrbus: in std_logic_vector((adr_w - 1) downto 0);
+ bus_address: in T_DATA;
cs: out std_logic
);
end component;
-signal fifoEmpty: std_logic;
-signal fifoFull: std_logic;
-signal fifoLI1: std_logic;
-signal fifoLI0: std_logic;
-signal BdR1: std_logic;
-signal BdR0: std_logic;
+
+--signal fifoEmpty: std_logic;
+--signal fifoFull: std_logic;
+--signal fifoLI1: std_logic;
+--signal fifoLI0: std_logic;
+--signal BdR1: std_logic;
+--signal BdR0: std_logic;
signal purge: std_logic;
signal geneck: std_logic;
signal txck: std_logic;
signal busck: std_logic;
-signal adrbus: std_logic_vector((adr_w - 1) downto 0);
-signal databus: std_logic_vector(7 downto 0);
+signal adrbus: T_DATA;
+signal databus: T_DATA;
signal rw: std_logic;
signal rst: std_logic;
signal txdata: std_logic;