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authorprot2004-02-25 12:38:49 +0000
committerprot2004-02-25 12:38:49 +0000
commitc50aca8c4be2ef778eb634df7a530cde2ff23f39 (patch)
treebd0ed67fec5836ed98c003580242c1b6c76c85cc /2004
parent8e9ab78e5c440b09dac2a743e318bc8f4efa0670 (diff)
.
Diffstat (limited to '2004')
-rw-r--r--2004/n/fpga/src/portserie/bch_txserie.vhd3
-rw-r--r--2004/n/fpga/src/portserie/decoder.vhd13
-rw-r--r--2004/n/fpga/src/portserie/portserie.sws5
-rw-r--r--2004/n/fpga/src/portserie/reg.sws158
-rw-r--r--2004/n/fpga/src/portserie/test.sws136
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd3
6 files changed, 11 insertions, 307 deletions
diff --git a/2004/n/fpga/src/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/bch_txserie.vhd
index 42c9f9b..f976ce3 100644
--- a/2004/n/fpga/src/portserie/bch_txserie.vhd
+++ b/2004/n/fpga/src/portserie/bch_txserie.vhd
@@ -72,7 +72,7 @@ begin
bus_address <= "0000000011",
"0000000100" after 3*CK_PERIOD,
"0000000010" after 5*CK_PERIOD;
- bus_data <= bus_data + 1 after 10 ns;
+ bus_data <= "01010101";--) after 10 ns;
masterck<= not masterck after (CK_PERIOD/3);
end sim1;
@@ -84,3 +84,4 @@ configuration cf1_bch_txserie of bch_txserie is
end cf1_bch_txserie;
+
diff --git a/2004/n/fpga/src/portserie/decoder.vhd b/2004/n/fpga/src/portserie/decoder.vhd
index 8ca3a67..920431d 100644
--- a/2004/n/fpga/src/portserie/decoder.vhd
+++ b/2004/n/fpga/src/portserie/decoder.vhd
@@ -14,7 +14,7 @@ entity decoder is
generic(adr : T_ADDRESS);
port(
bus_address : in T_ADDRESS;
- cs: out std_logic
+ cs: out std_logic:='0'
);
end decoder;
@@ -22,13 +22,14 @@ architecture rtl of decoder is
begin
process(bus_address)
begin
- if(bus_address=adr)
- then
+ --if(bus_address = adr)
+ --then
cs<='1';
- else
- cs<='0';
- end if;
+ --else
+ -- cs<='0';
+ --end if;
end process;
end rtl;
+
diff --git a/2004/n/fpga/src/portserie/portserie.sws b/2004/n/fpga/src/portserie/portserie.sws
index 8762f0d..6ec0881 100644
--- a/2004/n/fpga/src/portserie/portserie.sws
+++ b/2004/n/fpga/src/portserie/portserie.sws
@@ -149,11 +149,6 @@
[]
[]
[file]
- name = fifo/fifoctlr_cc.vhd
- [options]
- []
- []
- [file]
name = fifo.vhd
[options]
[]
diff --git a/2004/n/fpga/src/portserie/reg.sws b/2004/n/fpga/src/portserie/reg.sws
deleted file mode 100644
index 8d94e37..0000000
--- a/2004/n/fpga/src/portserie/reg.sws
+++ /dev/null
@@ -1,158 +0,0 @@
-#
-# This file has been automatically generated by the Symphony EDA IDE
-# Please do NOT modify this file manually. If you do, do it with
-# extreme care. This file represents your project settings. Corrupting
-# this file can render this file useless!!!
-#
-# Begin version identification section
-[version]
- version = 1
-[]
-# Begin libraries section (used by all tools)
-[libraries]
- ieee = $SYMPHONYEDA/lib/ieee/ieee.sym
- reg = reg.sym
-[]
-# End of libraries section
- [options]
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 0
- invert = 0
- []
- [stringoption]
- name = -breakon
- value = FAILURE
- []
- [stringoption]
- name = -stdin
- value = ""
- []
- [stringoption]
- name = -stdout
- value = ""
- []
- [stringoption]
- name = -coverage
- value = ""
- []
- [multistringoption]
- name = -nowarn
- []
- [multistringoption]
- name = -noaccel
- value = 1164
- []
- [multistringoption]
- name = -sdftyp
- []
- [multistringoption]
- name = -sdfmin
- []
- [multistringoption]
- name = -sdfmax
- []
- []
-# Begin description of library ieee
-[library]
- name = ieee
- [options]
- [booloption]
- name = -87
- value = 0
- invert = 0
- []
- [booloption]
- name = -x
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 1
- invert = 0
- []
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [intoption]
- name = -maxerrors
- value = 10
- []
- [booloption]
- name = -autoorder
- value = 1
- invert = 0
- []
- []
-[]
-# End description of library ieee
-# Begin description of library reg
-[library]
- name = reg
- toplevel = testreg(sim1)
- [options]
- [booloption]
- name = -87
- value = 0
- invert = 0
- []
- [booloption]
- name = -x
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 1
- invert = 0
- []
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [intoption]
- name = -maxerrors
- value = 10
- []
- [booloption]
- name = -autoorder
- value = 1
- invert = 0
- []
- []
- [file]
- name = isa_const.vhd
- [options]
- []
- []
- [file]
- name = nono_const.vhd
- [options]
- []
- []
- [file]
- name = registre.vhd
- [options]
- []
- []
- [file]
- name = test_reg.vhd
- [options]
- []
- []
-[]
-# End description of library reg
-# Begin various workspace properties
-[properties]
- work =reg
-[]
-# End workspace properties
diff --git a/2004/n/fpga/src/portserie/test.sws b/2004/n/fpga/src/portserie/test.sws
deleted file mode 100644
index 03e4ba0..0000000
--- a/2004/n/fpga/src/portserie/test.sws
+++ /dev/null
@@ -1,136 +0,0 @@
-#
-# This file has been automatically generated by the Symphony EDA IDE
-# Please do NOT modify this file manually. If you do, do it with
-# extreme care. This file represents your project settings. Corrupting
-# this file can render this file useless!!!
-#
-# Begin version identification section
-[version]
- version = 1
-[]
-# Begin libraries section (used by all tools)
-[libraries]
- ieee = $SYMPHONYEDA/lib/ieee/ieee.sym
- test = test.sym
-[]
-# End of libraries section
- [options]
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 0
- invert = 0
- []
- [stringoption]
- name = -breakon
- value = FAILURE
- []
- [stringoption]
- name = -stdin
- value = ""
- []
- [stringoption]
- name = -stdout
- value = ""
- []
- [stringoption]
- name = -coverage
- value = ""
- []
- [multistringoption]
- name = -nowarn
- []
- [multistringoption]
- name = -noaccel
- []
- [multistringoption]
- name = -sdftyp
- []
- [multistringoption]
- name = -sdfmin
- []
- [multistringoption]
- name = -sdfmax
- []
- []
-# Begin description of library ieee
-[library]
- name = ieee
- [options]
- [booloption]
- name = -87
- value = 0
- invert = 0
- []
- [booloption]
- name = -x
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 1
- invert = 0
- []
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [intoption]
- name = -maxerrors
- value = 10
- []
- [booloption]
- name = -autoorder
- value = 1
- invert = 0
- []
- []
-[]
-# End description of library ieee
-# Begin description of library test
-[library]
- name = test
- [options]
- [booloption]
- name = -87
- value = 0
- invert = 0
- []
- [booloption]
- name = -x
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 1
- invert = 0
- []
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [intoption]
- name = -maxerrors
- value = 10
- []
- [booloption]
- name = -autoorder
- value = 1
- invert = 0
- []
- []
-[]
-# End description of library test
-# Begin various workspace properties
-[properties]
- work =test
-[]
-# End workspace properties
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index 3b483b9..81b5b5c 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -118,7 +118,7 @@ end component;
--signal fifoLI0: std_logic;
--signal BdR1: std_logic;
--signal BdR0: std_logic;
-signal purge: std_logic;
+signal purge: std_logic:='0';
signal geneck: std_logic;
signal txck: std_logic;
signal busck: std_logic;
@@ -210,3 +210,4 @@ end rtl;
+