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authorprot2004-02-23 19:29:34 +0000
committerprot2004-02-23 19:29:34 +0000
commit62f4ff258c479cca9073c5c1a782ac4861fc125f (patch)
tree65cbd981d20275755682749c9e41bccb01b77812 /2004
parent18b367e7ff0e22d6b7fce2a08df28c36960c7c11 (diff)
ajout des fichiers vhd
Diffstat (limited to '2004')
-rw-r--r--2004/n/fpga/src/portserie/bch_modele.vhd65
-rw-r--r--2004/n/fpga/src/portserie/isa_const.vhd27
-rw-r--r--2004/n/fpga/src/portserie/nono_const.vhd52
-rw-r--r--2004/n/fpga/src/portserie/registre.vhd105
-rw-r--r--2004/n/fpga/src/portserie/test_reg.vhd76
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd215
6 files changed, 540 insertions, 0 deletions
diff --git a/2004/n/fpga/src/portserie/bch_modele.vhd b/2004/n/fpga/src/portserie/bch_modele.vhd
new file mode 100644
index 0000000..18bc9a7
--- /dev/null
+++ b/2004/n/fpga/src/portserie/bch_modele.vhd
@@ -0,0 +1,65 @@
+-- modele.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Fichier modèle pour la déclaration de module.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+
+entity bch_modele is
+end bch_modele;
+
+architecture sim1 of bch_modele is
+
+ component modele
+ generic (
+ -- adresses des différents registres du module.
+ A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION;
+ A_REG2 : T_ADDRESS := A_REG_IO_DATA;
+ A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK
+ -- si autre choses à déclarer...
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ rw : in std_logic; -- read / write
+ bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
+ bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
+ );
+ end component;
+
+ -- définiton des signaux
+ signal rst : std_logic;
+ signal clk : std_logic := '0';
+ signal rw : std_logic; -- read / write
+ signal bus_data : unsigned ((NB_BIT_DATA - 1) downto 0);
+ signal bus_address : unsigned ((NB_BIT_ADDRESS - 1) downto 0);
+
+begin
+ U1 : modele port map (
+ rst => rst,
+ clk => clk,
+ rw => rw,
+ bus_data => bus_data,
+ bus_address => bus_address
+ );
+
+ rst <= '1', '0' after CK_PERIOD;
+ clk <= not clk after (CK_PERIOD/2);
+ rw <= '0';
+ bus_address <= A_REG_IO_DIRECTION,
+ A_REG_IO_DATA after 3*CK_PERIOD,
+ A_REG_IO_INTERRUPT_MASK after 5*CK_PERIOD;
+end sim1;
+
+configuration cf1_bch_modele of bch_modele is
+ for sim1
+ for all : modele use entity work.modele(test_modele); end for;
+ end for;
+end cf1_bch_modele;
+
diff --git a/2004/n/fpga/src/portserie/isa_const.vhd b/2004/n/fpga/src/portserie/isa_const.vhd
new file mode 100644
index 0000000..12ab384
--- /dev/null
+++ b/2004/n/fpga/src/portserie/isa_const.vhd
@@ -0,0 +1,27 @@
+-- isa_const.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Fichier de déclaration de constantes.
+
+-- RQ : pour une indentation bien sous vim :
+-- 1 - ":set shiftwidth=4"
+-- 2 - se placer sous "package nono_const is"
+-- 3 - tapez : = puis shift+G
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+-- Constantes relatives au bus ISA
+package isa_const is
+
+ -- Temps d'une période d'horloge sur le bus ISA
+ constant ISA_CK_PERIOD : time := 50 ns;
+
+ -- Ligne RW : lecture et écriture
+ constant ISA_READ : std_logic := '0';
+ constant ISA_WRITE : std_logic := '1';
+end isa_const;
+
diff --git a/2004/n/fpga/src/portserie/nono_const.vhd b/2004/n/fpga/src/portserie/nono_const.vhd
new file mode 100644
index 0000000..5c2e04a
--- /dev/null
+++ b/2004/n/fpga/src/portserie/nono_const.vhd
@@ -0,0 +1,52 @@
+-- nono_const.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Fichier de déclaration de constantes.
+
+-- RQ : pour une indentation bien sous vim :
+-- 1 - ":set shiftwidth=4"
+-- 2 - se placer sous "package nono_const is"
+-- 3 - tapez : = puis shift+G
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+package nono_const is
+
+ -- Temps d'une période d'horloge
+ constant CK_PERIOD : time := 10 ns;
+
+ -- Taille d'une addresse sur la carte
+ -- RQ : 10 = nb suffisant
+ -- 12 = 3 digit en héxa
+ constant NB_BIT_ADDRESS : integer := 10;
+
+ -- Taille des données sur la carte
+ constant NB_BIT_DATA : integer := 8;
+
+ -- Définition d'un nouveau type : ADDRESS
+ subtype T_ADDRESS is unsigned ((NB_BIT_ADDRESS - 1) downto 0);
+
+ -- Les différentes banques d'adresses (4 x 256)
+ -- Rq pour Pierre : ça va influer sur le bloc de gestion du bus
+ constant START_ADDR_B0 : T_ADDRESS := "0000000000";
+ constant START_ADDR_B1 : T_ADDRESS := "0100000000";
+ constant START_ADDR_B2 : T_ADDRESS := "1000000000";
+ constant START_ADDR_B3 : T_ADDRESS := "1100000000";
+
+ -- Les addresses des différents registres.
+
+ -- gestion des interruptions
+ constant A_INTERRUPT_MANAGER : T_ADDRESS := START_ADDR_B0 + x"00";
+ -- Bloc d'IO
+ constant A_REG_IO_DIRECTION : T_ADDRESS := START_ADDR_B0 + x"01";
+ constant A_REG_IO_DATA : T_ADDRESS := START_ADDR_B0 + x"02";
+ constant A_REG_IO_INTERRUPT_MASK : T_ADDRESS := START_ADDR_B0 + x"03";
+ -- Bloc port série
+ -- Bloc caméra
+ -- Bloc PWM
+ -- Bloc I²C
+ -- Bloc servo-moteurs
+end nono_const;
diff --git a/2004/n/fpga/src/portserie/registre.vhd b/2004/n/fpga/src/portserie/registre.vhd
new file mode 100644
index 0000000..23a0079
--- /dev/null
+++ b/2004/n/fpga/src/portserie/registre.vhd
@@ -0,0 +1,105 @@
+-- txserie.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+-- registre IO adressable sur bus ISA
+
+-- MARCHE
+
+-- -------------------------------------------
+-- Registre générique à brancher sur un bus
+-- -------------------------------------------
+--
+-- * on peut écrire ou lire dans le registre depuis le bus :
+-- . Positionner l'adresse
+-- . Mettre 'rw' à 1=>read 0=>write
+-- . Front montant sur 'ck'
+-- Remarque : on ne peut pas écrire via le bus si 'load' est activé
+-- * on peut lire la valeur en permanence sur 'output'
+-- * on peut écrire dans le registre en permanence grâce à 'load'. Cette
+-- action est prioritaire sur l'écriture via le bus
+-- . Mettre 'load' à 1
+-- . Ecrire dans 'input' (actualisation immédiate)
+-- . Mettre 'load' à 0 pour latcher
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+entity regIO is
+ generic(adr : unsigned);
+ port(
+ bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
+ bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
+ input: in unsigned(7 downto 0);
+ output: out unsigned(7 downto 0);
+ rw: in std_logic;
+ load: in std_logic;
+ ck: in std_logic;
+ rst: in std_logic
+ );
+end entity;
+
+
+architecture rtl of regIO is
+signal REG : unsigned((NB_BIT_DATA - 1) downto 0):=(others => '1');
+
+begin
+ p_w:process(ck,load,input,rst)
+ begin
+ if(ck='1') then
+ if(bus_address=adr) then
+ if(rw='0') then
+ if(load='0') then
+ REG<=bus_data;
+ end if;
+ else -- RW=1 : la CM lit => on écrit sur le bus
+ bus_data<=REG;
+ end if;
+ else
+ bus_data<=(others => 'Z');
+ end if;
+ else
+ bus_data<=(others => 'Z');
+ end if;
+
+-- chargement : prioritaire sur l'écriture via le bus
+ if(load='1') then
+ REG<=input;
+ end if;
+
+-- reset : prioritaire sur tout
+ if(rst'event and rst='1') then
+ REG<=(others => '0');
+ bus_data<=(others => 'Z');
+ end if;
+
+ end process p_w;
+
+-- p_load : process(load,input)
+-- begin
+-- if(load='1') then
+-- REG<=input;
+-- end if;
+-- end process p_load;
+
+-- p_reset : process(rst)
+-- begin
+-- if(rst'event and rst='1') then
+-- REG<=(others => '0');
+-- bus_data<=(others => 'Z');
+-- end if;
+-- end process p_reset;
+
+ output<=REG;
+end rtl;
+
+
+
+
+
+
+
diff --git a/2004/n/fpga/src/portserie/test_reg.vhd b/2004/n/fpga/src/portserie/test_reg.vhd
new file mode 100644
index 0000000..7573ba4
--- /dev/null
+++ b/2004/n/fpga/src/portserie/test_reg.vhd
@@ -0,0 +1,76 @@
+-- testbench pour le registre
+
+-- MARCHE
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+entity testreg is
+constant adr_w : integer :=10;
+constant data_w : integer :=8;
+end testreg;
+
+architecture sim1 of testreg is
+component regIO
+ generic(adr:unsigned);
+ port(
+ bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
+ bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
+ input: in unsigned((data_w - 1) downto 0);
+ output: out unsigned((data_w - 1) downto 0);
+ rw: in std_logic;
+ load: in std_logic;
+ ck: in std_logic;
+ rst: in std_logic
+ );
+end component;
+
+signal bus_address: unsigned((adr_w - 1) downto 0):="0000000000";
+signal bus_data: unsigned((data_w - 1) downto 0):="00000000";
+signal input: unsigned((data_w - 1) downto 0):="00000000";
+signal output: unsigned((data_w - 1) downto 0);
+signal rw: std_logic:='0';
+signal load: std_logic:='0';
+signal ck: std_logic:='0';
+signal rst: std_logic:='1';
+
+begin
+ R0: regIO
+ generic map(adr => "0000000001")
+ port map(
+ bus_address=>bus_address,
+ bus_data=>bus_data,
+ input=>input,
+ output=>output,
+ rw=>rw,
+ load=>load,
+ ck=>ck,
+ rst=>rst
+ );
+
+ bus_address <= "0001001100" ,
+ "0000000001" after 40 ns;
+-- "0000001101" after 100 ns;
+-- "0000001100" after 100 ns;
+
+ input <= input + 1 after 3 ns;
+ bus_data <= "01010101", "ZZZZZZZZ" after 2 ns;
+ rw <= not rw after 11 ns;
+ load <= not load after 7 ns;
+ ck <= not ck after 5 ns;
+ rst <= '0','1' after 1 ns,'0' after 2 ns;
+
+end sim1;
+
+
+configuration cf1 of testreg is
+ for sim1
+ for all : regIO use entity work.regIO(rtl); end for;
+ end for;
+end cf1;
+
+
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
new file mode 100644
index 0000000..df1ec41
--- /dev/null
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -0,0 +1,215 @@
+-- txserie.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+
+-- -------------------------------------------
+-- Port série TX pour le fpga robot
+-- -------------------------------------------
+--
+-- * Prend 3 adresses mémoire :
+-- 0 - Txdata
+-- 1 - Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
+-- 2 - Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
+-- * Mettre le bit On/Off à 1 pour activer la transmission
+-- * Chaque écriture dans txdata charge la donnée dans la fifo
+-- * Dès que le registre à décalage est vide, il enlève le dernier élément de
+-- la fifo et le transmet
+-- * Deux bits de stop
+-- * Quand la fifo est pleine, met le flag Full/Int à 1 et génère une
+-- interruption. Il faut alors mettre à 0 le bit IntEn, qui sera remis à 1 à
+-- la prochaine écriture dans la fifo
+-- * On peut lire l'état de la pile dans le registre de flags
+-- * On peut vider la pile en mettant Purge à 1
+-- * Baudrate disponible :
+-- BdR1/0 ! Baudrate
+-- 00 ! 9600
+-- 01 ! 19200
+-- 10 ! 57600
+-- 11 ! 115200
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+entity txserie is
+ generic (
+ -- adresses des différents registres du module.
+ A_DATA : T_ADDRESS ;
+ A_CONFIG : T_ADDRESS ;
+ A_FLAG : T_ADDRESS
+ -- si autre choses à déclarer...
+ );
+ port (
+ rst : in std_logic;
+ busclk : in std_logic;
+ rw : in std_logic; -- read (0) / write (1)
+ bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
+ bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
+ masterck: in std_logic;
+ txout: out std_logic;
+ minIRQ: out std_logic;
+ );
+end txserie;
+
+architecture rtl of txserie is
+
+component registre
+ generic(adr : integer);
+ port(
+ bus_address: in unsigned((NB_BIT_ADRESS - 1) downto 0);
+ bus_data: inout unsigned(7 downto 0);
+ input: in std_logic_vector(7 downto 0);
+ output: out std_logic_vector(7 downto 0);
+ rw: in std_logic;
+ load: in std_logic;
+ ck: in std_logic;
+ rst: in std_logic
+ );
+end component;
+
+component fifo
+ port(
+ data_in: in std_logic_vector(7 downto 0);
+ data_out: in std_logic_vector(7 downto 0);
+ ck_in: in std_logic;
+ ck_out: in std_logic;
+ f0: out std_logic;
+ f1: out std_logic;
+ f2: out std_logic;
+ f3: out std_logic;
+ purge: in std_logic
+ );
+end component;
+
+component transmitter
+ port(
+ data_in: in std_logic_vector(7 downto 0);
+ ck: in std_logic;
+ flag: out std_logic;
+ txout: out std_logic
+ );
+end component;
+
+component clockgene
+ port(
+ ck_in: in std_logic;
+ ck_out: in std_logic;
+ param: in std_logic_vector(1 downto 0)
+ );
+end component;
+
+component decoder
+ generic(adr : integer);
+ port(
+ bus_address: in std_logic_vector((NB_BIT_ADRESS - 1) downto 0);
+ cs: out std_logic
+ );
+end component;
+
+
+signal fifoEmpty: std_logic;
+signal fifoFull: std_logic;
+signal fifoLI1: std_logic;
+signal fifoLI0: std_logic;
+signal BdR1: std_logic;
+signal BdR0: std_logic;
+signal purge: std_logic;
+signal geneck: std_logic;
+signal txck: std_logic;
+signal busck: std_logic;
+signal bus_address: std_logic_vector((NB_BIT_ADRESS - 1) downto 0);
+signal bus_data: std_logic_vector(7 downto 0);
+signal rw: std_logic;
+signal rst: std_logic;
+signal txdata: std_logic;
+signal txempty: std_logic;
+signal csFifo: std_logic;
+signal fifockin: std_logic;
+signal fifockout: std_logic;
+
+FIFO1: fifo
+ port map(
+ data_in=>bus_data,
+ data_out=>txdata,
+ ck_in=>fifockin,
+ ck_out=>fifockout
+ f0=>fifoEmpty,
+ f1=>fifoLI0,
+ f2=>fifoLI1,
+ f3=>fifoFull,
+ purge=>confreg(3)
+ );
+
+fifockin<=csFifo and not rw and busck;
+fifockout<=txempty; -- à vérifier !!! Cette ligne est valable pour
+ -- txempty=1 quand le tx est vide
+
+TX1 : transmitter
+ port map(
+ data_in=>txdata,
+ ck=>txck,
+ flag=>txempty,
+ txout=>txout,
+ );
+
+CLOCK1 : clockgene
+ port map(
+ ck_in=>geneck,
+ ck_out=>txck,
+ param=>confreg(1 downto 0)
+ );
+geneck<=confreg(4) and masterck; -- On/Off et masterck
+
+
+-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
+RCONF : registre
+ generic map(adr=>adr+1)
+ port map(
+ bus_address=>bus_address,
+ bus_data=>bus_data,
+ input=>(others => '0'),
+ output=>confreg,
+ rw=>rw,
+ load=>'0',
+ ck=>busck,
+ rst=>'0'
+ );
+
+-- Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
+RFLAG : registre
+ generic map(adr=>adr+2)
+ port map(
+ bus_address=>bus_address,
+ bus_data=>bus_data,
+ input=>flagreg,
+ output=>open,
+ rw=>rw,
+ load=>'1',
+ ck=>busck,
+ rst=>'0'
+ );
+
+flagreg(7 downto 3)<=(others => '0');
+flagreg(3)<=txempty;
+flagreg(2)<=fifoFull;
+flagreg(1)<=fifoLI1;
+flagreg(0)<=fifoLI0;
+
+-- la sortie intout est active si la pile est pleine ET si le bit de conf est
+-- activé
+intout<=fifoFull and confreg(2); -- IntEn et fifoFull
+
+DECOD : decoder
+ generic map(adr=>adr)
+ port map(
+ bus_address=>bus_address,
+ cs=>csFifo
+ );
+end rtl;
+
+