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authorprot2004-04-22 12:14:37 +0000
committerprot2004-04-22 12:14:37 +0000
commitcf64d6b24651a717ff2d507181401fad3e8f5ac2 (patch)
tree7fc836f1153e696d7b6d76d1f70cdecbcfd08e83 /2004/n
parent13686b9017bfee8266611872c8e13d6cf668fdd0 (diff)
Corrections bugs
Diffstat (limited to '2004/n')
-rw-r--r--2004/n/fpga/doc/dcd/rapport.tex35
1 files changed, 17 insertions, 18 deletions
diff --git a/2004/n/fpga/doc/dcd/rapport.tex b/2004/n/fpga/doc/dcd/rapport.tex
index 4d8af0e..386d5a2 100644
--- a/2004/n/fpga/doc/dcd/rapport.tex
+++ b/2004/n/fpga/doc/dcd/rapport.tex
@@ -80,7 +80,6 @@ réalisation du PCB.
\vfill
-=======
% Todo :
% Remerciements ?
@@ -193,13 +192,13 @@ RW <= not IOR
clk <= (IOR or IOW) and not AEN
CS prend la sortie du décodeur de la sous-adresse registre correspondant au registre voulu.
-\begin{figure}[htbp]
-\caption{Conversion des signaux de contrôle de bus}
-\begin{center}
-\includegraphics[width=1\textwidth,angle=90]{./convbus.pdf}
-\end{center}
-\label{convbus}
-\end{figure}
+%\begin{figure}[htbp]
+%\caption{Conversion des signaux de contrôle de bus}
+%\begin{center}
+%\includegraphics[width=1\textwidth,angle=90]{./convbus.pdf}
+%\end{center}
+%\label{convbus}
+%\end{figure}
\subsection{Implémentation}
@@ -387,37 +386,37 @@ Le fichier qui inclut le TX et le RX pour le testbench des deux
\pagebreak
\subsubsection{txserie.vhd}
-\label{sec:}
+\label{sec:txserie}
\lstinputlisting{../../src/portserie/portserie/txserie.vhd}
\pagebreak
-\subsubsection{bch_txserie.vhd}
-\label{sec:}
+\subsubsection{bch\_txserie.vhd}
+\label{sec:bch_txserie}
\lstinputlisting{../../src/portserie/portserie/bch_txserie.vhd}
\pagebreak
\subsubsection{rxserie.vhd}
-\label{sec:}
+\label{sec:rxserie}
\lstinputlisting{../../src/portserie/rxserie/rxserie.vhd}
\pagebreak
-\subsubsection{bch_rxserie.vhd}
-\label{sec:}
+\subsubsection{bch\_rxserie.vhd}
+\label{sec:bch_rxserie}
\lstinputlisting{../../src/portserie/rxserie/bch_rxserie.vhd}
\pagebreak
\subsubsection{clockgene.vhd}
-\label{sec:}
+\label{sec:clockgene}
\lstinputlisting{../../src/portserie/clockgene/clockgene.vhd}
\pagebreak
\subsubsection{fifodriver.vhd}
-\label{sec:}
+\label{sec:fifodriver}
\lstinputlisting{../../src/portserie/fifo/fifodriver.vhd}
\pagebreak
-\subsubsection{bch_fifodriver.vhd}
-\label{sec:}
+\subsubsection{bch\_fifodriver.vhd}
+\label{sec:bch_fifodriver}
\lstinputlisting{../../src/portserie/fifo/bch_fifodriver.vhd}
\pagebreak