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authorgalmes2004-04-28 18:29:26 +0000
committergalmes2004-04-28 18:29:26 +0000
commit130cf2e254043f28b912413f651a543d581e872e (patch)
tree163b0ab873d97c04cd47a79bd63d7c66bdf9d024 /2004/n
parentbfa75e6dcbe6ce7c5b99e877bf7c02d76e81066c (diff)
servo : les fichiers du bloc servo qui marche trop de bombe de balle. Il
faudra peut-être revoir les constantes à calibrer en fonction du servo.
Diffstat (limited to '2004/n')
-rw-r--r--2004/n/fpga/src/servo/convert_servo.vhd41
-rw-r--r--2004/n/fpga/src/servo/servo_generator.vhd52
-rw-r--r--2004/n/fpga/src/servo/servo_nono.vhd115
3 files changed, 208 insertions, 0 deletions
diff --git a/2004/n/fpga/src/servo/convert_servo.vhd b/2004/n/fpga/src/servo/convert_servo.vhd
new file mode 100644
index 0000000..af1e948
--- /dev/null
+++ b/2004/n/fpga/src/servo/convert_servo.vhd
@@ -0,0 +1,41 @@
+-------------------------------------------------------------------------------
+--convert_servo.vhd
+--Eurobot 2004 : APB Team
+--Auteur : Fidèle GAFAN
+--Module générateur des PWM
+--
+--REMARQUE(S):changer tccompt,q et data_out
+-- si CLK#32MHz et/ou qu'on modifie les valeurs de référence de T1
+-- et T2
+-- Tcmax=20ms/1us=20161cycles.
+--*Si DATACOMPT=0,on veut que T2 vale 0,5ms donc on initialise Q à la valeur
+--Q=0,5ms/1us=PWM_VALUE_MIN.
+--*Si DATACOMPT=255,on veut que T2 vale 1,5ms donc on initialise Q à la valeur
+--Q=1,5ms/1us=PWM_VALUE_MAX.
+--*Pour toute autre valeur de DATACOMPT comprise entre les deux précédentes et
+--différentes de ces dernières,on initialise Q avec
+--Q=(0,5ms/1us)+(DATACOMPT*min[((1,5ms-0,5ms)/1us)/(255-0)]
+-------------------------------------------------------------------------------
+--LIBRARY
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+use work.nono_const.all;
+use work.servo_const.all;
+
+--ENTITY
+entity convert_servo is
+port (
+ data_in : in T_OCTET;
+ data_out : out T_DOUBLE_OCTET --duree pdt laql la sortie
+ );
+end entity;
+
+
+architecture RTL of convert_servo is
+begin
+ data_out <= (SERVO_VALUE_MIN + (data_in * SERVO_INC_INT));
+
+end RTL;
diff --git a/2004/n/fpga/src/servo/servo_generator.vhd b/2004/n/fpga/src/servo/servo_generator.vhd
new file mode 100644
index 0000000..278cbff
--- /dev/null
+++ b/2004/n/fpga/src/servo/servo_generator.vhd
@@ -0,0 +1,52 @@
+-------------------------------------------------------------------------------
+-- servo_generator.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Fidèle GAFAN et Pierre-André Galmes
+
+-- TODO : reprendre les commentaires déjà faits !
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+use work.nono_const.all;
+use work.servo_const.all;
+
+--ENTITE
+entity servo_generator is
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ servo_in : in T_DOUBLE_OCTET;
+ servo_out : out std_logic
+ );
+end entity;
+
+--ARCHITECTURE
+architecture RTL of servo_generator is
+ signal compt : T_DOUBLE_OCTET;
+ signal reg : T_DOUBLE_OCTET;
+begin
+
+ process(rst, clk)
+ begin
+ if (rst = '1') then
+ compt <= x"0000";
+ reg <= x"0000";
+ servo_out <= '0';
+ elsif (clk'event and clk = '1') then
+ compt <= compt + x"0001";
+ if (compt < reg) then
+ servo_out <= '1';
+ else
+ servo_out <= '0';
+ if (compt = SERVO_NB_CYCLE_20MS) then
+ compt <= x"0000";
+ reg <= servo_in;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end RTL;
diff --git a/2004/n/fpga/src/servo/servo_nono.vhd b/2004/n/fpga/src/servo/servo_nono.vhd
new file mode 100644
index 0000000..a6c1d95
--- /dev/null
+++ b/2004/n/fpga/src/servo/servo_nono.vhd
@@ -0,0 +1,115 @@
+-- servo_nono.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Fidèle GAFAN et Pierre-andré Galmes
+-- Bloc de génération de servo.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+use work.nono_const.all;
+use work.isa_const.all;
+use work.servo_const.all;
+
+-- ENTITY
+entity servo_nono is
+port(
+ rst : in std_logic;
+ clk : in std_logic;
+ rw : in std_logic;
+ cs : in std_logic;
+ bus_data : inout T_DATA;
+ outservo : out std_logic
+);
+end servo_nono;
+
+
+-- ARCHITECTURE
+architecture RTL of servo_nono is
+
+-- Registre.
+component reg_rw is
+port (
+ clk : in std_logic;
+ rst : in std_logic;
+ rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
+ enable : in std_logic;
+ data : inout T_DATA;
+ data_out : out T_DATA -- data courant
+);
+end component;
+
+-- todo : supprimer l'horloge du moule et le mettre sur la carte !
+-- Générateur d'horloge à 1us.
+component clk1us is
+port(
+ RST : in std_logic;
+ CLK : in std_logic; --40MHz
+ CLK1USOUT : out std_logic
+);
+end component;
+
+-- Convertisseur [0-255] vers un temps.
+component convert_servo is
+port(
+ data_in : in T_OCTET;
+ data_out : out T_DOUBLE_OCTET --duree pdt laql la sortie
+);
+end component;
+
+-- Générateur de servo.
+component servo_generator is
+port (
+ rst : in std_logic;
+ clk : in std_logic;
+ servo_in : in T_DOUBLE_OCTET;
+ servo_out : out std_logic
+);
+end component;
+
+
+--DECLARATION DES SIGNAUX LOCAUX
+signal clkdiv : std_logic;
+signal reg_out : T_OCTET;
+signal convert_out : T_DOUBLE_OCTET;
+
+
+begin
+-- Mapping DES SIGNAUX.
+
+--
+registre : reg_rw
+port map(
+ clk,
+ rst,
+ rw,
+ cs,
+ bus_data,
+ reg_out
+);
+
+--
+Clock_div : clk1us
+port map(
+ rst,
+ clk,
+ clkdiv
+);
+
+--
+convert_nono : convert_servo
+port map(
+ reg_out,
+ convert_out
+);
+
+--
+servo_gene : servo_generator
+port map(
+ rst,
+ clkdiv,
+ convert_out,
+ outservo
+);
+
+
+end RTL;