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authorgalmes2004-04-05 18:20:37 +0000
committergalmes2004-04-05 18:20:37 +0000
commit9e8733884aea099d87f1cb257c880ec9b5fb9c7c (patch)
tree50c50f596970628b9f6220132a6a2ee7bd8b48f6 /2004/n/fpga
parent408461b4500f1afa51d9cd618d8557f9d02a04ec (diff)
reg_rw : code "enjolivé".
Diffstat (limited to '2004/n/fpga')
-rw-r--r--2004/n/fpga/src/registre/reg_rw.vhd15
1 files changed, 4 insertions, 11 deletions
diff --git a/2004/n/fpga/src/registre/reg_rw.vhd b/2004/n/fpga/src/registre/reg_rw.vhd
index 764eb0d..3f5eb52 100644
--- a/2004/n/fpga/src/registre/reg_rw.vhd
+++ b/2004/n/fpga/src/registre/reg_rw.vhd
@@ -22,7 +22,7 @@ entity reg_rw is
port (
clk : in std_logic;
rst : in std_logic;
- rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
+ rw : in std_logic; -- ISA_READ / ISA_WRITE
enable : in std_logic;
data : inout T_DATA;
data_out : out T_DATA -- data courant
@@ -40,23 +40,16 @@ begin
if (rst = '1') then
REG <= (others => '0');
data <= (others => 'Z');
- -- écriture des données.
+ -- Ecriture des données.
elsif (clk'event and clk = '1') then
if (enable = '1' and rw = ISA_WRITE) then
REG <= data;
--- end if;
- --else
- -- if (enable = '1' and rw = ISA_READ) then
- -- data <= REG;
- -- else
- -- data <= (others =>'Z');
- -- end if;
end if;
end if;
end process;
- -- partie combinatoire.
- -- commenter ligne suivante pour version 1
+ -- Partie combinatoire.
+ -- Lecture des données.
data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z');
data_out <= REG;