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authorburg2004-04-18 12:11:33 +0000
committerburg2004-04-18 12:11:33 +0000
commit7c792977220b90d54a05081a1a6add51ac206632 (patch)
tree9f166c0dd29051da96ac64f6044eb00e1f0b673c /2004/n/fpga
parentaa6b169bfab000dbdb6a9bac6cce430c39e7d946 (diff)
Tous les tableau de branchement ont été ajouté
Diffstat (limited to '2004/n/fpga')
-rw-r--r--2004/n/fpga/doc/dcd/carte/carte.tex154
1 files changed, 146 insertions, 8 deletions
diff --git a/2004/n/fpga/doc/dcd/carte/carte.tex b/2004/n/fpga/doc/dcd/carte/carte.tex
index 95e6ace..de4cc94 100644
--- a/2004/n/fpga/doc/dcd/carte/carte.tex
+++ b/2004/n/fpga/doc/dcd/carte/carte.tex
@@ -104,11 +104,12 @@ l'octet de poids fort.
\subsection{Table de correspondance avec le FPGA}
\subsubsection{ Interconnection avec le bus ISA}
+Voici comment le port ISA de l'ordinateur a t connecter sur le FPGA.
+
\begin{center}
-\begin{tabular}{c c c}
+\begin{tabular}{c c}
\begin{tabular}{|c|c||c|c|}
-\hline
\multicolumn{4}{c}{Donnes} \\
\hline
D15 & P206 & D7 & P138 \\ \hline
@@ -124,7 +125,6 @@ D8 & P199 & D0 & P148 \\ \hline
&
\begin{tabular}{|c|c||c|c|}
-\hline
\multicolumn{4}{c}{Adresse} \\
\hline
A0 & P195 & A1 & P194 \\ \hline
@@ -139,10 +139,9 @@ A16 & P167 & A17 & P166 \\ \hline
A18 & P164 & A19 & P162 \\ \hline
\end{tabular}
-&
+\end{tabular}
\begin{tabular}{|c|c||c|c|}
-\hline
\multicolumn{4}{c}{Autres connections} \\
\hline
MEMEW & P176 & MEMR & P174 \\ \hline
@@ -150,10 +149,149 @@ IOR & P165 & IOW & P163 \\ \hline
AEN & P161 & SBHE & P160 \\ \hline
IOCS16 & P152 & MEMCS16 & P151 \\ \hline
INT\_1 & P150 & INT\_2 & P149 \\ \hline
-CS\_DATA & P136 \\ \hline
+CS\_DATA & P136 & BUS\_CLK & P185 \\ \hline
\end{tabular}
-\\
+\end{center}
+\subsubsection{Ports externes et Ports ddi}
+
+Les ports externes permet d'avoir des entres/sorties programmable volonter.
+
+\begin{tabular}{c c c}
+
+\begin{tabular}{|c|c|}
+\multicolumn{2}{c}{Port 1 - JP10} \\
+\hline
+JP10 - 1 & P35 \\ \hline
+JP10 - 2 & P42 \\ \hline
+JP10 - 3 & P34 \\ \hline
+JP10 - 4 & P41 \\ \hline
+JP10 - 5 & P33 \\ \hline
+JP10 - 6 & P37 \\ \hline
+JP10 - 7 & P31 \\ \hline
+JP10 - 8 & P36 \\ \hline
+JP10 - 9 & 5V \\ \hline
+JP10 - 10 & GND \\ \hline
+\end{tabular}
+
+&
+
+\begin{tabular}{|c|c|}
+\multicolumn{2}{c}{Port 2 - JP6} \\
+\hline
+JP6 - 1 & P83 \\ \hline
+JP6 - 2 & P73 \\ \hline
+JP6 - 3 & P84 \\ \hline
+JP6 - 4 & P74 \\ \hline
+JP6 - 5 & P86 \\ \hline
+JP6 - 6 & P81 \\ \hline
+JP6 - 7 & P87 \\ \hline
+JP6 - 8 & P82 \\ \hline
+JP6 - 9 & 5V \\ \hline
+JP6 - 10 & GND \\ \hline
+\end{tabular}
+
+&
+
+\begin{tabular}{|c|c|}
+\multicolumn{2}{c}{Port 3 - JP7} \\
+\hline
+JP7 - 1 & P95 \\ \hline
+JP7 - 2 & P88 \\ \hline
+JP7 - 3 & P96 \\ \hline
+JP7 - 4 & P89 \\ \hline
+JP7 - 5 & P97 \\ \hline
+JP7 - 6 & P90 \\ \hline
+JP7 - 7 & P98 \\ \hline
+JP7 - 8 & P94 \\ \hline
+JP7 - 9 & 5V \\ \hline
+JP7 - 10 & GND \\ \hline
+\end{tabular}
+\end{tabular}
+
+
+\begin{tabular}{c c c}
+
+\begin{tabular}{|c|c|}
+\multicolumn{2}{c}{Port 4 - JP5} \\
+\hline
+JP5 - 1 & P108 \\ \hline
+JP5 - 2 & P99 \\ \hline
+JP5 - 3 & P109 \\ \hline
+JP5 - 4 & P100 \\ \hline
+JP5 - 5 & P110 \\ \hline
+JP5 - 6 & P101 \\ \hline
+JP5 - 7 & P111 \\ \hline
+JP5 - 8 & 102 \\ \hline
+JP5 - 9 & 5V \\ \hline
+JP5 - 10 & GND \\ \hline
+\end{tabular}
+
+&
+
+\begin{tabular}{|c|c|}
+\multicolumn{2}{c}{Port 5 - JP4} \\
+\hline
+JP6 - 1 & P119 \\ \hline
+JP6 - 2 & P112 \\ \hline
+JP6 - 3 & P120 \\ \hline
+JP6 - 4 & P113 \\ \hline
+JP6 - 5 & P121 \\ \hline
+JP6 - 6 & P114 \\ \hline
+JP6 - 7 & P122 \\ \hline
+JP6 - 8 & P115 \\ \hline
+JP6 - 9 & 5V \\ \hline
+JP6 - 4 & GND \\ \hline
+\end{tabular}
+
+&
+
+\begin{tabular}{|c|c|}
+\multicolumn{2}{c}{Divers} \\
+\hline
+LED1 & P133 \\ \hline
+LED2 & P134 \\ \hline
+Bonton& P132 \\ \hline
+I2C clk & P29 \\ \hline
+I2C data & P30 \\ \hline
+Clk-40Mhz & P126 \\ \hline
+Clk-24Mhz & P80 \\ \hline
+\end{tabular}
+\end{tabular}
+
+\begin{tabular}{c c}
+
+\begin{tabular}{|c|c||c|c|}
+\multicolumn{4}{c}{Port Parallle - JP8} \\
+\hline
+JP8 - 15 & P57 & JP8 - 20& P69 \\ \hline
+JP8 - 13 & P49 & JP8 - 18 & P68 \\ \hline
+JP8 - 11 & P48 & JP8 - 16 & P67 \\ \hline
+JP8 - 9 & P47 & JP8 - 14 & P63 \\ \hline
+JP8 - 7 & P46 & JP8 - 12 & P62 \\ \hline
+JP8 - 5 & P45 & JP8 - 10 & P61 \\ \hline
+JP8 - 3 & P44 & JP8 - 8 & P60 \\ \hline
+JP8 - 1 & P43 & JP8 - 6 & P59\\ \hline
+JP8 - 17 & P71 & JP8 - 4 & P58 \\ \hline
+JP8 - 19 & P70 & JP8 - 2 & GND \\ \hline
+\end{tabular}
+
+&
+
+\begin{tabular}{|c|c||c|c|}
+\multicolumn{4}{c}{Port Camera - JP12}\\
+\hline
+JP12-1 (Y0)& P3& JP12-13 (i2c clk) & P29 \\ \hline
+JP12-2 (Y1)& P4& JP12-14 (href) & P16 \\ \hline
+JP12-3 (Y2)& P5& JP12-18 (pclk) & P77 \\ \hline
+JP12-4 (Y3)& P6& JP12-23 (uv0) & P17 \\ \hline
+JP12-5 (Y4)& P7& JP12-24 (uv1) & P18 \\ \hline
+JP12-6 (Y5)& P8& JP12-25 (uv2) & P20 \\ \hline
+JP12-7 (Y6)& P9& JP12-26 (uv3) & P21 \\ \hline
+JP12-8 (Y7)& P10& JP12-27 (uv4) & P22 \\ \hline
+JP12-9 (reste)&P14 & JP12-28 (uv5) & P23 \\ \hline
+JP12-11 (i2c data)& P30 & JP12-29 (uv6) & P24 \\ \hline
+JP12-16 (vsyn)& P15 & JP12-30 (uv7) & P27 \\ \hline
+\end{tabular}
\end{tabular}
-\end{center}