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authorgalmes2004-03-12 17:05:35 +0000
committergalmes2004-03-12 17:05:35 +0000
commit642fc2f79fc10fa96232eec106344b48dd31eaf9 (patch)
tree55eec88b45168f56c60ca1dd097c179161ceaa7f /2004/n/fpga/src
parent0633b192515a68393c0adec67b9c79d7d0de6988 (diff)
Suppression du fichier conserv.vhd remplacé par conserv1.vhd.
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/interrupt/bch_conserv.vhd61
-rw-r--r--2004/n/fpga/src/interrupt/conserv.vhd67
2 files changed, 0 insertions, 128 deletions
diff --git a/2004/n/fpga/src/interrupt/bch_conserv.vhd b/2004/n/fpga/src/interrupt/bch_conserv.vhd
deleted file mode 100644
index 85f1222..0000000
--- a/2004/n/fpga/src/interrupt/bch_conserv.vhd
+++ /dev/null
@@ -1,61 +0,0 @@
--- bch_conserv.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Test de conserv.
-
-library ieee;
-use ieee.std_logic_1164.all;
---use ieee.std_logic_arith.all;
---use ieee.std_logic_unsigned.all;
-
-use work.isa_const.all;
-use work.nono_const.all;
-
-
-entity bch_conserv is
-end bch_conserv;
-
-architecture sim1 of bch_conserv is
-
- component conserv
- port (
- clk : in std_logic;
- rst : in std_logic;
- data_in : in T_DATA;
- data_out : out T_DATA
- );
- end component;
-
- -- définiton des signaux
- signal clk : std_logic := '0';
- signal rst : std_logic;
- signal data_in : T_DATA;
- signal data_out : T_DATA;
-
-begin
- U1 : conserv port map (
- clk => clk,
- rst => rst,
- data_in => data_in,
- data_out => data_out
- );
-
- clk <= not clk after CK_PERIOD/2;
- rst <= '1',
- '0' after CK_PERIOD,
- '1' after 7*CK_PERIOD,
- '0' after 8*CK_PERIOD;
- data_in <= x"01",
- x"00" after 2*CK_PERIOD,
- x"08" after 5*CK_PERIOD,
- x"01" after 7*CK_PERIOD,
- x"00" after 9*CK_PERIOD;
- --x"03" after 5*CK_PERIOD;
-end sim1;
-
-configuration cf1_bch_conserv of bch_conserv is
- for sim1
- for all : conserv use entity work.conserv(RTL); end for;
- end for;
-end cf1_bch_conserv;
-
diff --git a/2004/n/fpga/src/interrupt/conserv.vhd b/2004/n/fpga/src/interrupt/conserv.vhd
deleted file mode 100644
index f739f96..0000000
--- a/2004/n/fpga/src/interrupt/conserv.vhd
+++ /dev/null
@@ -1,67 +0,0 @@
--- conserv.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Lors de la détection d'un front, garde un état haut durant 2 cycles
--- d'horloge.
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.isa_const.all;
-use work.nono_const.all;
-
-
-entity conserv is
- port (
- clk : in std_logic;
- rst : in std_logic;
- data_in : in T_DATA;
- data_out : out T_DATA
- );
-end entity;
-
-architecture RTL of conserv is
-
- -- Signal interne
- -- registres à décalage pour compter 2 cycles.
- signal cycle0 : std_logic_vector (1 downto 0);
--- signal reg_dec 1 : std_logic_vector (2 downto 0);
--- signal reg_dec 2 : std_logic_vector (2 downto 0);
--- signal reg_dec 3 : std_logic_vector (2 downto 0);
--- signal reg_dec 4 : std_logic_vector (2 downto 0);
--- signal reg_dec 5 : std_logic_vector (2 downto 0);
--- signal reg_dec 6 : std_logic_vector (2 downto 0);
--- signal reg_dec 7 : std_logic_vector (2 downto 0);
-
-begin
- -- process séquentiel
- process (rst, clk)
- begin
- if (rst = '1') then
- data_out <= x"00";
- cycle0 <= "00";
-
- -- TODO : Ne peut-on pas faire en concurentiel ? Là, ne vat-il pas y
- -- avoir un retard entre data_out(0) et data_out(7) si on les met en
- -- séquentiel ?
- elsif (clk'event and clk = '1') then
- -- Remise à zéro.
- if (cycle0 = "10") then
- cycle0 <= "00";
- data_out(0) <= '0';
- end if;
- --
- if (data_in(0) /= '0' or cycle0 = "01") then
- cycle0 <= cycle0 + "01"; -- TODO : vérifier que valable.
- data_out(0) <= '1';
- end if;
-
- end if;
- end process;
-
- -- process combinatoire.
-
-end RTL;