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authorprot2004-03-14 23:56:14 +0000
committerprot2004-03-14 23:56:14 +0000
commit503437bcc6c78c18a1ffe53c8ce30d6b637e2423 (patch)
tree1b5a5f3186a150c320513b2d2d418fa8bd2ba8b3 /2004/n/fpga/src
parented85c54d3129c8c39327d07270f06edfd8538446 (diff)
Le port série tx qui marche
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/portserie/portserie/bch_txmit.vhd55
-rw-r--r--2004/n/fpga/src/portserie/portserie/bch_txserie.vhd301
-rw-r--r--2004/n/fpga/src/portserie/portserie/portserie.npl36
-rw-r--r--2004/n/fpga/src/portserie/portserie/sfifo.xco41
-rw-r--r--2004/n/fpga/src/portserie/portserie/txmit.vhd141
-rw-r--r--2004/n/fpga/src/portserie/portserie/txserie.vhd232
6 files changed, 806 insertions, 0 deletions
diff --git a/2004/n/fpga/src/portserie/portserie/bch_txmit.vhd b/2004/n/fpga/src/portserie/portserie/bch_txmit.vhd
new file mode 100644
index 0000000..8c855b9
--- /dev/null
+++ b/2004/n/fpga/src/portserie/portserie/bch_txmit.vhd
@@ -0,0 +1,55 @@
+
+-- VHDL Test Bench Created from source file txmit.vhd -- 03:08:15 03/11/2004
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY txmit_bch_txmit_vhd_tb IS
+END txmit_bch_txmit_vhd_tb;
+
+ARCHITECTURE behavior OF txmit_bch_txmit_vhd_tb IS
+
+ COMPONENT txmit
+ PORT(
+ MCLKX16 : IN std_logic;
+ WRITE : IN std_logic;
+ RESET : IN std_logic;
+ DATA : IN std_logic_vector(7 downto 0);
+ TX : OUT std_logic;
+ TXRDY : OUT std_logic
+ );
+ END COMPONENT;
+
+ SIGNAL clk : std_logic:='0';
+ SIGNAL WRITE : std_logic:='0';
+ SIGNAL rst : std_logic:='0';
+ SIGNAL DATA : std_logic_vector(7 downto 0):=(others => '0');
+ SIGNAL TX : std_logic:='0';
+ SIGNAL TXRDY : std_logic:='0';
+
+BEGIN
+
+ uut: txmit PORT MAP(
+ MCLKX16 => clk,
+ WRITE => WRITE,
+ RESET => rst,
+ DATA => DATA,
+ TX => TX,
+ TXRDY => TXRDY
+ );
+
+-- data <= std_logic_vector(unsigned(data) + 1) after 80 ns;
+ data <= "01010101","10101010" after 2000 ns;
+ rst<='1' , '0' after 10 ns;
+ clk <= not clk after 1 ns;
+ write <= not write after 400 ns;
+
+END;
diff --git a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
new file mode 100644
index 0000000..3400854
--- /dev/null
+++ b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
@@ -0,0 +1,301 @@
+-- modele.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Fichier modèle pour la déclaration de module.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+
+entity bch_txserie is
+end bch_txserie;
+
+architecture sim1 of bch_txserie is
+component txserie
+ port (
+ rst : in std_logic;
+ bus_clk : in std_logic;
+ rw : in std_logic; -- read (0) / write (1)
+ bus_data : inout T_DATA:=(others => 'Z');
+ clk: in std_logic;
+ txout: out std_logic;
+ minIRQ: out std_logic;
+ csData : in std_logic;
+ csConfig : in std_logic;
+ csFlag : in std_logic
+ );
+end component;
+
+
+-- définiton des signaux
+signal simclk:std_logic:='0';
+signal rst : std_logic;
+signal clk : std_logic;
+signal rw : std_logic;
+signal bus_data : T_DATA:=(others => 'Z');
+signal masterck: std_logic:='0';
+signal txout: std_logic;
+signal minIRQ: std_logic;
+signal csData : std_logic;
+signal csConfig : std_logic;
+signal csFlag : std_logic;
+
+signal state:integer:=-3;
+
+
+
+begin
+ U1 : txserie
+ port map(
+ rst => rst,
+ bus_clk => clk,
+ rw =>rw,
+ bus_data => bus_data,
+ clk => masterck,
+ txout => txout,
+ minIRQ => minirq,
+ csData => csData,
+ csConfig => csConfig,
+ csFlag => csFlag );
+
+
+ rst<='1','0' after 5 ns;
+ simclk<= not simclk after 10 ns;
+ masterck<= not masterck after 3 ns;
+
+ combi:process(state)
+ begin
+ clk <= '0';
+ rw <= '0';
+ bus_data <= (others => 'Z');
+ csData <= '0';
+ csConfig <= '0';
+ csFlag <= '0';
+
+ case state is
+ when 1 => bus_data<="00010110";
+ csConfig<='1';
+ rw<='0';
+ when 2 => bus_data<="00010110";
+ csConfig<='1';
+ rw<='0';
+ clk<='1';
+ when 4 => bus_data<="00010110";
+ csData<='1';
+ rw<='0';
+ when 5 => bus_data<="00010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+
+ when 70 => bus_data<="00010110";
+ csData<='1';
+ rw<='0';
+ when 71 => bus_data<="00010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+
+ when 12 => csFlag<='1';
+ rw<='1';
+ when 13 =>
+ csFlag<='1';
+ rw<='1';
+ clk<='1';
+
+
+ when 20 => bus_data<="01010101";
+ csData<='1';
+ rw<='0';
+ when 21 => bus_data<="01010101";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+
+ when 1004 => bus_data<="00010110";
+ csData<='1';
+ rw<='0';
+ when 1005 => bus_data<="00010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1007 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1008 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1010 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1011 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1013 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1014 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1016 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1017 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1019 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1020 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1022 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1023 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1025 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1026 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1028 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1029 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1031 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1032 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1034 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1035 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1037 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1038 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1040 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1041 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1043 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1044 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1046 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1047 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1049 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1050 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1052 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1053 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1055 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1056 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1058 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1059 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1061 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1062 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+--
+ when 1064 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ when 1065 => bus_data<="01010110";
+ csData<='1';
+ rw<='0';
+ clk<='1';
+
+
+ when others => null;
+ end case;
+ end process;
+
+ sequ:process(simclk)
+ begin
+ state<=state+1;
+ end process;
+
+
+
+
+end sim1;
+
diff --git a/2004/n/fpga/src/portserie/portserie/portserie.npl b/2004/n/fpga/src/portserie/portserie/portserie.npl
new file mode 100644
index 0000000..1743fbf
--- /dev/null
+++ b/2004/n/fpga/src/portserie/portserie/portserie.npl
@@ -0,0 +1,36 @@
+JDF G
+// Created by Project Navigator ver 1.0
+PROJECT txserie
+DESIGN portserie
+DEVFAM spartan2
+DEVFAMTIME 0
+DEVICE xc2s200
+DEVICETIME 1078190070
+DEVPKG pq208
+DEVPKGTIME 0
+DEVSPEED -6
+DEVSPEEDTIME 0
+DEVTOPLEVELMODULETYPE HDL
+TOPLEVELMODULETYPETIME 0
+DEVSYNTHESISTOOL XST (VHDL/Verilog)
+SYNTHESISTOOLTIME 0
+DEVSIMULATOR Modelsim
+SIMULATORTIME 0
+DEVGENERATEDSIMULATIONMODEL VHDL
+GENERATEDSIMULATIONMODELTIME 0
+SOURCE txserie.vhd
+STIMULUS bch_txserie.vhd
+SOURCE txmit.vhd
+SOURCE ..\..\modele\nono_const.vhd
+SOURCE ..\..\modele\isa_const.vhd
+SOURCE ..\..\registre\registre.vhd
+SOURCE ..\..\..\..\..\..\xilinx\vhdl\src\unisims\unisim_VCOMP.vhd
+SOURCE ..\fifo\fifodriver.vhd
+SOURCE ..\fifo\sfifo.xco
+STIMULUS bch_txmit.vhd
+STIMULUS ..\fifo\bch_fifodriver.vhd
+SOURCE ..\clockgene\clockgene.vhd
+[Normal]
+p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078871494, ModelSim SE
+[STRATEGY-LIST]
+Normal=True
diff --git a/2004/n/fpga/src/portserie/portserie/sfifo.xco b/2004/n/fpga/src/portserie/portserie/sfifo.xco
new file mode 100644
index 0000000..a2badbd
--- /dev/null
+++ b/2004/n/fpga/src/portserie/portserie/sfifo.xco
@@ -0,0 +1,41 @@
+# Xilinx CORE Generator 6.1.03i
+# Username = Administrateur
+# COREGenPath = D:\xilinx\coregen
+# ProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\portserie
+# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\portserie
+# OverwriteFiles = true
+# Core name: sfifo
+# Number of Primitives in design: 87
+# Number of CLBs used in design cannot be determined when there is no RPMed logic
+# Number of Slices used in design cannot be determined when there is no RPMed logic
+# Number of LUT sites used in design: 43
+# Number of LUTs used in design: 35
+# Number of REG used in design: 22
+# Number of SRL16s used in design: 8
+# Number of Distributed RAM primitives used in design: 0
+# Number of Block Memories used in design: 0
+# Number of Dedicated Multipliers used in design: 0
+# Number of HU_SETs used: 0
+#
+SET BusFormat = BusFormatAngleBracketNotRipped
+SET XilinxFamily = Spartan2
+SET OutputOption = OutputProducts
+SET FlowVendor = Foundation_iSE
+SET FormalVerification = None
+SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
+SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
+CSET data_width = 8
+CSET read_error_sense = Active_Low
+CSET read_error_flag = true
+CSET write_acknowledge_flag = true
+CSET write_error_flag = true
+CSET data_count = true
+CSET memory_type = Distributed_Memory
+CSET read_acknowledge_sense = Active_Low
+CSET component_name = sfifo
+CSET fifo_depth = 16
+CSET read_acknowledge_flag = true
+CSET data_count_width = 2
+CSET write_error_sense = Active_Low
+CSET write_acknowledge_sense = Active_Low
+GENERATE
diff --git a/2004/n/fpga/src/portserie/portserie/txmit.vhd b/2004/n/fpga/src/portserie/portserie/txmit.vhd
new file mode 100644
index 0000000..76bfbf8
--- /dev/null
+++ b/2004/n/fpga/src/portserie/portserie/txmit.vhd
@@ -0,0 +1,141 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+
+entity TXMIT is
+ port (
+ MCLKX16 : in std_logic;
+ WRITE : in std_logic;
+ RESET : in std_logic;
+ DATA : in std_logic_vector(7 downto 0);
+
+ TX : out std_logic;
+ TXRDY : out std_logic
+ );
+end TXMIT;
+
+architecture RTL of TXMIT is
+
+ signal WRITE1 : std_logic;
+ signal WRITE2 : std_logic;
+ signal TXDONE1 : std_logic;
+ signal TXDONE : std_logic;
+ signal THR : std_logic_vector(7 downto 0);
+ signal TSR : std_logic_vector(7 downto 0);
+ signal TAG1 : std_logic;
+ signal TAG2 : std_logic;
+ constant PARITYMODE : std_logic :='1';
+ signal TXPARITY : std_logic;
+ signal TXCLK : std_logic;
+ signal PARITYCYCLE : std_logic;
+ signal TXDATARDY : std_logic;
+ signal CNT : std_logic_vector(2 downto 0);
+
+
+begin
+
+ -- Paritycycle = 1 on next to last cycle, this means when tsr[1] gets tag2.
+
+ PARITYCYCLE <= TSR(1) and not (TAG2 or TAG1 or TSR(7) or TSR(6) or TSR(5)
+ or TSR(4) or TSR(3) or TSR(2));
+
+
+ -- txdone = 1 when done shifting, this means when tx gets tag2.
+
+ TXDONE <= not (TAG2 or TAG1 or TSR(7) or TSR(6) or TSR(5) or TSR(4) or TSR(3)
+ or TSR(2) or TSR(1) or TSR(0));
+
+
+-- *** AJOUT ***
+ -- Ready for new date to be written, when no data is in transmit hold register.
+-- (ajout :) et quand la transmission est finie !
+
+ TXRDY <= TXDONE and not TXDATARDY;
+
+
+ -- Latch data[7:0] into the transmit hold register at posedge of write.
+
+ THR_WRITE : process (RESET, WRITE)
+ begin
+ if (RESET = '1') then
+ THR <= "00000000";
+ elsif (WRITE'event and WRITE = '1') then
+ THR <= DATA;
+ end if;
+ end process;
+
+
+ -- Toggle txclk every 8 counts, which divides the clock by 16, to generate the baud clock
+
+ BAUD_CLOCK_GEN : process (MCLKX16, RESET)
+ begin
+ if (RESET = '1') then
+ TXCLK <= '0';
+ CNT <= "000";
+ elsif (MCLKX16'event and MCLKX16 = '1') then
+ if (CNT = "000") then
+ TXCLK <= not TXCLK;
+ end if;
+ CNT <= CNT + 1;
+ end if;
+ end process;
+
+
+ SHIFT_OUT : process (TXCLK, RESET)
+ begin
+ -- idle_reset;
+ if (RESET = '1') then
+ TSR <= (others => '0');
+ TAG2 <= '0';
+ TAG1 <= '0';
+ TXPARITY <= PARITYMODE;
+ TX <= '1';
+ elsif (TXCLK'event and TXCLK = '1') then
+ if (TXDONE = '1' and TXDATARDY = '1') then
+ -- load_data;
+ TSR <= THR;
+ TAG2 <= '1';
+ TAG1 <= '1';
+ TXPARITY <= PARITYMODE;
+ TX <= '0';
+ else
+ -- shift_data;
+ TSR <= '0'&tsr(7 downto 1);
+ TSR(7) <= TAG1;
+ TAG1 <= TAG2;
+ TAG2 <= '0';
+ TXPARITY <= TXPARITY xor TSR(0);
+
+ if (TXDONE = '1') then
+ TX <= '1';
+ elsif (PARITYCYCLE = '1') then
+ TX <= TXPARITY;
+ else
+ TX <= TSR(0);
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ process (MCLKX16, RESET)
+ begin
+ if (RESET = '1') then
+ TXDATARDY <= '0';
+ WRITE2 <= '1';
+ WRITE1 <= '1';
+ TXDONE1 <= '1';
+ elsif (MCLKX16'event and MCLKX16 = '1') then
+ if (WRITE1 = '1' and WRITE2 = '0') then
+ TXDATARDY <= '1';
+ elsif (TXDONE = '0' and TXDONE1 = '1') then
+ TXDATARDY <= '0';
+ end if;
+ WRITE2 <= WRITE1;
+ WRITE1 <= WRITE;
+ TXDONE1 <= TXDONE;
+ end if;
+ end process;
+
+end RTL;
+
diff --git a/2004/n/fpga/src/portserie/portserie/txserie.vhd b/2004/n/fpga/src/portserie/portserie/txserie.vhd
new file mode 100644
index 0000000..b1ceb53
--- /dev/null
+++ b/2004/n/fpga/src/portserie/portserie/txserie.vhd
@@ -0,0 +1,232 @@
+-- txserie.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+
+-- -------------------------------------------
+-- Port série TX pour le fpga robot
+-- -------------------------------------------
+--
+-- * Prend 3 adresses mémoire :
+-- 0 - Txdata
+-- 1 - Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
+-- 2 - Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
+-- * Mettre le bit On/Off à 1 pour activer la transmission
+-- * Chaque écriture dans txdata charge la donnée dans la fifo
+-- * Dès que le registre à décalage est vide, il enlève le dernier élément de
+-- la fifo et le transmet
+-- * Deux bits de stop
+-- * Quand la fifo est pleine, met le flag Full/Int à 1 et génère une
+-- interruption. Il faut alors mettre à 0 le bit IntEn, qui sera remis à 1 à
+-- la prochaine écriture dans la fifo
+-- * On peut lire l'état de la pile dans le registre de flags
+-- * On peut vider la pile en mettant Purge à 1
+-- * Baudrate disponible :
+-- BdR1/0 ! Baudrate
+-- 00 ! 9600
+-- 01 ! 19200
+-- 10 ! 57600
+-- 11 ! 115200
+
+
+-- librairies
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library unisim;
+use unisim.vcomponents.all;
+
+use work.nono_const.all;
+
+-- **** entité ****
+entity txserie is
+ port (
+ rst : in std_logic;
+ bus_clk : in std_logic;
+ rw : in std_logic; -- read (0) / write (1)
+ bus_data : inout T_DATA:=(others => 'Z');
+ clk: in std_logic;
+ txout: out std_logic;
+ minIRQ: out std_logic;
+ csData : in std_logic;
+ csConfig : in std_logic;
+ csFlag : in std_logic
+ );
+end txserie;
+
+-- **** architecture RTL ****
+architecture rtl of txserie is
+-- composants
+component clockgene
+ port(
+ rst: in std_logic;
+ ckin: in std_logic;
+ ckout: out std_logic;
+ param: in std_logic_vector(1 downto 0)
+ );
+end component;
+
+component regIO
+ port(
+ cs: in std_logic;
+ bus_data: inout T_DATA;
+ input: in T_DATA;
+ output: out T_DATA;
+ rw: in std_logic;
+ load: in std_logic;
+ ck: in std_logic;
+ rst: in std_logic);
+end component;
+
+component fifodriver
+ port(
+ clk: in std_logic;
+ rst: in std_logic;
+ readreq: in std_logic;
+ writereq: in std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ dready: out std_logic;
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0));
+END COMPONENT;
+
+component TXMIT
+ port (
+ MCLKX16 : in std_logic;
+ WRITE : in std_logic;
+ RESET : in std_logic;
+ DATA : in std_logic_vector(7 downto 0);
+ TX : out std_logic;
+ TXRDY : out std_logic);
+end component;
+
+
+-- signaux
+signal fifoEmpty: std_logic;
+signal fifoFull: std_logic;
+signal fifoLevel: std_logic_vector(1 downto 0);
+signal fifopurge: std_logic:='0';
+signal fifockin: std_logic;
+signal fifockout: std_logic;
+
+signal txck: std_logic;
+signal geneck:std_logic;
+
+signal txload: std_logic:='0';
+signal loadingtx: std_logic:='0';
+
+signal confreg: T_DATA:="00000000";
+signal flagreg: T_DATA:="00000000";
+signal inter_data: T_DATA;
+signal inter_fifo_bus: T_DATA;
+signal txready: std_logic:='1';
+signal fifodready :std_logic;
+signal state:integer:=1;
+signal state_next:integer:=1;
+signal state_txload:integer:=0;
+
+signal dummy : T_DATA :=(others =>'0');
+signal un: std_logic :='1';
+
+
+-- description de l'architecture
+begin
+CLOCK1 : clockgene port map(
+ rst => rst,
+ ckin=>geneck,
+ ckout=>txck,
+ param=>confreg(1 downto 0));
+
+FIFO1: fifodriver port map(
+ clk => clk,
+ rst => fifopurge,
+ readreq => fifockout,
+ writereq => fifockin,
+ din => bus_data,
+ dout => inter_data,
+ dready => fifodready,
+ full => fifoFull,
+ empty => fifoEmpty,
+ data_count => fifoLevel(1 downto 0));
+
+TX1 : TXMIT port map(
+ MCLKX16 => txck,
+ WRITE => txload,
+ RESET => rst,
+ DATA => inter_data,
+ TX => txout,
+ TXRDY => txready);
+
+-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
+RCONF : regIO port map(
+ cs=>csConfig,
+ bus_data=>bus_data,
+ input=>dummy,
+ output=>confreg,
+ rw=>rw,
+ load=>dummy(0),
+ ck=>bus_clk,
+ rst=>rst);
+
+-- Flag : (x ! x ! x ! x ! Empty ! Full ! FLI1 ! FLI0 )
+RFLAG : regIO port map(
+ cs=>csFlag,
+ bus_data=>bus_data,
+ input=>flagreg,
+ output=>open,
+ rw=>rw,
+ load=>un,
+ ck=>bus_clk,
+ rst=>rst);
+
+
+-- signaux
+
+-- config
+geneck <= (confreg(4) and clk); -- On/Off et masterck
+fifopurge <= '1' when (rst='1') else confreg(3); -- reset or purge
+
+-- flags
+flagreg(1 downto 0)<=fifoLevel(1 downto 0);
+flagreg(2)<=fifoFull;
+flagreg(3)<=fifoEmpty;
+
+-- irq
+minirq<=fifoFull and confreg(2); --fifo full AND Int/En
+
+-- controle des flux
+fifockin <= (csData and bus_clk and not rw and not rst);
+fifockout <= (txready and not fifoEmpty);
+
+process(fifodready,txready)
+begin
+ txload <= '0';
+ case state_txload is
+ when 0 => if(txready='1') then
+ state_txload <= 3;
+ elsif(fifodready='1') then
+ state_txload <= 1;
+ end if;
+ when 1 => if(txready='1') then
+ state_txload <= 2;
+ txload <= '1';
+ end if;
+ when 2 => if(txready='0') then
+ state_txload <= 0;
+ else
+ txload <= '1';
+ end if;
+
+ when 3 => if(fifodready='1') then
+ state_txload <= 2;
+ txload <= '1';
+ end if;
+ when others => null;
+ end case;
+end process;
+
+
+end rtl;
+