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authorgalmes2004-03-04 10:26:52 +0000
committergalmes2004-03-04 10:26:52 +0000
commit4988d00048a69ed9a11da864a9a6e93acd6debca (patch)
tree50c7883e7b616af17e46794d4fb766371db9e313 /2004/n/fpga/src
parentd20e1be6c4dc816cfb96a2fc5335144967139859 (diff)
Première version qui marche en partie du module conserv
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/interrupt/bch_conserv.vhd16
-rw-r--r--2004/n/fpga/src/interrupt/conserv.vhd57
2 files changed, 30 insertions, 43 deletions
diff --git a/2004/n/fpga/src/interrupt/bch_conserv.vhd b/2004/n/fpga/src/interrupt/bch_conserv.vhd
index e99bf5e..85f1222 100644
--- a/2004/n/fpga/src/interrupt/bch_conserv.vhd
+++ b/2004/n/fpga/src/interrupt/bch_conserv.vhd
@@ -22,8 +22,7 @@ architecture sim1 of bch_conserv is
clk : in std_logic;
rst : in std_logic;
data_in : in T_DATA;
- data_out : out T_DATA;
- it_detected : out std_logic
+ data_out : out T_DATA
);
end component;
@@ -32,26 +31,25 @@ architecture sim1 of bch_conserv is
signal rst : std_logic;
signal data_in : T_DATA;
signal data_out : T_DATA;
- signal it_detected : std_logic;
begin
U1 : conserv port map (
clk => clk,
rst => rst,
data_in => data_in,
- data_out => data_out,
- it_detected => it_detected
+ data_out => data_out
);
clk <= not clk after CK_PERIOD/2;
rst <= '1',
'0' after CK_PERIOD,
- '1' after 5*CK_PERIOD,
- '0' after 7*CK_PERIOD;
- data_in <= x"02",
+ '1' after 7*CK_PERIOD,
+ '0' after 8*CK_PERIOD;
+ data_in <= x"01",
x"00" after 2*CK_PERIOD,
x"08" after 5*CK_PERIOD,
- x"01" after 7*CK_PERIOD;
+ x"01" after 7*CK_PERIOD,
+ x"00" after 9*CK_PERIOD;
--x"03" after 5*CK_PERIOD;
end sim1;
diff --git a/2004/n/fpga/src/interrupt/conserv.vhd b/2004/n/fpga/src/interrupt/conserv.vhd
index 285c363..f739f96 100644
--- a/2004/n/fpga/src/interrupt/conserv.vhd
+++ b/2004/n/fpga/src/interrupt/conserv.vhd
@@ -7,8 +7,8 @@
library ieee;
use ieee.std_logic_1164.all;
---use ieee.std_logic_arith.all;
---use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
use work.isa_const.all;
use work.nono_const.all;
@@ -19,7 +19,7 @@ entity conserv is
clk : in std_logic;
rst : in std_logic;
data_in : in T_DATA;
- data_out : out T_DATA;
+ data_out : out T_DATA
);
end entity;
@@ -27,14 +27,14 @@ architecture RTL of conserv is
-- Signal interne
-- registres à décalage pour compter 2 cycles.
- signal reg_dec0 : std_logic_vector (2 downto 0);
- signal reg_dec1 : std_logic_vector (2 downto 0);
- signal reg_dec2 : std_logic_vector (2 downto 0);
- signal reg_dec3 : std_logic_vector (2 downto 0);
- signal reg_dec4 : std_logic_vector (2 downto 0);
- signal reg_dec5 : std_logic_vector (2 downto 0);
- signal reg_dec6 : std_logic_vector (2 downto 0);
- signal reg_dec7 : std_logic_vector (2 downto 0);
+ signal cycle0 : std_logic_vector (1 downto 0);
+-- signal reg_dec 1 : std_logic_vector (2 downto 0);
+-- signal reg_dec 2 : std_logic_vector (2 downto 0);
+-- signal reg_dec 3 : std_logic_vector (2 downto 0);
+-- signal reg_dec 4 : std_logic_vector (2 downto 0);
+-- signal reg_dec 5 : std_logic_vector (2 downto 0);
+-- signal reg_dec 6 : std_logic_vector (2 downto 0);
+-- signal reg_dec 7 : std_logic_vector (2 downto 0);
begin
-- process séquentiel
@@ -42,37 +42,26 @@ begin
begin
if (rst = '1') then
data_out <= x"00";
--- reg_dec0 <= "000";
--- reg_dec1 <= "000";
--- reg_dec2 <= "000";
--- reg_dec3 <= "000";
--- reg_dec4 <= "000";
--- reg_dec5 <= "000";
--- reg_dec6 <= "000";
--- reg_dec7 <= "000";
+ cycle0 <= "00";
+
+ -- TODO : Ne peut-on pas faire en concurentiel ? Là, ne vat-il pas y
+ -- avoir un retard entre data_out(0) et data_out(7) si on les met en
+ -- séquentiel ?
elsif (clk'event and clk = '1') then
- --
- if (cycle = "SS") then -- TODO
- cycle <= "00";
+ -- Remise à zéro.
+ if (cycle0 = "10") then
+ cycle0 <= "00";
+ data_out(0) <= '0';
end if;
--
- if (data_in /= x"00") then
-
- state_p <= data_in;
-
- if (cycle = "01") then
- cycle <= cycle + 1; -- TODO : vérifier que valable.
- if (data_out /= state_p) then
- data_out <= state_p;
- end if;
- end if;
+ if (data_in(0) /= '0' or cycle0 = "01") then
+ cycle0 <= cycle0 + "01"; -- TODO : vérifier que valable.
+ data_out(0) <= '1';
end if;
-
end if;
end process;
-- process combinatoire.
- data_out <=
end RTL;