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authorgalmes2004-03-12 15:37:15 +0000
committergalmes2004-03-12 15:37:15 +0000
commit0633b192515a68393c0adec67b9c79d7d0de6988 (patch)
tree2e3ce9e43965f3b998f92d1794a92c055e1120b8 /2004/n/fpga/src
parent6c1e42f741e1b0d599cb5a9c96165ce4e8d10422 (diff)
- Dans les fichiers .vhd : Changement d'un nom cs_reg_read_output en
cs_read_output. - Ajout du fig de l'architecture physique pour les gpio
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/gpio/bch_gpio.vhd30
-rw-r--r--2004/n/fpga/src/gpio/gpio.vhd8
-rw-r--r--2004/n/fpga/src/gpio/gpio_it_detect.vhd2
-rw-r--r--2004/n/fpga/src/packages/isa_const.vhd4
4 files changed, 22 insertions, 22 deletions
diff --git a/2004/n/fpga/src/gpio/bch_gpio.vhd b/2004/n/fpga/src/gpio/bch_gpio.vhd
index bf142e8..12939c8 100644
--- a/2004/n/fpga/src/gpio/bch_gpio.vhd
+++ b/2004/n/fpga/src/gpio/bch_gpio.vhd
@@ -29,10 +29,10 @@ architecture sim1 of bch_gpio is
bus_data : inout T_DATA;
io_output : inout T_DATA;
-- chip select
- cs_reg_data_write : in std_logic;
+ cs_reg_data : in std_logic;
cs_reg_direction : in std_logic;
cs_reg_it_mask : in std_logic;
- cs_reg_read_output : in std_logic
+ cs_read_output : in std_logic
);
end component;
@@ -45,10 +45,10 @@ architecture sim1 of bch_gpio is
signal bus_data : T_DATA := x"00";
signal io_output : T_DATA;
-- chip select
- signal cs_reg_data_write : std_logic := '0';
+ signal cs_reg_data : std_logic := '0';
signal cs_reg_direction : std_logic := '0';
signal cs_reg_it_mask : std_logic := '0';
- signal cs_reg_read_output : std_logic := '0';
+ signal cs_read_output : std_logic := '0';
constant REG_DATA : std_logic_vector(1 downto 0) := "00";
constant REG_DIRECTION : std_logic_vector(1 downto 0) := "01";
@@ -68,10 +68,10 @@ begin
interrupt => interrupt,
bus_data => bus_data,
io_output => io_output,
- cs_reg_read_output => cs_reg_read_output,
+ cs_read_output => cs_read_output,
cs_reg_it_mask => cs_reg_it_mask,
cs_reg_direction => cs_reg_direction,
- cs_reg_data_write => cs_reg_data_write
+ cs_reg_data => cs_reg_data
);
-- ---------------------------------
@@ -86,13 +86,13 @@ begin
procedure do_read (action : in std_logic_vector(1 downto 0)) is
begin
-- sélection du registre
- cs_reg_data_write <= '0';
+ cs_reg_data <= '0';
cs_reg_direction <= '0';
cs_reg_it_mask <= '0';
- cs_reg_read_output <= '0';
+ cs_read_output <= '0';
if (action = REG_DATA) then
- cs_reg_data_write <= '1';
+ cs_reg_data <= '1';
end if;
if (action = REG_DIRECTION) then
cs_reg_direction <= '1';
@@ -101,7 +101,7 @@ begin
cs_reg_it_mask <= '1';
end if;
if (action = READ_OUTPUT) then
- cs_reg_read_output <= '1';
+ cs_read_output <= '1';
end if;
-- on lit.
rw <= ISA_READ;
@@ -113,13 +113,13 @@ begin
T_DATA) is
begin
-- sélection du registre
- cs_reg_data_write <= '0';
+ cs_reg_data <= '0';
cs_reg_direction <= '0';
cs_reg_it_mask <= '0';
- cs_reg_read_output <= '0';
+ cs_read_output <= '0';
if (action = REG_DATA) then
- cs_reg_data_write <= '1';
+ cs_reg_data <= '1';
end if;
if (action = REG_DIRECTION) then
cs_reg_direction <= '1';
@@ -128,7 +128,7 @@ begin
cs_reg_it_mask <= '1';
end if;
if (action = READ_OUTPUT) then
- cs_reg_read_output <= '1';
+ cs_read_output <= '1';
end if;
-- On écrit.
rw <= ISA_WRITE;
@@ -152,7 +152,7 @@ begin
do_write (REG_IT, "11111000");
wait for (ISA_CK_PERIOD);
do_write (REG_DATA, x"01"); -- 3 bits poid faible : in.
--- cs_reg_data_write <= '0';
+-- cs_reg_data <= '0';
-- interruption sur les 5 bits de poid faible.
-- wait for (3*CK_PERIOD);
diff --git a/2004/n/fpga/src/gpio/gpio.vhd b/2004/n/fpga/src/gpio/gpio.vhd
index 88c1651..b85d5da 100644
--- a/2004/n/fpga/src/gpio/gpio.vhd
+++ b/2004/n/fpga/src/gpio/gpio.vhd
@@ -20,10 +20,10 @@ entity gpio is
bus_data : inout T_DATA;
io_output : inout T_DATA;
-- chip select
- cs_reg_data_write : in std_logic;
+ cs_reg_data : in std_logic;
cs_reg_direction : in std_logic;
cs_reg_it_mask : in std_logic;
- cs_reg_read_output : in std_logic
+ cs_read_output : in std_logic
);
end entity;
@@ -100,7 +100,7 @@ port map (
clk_i,
rst,
rw,
- cs_reg_data_write,
+ cs_reg_data,
bus_data,
bus_reg_data
);
@@ -119,7 +119,7 @@ port map (
--
read_output : tristate
port map (
- cs_reg_read_output,
+ cs_read_output,
io_output,
bus_data
);
diff --git a/2004/n/fpga/src/gpio/gpio_it_detect.vhd b/2004/n/fpga/src/gpio/gpio_it_detect.vhd
index 2e21970..003c00d 100644
--- a/2004/n/fpga/src/gpio/gpio_it_detect.vhd
+++ b/2004/n/fpga/src/gpio/gpio_it_detect.vhd
@@ -29,7 +29,7 @@ end entity;
architecture RTL of gpio_it_detect is
-- Constantes
- constant IT_ENABLE : std_logic := '1';
+ -- constant IT_ENABLE : std_logic := '1';
-- Signal interne
signal state_p : T_DATA; -- etat passe
diff --git a/2004/n/fpga/src/packages/isa_const.vhd b/2004/n/fpga/src/packages/isa_const.vhd
index 8db9836..88f558d 100644
--- a/2004/n/fpga/src/packages/isa_const.vhd
+++ b/2004/n/fpga/src/packages/isa_const.vhd
@@ -21,8 +21,8 @@ package isa_const is
constant ISA_CK_PERIOD : time := 50 ns;
-- Ligne RW : lecture et écriture
- constant ISA_READ : std_logic := '0';
- constant ISA_WRITE : std_logic := '1';
+ constant ISA_READ : std_logic := '1';
+ constant ISA_WRITE : std_logic := '0';
-- Comportement de la ligne IRQ.
constant IRQ_ON : std_logic := '0';