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authorgalmes2004-04-28 18:29:26 +0000
committergalmes2004-04-28 18:29:26 +0000
commit130cf2e254043f28b912413f651a543d581e872e (patch)
tree163b0ab873d97c04cd47a79bd63d7c66bdf9d024 /2004/n/fpga/src/servo/servo_nono.vhd
parentbfa75e6dcbe6ce7c5b99e877bf7c02d76e81066c (diff)
servo : les fichiers du bloc servo qui marche trop de bombe de balle. Il
faudra peut-être revoir les constantes à calibrer en fonction du servo.
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+-- servo_nono.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Fidèle GAFAN et Pierre-andré Galmes
+-- Bloc de génération de servo.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+use work.nono_const.all;
+use work.isa_const.all;
+use work.servo_const.all;
+
+-- ENTITY
+entity servo_nono is
+port(
+ rst : in std_logic;
+ clk : in std_logic;
+ rw : in std_logic;
+ cs : in std_logic;
+ bus_data : inout T_DATA;
+ outservo : out std_logic
+);
+end servo_nono;
+
+
+-- ARCHITECTURE
+architecture RTL of servo_nono is
+
+-- Registre.
+component reg_rw is
+port (
+ clk : in std_logic;
+ rst : in std_logic;
+ rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
+ enable : in std_logic;
+ data : inout T_DATA;
+ data_out : out T_DATA -- data courant
+);
+end component;
+
+-- todo : supprimer l'horloge du moule et le mettre sur la carte !
+-- Générateur d'horloge à 1us.
+component clk1us is
+port(
+ RST : in std_logic;
+ CLK : in std_logic; --40MHz
+ CLK1USOUT : out std_logic
+);
+end component;
+
+-- Convertisseur [0-255] vers un temps.
+component convert_servo is
+port(
+ data_in : in T_OCTET;
+ data_out : out T_DOUBLE_OCTET --duree pdt laql la sortie
+);
+end component;
+
+-- Générateur de servo.
+component servo_generator is
+port (
+ rst : in std_logic;
+ clk : in std_logic;
+ servo_in : in T_DOUBLE_OCTET;
+ servo_out : out std_logic
+);
+end component;
+
+
+--DECLARATION DES SIGNAUX LOCAUX
+signal clkdiv : std_logic;
+signal reg_out : T_OCTET;
+signal convert_out : T_DOUBLE_OCTET;
+
+
+begin
+-- Mapping DES SIGNAUX.
+
+--
+registre : reg_rw
+port map(
+ clk,
+ rst,
+ rw,
+ cs,
+ bus_data,
+ reg_out
+);
+
+--
+Clock_div : clk1us
+port map(
+ rst,
+ clk,
+ clkdiv
+);
+
+--
+convert_nono : convert_servo
+port map(
+ reg_out,
+ convert_out
+);
+
+--
+servo_gene : servo_generator
+port map(
+ rst,
+ clkdiv,
+ convert_out,
+ outservo
+);
+
+
+end RTL;