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authorprot2004-03-01 16:16:05 +0000
committerprot2004-03-01 16:16:05 +0000
commit16cbbd83d43093a12fbb18f0287fda5c286c28a7 (patch)
tree9fbd722678826f7502f099d0cc9dcffc9e0cfca6 /2004/n/fpga/src/registre/registre.vhd
parent76098ead389c3803b9d5b47c8f6e915e1123b03a (diff)
Modif du txserie pour adaptiation a la fifo coregen
// // // // a l'UART efrei
Diffstat (limited to '2004/n/fpga/src/registre/registre.vhd')
-rw-r--r--2004/n/fpga/src/registre/registre.vhd55
1 files changed, 29 insertions, 26 deletions
diff --git a/2004/n/fpga/src/registre/registre.vhd b/2004/n/fpga/src/registre/registre.vhd
index e0445fb..675eb83 100644
--- a/2004/n/fpga/src/registre/registre.vhd
+++ b/2004/n/fpga/src/registre/registre.vhd
@@ -30,7 +30,7 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity regIO is
- generic(adr : T_ADDRESS);
+ generic(adr : T_ADDRESS := "0000000001");
port(
bus_data: inout T_DATA;
bus_address: in T_ADDRESS;
@@ -48,37 +48,40 @@ architecture rtl of regIO is
signal REG : T_DATA :=(others => '0');
begin
- p_w:process(ck,load,input,rst)
- begin
- if(ck='1') then
- if(bus_address=adr) then
- if(rw='0') then
- if(load='0') then
- REG<=bus_data;
- end if;
- else -- RW=1 : la CM lit => on écrit sur le bus
- bus_data<=REG;
- end if;
- else
- bus_data<=(others => 'Z');
- end if;
- else
- bus_data<=(others => 'Z');
+ p_w:process(ck,rst,load,input)
+ begin
+
+ if( rst = '1') then
+ REG <= (others => '0');
+ bus_data <= (others => 'Z');
+
+ elsif(ck'event and ck='1') then
+ if(bus_address=adr) then
+ if(rw='0' and load='0') then
+ REG<=bus_data;
+ bus_data <= (others => 'Z');
+ elsif(rw='0' and load='1') then
+ bus_data <= (others => 'Z');
+ elsif(rw='1') then -- RW=1 : la CM lit => on écrit sur le bus
+ bus_data<=REG;
+ end if;
+ else
+ bus_data <= (others => 'Z');
+ end if;
end if;
+
+-- si la clock est à 0, alors le bus est forcément en Z
+ if(ck='0') then
+ bus_data <= (others => 'Z');
+ end if;
-- chargement : prioritaire sur l'écriture via le bus
if(load='1' and not(ck='1' and rw='1')) then
REG<=input;
end if;
-
--- reset : prioritaire sur tout
- if(rst'event and rst='1') then
- REG<=(others => '0');
- bus_data<=(others => 'Z');
- end if;
-
- end process p_w;
-
+ end process p_w;
+
+
-- p_load : process(load,input)
-- begin
-- if(load='1') then