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authorgalmes2004-04-17 12:30:33 +0000
committergalmes2004-04-17 12:30:33 +0000
commitbf43f96467369c8ce632a18766c04760ca233193 (patch)
treef23989e8291a27847069ee7ccf9e90b887dd35d7 /2004/n/fpga/src/pwm/pwm_generator.vhd
parent8b312363990e2df76a1085fa9120ea6467a88c1b (diff)
pwm : refit
Diffstat (limited to '2004/n/fpga/src/pwm/pwm_generator.vhd')
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diff --git a/2004/n/fpga/src/pwm/pwm_generator.vhd b/2004/n/fpga/src/pwm/pwm_generator.vhd
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+-------------------------------------------------------------------------------
+--pwm_generator.vhd
+--Eurobot 2004 : APB Team
+--Auteur : Fidèle GAFAN
+--Registre à décalage affichantles signaux PWM
+--
+
+-- Les commentaires ci-dessous ne sont plus trop valables.
+-- Maintenant, clock = 40MHz
+
+
+--REMARQUE(S):changer tccompt,q et valuecompt
+-- si CLK#32MHz et/ou qu'on modifie les valeurs de référence de T1
+-- et T2
+-- Tcmax = 20ms / 1us
+-- = 20161 cycles.
+
+-- Si DATACOMPT = 0, on veut que T2 vale 0,5ms donc on initialise Q à la
+-- valeur Q=0,5ms/1us=505.
+
+-- Si DATACOMPT=255,on veut que T2 vale 1,5ms donc on initialise Q à la
+-- valeur Q=1,5ms/1us=1515.
+
+-- Pour toute autre valeur de DATACOMPT comprise entre les deux
+-- précédentes et différentes de ces dernières,on initialise Q avec
+-- Q=(0,5ms/1us)+(DATACOMPT*min[((1,5ms-0,5ms)/1us)/(255-1)]
+
+------------------------------------------------rtl de la sortie pwm en fonction de tc
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+use work.nono_const.all;
+use work.pwm_const.all;
+
+--ENTITE
+entity pwm_generator is
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ pwm_in : in T_DOUBLE_OCTET;
+ pwm_out : out std_logic
+ );
+end entity;
+
+--ARCHITECTURE
+architecture RTL of pwm_generator is
+ signal compt : T_DOUBLE_OCTET;
+ signal reg : T_DOUBLE_OCTET;
+begin
+
+ process(rst, clk)
+ begin
+ if (rst = '1') then
+ compt <= x"0000";
+ reg <= x"0000";
+ pwm_out <= '0';
+ elsif (clk'event and clk = '1') then
+ compt <= compt + x"0001";
+ if (compt <= reg) then
+ pwm_out <= '1';
+ else
+ pwm_out <= '0';
+ if (compt = PWM_NB_CYCLE_20MS) then
+ compt <= x"0000";
+ reg <= pwm_in;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end RTL;