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authorprot2004-02-25 20:00:21 +0000
committerprot2004-02-25 20:00:21 +0000
commit7de0fd178d7b2dbccbf34cbffda38a1f4bdb4583 (patch)
tree622aface1b103ce9c470457eb2f8496217874cac /2004/n/fpga/src/fifo/fifobehav.vhd
parentc50aca8c4be2ef778eb634df7a530cde2ff23f39 (diff)
fifo comportementale
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+---------------------------------------------------------------------------
+-- --
+-- Module : fifoctlr_cc.vhd Last Update: 12/13/99 --
+-- --
+-- Description : FIFO controller top level. --
+-- Implements a 511x8 FIFO with common read/write clocks. --
+-- --
+-- The following VHDL code implements a 511x8 FIFO in a Spartan-II --
+-- device. The inputs are a Clock, a Read Enable, a Write Enable, --
+-- Write Data, and a FIFO_gsr signal as an initial reset. The outputs --
+-- are Read Data, Full, Empty, and the FIFOcount outputs, which --
+-- indicate roughly how full the FIFO is. --
+-- --
+---------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity fifobehav is
+ port (clock_in: IN std_logic;
+ read_enable_in: IN std_logic;
+ write_enable_in: IN std_logic;
+ write_data_in: IN std_logic_vector(7 downto 0);
+ fifo_gsr_in: IN std_logic;
+ read_data_out: OUT std_logic_vector(7 downto 0);
+ full_out: OUT std_logic;
+ empty_out: OUT std_logic;
+ fifocount_out: OUT std_logic_vector(3 downto 0));
+END fifobehav;
+
+
+architecture behav of fifobehav is
+signal full:std_logic:='0';
+
+begin
+full_out<=full;
+
+process(clock_in)
+variable contenu:std_logic_vector(7 downto 0);
+variable fullindicator:std_logic:='0';
+
+begin
+ if(read_enable_in='1') then
+ if (fullindicator='0') then
+ read_data_out<="00000000";
+ else
+ read_data_out<=contenu;
+ fullindicator:='0';
+ full<='0';
+ end if;
+ else
+ read_data_out<="00000000";
+ end if;
+
+ if(write_enable_in='1') then
+ if(fullindicator='0') then
+ contenu:=write_data_in;
+ fullindicator:='1';
+ full<='1';
+ end if;
+ end if;
+
+ if(fifo_gsr_in='1') then
+ contenu:="00000000";
+ fullindicator:='0';
+ full<='0';
+ end if;
+end process;
+end behav;
+