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authorgalmes2004-04-28 18:32:40 +0000
committergalmes2004-04-28 18:32:40 +0000
commit944910842767a26c9d2dac92f4acd094576579f1 (patch)
treec8cbd17dfee78f3bb4062534a9bb431dc2aaafb0 /2004/n/fpga/src/clk1us/clk1us.vhd
parent130cf2e254043f28b912413f651a543d581e872e (diff)
clk1us : bloc qui génère une horloge à 1us.
Diffstat (limited to '2004/n/fpga/src/clk1us/clk1us.vhd')
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+-- clk1us.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Fidle GAFAN et Pierre-Andr Galmes
+-- Module gnrateur d'horloge 1us-priodique
+--
+-- On fera attention que cette horloge repose sur la fq d'horloge du FPGA.
+-- Pour changer cette frquence, aller voir nono_const : FREQ_CLK.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+use work.nono_const.all;
+
+--ENTITY
+entity clk1us is
+ port (
+ RST : in std_logic;
+ CLK : in std_logic; --40MHz
+ CLK1USOUT : out std_logic
+ );
+end entity;
+
+--ARCHITECTURE
+architecture RTL of clk1us is
+ -- nombres de cycles de clk necessaires pour 1us incrmente.
+ signal compt: T_OCTET;
+begin
+ process(RST,CLK)
+ begin
+ if (RST = '1') then
+ CLK1USOUT <= '0';
+ compt <= x"00";
+ elsif (CLK'event and CLK = '1') then
+ compt <= compt + x"01";
+ if (compt = x"00") then -- 30
+ CLK1USOUT <= '1';
+ else
+ CLK1USOUT <= '0';
+ if (compt = (FREQ_CLK - x"01")) then
+ compt <= x"00"; -- 30
+ end if;
+ end if;
+ end if;
+ end process;
+end RTL;