/** @file @ingroup STM32F1xx @brief libopencm3 STM32F1xx Reset and Clock Control @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \ @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @author @htmlonly © @endhtmlonly 2010 Thomas Otto @date 18 May 2012 This library supports the Reset and Clock Control System in the STM32F1xx series of ARM Cortex Microcontrollers by ST Microelectronics. Clock settings and resets for many peripherals are given here rather than in the peripheral library. The library also provides a number of common configurations for the processor system clock. Not all possible configurations are given here. @bugs None known LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /** Default ppre1 peripheral clock frequency after reset. */ u32 rcc_ppre1_frequency = 8000000; /** Default ppre2 peripheral clock frequency after reset. */ u32 rcc_ppre2_frequency = 8000000; //----------------------------------------------------------------------------- /** @brief RCC Clear the Oscillator Ready Interrupt Clear the interrupt flag that was set when a clock oscillator became ready to use. @param[in] enum ::osc_t. Oscillator ID */ void rcc_osc_ready_int_clear(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYC; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYC; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYC; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYC; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYC; break; } } void rcc_osc_ready_int_enable(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYIE; break; } } void rcc_osc_ready_int_disable(osc_t osc) { switch (osc) { case PLL: RCC_CIR &= ~RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR &= ~RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR &= ~RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR &= ~RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR &= ~RCC_CIR_LSIRDYIE; break; } } int rcc_osc_ready_int_flag(osc_t osc) { switch (osc) { case PLL: return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); break; case HSE: return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); break; case HSI: return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); break; case LSE: return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); break; case LSI: return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); break; } /* Shouldn't be reached. */ return -1; } void rcc_css_int_clear(void) { RCC_CIR |= RCC_CIR_CSSC; } int rcc_css_int_flag(void) { return ((RCC_CIR & RCC_CIR_CSSF) != 0); } void rcc_wait_for_osc_ready(osc_t osc) { switch (osc) { case PLL: while ((RCC_CR & RCC_CR_PLLRDY) == 0); break; case HSE: while ((RCC_CR & RCC_CR_HSERDY) == 0); break; case HSI: while ((RCC_CR & RCC_CR_HSIRDY) == 0); break; case LSE: while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); break; case LSI: while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); break; } } void rcc_osc_on(osc_t osc) { switch (osc) { case PLL: RCC_CR |= RCC_CR_PLLON; break; case HSE: RCC_CR |= RCC_CR_HSEON; break; case HSI: RCC_CR |= RCC_CR_HSION; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEON; break; case LSI: RCC_CSR |= RCC_CSR_LSION; break; } } void rcc_osc_off(osc_t osc) { switch (osc) { case PLL: RCC_CR &= ~RCC_CR_PLLON; break; case HSE: RCC_CR &= ~RCC_CR_HSEON; break; case HSI: RCC_CR &= ~RCC_CR_HSION; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEON; break; case LSI: RCC_CSR &= ~RCC_CSR_LSION; break; } } void rcc_css_enable(void) { RCC_CR |= RCC_CR_CSSON; } void rcc_css_disable(void) { RCC_CR &= ~RCC_CR_CSSON; } void rcc_osc_bypass_enable(osc_t osc) { switch (osc) { case HSE: RCC_CR |= RCC_CR_HSEBYP; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEBYP; break; case PLL: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_osc_bypass_disable(osc_t osc) { switch (osc) { case HSE: RCC_CR &= ~RCC_CR_HSEBYP; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEBYP; break; case PLL: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } //----------------------------------------------------------------------------- /** @brief RCC Enable a peripheral clock. Enable the clock on a particular peripheral. Several peripherals could be enabled simultaneously if they are controlled by the same register. @param[in] Unsigned int32 *reg. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1RENR or RCC_APB2RENR) @param[in] Unsigned int32 en. OR of all enables to be set @li If register is RCC_AHBER, from @ref rcc_ahbenr_en @li If register is RCC_APB1RENR, from @ref rcc_apb1enr_en @li If register is RCC_APB2RENR, from @ref rcc_apb2enr_en */ void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) { *reg |= en; } void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en) { *reg &= ~en; } void rcc_peripheral_reset(volatile u32 *reg, u32 reset) { *reg |= reset; } void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset) { *reg &= ~clear_reset; } void rcc_set_sysclk_source(u32 clk) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 1) | (1 << 0)); RCC_CFGR = (reg32 | clk); } void rcc_set_pll_multiplication_factor(u32 mul) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18)); RCC_CFGR = (reg32 | (mul << 18)); } void rcc_set_pll_source(u32 pllsrc) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~(1 << 16); RCC_CFGR = (reg32 | (pllsrc << 16)); } void rcc_set_pllxtpre(u32 pllxtpre) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~(1 << 17); RCC_CFGR = (reg32 | (pllxtpre << 17)); } void rcc_set_adcpre(u32 adcpre) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 14) | (1 << 15)); RCC_CFGR = (reg32 | (adcpre << 14)); } void rcc_set_ppre2(u32 ppre2) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13)); RCC_CFGR = (reg32 | (ppre2 << 11)); } void rcc_set_ppre1(u32 ppre1) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10)); RCC_CFGR = (reg32 | (ppre1 << 8)); } void rcc_set_hpre(u32 hpre) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); RCC_CFGR = (reg32 | (hpre << 4)); } void rcc_set_usbpre(u32 usbpre) { u32 reg32; reg32 = RCC_CFGR; reg32 &= ~(1 << 22); RCC_CFGR = (reg32 | (usbpre << 22)); } u32 rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ return ((RCC_CFGR & 0x000c) >> 2); } /* * These functions are setting up the whole clock system for the most common * input clock and output clock configurations. */ void rcc_clock_setup_in_hsi_out_64mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */ /* * Sysclk is running with 64MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_LATENCY_2WS); /* * Set the PLL multiplication factor to 16. * 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL16); /* Select HSI/2 as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 32000000; rcc_ppre2_frequency = 64000000; } void rcc_clock_setup_in_hsi_out_48mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 48MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 6MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 24MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 48MHz Max. 72MHz */ rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* Set. 48MHz Max. 48MHz */ /* * Sysclk runs with 48MHz -> 1 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_LATENCY_1WS); /* * Set the PLL multiplication factor to 12. * 8MHz (internal) * 12 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 48MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL12); /* Select HSI/2 as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 24000000; rcc_ppre2_frequency = 48000000; } void rcc_clock_setup_in_hsi_out_24mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 24MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 12MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */ /* * Sysclk is (will be) running with 24MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_LATENCY_0WS); /* * Set the PLL multiplication factor to 6. * 8MHz (internal) * 6 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 24MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6); /* Select HSI/2 as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 24000000; rcc_ppre2_frequency = 24000000; } void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 8MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */ /* * Sysclk runs with 24MHz -> 0 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_LATENCY_0WS); /* * Set the PLL multiplication factor to 3. * 8MHz (external) * 3 (multiplier) = 24MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL3); /* Select HSE as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * External frequency undivided before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 24000000; rcc_ppre2_frequency = 24000000; } void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 8MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. * 8MHz (external) * 9 (multiplier) = 72MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); /* Select HSE as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * External frequency undivided before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 36000000; rcc_ppre2_frequency = 72000000; } void rcc_clock_setup_in_hse_12mhz_out_72mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 16MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. * 12MHz (external) * 6 (multiplier) / 1 (PLLXTPRE_HSE_CLK) = 72MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6); /* Select HSI as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * Divide external frequency by 2 before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 36000000; rcc_ppre2_frequency = 72000000; } void rcc_clock_setup_in_hse_16mhz_out_72mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 16MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. * 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); /* Select HSI as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * Divide external frequency by 2 before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 36000000; rcc_ppre2_frequency = 72000000; } void rcc_backupdomain_reset(void) { /* Set the backup domain software reset. */ RCC_BDCR |= RCC_BDCR_BDRST; /* Clear the backup domain software reset. */ RCC_BDCR &= ~RCC_BDCR_BDRST; }