/* * This file is part of the libopenstm32 project. * * Copyright (C) 2009 Uwe Hermann * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef LIBOPENSTM32_MEMORYMAP_H #define LIBOPENSTM32_MEMORYMAP_H /* Memory map for all busses */ #define PERIPH_BASE 0x40000000 #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) #define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000) /* Register boundary addresses */ /* APB1 */ #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) #define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) #define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) #define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) #define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) #define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) #define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) #define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) #define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) /* APB2 */ #define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) #define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) #define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800) #define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00) #define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000) #define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400) #define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800) #define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00) #define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000) #define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) #define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800) #define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) #define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) #define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) #define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) /* AHB */ #define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) #define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) #define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) #define RCC_BASE (PERIPH_BASE_AHB + 0x09000) #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) #define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) #define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) #define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0x10000000) #endif