From e831f4db51f9bd60654a38fd779cf1bf9613ee1a Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Thu, 6 Dec 2012 03:09:33 +1030 Subject: I2C to common area F2/4 has now I2C3 included --- lib/stm32/common/i2c_common_all.c | 411 +++++++++++++++++++++++++++++++++++++ lib/stm32/f1/Makefile | 2 +- lib/stm32/f1/i2c.c | 28 +++ lib/stm32/f2/Makefile | 2 +- lib/stm32/f2/i2c.c | 28 +++ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/i2c.c | 28 +++ lib/stm32/i2c.c | 415 -------------------------------------- lib/stm32/l1/Makefile | 3 +- lib/stm32/l1/i2c.c | 28 +++ 10 files changed, 528 insertions(+), 419 deletions(-) create mode 100644 lib/stm32/common/i2c_common_all.c create mode 100644 lib/stm32/f1/i2c.c create mode 100644 lib/stm32/f2/i2c.c create mode 100644 lib/stm32/f4/i2c.c delete mode 100644 lib/stm32/i2c.c create mode 100644 lib/stm32/l1/i2c.c (limited to 'lib') diff --git a/lib/stm32/common/i2c_common_all.c b/lib/stm32/common/i2c_common_all.c new file mode 100644 index 0000000..28ae199 --- /dev/null +++ b/lib/stm32/common/i2c_common_all.c @@ -0,0 +1,411 @@ +/** @addtogroup i2c_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 15 October 2012 + +Devices can have up to two I2C peripherals. The peripherals support SMBus and +PMBus variants. + +A peripheral begins after reset in Slave mode. To become a Master a start +condition must be generated. The peripheral will remain in Master mode unless +a multimaster contention is lost or a stop condition is generated. + +@todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status +register access, Error conditions + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Reset. + +The I2C peripheral and all its associated configuration registers are placed in the +reset condition. The reset is effected via the RCC peripheral reset system. + +@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. +*/ + +void i2c_reset(u32 i2c) +{ + switch (i2c) { + case I2C1: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); + break; + case I2C2: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Peripheral Enable. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_peripheral_enable(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_PE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Peripheral Disable. + +This must not be reset while in Master mode until a communication has finished. +In Slave mode, the peripheral is disabled only after communication has ended. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_peripheral_disable(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_PE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Start Condition. + +If in Master mode this will cause a restart condition to occur at the end of the +current transmission. If in Slave mode, this will initiate a start condition +when the current bus activity is completed. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_send_start(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_START; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Stop Condition. + +After the current byte transfer this will initiate a stop condition if in Master +mode, or simply release the bus if in Slave mode. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_send_stop(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_STOP; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Clear Stop Flag. + +Clear the "Send Stop" flag in the I2C config register + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_clear_stop(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_STOP; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the 7 bit Slave Address for the Peripheral. + +This sets an address for Slave mode operation, in 7 bit form. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int8. Slave address 0...127. +*/ + +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) +{ + I2C_OAR1(i2c) = (u16)(slave << 1); + I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; + I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the 10 bit Slave Address for the Peripheral. + +This sets an address for Slave mode operation, in 10 bit form. + +@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int16. Slave address 0...1023. +*/ + +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) +{ + I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Fast Mode. + +Set the clock frequency to the high clock rate mode (up to 400kHz). The actual +clock frequency must be set with @ref i2c_set_clock_frequency + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_set_fast_mode(u32 i2c) +{ + I2C_CCR(i2c) |= I2C_CCR_FS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Standard Mode. + +Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual +clock frequency must be set with @ref i2c_set_clock_frequency + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_set_standard_mode(u32 i2c) +{ + I2C_CCR(i2c) &= ~I2C_CCR_FS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Peripheral Clock Frequency. + +Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that +this is not the I2C bus clock. This is set in conjunction with the Clock +Control register to generate the Master bus clock, see @ref i2c_set_ccr + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock. +*/ + +void i2c_set_clock_frequency(u32 i2c, u8 freq) +{ + u16 reg16; + reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ + reg16 |= freq; + I2C_CR2(i2c) = reg16; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Bus Clock Frequency. + +Set the bus clock frequency. This is a 12 bit number (0...4095) calculated +from the formulae given in the STM32F1 reference manual in the description +of the CCR field. It is a divisor of the peripheral clock frequency +@ref i2c_set_clock_frequency modified by the fast mode setting +@ref i2c_set_fast_mode + +@todo provide additional API assitance to set the clock, eg macros + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095. +*/ + +void i2c_set_ccr(u32 i2c, u16 freq) +{ + u16 reg16; + reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ + reg16 |= freq; + I2C_CCR(i2c) = reg16; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the Rise Time. + +Set the maximum rise time on the bus according to the I2C specification, as 1 +more than the specified rise time in peripheral clock cycles. This is a 6 bit +number. + +@todo provide additional APIP assistance. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] trise Unsigned int16. Rise Time Setting 0...63. +*/ + +void i2c_set_trise(u32 i2c, u16 trise) +{ + I2C_TRISE(i2c) = trise; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send the 7-bit Slave Address. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int16. Slave address 0...1023. +@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw. +*/ + +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) +{ + I2C_DR(i2c) = (u8)((slave << 1) | readwrite); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Data. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] data Unsigned int8. Byte to send. +*/ + +void i2c_send_data(u32 i2c, u8 data) +{ + I2C_DR(i2c) = data; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Get Data. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +uint8_t i2c_get_data(u32 i2c) +{ + return I2C_DR(i2c) & 0xff; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Enable Interrupt + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] interrupt Unsigned int32. Interrupt to enable. +*/ +void i2c_enable_interrupt(u32 i2c, u32 interrupt) +{ + I2C_CR2(i2c) |= interrupt; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Disable Interrupt + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] interrupt Unsigned int32. Interrupt to disable. +*/ +void i2c_disable_interrupt(u32 i2c, u32 interrupt) +{ + I2C_CR2(i2c) &= ~interrupt; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Enable ACK + +Enables acking of own 7/10 bit address +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_enable_ack(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_ACK; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Disable ACK + +Disables acking of own 7/10 bit address +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_disable_ack(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_ACK; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C NACK Next Byte + +Causes the I2C controller to NACK the reception of the next byte +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_nack_next(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_POS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C NACK Next Byte + +Causes the I2C controller to NACK the reception of the current byte + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_nack_current(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_POS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set clock duty cycle + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle. +*/ +void i2c_set_dutycycle(u32 i2c, u32 dutycycle) +{ + if (dutycycle == I2C_CCR_DUTY_DIV2) + I2C_CCR(i2c) &= ~I2C_CCR_DUTY; + else + I2C_CCR(i2c) |= I2C_CCR_DUTY; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Enable DMA + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_enable_dma(u32 i2c) +{ + I2C_CR2(i2c) |= I2C_CR2_DMAEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Disable DMA + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_disable_dma(u32 i2c) +{ + I2C_CR2(i2c) &= ~I2C_CR2_DMAEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set DMA last transfer + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_set_dma_last_transfer(u32 i2c) +{ + I2C_CR2(i2c) |= I2C_CR2_LAST; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Clear DMA last transfer + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_clear_dma_last_transfer(u32 i2c) +{ + I2C_CR2(i2c) &= ~I2C_CR2_LAST; +} + +/**@}*/ diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index e2c4284..93cc3cf 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -34,7 +34,7 @@ OBJS = rcc.o gpio.o usart.o adc.o flash.o \ timer.o usb_f107.o desig.o crc.o pwr.o \ usb_fx07_common.o \ gpio_common_all.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/i2c.c b/lib/stm32/f1/i2c.c new file mode 100644 index 0000000..2d86bf3 --- /dev/null +++ b/lib/stm32/f1/i2c.c @@ -0,0 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx I2C + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index d0b1ac8..9a21857 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -31,7 +31,7 @@ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o timer.o \ gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/i2c.c b/lib/stm32/f2/i2c.c new file mode 100644 index 0000000..f20a840 --- /dev/null +++ b/lib/stm32/f2/i2c.c @@ -0,0 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32F2xx + +@brief libopencm3 STM32F2xx I2C + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index dc7db87..7d02d55 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -34,7 +34,7 @@ OBJS = rcc.o gpio.o usart.o flash.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f4/i2c.c b/lib/stm32/f4/i2c.c new file mode 100644 index 0000000..3250faa --- /dev/null +++ b/lib/stm32/f4/i2c.c @@ -0,0 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx I2C + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/i2c.c b/lib/stm32/i2c.c deleted file mode 100644 index a67bece..0000000 --- a/lib/stm32/i2c.c +++ /dev/null @@ -1,415 +0,0 @@ -/** @defgroup i2c_file I2C - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxxx I2C - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies - -@date 15 October 2012 - -Devices can have up to two I2C peripherals. The peripherals support SMBus and -PMBus variants. - -A peripheral begins after reset in Slave mode. To become a Master a start -condition must be generated. The peripheral will remain in Master mode unless -a multimaster contention is lost or a stop condition is generated. - -@todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status -register access, Error conditions - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -/**@{*/ - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Reset. - -The I2C peripheral and all its associated configuration registers are placed in the -reset condition. The reset is effected via the RCC peripheral reset system. - -@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. -*/ - -void i2c_reset(u32 i2c) -{ - switch (i2c) { - case I2C1: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); - break; - case I2C2: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Peripheral Enable. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_peripheral_enable(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_PE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Peripheral Disable. - -This must not be reset while in Master mode until a communication has finished. -In Slave mode, the peripheral is disabled only after communication has ended. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_peripheral_disable(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_PE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Send Start Condition. - -If in Master mode this will cause a restart condition to occur at the end of the -current transmission. If in Slave mode, this will initiate a start condition -when the current bus activity is completed. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_send_start(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_START; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Send Stop Condition. - -After the current byte transfer this will initiate a stop condition if in Master -mode, or simply release the bus if in Slave mode. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_send_stop(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_STOP; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Clear Stop Flag. - -Clear the "Send Stop" flag in the I2C config register - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_clear_stop(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_STOP; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set the 7 bit Slave Address for the Peripheral. - -This sets an address for Slave mode operation, in 7 bit form. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] slave Unsigned int8. Slave address 0...127. -*/ - -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) -{ - I2C_OAR1(i2c) = (u16)(slave << 1); - I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; - I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set the 10 bit Slave Address for the Peripheral. - -This sets an address for Slave mode operation, in 10 bit form. - -@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] slave Unsigned int16. Slave address 0...1023. -*/ - -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) -{ - I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set Fast Mode. - -Set the clock frequency to the high clock rate mode (up to 400kHz). The actual -clock frequency must be set with @ref i2c_set_clock_frequency - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_set_fast_mode(u32 i2c) -{ - I2C_CCR(i2c) |= I2C_CCR_FS; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set Standard Mode. - -Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual -clock frequency must be set with @ref i2c_set_clock_frequency - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_set_standard_mode(u32 i2c) -{ - I2C_CCR(i2c) &= ~I2C_CCR_FS; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set Peripheral Clock Frequency. - -Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that -this is not the I2C bus clock. This is set in conjunction with the Clock -Control register to generate the Master bus clock, see @ref i2c_set_ccr - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock. -*/ - -void i2c_set_clock_frequency(u32 i2c, u8 freq) -{ - u16 reg16; - reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ - reg16 |= freq; - I2C_CR2(i2c) = reg16; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set Bus Clock Frequency. - -Set the bus clock frequency. This is a 12 bit number (0...4095) calculated -from the formulae given in the STM32F1 reference manual in the description -of the CCR field. It is a divisor of the peripheral clock frequency -@ref i2c_set_clock_frequency modified by the fast mode setting -@ref i2c_set_fast_mode - -@todo provide additional API assitance to set the clock, eg macros - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095. -*/ - -void i2c_set_ccr(u32 i2c, u16 freq) -{ - u16 reg16; - reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ - reg16 |= freq; - I2C_CCR(i2c) = reg16; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set the Rise Time. - -Set the maximum rise time on the bus according to the I2C specification, as 1 -more than the specified rise time in peripheral clock cycles. This is a 6 bit -number. - -@todo provide additional APIP assistance. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] trise Unsigned int16. Rise Time Setting 0...63. -*/ - -void i2c_set_trise(u32 i2c, u16 trise) -{ - I2C_TRISE(i2c) = trise; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Send the 7-bit Slave Address. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] slave Unsigned int16. Slave address 0...1023. -@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw. -*/ - -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) -{ - I2C_DR(i2c) = (u8)((slave << 1) | readwrite); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Send Data. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] data Unsigned int8. Byte to send. -*/ - -void i2c_send_data(u32 i2c, u8 data) -{ - I2C_DR(i2c) = data; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Get Data. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -uint8_t i2c_get_data(u32 i2c) -{ - return I2C_DR(i2c) & 0xff; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Enable Interrupt - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] interrupt Unsigned int32. Interrupt to enable. -*/ -void i2c_enable_interrupt(u32 i2c, u32 interrupt) -{ - I2C_CR2(i2c) |= interrupt; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Disable Interrupt - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] interrupt Unsigned int32. Interrupt to disable. -*/ -void i2c_disable_interrupt(u32 i2c, u32 interrupt) -{ - I2C_CR2(i2c) &= ~interrupt; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Enable ACK - -Enables acking of own 7/10 bit address -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_enable_ack(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_ACK; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Disable ACK - -Disables acking of own 7/10 bit address -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_disable_ack(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_ACK; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C NACK Next Byte - -Causes the I2C controller to NACK the reception of the next byte -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_nack_next(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_POS; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C NACK Next Byte - -Causes the I2C controller to NACK the reception of the current byte - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_nack_current(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_POS; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set clock duty cycle - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle. -*/ -void i2c_set_dutycycle(u32 i2c, u32 dutycycle) -{ - if (dutycycle == I2C_CCR_DUTY_DIV2) - I2C_CCR(i2c) &= ~I2C_CCR_DUTY; - else - I2C_CCR(i2c) |= I2C_CCR_DUTY; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Enable DMA - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_enable_dma(u32 i2c) -{ - I2C_CR2(i2c) |= I2C_CR2_DMAEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Disable DMA - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_disable_dma(u32 i2c) -{ - I2C_CR2(i2c) &= ~I2C_CR2_DMAEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set DMA last transfer - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_set_dma_last_transfer(u32 i2c) -{ - I2C_CR2(i2c) |= I2C_CR2_LAST; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Clear DMA last transfer - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_clear_dma_last_transfer(u32 i2c) -{ - I2C_CR2(i2c) &= ~I2C_CR2_LAST; -} - -/**@}*/ diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index c48f5b9..8578fe3 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -29,7 +29,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o -OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o usart_common_all.o iwdg_common_all.o +OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o +OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/i2c.c b/lib/stm32/l1/i2c.c new file mode 100644 index 0000000..7a6fe84 --- /dev/null +++ b/lib/stm32/l1/i2c.c @@ -0,0 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx I2C + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + -- cgit v1.2.3