From 5dce4172a8ce3c80b37f4b45706c3a6032e9c34d Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Wed, 25 Jan 2012 22:09:54 -0800 Subject: Fix bug with F4 clock settings, change HPRE to PPRE. --- lib/stm32/f4/rcc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index e10ef21..1a5d868 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -35,8 +35,8 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = .pllp = 2, .pllq = 5, .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_HPRE_DIV_4, - .ppre2 = RCC_CFGR_HPRE_DIV_2, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS, .apb1_frequency = 30000000, @@ -48,8 +48,8 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = .pllp = 2, .pllq = 7, .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_HPRE_DIV_4, - .ppre2 = RCC_CFGR_HPRE_DIV_2, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_5WS, .apb1_frequency = 42000000, .apb2_frequency = 84000000, -- cgit v1.2.3