From 584052c28cdfe5c383f13471deb891ba9438843a Mon Sep 17 00:00:00 2001 From: Daniel Serpell Date: Wed, 22 Aug 2012 00:05:09 -0400 Subject: Compile stm32-f4 library with floating point support. This enables hard-float in the compilation of library and examples for the stm32f40* chips. --- lib/stm32/f4/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 5760d29..881ef5d 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -24,7 +24,8 @@ PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ - -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \ + -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32F4 # ARFLAGS = rcsv ARFLAGS = rcs -- cgit v1.2.3 From e4819d3cd284e76339887a45598269dbe1479da7 Mon Sep 17 00:00:00 2001 From: Daniel Serpell Date: Wed, 22 Aug 2012 00:05:08 -0400 Subject: Enable floating-point coprocessor on reset. Always enable the floating-point coprocessor with full access on reset, allowing usage of hard-fp toolchains. --- lib/stm32/f4/vector.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'lib') diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c index 3429bfb..01b5e64 100644 --- a/lib/stm32/f4/vector.c +++ b/lib/stm32/f4/vector.c @@ -18,6 +18,8 @@ * along with this library. If not, see . */ +#include + #define WEAK __attribute__ ((weak)) /* Symbols exported by the linker script(s): */ @@ -224,6 +226,9 @@ void reset_handler(void) __asm__("MSR msp, %0" : : "r"(&_stack)); + /* Enable access to Floating-Point coprocessor. */ + SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; -- cgit v1.2.3 From fc4047e4b4b38c6c778f2d5f71c7412ecbab3152 Mon Sep 17 00:00:00 2001 From: Tomaz Solc Date: Mon, 24 Sep 2012 12:54:53 +0200 Subject: Add assert macros to aid in debugging. Adds libopencm3/cm3/assert.h header that provides assertion check macros similar to those provided by the standard C library. Thanks to Nicolas Schodet for help. --- include/libopencm3/cm3/assert.h | 136 ++++++++++++++++++++++++++++++++++++++++ lib/cm3/assert.c | 34 ++++++++++ lib/lm3s/Makefile | 4 +- lib/lpc13xx/Makefile | 4 +- lib/lpc17xx/Makefile | 4 +- lib/lpc43xx/Makefile | 5 +- lib/stm32/f1/Makefile | 4 +- lib/stm32/f1/rcc.c | 4 +- lib/stm32/f2/Makefile | 4 +- lib/stm32/f2/rcc.c | 4 +- lib/stm32/f4/Makefile | 3 +- lib/stm32/f4/rcc.c | 4 +- 12 files changed, 191 insertions(+), 19 deletions(-) create mode 100644 include/libopencm3/cm3/assert.h create mode 100644 lib/cm3/assert.c (limited to 'lib') diff --git a/include/libopencm3/cm3/assert.h b/include/libopencm3/cm3/assert.h new file mode 100644 index 0000000..0ccb0f7 --- /dev/null +++ b/include/libopencm3/cm3/assert.h @@ -0,0 +1,136 @@ +/** @defgroup debugging Debugging + +@brief Macros and functions to aid in debugging + +@version 1.0.0 + +@date 25 September 2012 + +Two preprocessor defines control the behavior of assertion check macros in +this module. They allow the choice between generated code size and ease of +debugging. + +If NDEBUG is defined, all assertion checks are disabled and macros do not +generate any code. + +If CM3_ASSERT_VERBOSE is defined, information regarding the position of +assertion checks will be stored in the binary, allowing for more +informative error messages, but also significantly increased code size. As +default assertion checks do not use this information it is only useful if +the application linked with libopencm3 defines its own +cm3_assert_failed_verbose() implementation. + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Tomaz Solc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_CM3_ASSERT_H +#define LIBOPENCM3_CM3_ASSERT_H + +#include + +#define CM3_LIKELY(expr) (__builtin_expect (!!(expr), 1)) + +#ifdef NDEBUG +# define cm3_assert(expr) do { (void)0; } while(0) +# define cm3_assert_not_reached() while(1) +#else +# ifdef CM3_ASSERT_VERBOSE +# define cm3_assert(expr) do { \ + if(CM3_LIKELY(expr)) { (void)0; } else { \ + cm3_assert_failed_verbose( \ + __FILE__, __LINE__, \ + __func__, #expr); \ + } \ + } while(0) +# define cm3_assert_not_reached() do { \ + cm3_assert_failed_verbose( \ + __FILE__, __LINE__, \ + __func__, 0); \ + } while(0) +# else +/** @brief Check if assertion is true. + * + * If NDEBUG macro is defined, this macro generates no code. Otherwise + * cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion + * is false. + * + * The purpose of this macro is to aid in debugging libopencm3 and + * applications using it. It can be used for example to check if function + * arguments are within expected ranges and stop execution in case an + * unexpected state is reached. + * + * @param expr expression to check */ +# define cm3_assert(expr) do { \ + if(CM3_LIKELY(expr)) { (void)0; } else { \ + cm3_assert_failed(); \ + } \ + } while(0) +/** @brief Check if unreachable code is reached. + * + * If NDEBUG macro is defined, this macro generates code for an infinite loop. + * Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if + * the macro is ever reached. + * + * The purpose of this macro is to aid in debugging libopencm3 and + * applications using it. It can be used for example to stop execution if an + * unreachable portion of code is reached. */ +# define cm3_assert_not_reached() do { \ + cm3_assert_failed(); \ + } while(0) +# endif +#endif + +BEGIN_DECLS + +/** @brief Called on a failed assertion. + * + * Halts execution in an infinite loop. This function never returns. + * + * Defined as a weak symbol, so applications can define their own + * implementation. Usually, a custom implementation of this function should + * report an error in some way (print a message to a debug console, display, + * LED, ...) and halt execution or reboot the device. */ +void cm3_assert_failed(void) __attribute__ ((__noreturn__)); + +/** @brief Called on a failed assertion with verbose messages enabled. + * + * Halts execution in an infinite loop. This function never returns. + * + * Defined as a weak symbol, so applications can define their own + * implementation. Usually, a custom implementation of this function should + * report an error in some way (print a message to a debug console, display, + * LED, ...) and halt execution or reboot the device. + * + * @param file File name where the failed assertion occurred + * @param line Line number where the failed assertion occurred + * @param func Name of the function where the failed assertion occurred + * @param assert_expr Expression that evaluated to false (can be NULL) */ +void cm3_assert_failed_verbose(const char *file, int line, const char *func, + const char *assert_expr) __attribute__ ((__noreturn__)); + +END_DECLS + +#endif + +/**@}*/ diff --git a/lib/cm3/assert.c b/lib/cm3/assert.c new file mode 100644 index 0000000..d76c578 --- /dev/null +++ b/lib/cm3/assert.c @@ -0,0 +1,34 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Tomaz Solc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void __attribute__((weak)) cm3_assert_failed(void) +{ + while(1); +} + +void __attribute__((weak)) cm3_assert_failed_verbose( + const char *file __attribute__((unused)), + int line __attribute__((unused)), + const char *func __attribute__((unused)), + const char *assert_expr __attribute__((unused))) +{ + cm3_assert_failed(); +} diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile index bdad3a4..e471a00 100644 --- a/lib/lm3s/Makefile +++ b/lib/lm3s/Makefile @@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o +OBJS = gpio.o vector.o assert.o -# VPATH += ../usb +VPATH += ../cm3 include ../Makefile.include diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile index 158a5bf..e1e69f7 100644 --- a/lib/lpc13xx/Makefile +++ b/lib/lpc13xx/Makefile @@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o +OBJS = gpio.o assert.o -# VPATH += ../usb +VPATH += ../cm3 include ../Makefile.include diff --git a/lib/lpc17xx/Makefile b/lib/lpc17xx/Makefile index f688716..d1da64a 100644 --- a/lib/lpc17xx/Makefile +++ b/lib/lpc17xx/Makefile @@ -28,8 +28,8 @@ CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o +OBJS = gpio.o vector.o assert.o -# VPATH += ../usb +VPATH += ../cm3 include ../Makefile.include diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 67e74d7..6e08ea0 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,8 +31,9 @@ CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o +OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o \ + assert.o -# VPATH += ../usb +VPATH += ../cm3 include ../Makefile.include diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 3b4252b..4fdbf43 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -31,9 +31,9 @@ ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o + timer.o usb_f107.o desig.o crc.o assert.o -VPATH += ../../usb:../ +VPATH += ../../usb:../:../../cm3 include ../../Makefile.include diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index 5fd9c62..ab3350b 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -48,6 +48,7 @@ LGPL License Terms @ref lgpl_license /**@{*/ +#include #include #include @@ -166,8 +167,7 @@ int rcc_osc_ready_int_flag(osc_t osc) break; } - /* Shouldn't be reached. */ - return -1; + cm3_assert_not_reached(); } /*-----------------------------------------------------------------------------*/ diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index bd6f275..c127d61 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -29,8 +29,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \ - i2c.o systick.o exti.o scb.o timer.o \ + i2c.o systick.o exti.o scb.o timer.o assert.o -VPATH += ../../usb:../ +VPATH += ../../usb:../:../../cm3 include ../../Makefile.include diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index 9461a24..cc2c9bb 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -19,6 +19,7 @@ * along with this library. If not, see . */ +#include #include #include @@ -125,8 +126,7 @@ int rcc_osc_ready_int_flag(osc_t osc) break; } - /* Shouldn't be reached. */ - return -1; + cm3_assert_not_reached(); } void rcc_css_int_clear(void) diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 5760d29..85870a7 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -31,7 +31,8 @@ ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \ i2c.o systick.o exti.o scb.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_f107.o \ + assert.o -VPATH += ../../usb:../ +VPATH += ../../usb:../:../../cm3 include ../../Makefile.include diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 6294ff7..f506d4b 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -19,6 +19,7 @@ * along with this library. If not, see . */ +#include #include #include #include @@ -139,8 +140,7 @@ int rcc_osc_ready_int_flag(osc_t osc) break; } - /* Shouldn't be reached. */ - return -1; + cm3_assert_not_reached(); } void rcc_css_int_clear(void) -- cgit v1.2.3 From a69d83d312396ee604426dce5341a54316c7c9b5 Mon Sep 17 00:00:00 2001 From: chrysn Date: Wed, 3 Oct 2012 18:15:20 +0200 Subject: unified vector table initialization the cortex generic interrupts get moved to lib/cm3/vector.c, the platorms' individual irq names, initialization and handler prototypes go to platoform specific irq.h files. as the vector.c file heavily depends on platoform specific headers, it can't be built once-and-for-all in lib/cm3/, so there are inclusion stubs in the various architecture dirs; this might be better solved with Makefile / include path handling. one particular file is lib/lpc43xx/vector.c; that platform's initialization code contains an additional section to copy everything from flash to ram (which probably performs better there). that code still resides in the inclusion stub, and gets mashed in using defines. would need a cleaner implementation together with the Makefile solution. this commit contains some files of the upcoming efm32 branch, from which it was cherry-picked. the .bin files produced from before and after this commit only differ in lpc43xx, where the startup sequence was subtly modified. --- include/libopencm3/cm3/vector.h | 65 ++++++ include/libopencm3/efm32/tinygecko/irq.h | 130 +++++++++++ include/libopencm3/lm3s/irq.h | 33 +++ include/libopencm3/lpc17xx/irq.h | 33 +++ include/libopencm3/lpc43xx/irq.h | 234 ++++++++++++++++++++ include/libopencm3/stm32/f1/irq.h | 306 ++++++++++++++++++++++++++ include/libopencm3/stm32/f2/irq.h | 359 +++++++++++++++++++++++++++++++ include/libopencm3/stm32/f4/irq.h | 359 +++++++++++++++++++++++++++++++ lib/cm3/vector.c | 95 ++++++++ lib/efm32/tinygecko/vector.c | 2 + lib/lm3s/vector.c | 98 +-------- lib/lpc17xx/vector.c | 97 +-------- lib/lpc43xx/vector.c | 224 +------------------ lib/stm32/f1/vector.c | 298 +------------------------ lib/stm32/f2/vector.c | 338 +---------------------------- lib/stm32/f4/vector.c | 338 +---------------------------- 16 files changed, 1633 insertions(+), 1376 deletions(-) create mode 100644 include/libopencm3/cm3/vector.h create mode 100644 include/libopencm3/efm32/tinygecko/irq.h create mode 100644 include/libopencm3/lm3s/irq.h create mode 100644 include/libopencm3/lpc17xx/irq.h create mode 100644 include/libopencm3/lpc43xx/irq.h create mode 100644 include/libopencm3/stm32/f1/irq.h create mode 100644 include/libopencm3/stm32/f2/irq.h create mode 100644 include/libopencm3/stm32/f4/irq.h create mode 100644 lib/cm3/vector.c create mode 100644 lib/efm32/tinygecko/vector.c (limited to 'lib') diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h new file mode 100644 index 0000000..198992b --- /dev/null +++ b/include/libopencm3/cm3/vector.h @@ -0,0 +1,65 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions for handling vector tables. + * + * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2 + * (from the EFM32 documentation at + * http://www.energymicro.com/downloads/datasheets), and was seen analogously + * in other ARM implementations' libopencm3 files. + * + * The structure of the vector table is implemented independently of the system + * vector table starting at memory position 0x0, as it can be relocated to + * other memory locations too. + * + * The exact size of a vector interrupt table depends on the number of + * interrupts IRQ_COUNT, which is defined per family. + */ + +#ifndef LIBOPENCM3_VECTOR_H +#define LIBOPENCM3_VECTOR_H + +#include + +// #include "irq.h" /* we'll nede some definitions */ + +/** Type of an interrupt function. Only used to avoid hard-to-read function + * pointers in the efm32_vector_table_t struct. */ +typedef void (*vector_table_entry_t)(void); + +typedef struct { + unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ + vector_table_entry_t reset; + vector_table_entry_t nmi; + vector_table_entry_t hard_fault; + vector_table_entry_t memory_manage_fault; + vector_table_entry_t bus_fault; + vector_table_entry_t usage_fault; + vector_table_entry_t reserved_x001c[4]; + vector_table_entry_t sv_call; + vector_table_entry_t debug_monitor; + vector_table_entry_t reserved_x0034; + vector_table_entry_t pend_sv; + vector_table_entry_t systick; + vector_table_entry_t irq[IRQ_COUNT]; +} vector_table_t; + +#endif diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h new file mode 100644 index 0000000..f5263ae --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq.h @@ -0,0 +1,130 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions of interrupt names on EFM32 Tiny Gecko systems + * + * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. + */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H + +#define IRQ_DMA 0 +#define IRQ_GPIO_EVEN 1 +#define IRQ_TIMER0 2 +#define IRQ_USART0_RX 3 +#define IRQ_USART0_TX 4 +#define IRQ_ACMP01 5 +#define IRQ_ADC0 6 +#define IRQ_DAC0 7 +#define IRQ_I2C0 8 +#define IRQ_GPIO_ODD 9 +#define IRQ_TIMER1 10 +#define IRQ_USART1_RX 11 +#define IRQ_USART1_TX 12 +#define IRQ_LESENSE 13 +#define IRQ_LEUART0 14 +#define IRQ_LETIMER0 15 +#define IRQ_PCNT0 16 +#define IRQ_RTC 17 +#define IRQ_CMU 18 +#define IRQ_VCMP 19 +#define IRQ_LCD 20 +#define IRQ_MSC 21 +#define IRQ_AES 22 +#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ + +#define WEAK __attribute__ ((weak)) + +void WEAK dma_isr(void); +void WEAK gpio_even_isr(void); +void WEAK timer0_isr(void); +void WEAK usart0_rx_isr(void); +void WEAK usart0_tx_isr(void); +void WEAK acmp01_isr(void); +void WEAK adc0_isr(void); +void WEAK dac0_isr(void); +void WEAK i2c0_isr(void); +void WEAK gpio_odd_isr(void); +void WEAK timer1_isr(void); +void WEAK usart1_rx_isr(void); +void WEAK usart1_tx_isr(void); +void WEAK lesense_isr(void); +void WEAK leuart0_isr(void); +void WEAK letimer0_isr(void); +void WEAK pcnt0_isr(void); +void WEAK rtc_isr(void); +void WEAK cmu_isr(void); +void WEAK vcmp_isr(void); +void WEAK lcd_isr(void); +void WEAK msc_isr(void); +void WEAK aes_isr(void); + +#pragma weak dma_isr = blocking_handler +#pragma weak gpio_even_isr = blocking_handler +#pragma weak timer0_isr = blocking_handler +#pragma weak usart0_rx_isr = blocking_handler +#pragma weak usart0_tx_isr = blocking_handler +#pragma weak acmp01_isr = blocking_handler +#pragma weak adc0_isr = blocking_handler +#pragma weak dac0_isr = blocking_handler +#pragma weak i2c0_isr = blocking_handler +#pragma weak gpio_odd_isr = blocking_handler +#pragma weak timer1_isr = blocking_handler +#pragma weak usart1_rx_isr = blocking_handler +#pragma weak usart1_tx_isr = blocking_handler +#pragma weak lesense_isr = blocking_handler +#pragma weak leuart0_isr = blocking_handler +#pragma weak letimer0_isr = blocking_handler +#pragma weak pcnt0_isr = blocking_handler +#pragma weak rtc_isr = blocking_handler +#pragma weak cmu_isr = blocking_handler +#pragma weak vcmp_isr = blocking_handler +#pragma weak lcd_isr = blocking_handler +#pragma weak msc_isr = blocking_handler +#pragma weak aes_isr = blocking_handler + +#define IRQ_HANDLERS \ + [IRQ_DMA] = dma_isr, \ + [IRQ_GPIO_EVEN] = gpio_even_isr, \ + [IRQ_TIMER0] = timer0_isr, \ + [IRQ_USART0_RX] = usart0_rx_isr, \ + [IRQ_USART0_TX] = usart0_tx_isr, \ + [IRQ_ACMP01] = acmp01_isr, \ + [IRQ_ADC0] = adc0_isr, \ + [IRQ_DAC0] = dac0_isr, \ + [IRQ_I2C0] = i2c0_isr, \ + [IRQ_GPIO_ODD] = gpio_odd_isr, \ + [IRQ_TIMER1] = timer1_isr, \ + [IRQ_USART1_RX] = usart1_rx_isr, \ + [IRQ_USART1_TX] = usart1_tx_isr, \ + [IRQ_LESENSE] = lesense_isr, \ + [IRQ_LEUART0] = leuart0_isr, \ + [IRQ_LETIMER0] = letimer0_isr, \ + [IRQ_PCNT0] = pcnt0_isr, \ + [IRQ_RTC] = rtc_isr, \ + [IRQ_CMU] = cmu_isr, \ + [IRQ_VCMP] = vcmp_isr, \ + [IRQ_LCD] = lcd_isr, \ + [IRQ_MSC] = msc_isr, \ + [IRQ_AES] = aes_isr, + +#endif diff --git a/include/libopencm3/lm3s/irq.h b/include/libopencm3/lm3s/irq.h new file mode 100644 index 0000000..948c563 --- /dev/null +++ b/include/libopencm3/lm3s/irq.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LM3S_IRQ_H +#define LIBOPENCM3_LM3S_IRQ_H + +/* TODO: Interrupt definitions */ +#define IRQ_COUNT 0 + +/* TODO: Interrupt handler prototypes */ + +/* TODO: Interrupt handler weak aliases */ + +#define IRQ_HANDLERS + +#endif diff --git a/include/libopencm3/lpc17xx/irq.h b/include/libopencm3/lpc17xx/irq.h new file mode 100644 index 0000000..9c31267 --- /dev/null +++ b/include/libopencm3/lpc17xx/irq.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LPC17xx_IRQ_H +#define LIBOPENCM3_LPC17xx_IRQ_H + +/* TODO: Interrupt definitions */ +#define IRQ_COUNT 0 + +/* TODO: Interrupt handler prototypes */ + +/* TODO: Interrupt handler weak aliases */ + +#define IRQ_HANDLERS + +#endif diff --git a/include/libopencm3/lpc43xx/irq.h b/include/libopencm3/lpc43xx/irq.h new file mode 100644 index 0000000..a83a8d7 --- /dev/null +++ b/include/libopencm3/lpc43xx/irq.h @@ -0,0 +1,234 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LPC43XX_IRQ_H +#define LIBOPENCM3_LPC43XX_IRQ_H + +#define IRQ_DAC 0 +#define IRQ_M0CORE 1 +#define IRQ_DMA 2 +/* reserved: 3 */ +/* reserved: 4 */ +#define IRQ_ETHERNET 5 +#define IRQ_SDIO 6 +#define IRQ_LCD 7 +#define IRQ_USB0 8 +#define IRQ_USB1 9 +#define IRQ_SCT 10 +#define IRQ_RITIMER 11 +#define IRQ_TIMER0 12 +#define IRQ_TIMER1 13 +#define IRQ_TIMER2 14 +#define IRQ_TIMER3 15 +#define IRQ_MCPWM 16 +#define IRQ_ADC0 17 +#define IRQ_I2C0 18 +#define IRQ_I2C1 19 +#define IRQ_SPI 20 +#define IRQ_ADC1 21 +#define IRQ_SSP0 22 +#define IRQ_SSP1 23 +#define IRQ_USART0 24 +#define IRQ_UART1 25 +#define IRQ_USART2 26 +#define IRQ_USART3 27 +#define IRQ_I2S0 28 +#define IRQ_I2S1 29 +#define IRQ_SPIFI 30 +#define IRQ_SGPIO 31 +#define IRQ_PIN_INT0 32 +#define IRQ_PIN_INT1 33 +#define IRQ_PIN_INT2 34 +#define IRQ_PIN_INT3 35 +#define IRQ_PIN_INT4 36 +#define IRQ_PIN_INT5 37 +#define IRQ_PIN_INT6 38 +#define IRQ_PIN_INT7 39 +#define IRQ_GINT0 40 +#define IRQ_GINT1 41 +#define IRQ_EVENTROUTER 42 +#define IRQ_C_CAN1 43 +/* reserved: 44 */ +/* reserved: 45 */ +#define IRQ_ATIMER 46 +#define IRQ_RTC 47 +/* reserved: 48 */ +#define IRQ_WWDT 49 +/* reserved: 50 */ +#define IRQ_C_CAN0 51 +#define IRQ_QEI 52 + +#define IRQ_COUNT 53 + +#define WEAK __attribute__ ((weak)) + +void WEAK dac_irqhandler(void); +void WEAK m0core_irqhandler(void); +void WEAK dma_irqhandler(void); +void WEAK ethernet_irqhandler(void); +void WEAK sdio_irqhandler(void); +void WEAK lcd_irqhandler(void); +void WEAK usb0_irqhandler(void); +void WEAK usb1_irqhandler(void); +void WEAK sct_irqhandler(void); +void WEAK ritimer_irqhandler(void); +void WEAK timer0_irqhandler(void); +void WEAK timer1_irqhandler(void); +void WEAK timer2_irqhandler(void); +void WEAK timer3_irqhandler(void); +void WEAK mcpwm_irqhandler(void); +void WEAK adc0_irqhandler(void); +void WEAK i2c0_irqhandler(void); +void WEAK i2c1_irqhandler(void); +void WEAK spi_irqhandler(void); +void WEAK adc1_irqhandler(void); +void WEAK ssp0_irqhandler(void); +void WEAK ssp1_irqhandler(void); +void WEAK usart0_irqhandler(void); +void WEAK uart1_irqhandler(void); +void WEAK usart2_irqhandler(void); +void WEAK usart3_irqhandler(void); +void WEAK i2s0_irqhandler(void); +void WEAK i2s1_irqhandler(void); +void WEAK spifi_irqhandler(void); +void WEAK sgpio_irqhandler(void); +void WEAK pin_int0_irqhandler(void); +void WEAK pin_int1_irqhandler(void); +void WEAK pin_int2_irqhandler(void); +void WEAK pin_int3_irqhandler(void); +void WEAK pin_int4_irqhandler(void); +void WEAK pin_int5_irqhandler(void); +void WEAK pin_int6_irqhandler(void); +void WEAK pin_int7_irqhandler(void); +void WEAK gint0_irqhandler(void); +void WEAK gint1_irqhandler(void); +void WEAK eventrouter_irqhandler(void); +void WEAK c_can1_irqhandler(void); +void WEAK atimer_irqhandler(void); +void WEAK rtc_irqhandler(void); +void WEAK wwdt_irqhandler(void); +void WEAK c_can0_irqhandler(void); +void WEAK qei_irqhandler(void); + +#pragma weak dac_irqhandler = null_handler +#pragma weak m0core_irqhandler = null_handler +#pragma weak dma_irqhandler = null_handler +#pragma weak ethernet_irqhandler = null_handler +#pragma weak sdio_irqhandler = null_handler +#pragma weak lcd_irqhandler = null_handler +#pragma weak usb0_irqhandler = null_handler +#pragma weak usb1_irqhandler = null_handler +#pragma weak sct_irqhandler = null_handler +#pragma weak ritimer_irqhandler = null_handler +#pragma weak timer0_irqhandler = null_handler +#pragma weak timer1_irqhandler = null_handler +#pragma weak timer2_irqhandler = null_handler +#pragma weak timer3_irqhandler = null_handler +#pragma weak mcpwm_irqhandler = null_handler +#pragma weak adc0_irqhandler = null_handler +#pragma weak i2c0_irqhandler = null_handler +#pragma weak i2c1_irqhandler = null_handler +#pragma weak spi_irqhandler = null_handler +#pragma weak adc1_irqhandler = null_handler +#pragma weak ssp0_irqhandler = null_handler +#pragma weak ssp1_irqhandler = null_handler +#pragma weak usart0_irqhandler = null_handler +#pragma weak uart1_irqhandler = null_handler +#pragma weak usart2_irqhandler = null_handler +#pragma weak usart3_irqhandler = null_handler +#pragma weak i2s0_irqhandler = null_handler +#pragma weak i2s1_irqhandler = null_handler +#pragma weak spifi_irqhandler = null_handler +#pragma weak sgpio_irqhandler = null_handler +#pragma weak pin_int0_irqhandler = null_handler +#pragma weak pin_int1_irqhandler = null_handler +#pragma weak pin_int2_irqhandler = null_handler +#pragma weak pin_int3_irqhandler = null_handler +#pragma weak pin_int4_irqhandler = null_handler +#pragma weak pin_int5_irqhandler = null_handler +#pragma weak pin_int6_irqhandler = null_handler +#pragma weak pin_int7_irqhandler = null_handler +#pragma weak gint0_irqhandler = null_handler +#pragma weak gint1_irqhandler = null_handler +#pragma weak eventrouter_irqhandler = null_handler +#pragma weak c_can1_irqhandler = null_handler +#pragma weak atimer_irqhandler = null_handler +#pragma weak rtc_irqhandler = null_handler +#pragma weak wwdt_irqhandler = null_handler +#pragma weak c_can0_irqhandler = null_handler +#pragma weak qei_irqhandler = null_handler + +#define IRQ_HANDLERS \ + dac_irqhandler, \ + m0core_irqhandler, \ + dma_irqhandler, \ + 0, /* reserved */ \ + 0, /* reserved */ \ + ethernet_irqhandler, \ + sdio_irqhandler, \ + lcd_irqhandler, \ + usb0_irqhandler, \ + usb1_irqhandler, \ + sct_irqhandler, \ + ritimer_irqhandler, \ + timer0_irqhandler, \ + timer1_irqhandler, \ + timer2_irqhandler, \ + timer3_irqhandler, \ + mcpwm_irqhandler, \ + adc0_irqhandler, \ + i2c0_irqhandler, \ + i2c1_irqhandler, \ + spi_irqhandler, \ + adc1_irqhandler, \ + ssp0_irqhandler, \ + ssp1_irqhandler, \ + usart0_irqhandler, \ + uart1_irqhandler, \ + usart2_irqhandler, \ + usart3_irqhandler, \ + i2s0_irqhandler, \ + i2s1_irqhandler, \ + spifi_irqhandler, \ + sgpio_irqhandler, \ + pin_int0_irqhandler, \ + pin_int1_irqhandler, \ + pin_int2_irqhandler, \ + pin_int3_irqhandler, \ + pin_int4_irqhandler, \ + pin_int5_irqhandler, \ + pin_int6_irqhandler, \ + pin_int7_irqhandler, \ + gint0_irqhandler, \ + gint1_irqhandler, \ + eventrouter_irqhandler, \ + c_can1_irqhandler, \ + 0, /* reserved */ \ + 0, /* reserved */ \ + atimer_irqhandler, \ + rtc_irqhandler, \ + 0, /* reserved */ \ + wwdt_irqhandler, \ + 0, /* reserved */ \ + c_can0_irqhandler, \ + qei_irqhandler, + +#endif diff --git a/include/libopencm3/stm32/f1/irq.h b/include/libopencm3/stm32/f1/irq.h new file mode 100644 index 0000000..cfa07f1 --- /dev/null +++ b/include/libopencm3/stm32/f1/irq.h @@ -0,0 +1,306 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F1_IRQ_H +#define LIBOPENCM3_STM32_F1_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMPER 2 +#define IRQ_RTC 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_CHANNEL1 11 +#define IRQ_DMA1_CHANNEL2 12 +#define IRQ_DMA1_CHANNEL3 13 +#define IRQ_DMA1_CHANNEL4 14 +#define IRQ_DMA1_CHANNEL5 15 +#define IRQ_DMA1_CHANNEL6 16 +#define IRQ_DMA1_CHANNEL7 17 +#define IRQ_ADC1_2 18 +#define IRQ_USB_HP_CAN_TX 19 +#define IRQ_USB_LP_CAN_RX0 20 +#define IRQ_CAN_RX1 21 +#define IRQ_CAN_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK 24 +#define IRQ_TIM1_UP 25 +#define IRQ_TIM1_TRG_COM 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_WAKEUP 42 +#define IRQ_TIM8_BRK 43 +#define IRQ_TIM8_UP 44 +#define IRQ_TIM8_TRG_COM 45 +#define IRQ_TIM8_CC 46 +#define IRQ_ADC3 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_CHANNEL1 56 +#define IRQ_DMA2_CHANNEL2 57 +#define IRQ_DMA2_CHANNEL3 58 +#define IRQ_DMA2_CHANNEL4_5 59 +#define IRQ_DMA2_CHANNEL5 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 + +/* FIXME: number from list in lib/stm32/f1/vector.c, might miss irqs */ +#define IRQ_COUNT 68 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamper_isr(void); +void WEAK rtc_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_channel1_isr(void); +void WEAK dma1_channel2_isr(void); +void WEAK dma1_channel3_isr(void); +void WEAK dma1_channel4_isr(void); +void WEAK dma1_channel5_isr(void); +void WEAK dma1_channel6_isr(void); +void WEAK dma1_channel7_isr(void); +void WEAK adc1_2_isr(void); +void WEAK usb_hp_can_tx_isr(void); +void WEAK usb_lp_can_rx0_isr(void); +void WEAK can_rx1_isr(void); +void WEAK can_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_isr(void); +void WEAK tim1_up_isr(void); +void WEAK tim1_trg_com_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_wakeup_isr(void); +void WEAK tim8_brk_isr(void); +void WEAK tim8_up_isr(void); +void WEAK tim8_trg_com_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK adc3_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_channel1_isr(void); +void WEAK dma2_channel2_isr(void); +void WEAK dma2_channel3_isr(void); +void WEAK dma2_channel4_5_isr(void); +void WEAK dma2_channel5_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamper_isr = null_handler +#pragma weak rtc_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_channel1_isr = null_handler +#pragma weak dma1_channel2_isr = null_handler +#pragma weak dma1_channel3_isr = null_handler +#pragma weak dma1_channel4_isr = null_handler +#pragma weak dma1_channel5_isr = null_handler +#pragma weak dma1_channel6_isr = null_handler +#pragma weak dma1_channel7_isr = null_handler +#pragma weak adc1_2_isr = null_handler +#pragma weak usb_hp_can_tx_isr = null_handler +#pragma weak usb_lp_can_rx0_isr = null_handler +#pragma weak can_rx1_isr = null_handler +#pragma weak can_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_isr = null_handler +#pragma weak tim1_up_isr = null_handler +#pragma weak tim1_trg_com_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_wakeup_isr = null_handler +#pragma weak tim8_brk_isr = null_handler +#pragma weak tim8_up_isr = null_handler +#pragma weak tim8_trg_com_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak adc3_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_channel1_isr = null_handler +#pragma weak dma2_channel2_isr = null_handler +#pragma weak dma2_channel3_isr = null_handler +#pragma weak dma2_channel4_5_isr = null_handler +#pragma weak dma2_channel5_isr +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamper_isr, \ + rtc_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_channel1_isr, \ + dma1_channel2_isr, \ + dma1_channel3_isr, \ + dma1_channel4_isr, \ + dma1_channel5_isr, \ + dma1_channel6_isr, \ + dma1_channel7_isr, \ + adc1_2_isr, \ + usb_hp_can_tx_isr, \ + usb_lp_can_rx0_isr, \ + can_rx1_isr, \ + can_sce_isr, \ + exti9_5_isr, \ + tim1_brk_isr, \ + tim1_up_isr, \ + tim1_trg_com_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_wakeup_isr, \ + tim8_brk_isr, \ + tim8_up_isr, \ + tim8_trg_com_isr, \ + tim8_cc_isr, \ + adc3_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_isr, \ + tim7_isr, \ + dma2_channel1_isr, \ + dma2_channel2_isr, \ + dma2_channel3_isr, \ + dma2_channel4_5_isr, \ + dma2_channel5_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + +#endif diff --git a/include/libopencm3/stm32/f2/irq.h b/include/libopencm3/stm32/f2/irq.h new file mode 100644 index 0000000..7aec142 --- /dev/null +++ b/include/libopencm3/stm32/f2/irq.h @@ -0,0 +1,359 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F2_IRQ_H +#define LIBOPENCM3_STM32_F2_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMP_STAMP 2 +#define IRQ_RTC_WKUP 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_STREAM0 11 +#define IRQ_DMA1_STREAM1 12 +#define IRQ_DMA1_STREAM2 13 +#define IRQ_DMA1_STREAM3 14 +#define IRQ_DMA1_STREAM4 15 +#define IRQ_DMA1_STREAM5 16 +#define IRQ_DMA1_STREAM6 17 +#define IRQ_ADC 18 +#define IRQ_CAN1_TX 19 +#define IRQ_CAN1_RX0 20 +#define IRQ_CAN1_RX1 21 +#define IRQ_CAN1_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK_TIM9 24 +#define IRQ_TIM1_UP_TIM10 25 +#define IRQ_TIM1_TRG_COM_TIM11 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_FS_WKUP 42 +#define IRQ_TIM8_BRK_TIM12 43 +#define IRQ_TIM8_UP_TIM13 44 +#define IRQ_TIM8_TRG_COM_TIM14 45 +#define IRQ_TIM8_CC 46 +#define IRQ_DMA1_STREAM7 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6_DAC 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_STREAM0 56 +#define IRQ_DMA2_STREAM1 57 +#define IRQ_DMA2_STREAM2 58 +#define IRQ_DMA2_STREAM3 59 +#define IRQ_DMA2_STREAM4 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 +#define IRQ_DMA2_STREAM5 68 +#define IRQ_DMA2_STREAM6 69 +#define IRQ_DMA2_STREAM7 70 +#define IRQ_USART6 71 +#define IRQ_I2C3_EV 72 +#define IRQ_I2C3_ER 73 +#define IRQ_OTG_HS_EP1_OUT 74 +#define IRQ_OTG_HS_EP1_IN 75 +#define IRQ_OTG_HS_WKUP 76 +#define IRQ_OTG_HS 77 +#define IRQ_DCMI 78 +#define IRQ_CRYP 79 +#define IRQ_HASH_RNG 80 + +/* FIXME: number from list in lib/stm32/f2/vector.c, might miss irqs */ +#define IRQ_COUNT 81 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamp_stamp_isr, \ + rtc_wkup_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_stream0_isr, \ + dma1_stream1_isr, \ + dma1_stream2_isr, \ + dma1_stream3_isr, \ + dma1_stream4_isr, \ + dma1_stream5_isr, \ + dma1_stream6_isr, \ + adc_isr, \ + can1_tx_isr, \ + can1_rx0_isr, \ + can1_rx1_isr, \ + can1_sce_isr, \ + exti9_5_isr, \ + tim1_brk_tim9_isr, \ + tim1_up_tim10_isr, \ + tim1_trg_com_tim11_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_fs_wkup_isr, \ + tim8_brk_tim12_isr, \ + tim8_up_tim13_isr, \ + tim8_trg_com_tim14_isr, \ + tim8_cc_isr, \ + dma1_stream7_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_dac_isr, \ + tim7_isr, \ + dma2_stream0_isr, \ + dma2_stream1_isr, \ + dma2_stream2_isr, \ + dma2_stream3_isr, \ + dma2_stream4_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + dma2_stream5_isr, \ + dma2_stream6_isr, \ + dma2_stream7_isr, \ + usart6_isr, \ + i2c3_ev_isr, \ + i2c3_er_isr, \ + otg_hs_ep1_out_isr, \ + otg_hs_ep1_in_isr, \ + otg_hs_wkup_isr, \ + otg_hs_isr, \ + dcmi_isr, \ + cryp_isr, \ + hash_rng_isr, + +#endif diff --git a/include/libopencm3/stm32/f4/irq.h b/include/libopencm3/stm32/f4/irq.h new file mode 100644 index 0000000..4f4f5e5 --- /dev/null +++ b/include/libopencm3/stm32/f4/irq.h @@ -0,0 +1,359 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F4_IRQ_H +#define LIBOPENCM3_STM32_F4_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMP_STAMP 2 +#define IRQ_RTC_WKUP 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_STREAM0 11 +#define IRQ_DMA1_STREAM1 12 +#define IRQ_DMA1_STREAM2 13 +#define IRQ_DMA1_STREAM3 14 +#define IRQ_DMA1_STREAM4 15 +#define IRQ_DMA1_STREAM5 16 +#define IRQ_DMA1_STREAM6 17 +#define IRQ_ADC 18 +#define IRQ_CAN1_TX 19 +#define IRQ_CAN1_RX0 20 +#define IRQ_CAN1_RX1 21 +#define IRQ_CAN1_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK_TIM9 24 +#define IRQ_TIM1_UP_TIM10 25 +#define IRQ_TIM1_TRG_COM_TIM11 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_FS_WKUP 42 +#define IRQ_TIM8_BRK_TIM12 43 +#define IRQ_TIM8_UP_TIM13 44 +#define IRQ_TIM8_TRG_COM_TIM14 45 +#define IRQ_TIM8_CC 46 +#define IRQ_DMA1_STREAM7 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6_DAC 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_STREAM0 56 +#define IRQ_DMA2_STREAM1 57 +#define IRQ_DMA2_STREAM2 58 +#define IRQ_DMA2_STREAM3 59 +#define IRQ_DMA2_STREAM4 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 +#define IRQ_DMA2_STREAM5 68 +#define IRQ_DMA2_STREAM6 69 +#define IRQ_DMA2_STREAM7 70 +#define IRQ_USART6 71 +#define IRQ_I2C3_EV 72 +#define IRQ_I2C3_ER 73 +#define IRQ_OTG_HS_EP1_OUT 74 +#define IRQ_OTG_HS_EP1_IN 75 +#define IRQ_OTG_HS_WKUP 76 +#define IRQ_OTG_HS 77 +#define IRQ_DCMI 78 +#define IRQ_CRYP 79 +#define IRQ_HASH_RNG 80 + +/* FIXME: number from list in lib/stm32/f4/vector.c, might miss irqs */ +#define IRQ_COUNT 81 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamp_stamp_isr, \ + rtc_wkup_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_stream0_isr, \ + dma1_stream1_isr, \ + dma1_stream2_isr, \ + dma1_stream3_isr, \ + dma1_stream4_isr, \ + dma1_stream5_isr, \ + dma1_stream6_isr, \ + adc_isr, \ + can1_tx_isr, \ + can1_rx0_isr, \ + can1_rx1_isr, \ + can1_sce_isr, \ + exti9_5_isr, \ + tim1_brk_tim9_isr, \ + tim1_up_tim10_isr, \ + tim1_trg_com_tim11_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_fs_wkup_isr, \ + tim8_brk_tim12_isr, \ + tim8_up_tim13_isr, \ + tim8_trg_com_tim14_isr, \ + tim8_cc_isr, \ + dma1_stream7_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_dac_isr, \ + tim7_isr, \ + dma2_stream0_isr, \ + dma2_stream1_isr, \ + dma2_stream2_isr, \ + dma2_stream3_isr, \ + dma2_stream4_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + dma2_stream5_isr, \ + dma2_stream6_isr, \ + dma2_stream7_isr, \ + usart6_isr, \ + i2c3_ev_isr, \ + i2c3_er_isr, \ + otg_hs_ep1_out_isr, \ + otg_hs_ep1_in_isr, \ + otg_hs_wkup_isr, \ + otg_hs_isr, \ + dcmi_isr, \ + cryp_isr, \ + hash_rng_isr, + +#endif diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c new file mode 100644 index 0000000..200e8e5 --- /dev/null +++ b/lib/cm3/vector.c @@ -0,0 +1,95 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski , + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by the linker script(s): */ +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; + +void main(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK reset_handler(void); +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); + +__attribute__ ((section(".vectors"))) +vector_table_t vector_table = { + .initial_sp_value = &_stack, + .reset = reset_handler, + .nmi = nmi_handler, + .hard_fault = hard_fault_handler, + .memory_manage_fault = mem_manage_handler, + .bus_fault = bus_fault_handler, + .usage_fault = usage_fault_handler, + .debug_monitor = debug_monitor_handler, + .sv_call = sv_call_handler, + .pend_sv = pend_sv_handler, + .systick = sys_tick_handler, + .irq = { + IRQ_HANDLERS + } +}; + +void WEAK reset_handler(void) +{ + volatile unsigned *src, *dest; + + __asm__("MSR msp, %0" : : "r"(&_stack)); + + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c new file mode 100644 index 0000000..d6da5a2 --- /dev/null +++ b/lib/efm32/tinygecko/vector.c @@ -0,0 +1,2 @@ +#include +#include "../../cm3/vector.c" diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c index 3a1c4d1..e9e7e06 100644 --- a/lib/lm3s/vector.c +++ b/lib/lm3s/vector.c @@ -1,96 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); - -/* TODO: Interrupt handler prototypes */ - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - - /* TODO: Interrupt handlers */ -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#include +#include "../cm3/vector.c" diff --git a/lib/lpc17xx/vector.c b/lib/lpc17xx/vector.c index 518f562..61342f4 100644 --- a/lib/lpc17xx/vector.c +++ b/lib/lpc17xx/vector.c @@ -1,95 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); - -/* TODO: Interrupt handler prototypes */ - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void*)&_stack, /* Addr: 0x0000_0000 */ - reset_handler, /* Addr: 0x0000_0004 */ - nmi_handler, /* Addr: 0x0000_0008 */ - hard_fault_handler, /* Addr: 0x0000_000C */ - mem_manage_handler, /* Addr: 0x0000_0010 */ - bus_fault_handler, /* Addr: 0x0000_0014 */ - usage_fault_handler, /* Addr: 0x0000_0018 */ - 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ - sv_call_handler, /* Addr: 0x0000_002C */ - debug_monitor_handler, /* Addr: 0x0000_0030 */ - 0, /* Reserved Addr: 0x0000_00034 */ - pend_sv_handler, /* Addr: 0x0000_0038 */ - sys_tick_handler, /* Addr: 0x0000_003C */ -}; - - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#include +#include "../cm3/vector.c" diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 23008bc..66e9b63 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -18,156 +18,20 @@ * along with this library. If not, see . */ -#define WEAK __attribute__ ((weak)) +#include +#define reset_handler original_reset_handler +#include "../cm3/vector.c" +#undef reset_handler +#include -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; extern unsigned _etext_ram, _text_ram, _etext_rom; -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK dac_irqhandler(void); -void WEAK m0core_irqhandler(void); -void WEAK dma_irqhandler(void); -void WEAK ethernet_irqhandler(void); -void WEAK sdio_irqhandler(void); -void WEAK lcd_irqhandler(void); -void WEAK usb0_irqhandler(void); -void WEAK usb1_irqhandler(void); -void WEAK sct_irqhandler(void); -void WEAK ritimer_irqhandler(void); -void WEAK timer0_irqhandler(void); -void WEAK timer1_irqhandler(void); -void WEAK timer2_irqhandler(void); -void WEAK timer3_irqhandler(void); -void WEAK mcpwm_irqhandler(void); -void WEAK adc0_irqhandler(void); -void WEAK i2c0_irqhandler(void); -void WEAK i2c1_irqhandler(void); -void WEAK spi_irqhandler(void); -void WEAK adc1_irqhandler(void); -void WEAK ssp0_irqhandler(void); -void WEAK ssp1_irqhandler(void); -void WEAK usart0_irqhandler(void); -void WEAK uart1_irqhandler(void); -void WEAK usart2_irqhandler(void); -void WEAK usart3_irqhandler(void); -void WEAK i2s0_irqhandler(void); -void WEAK i2s1_irqhandler(void); -void WEAK spifi_irqhandler(void); -void WEAK sgpio_irqhandler(void); -void WEAK pin_int0_irqhandler(void); -void WEAK pin_int1_irqhandler(void); -void WEAK pin_int2_irqhandler(void); -void WEAK pin_int3_irqhandler(void); -void WEAK pin_int4_irqhandler(void); -void WEAK pin_int5_irqhandler(void); -void WEAK pin_int6_irqhandler(void); -void WEAK pin_int7_irqhandler(void); -void WEAK gint0_irqhandler(void); -void WEAK gint1_irqhandler(void); -void WEAK eventrouter_irqhandler(void); -void WEAK c_can1_irqhandler(void); -void WEAK atimer_irqhandler(void); -void WEAK rtc_irqhandler(void); -void WEAK wwdt_irqhandler(void); -void WEAK c_can0_irqhandler(void); -void WEAK qei_irqhandler(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - /* Cortex-M4 interrupts */ - (void*)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* reserved */ - pend_sv_handler, - sys_tick_handler, - - /* LPC43xx interrupts */ - dac_irqhandler, - m0core_irqhandler, - dma_irqhandler, - 0, /* reserved */ - 0, /* reserved */ - ethernet_irqhandler, - sdio_irqhandler, - lcd_irqhandler, - usb0_irqhandler, - usb1_irqhandler, - sct_irqhandler, - ritimer_irqhandler, - timer0_irqhandler, - timer1_irqhandler, - timer2_irqhandler, - timer3_irqhandler, - mcpwm_irqhandler, - adc0_irqhandler, - i2c0_irqhandler, - i2c1_irqhandler, - spi_irqhandler, - adc1_irqhandler, - ssp0_irqhandler, - ssp1_irqhandler, - usart0_irqhandler, - uart1_irqhandler, - usart2_irqhandler, - usart3_irqhandler, - i2s0_irqhandler, - i2s1_irqhandler, - spifi_irqhandler, - sgpio_irqhandler, - pin_int0_irqhandler, - pin_int1_irqhandler, - pin_int2_irqhandler, - pin_int3_irqhandler, - pin_int4_irqhandler, - pin_int5_irqhandler, - pin_int6_irqhandler, - pin_int7_irqhandler, - gint0_irqhandler, - gint1_irqhandler, - eventrouter_irqhandler, - c_can1_irqhandler, - 0, /* reserved */ - 0, /* reserved */ - atimer_irqhandler, - rtc_irqhandler, - 0, /* reserved */ - wwdt_irqhandler, - 0, /* reserved */ - c_can0_irqhandler, - qei_irqhandler, -}; - -#define MMIO32(addr) (*(volatile unsigned long*)(addr)) #define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) ) -void reset_handler(void) +void WEAK reset_handler(void) { volatile unsigned *src, *dest; - __asm__("MSR msp, %0" : : "r"(&_stack)); - /* Copy the code from ROM to Real RAM (if enabled) */ if( (&_etext_ram-&_text_ram) > 0 ) { @@ -186,79 +50,5 @@ void reset_handler(void) /* Continue Execution in RAM */ } - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); + original_reset_handler(); } - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak dac_irqhandler = null_handler -#pragma weak m0core_irqhandler = null_handler -#pragma weak dma_irqhandler = null_handler -#pragma weak ethernet_irqhandler = null_handler -#pragma weak sdio_irqhandler = null_handler -#pragma weak lcd_irqhandler = null_handler -#pragma weak usb0_irqhandler = null_handler -#pragma weak usb1_irqhandler = null_handler -#pragma weak sct_irqhandler = null_handler -#pragma weak ritimer_irqhandler = null_handler -#pragma weak timer0_irqhandler = null_handler -#pragma weak timer1_irqhandler = null_handler -#pragma weak timer2_irqhandler = null_handler -#pragma weak timer3_irqhandler = null_handler -#pragma weak mcpwm_irqhandler = null_handler -#pragma weak adc0_irqhandler = null_handler -#pragma weak i2c0_irqhandler = null_handler -#pragma weak i2c1_irqhandler = null_handler -#pragma weak spi_irqhandler = null_handler -#pragma weak adc1_irqhandler = null_handler -#pragma weak ssp0_irqhandler = null_handler -#pragma weak ssp1_irqhandler = null_handler -#pragma weak usart0_irqhandler = null_handler -#pragma weak uart1_irqhandler = null_handler -#pragma weak usart2_irqhandler = null_handler -#pragma weak usart3_irqhandler = null_handler -#pragma weak i2s0_irqhandler = null_handler -#pragma weak i2s1_irqhandler = null_handler -#pragma weak spifi_irqhandler = null_handler -#pragma weak sgpio_irqhandler = null_handler -#pragma weak pin_int0_irqhandler = null_handler -#pragma weak pin_int1_irqhandler = null_handler -#pragma weak pin_int2_irqhandler = null_handler -#pragma weak pin_int3_irqhandler = null_handler -#pragma weak pin_int4_irqhandler = null_handler -#pragma weak pin_int5_irqhandler = null_handler -#pragma weak pin_int6_irqhandler = null_handler -#pragma weak pin_int7_irqhandler = null_handler -#pragma weak gint0_irqhandler = null_handler -#pragma weak gint1_irqhandler = null_handler -#pragma weak eventrouter_irqhandler = null_handler -#pragma weak c_can1_irqhandler = null_handler -#pragma weak atimer_irqhandler = null_handler -#pragma weak rtc_irqhandler = null_handler -#pragma weak wwdt_irqhandler = null_handler -#pragma weak c_can0_irqhandler = null_handler -#pragma weak qei_irqhandler = null_handler diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c index f496ae4..795773b 100644 --- a/lib/stm32/f1/vector.c +++ b/lib/stm32/f1/vector.c @@ -1,296 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamper_isr(void); -void WEAK rtc_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_channel1_isr(void); -void WEAK dma1_channel2_isr(void); -void WEAK dma1_channel3_isr(void); -void WEAK dma1_channel4_isr(void); -void WEAK dma1_channel5_isr(void); -void WEAK dma1_channel6_isr(void); -void WEAK dma1_channel7_isr(void); -void WEAK adc1_2_isr(void); -void WEAK usb_hp_can_tx_isr(void); -void WEAK usb_lp_can_rx0_isr(void); -void WEAK can_rx1_isr(void); -void WEAK can_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_isr(void); -void WEAK tim1_up_isr(void); -void WEAK tim1_trg_com_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_wakeup_isr(void); -void WEAK tim8_brk_isr(void); -void WEAK tim8_up_isr(void); -void WEAK tim8_trg_com_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK adc3_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_channel1_isr(void); -void WEAK dma2_channel2_isr(void); -void WEAK dma2_channel3_isr(void); -void WEAK dma2_channel4_5_isr(void); -void WEAK dma2_channel5_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); - - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void*)&_stack, /* Addr: 0x0000_0000 */ - reset_handler, /* Addr: 0x0000_0004 */ - nmi_handler, /* Addr: 0x0000_0008 */ - hard_fault_handler, /* Addr: 0x0000_000C */ - mem_manage_handler, /* Addr: 0x0000_0010 */ - bus_fault_handler, /* Addr: 0x0000_0014 */ - usage_fault_handler, /* Addr: 0x0000_0018 */ - 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ - sv_call_handler, /* Addr: 0x0000_002C */ - debug_monitor_handler, /* Addr: 0x0000_0030*/ - 0, /* Reserved Addr: 0x0000_00034 */ - pend_sv_handler, /* Addr: 0x0000_0038 */ - sys_tick_handler, /* Addr: 0x0000_003C */ - wwdg_isr, /* Addr: 0x0000_0040 */ - pvd_isr, /* Addr: 0x0000_0044 */ - tamper_isr, /* Addr: 0x0000_0048 */ - rtc_isr, /* Addr: 0x0000_004C */ - flash_isr, /* Addr: 0x0000_0050 */ - rcc_isr, /* Addr: 0x0000_0054 */ - exti0_isr, /* Addr: 0x0000_0058 */ - exti1_isr, /* Addr: 0x0000_005C */ - exti2_isr, /* Addr: 0x0000_0060 */ - exti3_isr, /* Addr: 0x0000_0064 */ - exti4_isr, /* Addr: 0x0000_0068 */ - dma1_channel1_isr, /* Addr: 0x0000_006C */ - dma1_channel2_isr, /* Addr: 0x0000_0070 */ - dma1_channel3_isr, /* Addr: 0x0000_0074 */ - dma1_channel4_isr, /* Addr: 0x0000_0078 */ - dma1_channel5_isr, /* Addr: 0x0000_007C */ - dma1_channel6_isr, /* Addr: 0x0000_0080 */ - dma1_channel7_isr, /* Addr: 0x0000_0084 */ - adc1_2_isr, /* Addr: 0x0000_0088 */ - usb_hp_can_tx_isr, /* Addr: 0x0000_008C */ - usb_lp_can_rx0_isr, /* Addr: 0x0000_0090 */ - can_rx1_isr, /* Addr: 0x0000_0094 */ - can_sce_isr, /* Addr: 0x0000_0098 */ - exti9_5_isr, /* Addr: 0x0000_009C */ - tim1_brk_isr, /* Addr: 0x0000_00A0 */ - tim1_up_isr, /* Addr: 0x0000_00A4 */ - tim1_trg_com_isr, /* Addr: 0x0000_00A8 */ - tim1_cc_isr, /* Addr: 0x0000_00AC */ - tim2_isr, /* Addr: 0x0000_00B0 */ - tim3_isr, /* Addr: 0x0000_00B4 */ - tim4_isr, /* Addr: 0x0000_00B8 */ - i2c1_ev_isr, /* Addr: 0x0000_00BC */ - i2c1_er_isr, /* Addr: 0x0000_00C0 */ - i2c2_ev_isr, /* Addr: 0x0000_00C4 */ - i2c2_er_isr, /* Addr: 0x0000_00C8 */ - spi1_isr, /* Addr: 0x0000_00CC */ - spi2_isr, /* Addr: 0x0000_00D0 */ - usart1_isr, /* Addr: 0x0000_00D4 */ - usart2_isr, /* Addr: 0x0000_00D8 */ - usart3_isr, /* Addr: 0x0000_00DC */ - exti15_10_isr, /* Addr: 0x0000_00E0 */ - rtc_alarm_isr, /* Addr: 0x0000_00E4 */ - usb_wakeup_isr, /* Addr: 0x0000_00E8 */ - tim8_brk_isr, /* Addr: 0x0000_00EC */ - tim8_up_isr, /* Addr: 0x0000_00F0 */ - tim8_trg_com_isr, /* Addr: 0x0000_00F4 */ - tim8_cc_isr, /* Addr: 0x0000_00F8 */ - adc3_isr, /* Addr: 0x0000_00FC */ - fsmc_isr, /* Addr: 0x0000_0100 */ - sdio_isr, /* Addr: 0x0000_0104 */ - tim5_isr, /* Addr: 0x0000_0108 */ - spi3_isr, /* Addr: 0x0000_010C */ - uart4_isr, /* Addr: 0x0000_0110 */ - uart5_isr, /* Addr: 0x0000_0114 */ - tim6_isr, /* Addr: 0x0000_0118 */ - tim7_isr, /* Addr: 0x0000_011C */ - dma2_channel1_isr, /* Addr: 0x0000_0120 */ - dma2_channel2_isr, /* Addr: 0x0000_0124 */ - dma2_channel3_isr, /* Addr: 0x0000_0128 */ - dma2_channel4_5_isr, /* Addr: 0x0000_012C */ - dma2_channel5_isr, /* Addr: 0x0000_0130 */ - eth_isr, /* Addr: 0x0000_0134 */ - eth_wkup_isr, /* Addr: 0x0000_0138 */ - can2_tx_isr, /* Addr: 0x0000_013C */ - can2_rx0_isr, /* Addr: 0x0000_0140 */ - can2_rx1_isr, /* Addr: 0x0000_0144 */ - can2_sce_isr, /* Addr: 0x0000_0148 */ - otg_fs_isr, /* Addr: 0x0000_014C */ -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamper_isr = null_handler -#pragma weak rtc_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_channel1_isr = null_handler -#pragma weak dma1_channel2_isr = null_handler -#pragma weak dma1_channel3_isr = null_handler -#pragma weak dma1_channel4_isr = null_handler -#pragma weak dma1_channel5_isr = null_handler -#pragma weak dma1_channel6_isr = null_handler -#pragma weak dma1_channel7_isr = null_handler -#pragma weak adc1_2_isr = null_handler -#pragma weak usb_hp_can_tx_isr = null_handler -#pragma weak usb_lp_can_rx0_isr = null_handler -#pragma weak can_rx1_isr = null_handler -#pragma weak can_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_isr = null_handler -#pragma weak tim1_up_isr = null_handler -#pragma weak tim1_trg_com_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_wakeup_isr = null_handler -#pragma weak tim8_brk_isr = null_handler -#pragma weak tim8_up_isr = null_handler -#pragma weak tim8_trg_com_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak adc3_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_channel1_isr = null_handler -#pragma weak dma2_channel2_isr = null_handler -#pragma weak dma2_channel3_isr = null_handler -#pragma weak dma2_channel4_5_isr = null_handler -#pragma weak dma2_channel5_isr -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler +#include +#include "../../cm3/vector.c" diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c index 3429bfb..24d1185 100644 --- a/lib/stm32/f2/vector.c +++ b/lib/stm32/f2/vector.c @@ -1,336 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK reset_handler(void); -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - wwdg_isr, - pvd_isr, - tamp_stamp_isr, - rtc_wkup_isr, - flash_isr, - rcc_isr, - exti0_isr, - exti1_isr, - exti2_isr, - exti3_isr, - exti4_isr, - dma1_stream0_isr, - dma1_stream1_isr, - dma1_stream2_isr, - dma1_stream3_isr, - dma1_stream4_isr, - dma1_stream5_isr, - dma1_stream6_isr, - adc_isr, - can1_tx_isr, - can1_rx0_isr, - can1_rx1_isr, - can1_sce_isr, - exti9_5_isr, - tim1_brk_tim9_isr, - tim1_up_tim10_isr, - tim1_trg_com_tim11_isr, - tim1_cc_isr, - tim2_isr, - tim3_isr, - tim4_isr, - i2c1_ev_isr, - i2c1_er_isr, - i2c2_ev_isr, - i2c2_er_isr, - spi1_isr, - spi2_isr, - usart1_isr, - usart2_isr, - usart3_isr, - exti15_10_isr, - rtc_alarm_isr, - usb_fs_wkup_isr, - tim8_brk_tim12_isr, - tim8_up_tim13_isr, - tim8_trg_com_tim14_isr, - tim8_cc_isr, - dma1_stream7_isr, - fsmc_isr, - sdio_isr, - tim5_isr, - spi3_isr, - uart4_isr, - uart5_isr, - tim6_dac_isr, - tim7_isr, - dma2_stream0_isr, - dma2_stream1_isr, - dma2_stream2_isr, - dma2_stream3_isr, - dma2_stream4_isr, - eth_isr, - eth_wkup_isr, - can2_tx_isr, - can2_rx0_isr, - can2_rx1_isr, - can2_sce_isr, - otg_fs_isr, - dma2_stream5_isr, - dma2_stream6_isr, - dma2_stream7_isr, - usart6_isr, - i2c3_ev_isr, - i2c3_er_isr, - otg_hs_ep1_out_isr, - otg_hs_ep1_in_isr, - otg_hs_wkup_isr, - otg_hs_isr, - dcmi_isr, - cryp_isr, - hash_rng_isr, -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler +#include +#include "../../cm3/vector.c" diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c index 3429bfb..8d158a6 100644 --- a/lib/stm32/f4/vector.c +++ b/lib/stm32/f4/vector.c @@ -1,336 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK reset_handler(void); -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - wwdg_isr, - pvd_isr, - tamp_stamp_isr, - rtc_wkup_isr, - flash_isr, - rcc_isr, - exti0_isr, - exti1_isr, - exti2_isr, - exti3_isr, - exti4_isr, - dma1_stream0_isr, - dma1_stream1_isr, - dma1_stream2_isr, - dma1_stream3_isr, - dma1_stream4_isr, - dma1_stream5_isr, - dma1_stream6_isr, - adc_isr, - can1_tx_isr, - can1_rx0_isr, - can1_rx1_isr, - can1_sce_isr, - exti9_5_isr, - tim1_brk_tim9_isr, - tim1_up_tim10_isr, - tim1_trg_com_tim11_isr, - tim1_cc_isr, - tim2_isr, - tim3_isr, - tim4_isr, - i2c1_ev_isr, - i2c1_er_isr, - i2c2_ev_isr, - i2c2_er_isr, - spi1_isr, - spi2_isr, - usart1_isr, - usart2_isr, - usart3_isr, - exti15_10_isr, - rtc_alarm_isr, - usb_fs_wkup_isr, - tim8_brk_tim12_isr, - tim8_up_tim13_isr, - tim8_trg_com_tim14_isr, - tim8_cc_isr, - dma1_stream7_isr, - fsmc_isr, - sdio_isr, - tim5_isr, - spi3_isr, - uart4_isr, - uart5_isr, - tim6_dac_isr, - tim7_isr, - dma2_stream0_isr, - dma2_stream1_isr, - dma2_stream2_isr, - dma2_stream3_isr, - dma2_stream4_isr, - eth_isr, - eth_wkup_isr, - can2_tx_isr, - can2_rx0_isr, - can2_rx1_isr, - can2_sce_isr, - otg_fs_isr, - dma2_stream5_isr, - dma2_stream6_isr, - dma2_stream7_isr, - usart6_isr, - i2c3_ev_isr, - i2c3_er_isr, - otg_hs_ep1_out_isr, - otg_hs_ep1_in_isr, - otg_hs_wkup_isr, - otg_hs_isr, - dcmi_isr, - cryp_isr, - hash_rng_isr, -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler +#include +#include "../../cm3/vector.c" -- cgit v1.2.3 From 7d0611609bc83abc6c942fe3fd6aeab16376fd7f Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 5 Oct 2012 13:50:42 +0930 Subject: Code changes to stm32f1 adc.c and adc.h remove rcc_set_adc_clk - use rcc version Added functions: - adc_power_on - adc_start_conversion_direct - adc_set_dual_mode - adc_eoc - adc_eoc_injected - adc_read_regular - adc_read_injected - adc_set_injected_offset Tested dual mode scanned regular, but no tests of injected yet. Changes: "discontinuous" was misspelled. - adc_set_discontinuous_mode_regular - added "length" parameter - adc_disable_discontinuous_mode_regular - name change - adc_enable_discontinuous_mode_injected - name change - adc_enable_automatic_injected_group_conversion - disable triggers - adc_enable_jeoc_interrupt - name change to match common usage in lib - adc_disable_jeoc_interrupt - ditto - adc_enable_external_trigger_regular - remove incorrect test on parameter - adc_enable_external_trigger_injected - ditto - adc_set_sample_time - name change to match function's purpose - adc_set_conversion_time_on_all_channels - ditto - adc_set_injected_sequence - changed order of register loading (ref Barlow's issue) - adc_enable_analog_watchdog_on_all_channels - flipped AWDSGL - adc_enable_analog_watchdog_on_selected_channel - ditto added aliases for expected commonly used functions to avoid sudden user code breakage In adc.h, corrected errors in SQR names added "deprecated" compiler warnings to adc_on and to aliases defined in adc.c --- examples/stm32/f1/lisa-m-2/adc_regular/adc.c | 11 +- .../stm32/f1/other/adc_temperature_sensor/adc.c | 10 +- include/libopencm3/stm32/f1/adc.h | 89 ++++----- lib/stm32/f1/adc.c | 198 +++++++++++++++++---- 4 files changed, 219 insertions(+), 89 deletions(-) (limited to 'lib') diff --git a/examples/stm32/f1/lisa-m-2/adc_regular/adc.c b/examples/stm32/f1/lisa-m-2/adc_regular/adc.c index 91d029f..f6442b1 100644 --- a/examples/stm32/f1/lisa-m-2/adc_regular/adc.c +++ b/examples/stm32/f1/lisa-m-2/adc_regular/adc.c @@ -3,6 +3,7 @@ * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -71,14 +72,13 @@ void adc_setup(void) /* We configure everything for one single conversion. */ adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); - adc_enable_discontinous_mode_regular(ADC1); adc_disable_external_trigger_regular(ADC1); adc_set_right_aligned(ADC1); /* We want to read the temperature sensor, so we have to enable it. */ adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); - adc_on(ADC1); + adc_power_on(ADC1); /* Wait for ADC starting up. */ for (i = 0; i < 800000; i++) /* Wait a bit. */ @@ -138,10 +138,9 @@ int main(void) /* Continously convert and poll the temperature ADC. */ while (1) { /* - * If the ADC_CR2_ON bit is already set -> setting it another time - * starts the conversion. + * Start the conversion directly (ie without a trigger). */ - adc_on(ADC1); + adc_start_conversion_direct(ADC1); /* Wait for end of conversion. */ while (!(ADC_SR(ADC1) & ADC_SR_EOC)); diff --git a/examples/stm32/f1/other/adc_temperature_sensor/adc.c b/examples/stm32/f1/other/adc_temperature_sensor/adc.c index dea6a7c..70cc5da 100644 --- a/examples/stm32/f1/other/adc_temperature_sensor/adc.c +++ b/examples/stm32/f1/other/adc_temperature_sensor/adc.c @@ -69,14 +69,13 @@ void adc_setup(void) /* We configure everything for one single conversion. */ adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); - adc_enable_discontinous_mode_regular(ADC1); adc_disable_external_trigger_regular(ADC1); adc_set_right_aligned(ADC1); /* We want to read the temperature sensor, so we have to enable it. */ adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); - adc_on(ADC1); + adc_power_on(ADC1); /* Wait for ADC starting up. */ for (i = 0; i < 800000; i++) /* Wait a bit. */ @@ -131,10 +130,9 @@ int main(void) adc_set_regular_sequence(ADC1, 1, channel_array); /* - * If the ADC_CR2_ON bit is already set -> setting it another time - * starts the conversion. + * Start the conversion directly (not trigger mode). */ - adc_on(ADC1); + adc_start_conversion_direct(ADC1); /* Wait for end of conversion. */ while (!(ADC_SR(ADC1) & ADC_SR_EOC)); diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index 116aeaa..aa54bdf 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -252,7 +252,7 @@ LGPL License Terms @ref lgpl_license #define ADC_CR1_DUALMOD_MASK (0xF << 16) #define ADC_CR1_DUALMOD_SHIFT 16 -/* DISCNUM[2:0]: Discontinous mode channel count. */ +/* DISCNUM[2:0]: Discontinuous mode channel count. */ /****************************************************************************/ /** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. @ingroup STM32F1xx_adc_defines @@ -270,10 +270,10 @@ LGPL License Terms @ref lgpl_license #define ADC_CR1_DISCNUM_MASK (0x7 << 13) #define ADC_CR1_DISCNUM_SHIFT 13 -/* JDISCEN: */ /** Discontinous mode on injected channels. */ +/* JDISCEN: */ /** Discontinuous mode on injected channels. */ #define ADC_CR1_JDISCEN (1 << 12) -/* DISCEN: */ /** Discontinous mode on regular channels. */ +/* DISCEN: */ /** Discontinuous mode on regular channels. */ #define ADC_CR1_DISCEN (1 << 11) /* JAUTO: */ /** Automatic Injection Group conversion. */ @@ -557,7 +557,7 @@ LGPL License Terms @ref lgpl_license /* --- ADC_SMPRx generic values -------------------------------------------- */ /****************************************************************************/ /* ADC_SMPRG ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample_rg ADC Sample Time Selection Generic +/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels @ingroup STM32F1xx_adc_defines @{*/ @@ -587,18 +587,11 @@ LGPL License Terms @ref lgpl_license #define ADC_SQR1_SQ15_LSB 10 #define ADC_SQR1_SQ14_LSB 5 #define ADC_SQR1_SQ13_LSB 0 -#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB) -#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB) -#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB) -#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB) -#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB) -/* TODO Fix error #define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) #define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) #define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) #define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) #define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) -*/ /* --- ADC_SQR2 values ----------------------------------------------------- */ @@ -608,20 +601,12 @@ LGPL License Terms @ref lgpl_license #define ADC_SQR2_SQ9_LSB 10 #define ADC_SQR2_SQ8_LSB 5 #define ADC_SQR2_SQ7_LSB 0 -#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB) -#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB) -#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB) -#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB) -#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB) -#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB) -/* TODO Fix error #define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) #define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) #define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) #define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) #define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) #define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) -*/ /* --- ADC_SQR3 values ----------------------------------------------------- */ @@ -631,20 +616,12 @@ LGPL License Terms @ref lgpl_license #define ADC_SQR3_SQ3_LSB 10 #define ADC_SQR3_SQ2_LSB 5 #define ADC_SQR3_SQ1_LSB 0 -#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB) -#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB) -#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB) -#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB) -#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB) -#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB) -/* TODO Fix error #define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) #define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) #define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) #define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) #define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) #define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) -*/ /* --- ADC_JSQR values ----------------------------------------------------- */ #define ADC_JSQR_JL_LSB 20 @@ -652,18 +629,24 @@ LGPL License Terms @ref lgpl_license #define ADC_JSQR_JSQ3_LSB 10 #define ADC_JSQR_JSQ2_LSB 5 #define ADC_JSQR_JSQ1_LSB 0 -#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB) -#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB) -#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB) -#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB) -#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB) -/* TODO Fix error + +/* JL[2:0]: Discontinous mode channel count injected channels. */ +/****************************************************************************/ +/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels. +@ingroup STM32F1xx_adc_defines + +@{*/ +#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB) +/**@}*/ +#define ADC_JSQR_JL_SHIFT 13 #define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) #define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) #define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) #define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) -*/ /* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ @@ -679,22 +662,31 @@ LGPL License Terms @ref lgpl_license BEGIN_DECLS +void adc_power_on(u32 adc); +void adc_start_conversion_direct(u32 adc); +void adc_set_single_channel(u32 adc, u8 channel); +void adc_set_dual_mode(u32 mode); +bool adc_eoc(u32 adc); +bool adc_eoc_injected(u32 adc); +u32 adc_read_regular(u32 adc); +u32 adc_read_injected(u32 adc, u8 reg); +void adc_set_injected_offset(u32 adc, u8 reg, u32 offset); void adc_enable_analog_watchdog_regular(u32 adc); void adc_disable_analog_watchdog_regular(u32 adc); void adc_enable_analog_watchdog_injected(u32 adc); void adc_disable_analog_watchdog_injected(u32 adc); -void adc_enable_discontinous_mode_regular(u32 adc); -void adc_disable_discontinous_mode_regular(u32 adc); -void adc_enable_discontinous_mode_injected(u32 adc); -void adc_disable_discontinous_mode_injected(u32 adc); +void adc_enable_discontinuous_mode_regular(u32 adc, u8 length); +void adc_disable_discontinuous_mode_regular(u32 adc); +void adc_enable_discontinuous_mode_injected(u32 adc); +void adc_disable_discontinuous_mode_injected(u32 adc); void adc_enable_automatic_injected_group_conversion(u32 adc); void adc_disable_automatic_injected_group_conversion(u32 adc); void adc_enable_analog_watchdog_on_all_channels(u32 adc); void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel); void adc_enable_scan_mode(u32 adc); void adc_disable_scan_mode(u32 adc); -void adc_enable_jeoc_interrupt(u32 adc); -void adc_disable_jeoc_interrupt(u32 adc); +void adc_enable_eoc_interrupt_injected(u32 adc); +void adc_disable_eoc_interrupt_injected(u32 adc); void adc_enable_awd_interrupt(u32 adc); void adc_disable_awd_interrupt(u32 adc); void adc_enable_eoc_interrupt(u32 adc); @@ -713,17 +705,28 @@ void adc_enable_dma(u32 adc); void adc_disable_dma(u32 adc); void adc_reset_calibration(u32 adc); void adc_calibration(u32 adc); -void adc_set_continous_conversion_mode(u32 adc); +void adc_set_continuous_conversion_mode(u32 adc); void adc_set_single_conversion_mode(u32 adc); +#ifdef __GNUC__ +void adc_on(u32 adc) __attribute__ ((deprecated ("will be removed in the first release"))); +#else void adc_on(u32 adc); +#endif void adc_off(u32 adc); -void adc_set_conversion_time(u32 adc, u8 channel, u8 time); -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time); +void adc_set_sample_time(u32 adc, u8 channel, u8 time); +void adc_set_sample_time_on_all_channels(u32 adc, u8 time); void adc_set_watchdog_high_threshold(u32 adc, u16 threshold); void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); +#ifdef __GNUC__ +void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((deprecated ("change to adc_set_continuous_conversion_mode"))); +void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time"))); +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time_on_all_channels"))); +void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_enable_eoc_interrupt_injected"))); +void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_disable_eoc_interrupt_injected"))); +#endif END_DECLS #endif diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c index 433cdd2..a8bb746 100644 --- a/lib/stm32/f1/adc.c +++ b/lib/stm32/f1/adc.c @@ -102,38 +102,156 @@ LGPL License Terms @ref lgpl_license #include -void rcc_set_adc_clk(u32 prescaler) +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Power On + +If the ADC is in power-down mode then it is powered up. The application needs +to wait a time of about 3 microseconds for stabilization before using the ADC. +If the ADC is already on this function call has no effect. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_power_on(u32 adc) { - /* TODO */ + if (!(ADC_CR2(adc) & ADC_CR2_ADON)) + ADC_CR2(adc) |= ADC_CR2_ADON; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Start a Conversion Without Trigger + +This initiates a conversion by software without a trigger. The ADC needs to be +powered on before this is called, otherwise this function has no effect. + +Note that this is not available in other STM32F families. To ensure code compatibility, +enable triggering and use a software trigger source @see adc_start_conversion_regular. - /* FIXME: QUICK HACK to prevent compiler warnings. */ - prescaler = prescaler; +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_start_conversion_direct(u32 adc) +{ + if (ADC_CR2(adc) & ADC_CR2_ADON) + ADC_CR2(adc) |= ADC_CR2_ADON; } -void adc_set_mode(u32 block, /* TODO */ u8 mode) +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set Dual A/D Mode + +The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting +is applied to ADC1 only. Start of conversion when triggered can cause simultaneous +conversion with ADC2, or alternate conversion. Regular and injected conversions +can be configured, each one being separately simultaneous or alternate. + +@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod +*/ + +void adc_set_dual_mode(u32 mode) { - /* TODO */ + ADC1_CR1 |= mode; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read the End-of-Conversion Flag + +This flag is set after all channels of a regular or injected group have been +converted. - /* FIXME: QUICK HACK to prevent compiler warnings. */ - block = block; - mode = mode; +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. End of conversion flag. +*/ + +bool adc_eoc(u32 adc) +{ + return ((ADC_SR(adc) & ADC_SR_EOC) != 0); } /*-----------------------------------------------------------------------------*/ -/** @brief ADC Read from a Conversion Result Register +/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion + +This flag is set after all channels of an injected group have been converted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. End of conversion flag. +*/ + +bool adc_eoc_injected(u32 adc) +{ + return ((ADC_SR(adc) & ADC_SR_JEOC) != 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read from the Regular Conversion Result Register + +The result read back is 12 bits, right or left aligned within the first 16 bits. +For ADC1 only, the higher 16 bits will hold the result from ADC2 if +an appropriate dual mode has been set @see adc_set_dual_mode. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +u32 adc_read_regular(u32 adc) +{ + return ADC_DR(adc); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read from an Injected Conversion Result Register + +The result read back from the selected injected result register (one of four) is +12 bits, right or left aligned within the first 16 bits. The result can have a +negative value if the injected channel offset has been set @see adc_set_injected_offset. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] reg Unsigned int8. Register number (1 ... 4). @returns Unsigned int32 conversion result. */ -void adc_read(u32 block, u32 channel) +u32 adc_read_injected(u32 adc, u8 reg) { - /* TODO */ + switch (reg) { + case 1: + return ADC_JDR1(adc); + case 2: + return ADC_JDR2(adc); + case 3: + return ADC_JDR3(adc); + case 4: + return ADC_JDR4(adc); + } + return 0; +} - /* FIXME: QUICK HACK to prevent compiler warnings. */ - block = block; - channel = channel; +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set the Injected Channel Data Offset + +This value is subtracted from the injected channel results after conversion +is complete, and can result in negative results. A separate value can be specified +for each injected data register. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] reg Unsigned int8. Register number (1 ... 4). +@param[in] offset Unsigned int32. +*/ + +void adc_set_injected_offset(u32 adc, u8 reg, u32 offset) +{ + switch (reg) { + case 1: + ADC_JOFR1(adc) = offset; + break; + case 2: + ADC_JOFR2(adc) = offset; + break; + case 3: + ADC_JOFR3(adc) = offset; + break; + case 4: + ADC_JOFR4(adc) = offset; + break; + } } /*-----------------------------------------------------------------------------*/ @@ -203,9 +321,11 @@ of the subgroup at the beginning of the whole group. @param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum */ -void adc_enable_discontinous_mode_regular(u32 adc) +void adc_enable_discontinuous_mode_regular(u32 adc, u8 length) { - ADC_CR1(adc) |= ADC_CR1_DISCEN; + if ( (length-1) > 7 ) return; + ADC_CR1(adc) |= ADC_CR1_DISCEN; + ADC_CR2(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); } /*-----------------------------------------------------------------------------*/ @@ -214,7 +334,7 @@ void adc_enable_discontinous_mode_regular(u32 adc) @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_disable_discontinous_mode_regular(u32 adc) +void adc_disable_discontinuous_mode_regular(u32 adc) { ADC_CR1(adc) &= ~ADC_CR1_DISCEN; } @@ -229,7 +349,7 @@ entire group has been converted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_enable_discontinous_mode_injected(u32 adc) +void adc_enable_discontinuous_mode_injected(u32 adc) { ADC_CR1(adc) |= ADC_CR1_JDISCEN; } @@ -240,7 +360,7 @@ void adc_enable_discontinous_mode_injected(u32 adc) @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_disable_discontinous_mode_injected(u32 adc) +void adc_disable_discontinuous_mode_injected(u32 adc) { ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; } @@ -257,6 +377,7 @@ channels is disabled as required. void adc_enable_automatic_injected_group_conversion(u32 adc) { + adc_disable_external_trigger_injected(adc); ADC_CR1(adc) |= ADC_CR1_JAUTO; } @@ -288,7 +409,7 @@ disabled. void adc_enable_analog_watchdog_on_all_channels(u32 adc) { - ADC_CR1(adc) |= ADC_CR1_AWDSGL; + ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; } /*-----------------------------------------------------------------------------*/ @@ -315,7 +436,7 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel) if (channel < 18) reg32 |= channel; ADC_CR1(adc) = reg32; - ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; + ADC_CR1(adc) |= ADC_CR1_AWDSGL; } /*-----------------------------------------------------------------------------*/ @@ -350,7 +471,7 @@ void adc_disable_scan_mode(u32 adc) @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_enable_jeoc_interrupt(u32 adc) +void adc_enable_eoc_interrupt_injected(u32 adc) { ADC_CR1(adc) |= ADC_CR1_JEOCIE; } @@ -361,7 +482,7 @@ void adc_enable_jeoc_interrupt(u32 adc) @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_disable_jeoc_interrupt(u32 adc) +void adc_disable_eoc_interrupt_injected(u32 adc) { ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; } @@ -519,8 +640,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger) u32 reg32; reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK)); - if (trigger < 8) - reg32 |= (trigger); + reg32 |= (trigger); ADC_CR2(adc) = reg32; ADC_CR2(adc) |= ADC_CR2_EXTTRIG; } @@ -565,14 +685,12 @@ For ADC3 @param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12 for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3 */ - void adc_enable_external_trigger_injected(u32 adc, u32 trigger) { u32 reg32; reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]. */ - if (trigger < 8) - reg32 |= (trigger); + reg32 |= (trigger); ADC_CR2(adc) = reg32; ADC_CR2(adc) |= ADC_CR2_JEXTTRIG; } @@ -681,7 +799,7 @@ group immediately following completion of the previous channel group conversion. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_set_continous_conversion_mode(u32 adc) +void adc_set_continuous_conversion_mode(u32 adc) { ADC_CR2(adc) |= ADC_CR2_CONT; } @@ -707,7 +825,7 @@ If the ADC is in power-down mode then it is powered up. The application needs to wait a time of about 3 microseconds for stabilization before using the ADC. If the ADC is already on this function call will initiate a conversion. -@todo fix this. +@deprecated to be removed in a later release @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ @@ -740,7 +858,7 @@ The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ -void adc_set_conversion_time(u32 adc, u8 channel, u8 time) +void adc_set_sample_time(u32 adc, u8 channel, u8 time) { u32 reg32; @@ -767,7 +885,7 @@ all channels. @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) +void adc_set_sample_time_on_all_channels(u32 adc, u8 time) { u8 i; u32 reg32 = 0; @@ -871,12 +989,24 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) return; for (i = 1; i <= length; i++) - reg32 |= (channel[i - 1] << ((i - 1) * 5)); + reg32 |= (channel[4 - i] << ((4 - i) * 5)); reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); ADC_JSQR(adc) = reg32; } +/*-----------------------------------------------------------------------------*/ + +/* Aliases */ + +#ifdef __GNUC__ +void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((alias("adc_set_continuous_conversion_mode"))); +void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((alias ("adc_set_sample_time"))); +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((alias ("adc_set_sample_time_on_all_channels"))); +void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_enable_eoc_interrupt_injected"))); +void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_disable_eoc_interrupt_injected"))); +#endif + /**@}*/ -- cgit v1.2.3 From 4efa64c2785692b422988f7444e737c67931ea5d Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 5 Oct 2012 14:04:40 +0930 Subject: Doc changes to go with previous commit --- lib/stm32/f1/adc.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c index a8bb746..0a05aac 100644 --- a/lib/stm32/f1/adc.c +++ b/lib/stm32/f1/adc.c @@ -44,12 +44,12 @@ conversion, which occurs after all channels have been scanned. @section adc_api_ex Basic ADC Handling API. Example 1: Simple single channel conversion polled. Enable the peripheral clock -and ADC, reset ADC and set the prescaler divider. Set dual mode to independent. +and ADC, reset ADC and set the prescaler divider. Set dual mode to independent +(default). Enable triggering for a software trigger. @code rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); - adc_power_on(ADC1); - adc_calibration(ADC1); + adc_off(ADC1); rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); @@ -58,6 +58,10 @@ and ADC, reset ADC and set the prescaler divider. Set dual mode to independent. adc_set_single_conversion_mode(ADC1); adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); adc_set_single_channel(ADC1, ADC_CHANNEL0); + adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART); + adc_power_on(ADC1); + adc_reset_calibration(ADC1); + adc_calibration(ADC1); adc_start_conversion_regular(ADC1); while (! adc_eoc(ADC1)); reg16 = adc_read_regular(ADC1); @@ -144,6 +148,31 @@ is applied to ADC1 only. Start of conversion when triggered can cause simultaneo conversion with ADC2, or alternate conversion. Regular and injected conversions can be configured, each one being separately simultaneous or alternate. +Fast interleaved mode starts ADC1 immediately on trigger, and ADC2 seven clock +cycles later. + +Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen clock +cycles later, followed by ADC1 fourteen cycles later again. This can only be used +on a single channel. + +Alternate trigger mode must occur on an injected channel group, and alternates +between the ADCs on each trigger. + +Note that sampling must not overlap between ADCs on the same channel. + +Dual A/D converter modes possible: + +@li IND: Independent mode. +@li CRSISM: Combined regular simultaneous + injected simultaneous mode. +@li CRSATM: Combined regular simultaneous + alternate trigger mode. +@li CISFIM: Combined injected simultaneous + fast interleaved mode. +@li CISSIM: Combined injected simultaneous + slow interleaved mode. +@li ISM: Injected simultaneous mode only. +@li RSM: Regular simultaneous mode only. +@li FIM: Fast interleaved mode only. +@li SIM: Slow interleaved mode only. +@li ATM: Alternate trigger mode only. + @param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod */ -- cgit v1.2.3 From 8f9f2bdc005648c19fbe62426210b3b560662776 Mon Sep 17 00:00:00 2001 From: Thomas W. Barr Date: Mon, 8 Oct 2012 16:40:36 -0500 Subject: complete peripheral handlers in vector table --- lib/lm3s/vector.c | 364 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 361 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c index 3a1c4d1..b7c92ae 100644 --- a/lib/lm3s/vector.c +++ b/lib/lm3s/vector.c @@ -37,7 +37,117 @@ void WEAK debug_monitor_handler(void); void WEAK pend_sv_handler(void); void WEAK sys_tick_handler(void); -/* TODO: Interrupt handler prototypes */ +void WEAK gpioa_handler(void); +void WEAK gpiob_handler(void); +void WEAK gpioc_handler(void); +void WEAK gpiod_handler(void); +void WEAK gpioe_handler(void); +void WEAK uart0_handler(void); +void WEAK uart1_handler(void); +void WEAK ssi0_handler(void); +void WEAK i2c0_handler(void); +void WEAK pwm0_fault_handler(void); +void WEAK pwm0_0_handler(void); +void WEAK pwm0_1_handler(void); +void WEAK pwm0_2_handler(void); +void WEAK qei0_handler(void); +void WEAK adc0ss0_handler(void); +void WEAK adc0ss1_handler(void); +void WEAK adc0ss2_handler(void); +void WEAK adc0ss3_handler(void); +void WEAK watchdog_handler(void); +void WEAK timer0a_handler(void); +void WEAK timer0b_handler(void); +void WEAK timer1a_handler(void); +void WEAK timer1b_handler(void); +void WEAK timer2a_handler(void); +void WEAK timer2b_handler(void); +void WEAK comp0_handler(void); +void WEAK comp1_handler(void); +void WEAK comp2_handler(void); +void WEAK sysctl_handler(void); +void WEAK flash_handler(void); +void WEAK gpiof_handler(void); +void WEAK gpiog_handler(void); +void WEAK gpioh_handler(void); +void WEAK uart2_handler(void); +void WEAK ssi1_handler(void); +void WEAK timer3a_handler(void); +void WEAK timer3b_handler(void); +void WEAK i2c1_handler(void); +void WEAK qei1_handler(void); +void WEAK can0_handler(void); +void WEAK can1_handler(void); +void WEAK can2_handler(void); +void WEAK eth_handler(void); +void WEAK hibernate_handler(void); +void WEAK usb0_handler(void); +void WEAK pwm0_3_handler(void); +void WEAK udma_handler(void); +void WEAK udmaerr_handler(void); +void WEAK adc1ss0_handler(void); +void WEAK adc1ss1_handler(void); +void WEAK adc1ss2_handler(void); +void WEAK adc1ss3_handler(void); +void WEAK i2s0_handler(void); +void WEAK epi0_handler(void); +void WEAK gpioj_handler(void); +void WEAK gpiok_handler(void); +void WEAK gpiol_handler(void); +void WEAK ssi2_handler(void); +void WEAK ssi3_handler(void); +void WEAK uart3_handler(void); +void WEAK uart4_handler(void); +void WEAK uart5_handler(void); +void WEAK uart6_handler(void); +void WEAK uart7_handler(void); +void WEAK i2c2_handler(void); +void WEAK i2c3_handler(void); +void WEAK timer4a_handler(void); +void WEAK timer4b_handler(void); +void WEAK timer5a_handler(void); +void WEAK timer5b_handler(void); +void WEAK wtimer0a_handler(void); +void WEAK wtimer0b_handler(void); +void WEAK wtimer1a_handler(void); +void WEAK wtimer1b_handler(void); +void WEAK wtimer2a_handler(void); +void WEAK wtimer2b_handler(void); +void WEAK wtimer3a_handler(void); +void WEAK wtimer3b_handler(void); +void WEAK wtimer4a_handler(void); +void WEAK wtimer4b_handler(void); +void WEAK wtimer5a_handler(void); +void WEAK wtimer5b_handler(void); +void WEAK sysexc_handler(void); +void WEAK peci0_handler(void); +void WEAK lpc0_handler(void); +void WEAK i2c4_handler(void); +void WEAK i2c5_handler(void); +void WEAK gpiom_handler(void); +void WEAK gpion_handler(void); +void WEAK fan0_handler(void); +void WEAK gpiop0_handler(void); +void WEAK gpiop1_handler(void); +void WEAK gpiop2_handler(void); +void WEAK gpiop3_handler(void); +void WEAK gpiop4_handler(void); +void WEAK gpiop5_handler(void); +void WEAK gpiop6_handler(void); +void WEAK gpiop7_handler(void); +void WEAK gpioq0_handler(void); +void WEAK gpioq1_handler(void); +void WEAK gpioq2_handler(void); +void WEAK gpioq3_handler(void); +void WEAK gpioq4_handler(void); +void WEAK gpioq5_handler(void); +void WEAK gpioq6_handler(void); +void WEAK gpioq7_handler(void); +void WEAK pwm1_0_handler(void); +void WEAK pwm1_1_handler(void); +void WEAK pwm1_2_handler(void); +void WEAK pwm1_3_handler(void); +void WEAK pwm1_fault_handler(void); __attribute__ ((section(".vectors"))) void (*const vector_table[]) (void) = { @@ -55,7 +165,145 @@ void (*const vector_table[]) (void) = { pend_sv_handler, sys_tick_handler, - /* TODO: Interrupt handlers */ + gpioa_handler, /* 16 */ + gpiob_handler, /* 17 */ + gpioc_handler, /* 18 */ + gpiod_handler, /* 19 */ + gpioe_handler, /* 20 */ + uart0_handler, /* 21 */ + uart1_handler, /* 22 */ + ssi0_handler, /* 23 */ + i2c0_handler, /* 24 */ + pwm0_fault_handler, /* 25 */ + pwm0_0_handler, /* 26 */ + pwm0_1_handler, /* 27 */ + pwm0_2_handler, /* 28 */ + qei0_handler, /* 29 */ + adc0ss0_handler, /* 30 */ + adc0ss1_handler, /* 31 */ + adc0ss2_handler, /* 32 */ + adc0ss3_handler, /* 33 */ + watchdog_handler, /* 34 */ + timer0a_handler, /* 35 */ + timer0b_handler, /* 36 */ + timer1a_handler, /* 37 */ + timer1b_handler, /* 38 */ + timer2a_handler, /* 39 */ + timer2b_handler, /* 40 */ + comp0_handler, /* 41 */ + comp1_handler, /* 42 */ + comp2_handler, /* 43 */ + sysctl_handler, /* 44 */ + flash_handler, /* 45 */ + gpiof_handler, /* 46 */ + gpiog_handler, /* 47 */ + gpioh_handler, /* 48 */ + uart2_handler, /* 49 */ + ssi1_handler, /* 50 */ + timer3a_handler, /* 51 */ + timer3b_handler, /* 52 */ + i2c1_handler, /* 53 */ + qei1_handler, /* 54 */ + can0_handler, /* 55 */ + can1_handler, /* 56 */ + can2_handler, /* 57 */ + eth_handler, /* 58 */ + hibernate_handler, /* 59 */ + usb0_handler, /* 60 */ + pwm0_3_handler, /* 61 */ + udma_handler, /* 62 */ + udmaerr_handler, /* 63 */ + adc1ss0_handler, /* 64 */ + adc1ss1_handler, /* 65 */ + adc1ss2_handler, /* 66 */ + adc1ss3_handler, /* 67 */ + i2s0_handler, /* 68 */ + epi0_handler, /* 69 */ + gpioj_handler, /* 70 */ + gpiok_handler, /* 71 */ + gpiol_handler, /* 72 */ + ssi2_handler, /* 73 */ + ssi3_handler, /* 74 */ + uart3_handler, /* 75 */ + uart4_handler, /* 76 */ + uart5_handler, /* 77 */ + uart6_handler, /* 78 */ + uart7_handler, /* 79 */ + 0, /* 80 */ + 0, /* 81 */ + 0, /* 82 */ + 0, /* 83 */ + i2c2_handler, /* 84 */ + i2c3_handler, /* 85 */ + timer4a_handler, /* 86 */ + timer4b_handler, /* 87 */ + 0, /* 88 */ + 0, /* 89 */ + 0, /* 90 */ + 0, /* 91 */ + 0, /* 92 */ + 0, /* 93 */ + 0, /* 94 */ + 0, /* 95 */ + 0, /* 96 */ + 0, /* 97 */ + 0, /* 98 */ + 0, /* 99 */ + 0, /* 100 */ + 0, /* 101 */ + 0, /* 102 */ + 0, /* 103 */ + 0, /* 104 */ + 0, /* 105 */ + 0, /* 106 */ + 0, /* 107 */ + timer5a_handler, /* 108 */ + timer5b_handler, /* 109 */ + wtimer0a_handler, /* 110 */ + wtimer0b_handler, /* 111 */ + wtimer1a_handler, /* 112 */ + wtimer1b_handler, /* 113 */ + wtimer2a_handler, /* 114 */ + wtimer2b_handler, /* 115 */ + wtimer3a_handler, /* 116 */ + wtimer3b_handler, /* 117 */ + wtimer4a_handler, /* 118 */ + wtimer4b_handler, /* 119 */ + wtimer5a_handler, /* 120 */ + wtimer5b_handler, /* 121 */ + sysexc_handler, /* 122 */ + peci0_handler, /* 123 */ + lpc0_handler, /* 124 */ + i2c4_handler, /* 125 */ + i2c5_handler, /* 126 */ + gpiom_handler, /* 127 */ + gpion_handler, /* 128 */ + 0, /* 129 */ + fan0_handler, /* 130 */ + 0, /* 131 */ + gpiop0_handler, /* 132 */ + gpiop1_handler, /* 133 */ + gpiop2_handler, /* 134 */ + gpiop3_handler, /* 135 */ + gpiop4_handler, /* 136 */ + gpiop5_handler, /* 137 */ + gpiop6_handler, /* 138 */ + gpiop7_handler, /* 139 */ + gpioq0_handler, /* 140 */ + gpioq1_handler, /* 141 */ + gpioq2_handler, /* 142 */ + gpioq3_handler, /* 143 */ + gpioq4_handler, /* 144 */ + gpioq5_handler, /* 145 */ + gpioq6_handler, /* 146 */ + gpioq7_handler, /* 147 */ + 0, /* 148 */ + 0, /* 149 */ + pwm1_0_handler, /* 150 */ + pwm1_1_handler, /* 151 */ + pwm1_2_handler, /* 152 */ + pwm1_3_handler, /* 153 */ + pwm1_fault_handler, /* 154 */ }; void reset_handler(void) @@ -93,4 +341,114 @@ void null_handler(void) #pragma weak debug_monitor_handler = null_handler #pragma weak pend_sv_handler = null_handler #pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#pragma weak gpioa_handler = null_handler +#pragma weak gpiob_handler = null_handler +#pragma weak gpioc_handler = null_handler +#pragma weak gpiod_handler = null_handler +#pragma weak gpioe_handler = null_handler +#pragma weak uart0_handler = null_handler +#pragma weak uart1_handler = null_handler +#pragma weak ssi0_handler = null_handler +#pragma weak i2c0_handler = null_handler +#pragma weak pwm0_fault_handler = null_handler +#pragma weak pwm0_0_handler = null_handler +#pragma weak pwm0_1_handler = null_handler +#pragma weak pwm0_2_handler = null_handler +#pragma weak qei0_handler = null_handler +#pragma weak adc0ss0_handler = null_handler +#pragma weak adc0ss1_handler = null_handler +#pragma weak adc0ss2_handler = null_handler +#pragma weak adc0ss3_handler = null_handler +#pragma weak watchdog_handler = null_handler +#pragma weak timer0a_handler = null_handler +#pragma weak timer0b_handler = null_handler +#pragma weak timer1a_handler = null_handler +#pragma weak timer1b_handler = null_handler +#pragma weak timer2a_handler = null_handler +#pragma weak timer2b_handler = null_handler +#pragma weak comp0_handler = null_handler +#pragma weak comp1_handler = null_handler +#pragma weak comp2_handler = null_handler +#pragma weak sysctl_handler = null_handler +#pragma weak flash_handler = null_handler +#pragma weak gpiof_handler = null_handler +#pragma weak gpiog_handler = null_handler +#pragma weak gpioh_handler = null_handler +#pragma weak uart2_handler = null_handler +#pragma weak ssi1_handler = null_handler +#pragma weak timer3a_handler = null_handler +#pragma weak timer3b_handler = null_handler +#pragma weak i2c1_handler = null_handler +#pragma weak qei1_handler = null_handler +#pragma weak can0_handler = null_handler +#pragma weak can1_handler = null_handler +#pragma weak can2_handler = null_handler +#pragma weak eth_handler = null_handler +#pragma weak hibernate_handler = null_handler +#pragma weak usb0_handler = null_handler +#pragma weak pwm0_3_handler = null_handler +#pragma weak udma_handler = null_handler +#pragma weak udmaerr_handler = null_handler +#pragma weak adc1ss0_handler = null_handler +#pragma weak adc1ss1_handler = null_handler +#pragma weak adc1ss2_handler = null_handler +#pragma weak adc1ss3_handler = null_handler +#pragma weak i2s0_handler = null_handler +#pragma weak epi0_handler = null_handler +#pragma weak gpioj_handler = null_handler +#pragma weak gpiok_handler = null_handler +#pragma weak gpiol_handler = null_handler +#pragma weak ssi2_handler = null_handler +#pragma weak ssi3_handler = null_handler +#pragma weak uart3_handler = null_handler +#pragma weak uart4_handler = null_handler +#pragma weak uart5_handler = null_handler +#pragma weak uart6_handler = null_handler +#pragma weak uart7_handler = null_handler +#pragma weak i2c2_handler = null_handler +#pragma weak i2c3_handler = null_handler +#pragma weak timer4a_handler = null_handler +#pragma weak timer4b_handler = null_handler +#pragma weak timer5a_handler = null_handler +#pragma weak timer5b_handler = null_handler +#pragma weak wtimer0a_handler = null_handler +#pragma weak wtimer0b_handler = null_handler +#pragma weak wtimer1a_handler = null_handler +#pragma weak wtimer1b_handler = null_handler +#pragma weak wtimer2a_handler = null_handler +#pragma weak wtimer2b_handler = null_handler +#pragma weak wtimer3a_handler = null_handler +#pragma weak wtimer3b_handler = null_handler +#pragma weak wtimer4a_handler = null_handler +#pragma weak wtimer4b_handler = null_handler +#pragma weak wtimer5a_handler = null_handler +#pragma weak wtimer5b_handler = null_handler +#pragma weak sysexc_handler = null_handler +#pragma weak peci0_handler = null_handler +#pragma weak lpc0_handler = null_handler +#pragma weak i2c4_handler = null_handler +#pragma weak i2c5_handler = null_handler +#pragma weak gpiom_handler = null_handler +#pragma weak gpion_handler = null_handler +#pragma weak fan0_handler = null_handler +#pragma weak gpiop0_handler = null_handler +#pragma weak gpiop1_handler = null_handler +#pragma weak gpiop2_handler = null_handler +#pragma weak gpiop3_handler = null_handler +#pragma weak gpiop4_handler = null_handler +#pragma weak gpiop5_handler = null_handler +#pragma weak gpiop6_handler = null_handler +#pragma weak gpiop7_handler = null_handler +#pragma weak gpioq0_handler = null_handler +#pragma weak gpioq1_handler = null_handler +#pragma weak gpioq2_handler = null_handler +#pragma weak gpioq3_handler = null_handler +#pragma weak gpioq4_handler = null_handler +#pragma weak gpioq5_handler = null_handler +#pragma weak gpioq6_handler = null_handler +#pragma weak gpioq7_handler = null_handler +#pragma weak pwm1_0_handler = null_handler +#pragma weak pwm1_1_handler = null_handler +#pragma weak pwm1_2_handler = null_handler +#pragma weak pwm1_3_handler = null_handler +#pragma weak pwm1_fault_handler = null_handler -- cgit v1.2.3 From f94d71efee4afd49e475f056707fa34b0820e664 Mon Sep 17 00:00:00 2001 From: Thomas W. Barr Date: Mon, 8 Oct 2012 16:42:47 -0500 Subject: add _end and __end symbols for compatibility with code written against CodeSourcery linkers --- lib/lm3s/libopencm3_lm3s.ld | 2 ++ 1 file changed, 2 insertions(+) (limited to 'lib') diff --git a/lib/lm3s/libopencm3_lm3s.ld b/lib/lm3s/libopencm3_lm3s.ld index ceb391a..4aaf4d9 100644 --- a/lib/lm3s/libopencm3_lm3s.ld +++ b/lib/lm3s/libopencm3_lm3s.ld @@ -77,6 +77,8 @@ SECTIONS . = ALIGN(4); end = .; + _end = .; + __end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); -- cgit v1.2.3 From 0834f41383df854c30f4db973c3632439d7d9cca Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Tue, 9 Oct 2012 11:50:57 +1030 Subject: stm32f1: Add object files to Makefile to include new modules into lib. Correct typo in pwr.c Add two new functions to timer.c to preset the counter (for use with deadman style timeouts) and to identify an interrupt source. Also noticed lib/makefile.include didn't clean lib/stm32, which isn't a target. Added a fix. --- include/libopencm3/stm32/timer.h | 2 ++ lib/Makefile.include | 2 +- lib/stm32/f1/Makefile | 2 +- lib/stm32/f1/pwr.c | 10 +++++----- lib/stm32/f1/timer.c | 39 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 48 insertions(+), 7 deletions(-) (limited to 'lib') diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index b6f8949..61d40e9 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -1028,6 +1028,7 @@ BEGIN_DECLS void timer_reset(u32 timer_peripheral); void timer_enable_irq(u32 timer_peripheral, u32 irq); void timer_disable_irq(u32 timer_peripheral, u32 irq); +bool timer_return_interrupt_source(u32 timer_peripheral, u32 flag); bool timer_get_flag(u32 timer_peripheral, u32 flag); void timer_clear_flag(u32 timer_peripheral, u32 flag); void timer_set_mode(u32 timer_peripheral, u32 clock_div, @@ -1090,6 +1091,7 @@ void timer_set_break_lock(u32 timer_peripheral, u32 lock); void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); void timer_generate_event(u32 timer_peripheral, u32 event); u32 timer_get_counter(u32 timer_peripheral); +void timer_set_counter(u32 timer_peripheral, u32 count); void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt); void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc); diff --git a/lib/Makefile.include b/lib/Makefile.include index f2f1f7b..9fbea24 100644 --- a/lib/Makefile.include +++ b/lib/Makefile.include @@ -40,7 +40,7 @@ $(SRCLIBDIR)/$(LIBNAME).ld: $(LIBNAME).ld clean: @printf " CLEAN lib/stm32/f1\n" - $(Q)rm -f *.o *.d + $(Q)rm -f *.o *.d ../*.o ../*.d $(Q)rm -f $(SRCLIBDIR)/$(LIBNAME).a $(Q)rm -f $(SRCLIBDIR)/$(LIBNAME).ld $(Q)rm -f $(SRCLIBDIR)/$(LIBNAME)_rom_to_ram.ld diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 4fdbf43..a2f7bf2 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -31,7 +31,7 @@ ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o assert.o + timer.o usb_f107.o desig.o crc.o assert.o dac.o iwdg.o pwr.o VPATH += ../../usb:../:../../cm3 diff --git a/lib/stm32/f1/pwr.c b/lib/stm32/f1/pwr.c index 83c3dba..451ed1c 100644 --- a/lib/stm32/f1/pwr.c +++ b/lib/stm32/f1/pwr.c @@ -157,7 +157,7 @@ The wakeup pin is used for waking the processor from standby mode. void pwr_enable_wakeup_pin(void) { - PWR_CSR |= PWR_CR_EWUP; + PWR_CSR |= PWR_CSR_EWUP; } /*---------------------------------------------------------------------------*/ @@ -168,7 +168,7 @@ The wakeup pin is used for general purpose I/O. void pwr_disable_wakeup_pin(void) { - PWR_CSR &= ~PWR_CR_EWUP; + PWR_CSR &= ~PWR_CSR_EWUP; } /*---------------------------------------------------------------------------*/ @@ -183,7 +183,7 @@ threshold. bool pwr_voltage_high(void) { - return (PWR_CSR & PWR_CR_PVDO); + return (PWR_CSR & PWR_CSR_PVDO); } /*---------------------------------------------------------------------------*/ @@ -197,7 +197,7 @@ cleared by software (see @ref pwr_clear_standby_flag). bool pwr_get_standby_flag(void) { - return (PWR_CSR & PWR_CR_SBF); + return (PWR_CSR & PWR_CSR_SBF); } /*---------------------------------------------------------------------------*/ @@ -211,7 +211,7 @@ cleared by software (see @ref pwr_clear_wakeup_flag). bool pwr_get_wakeup_flag(void) { - return (PWR_CSR & PWR_CR_WUF); + return (PWR_CSR & PWR_CSR_WUF); } /**@}*/ diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c index c5ea921..384eaaf 100644 --- a/lib/stm32/f1/timer.c +++ b/lib/stm32/f1/timer.c @@ -198,6 +198,31 @@ void timer_disable_irq(u32 timer_peripheral, u32 irq) TIM_DIER(timer_peripheral) &= ~irq; } +/*---------------------------------------------------------------------------*/ +/** @brief Return Interrupt Source. + +Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or COMIF +for advanced timers) was set and the interrupt was enabled. If the specified flag +is not an interrupt flag, the function returns false. + +@todo Timers 6-7, 9-14 have fewer interrupts, but invalid flags are not caught here. + +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] flag Unsigned int32. Status register flag @ref tim_sr_values. +@returns boolean: flag set. +*/ + +bool timer_interrupt_source(u32 timer_peripheral, u32 flag) +{ +/* flag not set or interrupt disabled or not an interrupt source */ + if (((TIM_SR(timer_peripheral) & TIM_DIER(timer_peripheral) & flag) == 0) || + (flag > TIM_SR_BIF)) return false; +/* Only an interrupt source for advanced timers */ + if ((flag == TIM_SR_BIF) || (flag == TIM_SR_COMIF)) + return ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)); + return true; +} + /*---------------------------------------------------------------------------*/ /** @brief Read a Status Flag. @@ -1671,6 +1696,20 @@ u32 timer_get_counter(u32 timer_peripheral) return TIM_CNT(timer_peripheral); } +/*---------------------------------------------------------------------------*/ +/** @brief Set Counter + +Set the value of a timer's counter register contents. + +@param[in] timer_peripheral Unsigned int32. Timer register address base +@param[in] Unsigned int32. Counter value. +*/ + +void timer_set_counter(u32 timer_peripheral, u32 count) +{ + TIM_CNT(timer_peripheral) = count; +} + /*---------------------------------------------------------------------------*/ /** @brief Set Input Capture Filter Parameters -- cgit v1.2.3 From 6ee8e44bd7743806eeb1ba0983fd1113c519f71c Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 10 Oct 2012 21:31:31 +1030 Subject: Initial documentation for stm32/usart.c, usart.h Some minor documentation corrections to timer.h --- doc/stm32f1/DoxygenLayout_stm32f1.xml | 2 +- include/libopencm3/stm32/timer.h | 26 ++--- include/libopencm3/stm32/usart.h | 77 ++++++++++++-- lib/stm32/usart.c | 187 ++++++++++++++++++++++++++++++++++ 4 files changed, 267 insertions(+), 25 deletions(-) (limited to 'lib') diff --git a/doc/stm32f1/DoxygenLayout_stm32f1.xml b/doc/stm32f1/DoxygenLayout_stm32f1.xml index 912f2c4..6ed9bba 100644 --- a/doc/stm32f1/DoxygenLayout_stm32f1.xml +++ b/doc/stm32f1/DoxygenLayout_stm32f1.xml @@ -6,7 +6,7 @@ - + diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index 61d40e9..4977674 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -1,6 +1,6 @@ /** @defgroup STM32F_tim_defines Timers Defines -@brief libopencm3 Defined Constants and Types for the STM32F1xx Timers +@brief libopencm3 Defined Constants and Types for the STM32 Timers @ingroup STM32F_defines @@ -44,7 +44,7 @@ LGPL License Terms @ref lgpl_license /* Timer register base adresses (for convenience) */ /****************************************************************************/ /** @defgroup tim_reg_base Timer register base addresses -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM1 TIM1_BASE @@ -251,7 +251,7 @@ LGPL License Terms @ref lgpl_license /****************************************************************************/ /** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* CKD[1:0]: Clock division */ @@ -267,7 +267,7 @@ LGPL License Terms @ref lgpl_license /* CMS[1:0]: Center-aligned mode selection */ /****************************************************************************/ /** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR1_CMS_EDGE (0x0 << 5) @@ -280,7 +280,7 @@ LGPL License Terms @ref lgpl_license /* DIR: Direction */ /****************************************************************************/ /** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR1_DIR_UP (0 << 4) @@ -303,7 +303,7 @@ LGPL License Terms @ref lgpl_license /****************************************************************************/ /** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* OIS4:*//** Output idle state 4 (OC4 output) */ @@ -335,7 +335,7 @@ LGPL License Terms @ref lgpl_license /* MMS[2:0]: Master mode selection */ /****************************************************************************/ /** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR2_MMS_RESET (0x0 << 4) @@ -397,7 +397,7 @@ LGPL License Terms @ref lgpl_license /* TS[2:0]: Trigger selection */ /** @defgroup tim_ts TS Trigger selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /** Internal Trigger 0 (ITR0) */ @@ -421,7 +421,7 @@ LGPL License Terms @ref lgpl_license /* SMS[2:0]: Slave mode selection */ /** @defgroup tim_sms SMS Slave mode selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /** Slave mode disabled */ @@ -451,7 +451,7 @@ and generates an update of the registers. */ /****************************************************************************/ /** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* TDE:*//** Trigger DMA request enable */ @@ -503,7 +503,7 @@ and generates an update of the registers. */ /* --- TIMx_SR values ------------------------------------------------------ */ /****************************************************************************/ /** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ @@ -548,7 +548,7 @@ and generates an update of the registers. */ /****************************************************************************/ /** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ @@ -908,7 +908,7 @@ and generates an update of the registers. */ /* LOCK[1:0]: Lock configuration */ /****************************************************************************/ /** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_BDTR_LOCK_OFF (0x0 << 8) diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 9ec6c3d..911781b 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -1,3 +1,18 @@ +/** @defgroup STM32F_usart_defines USART Defines + +@brief libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter + +@ingroup STM32F_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 1 September 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * @@ -17,6 +32,8 @@ * along with this library. If not, see . */ +/**@{*/ + #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H @@ -25,9 +42,15 @@ /* --- Convenience macros -------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_reg_base USART register base addresses +@ingroup STM32F_usart_defines + +@{*/ #define USART1 USART1_BASE #define USART2 USART2_BASE #define USART3 USART3_BASE +/**@}*/ #define UART4 UART4_BASE #define UART5 UART5_BASE @@ -90,37 +113,43 @@ #define UART5_GTPR USART_GTPR(UART5_BASE) /* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines -/* CTS: CTS flag */ -/* Note: N/A on UART4/5 */ +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ #define USART_SR_CTS (1 << 9) -/* LBD: LIN break detection flag */ +/** LBD: LIN break detection flag */ #define USART_SR_LBD (1 << 8) -/* TXE: Transmit data buffer empty */ +/** TXE: Transmit data buffer empty */ #define USART_SR_TXE (1 << 7) -/* TC: Transmission complete */ +/** TC: Transmission complete */ #define USART_SR_TC (1 << 6) -/* RXNE: Read data register not empty */ +/** RXNE: Read data register not empty */ #define USART_SR_RXNE (1 << 5) -/* IDLE: Idle line detected */ +/** IDLE: Idle line detected */ #define USART_SR_IDLE (1 << 4) -/* ORE: Overrun error */ +/** ORE: Overrun error */ #define USART_SR_ORE (1 << 3) -/* NE: Noise error flag */ +/** NE: Noise error flag */ #define USART_SR_NE (1 << 2) -/* FE: Framing error */ +/** FE: Framing error */ #define USART_SR_FE (1 << 1) -/* PE: Parity error */ +/** PE: Parity error */ #define USART_SR_PE (1 << 0) +/**@}*/ /* --- USART_DR values ----------------------------------------------------- */ @@ -269,27 +298,51 @@ /* --- Convenience defines ------------------------------------------------- */ /* CR1_PCE / CR1_PS combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_parity USART Parity Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_PARITY_NONE 0x00 #define USART_PARITY_EVEN USART_CR1_PCE #define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) +/**@}*/ #define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) /* CR1_TE/CR1_RE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_MODE_RX USART_CR1_RE #define USART_MODE_TX USART_CR1_TE #define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +/**@}*/ #define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) +/****************************************************************************/ +/** @defgroup usart_cr2_stopbits USART Stop Bit Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ #define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ #define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ #define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ +/**@}*/ /* CR3_CTSE/CR3_RTSE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_FLOWCONTROL_NONE 0x00 #define USART_FLOWCONTROL_RTS USART_CR3_RTSE #define USART_FLOWCONTROL_CTS USART_CR3_CTSE #define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +/**@}*/ #define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) /* --- Function prototypes ------------------------------------------------- */ @@ -318,3 +371,5 @@ void usart_disable_tx_dma(u32 usart); END_DECLS #endif +/**@}*/ + diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c index 1d0ea9b..2958d7c 100644 --- a/lib/stm32/usart.c +++ b/lib/stm32/usart.c @@ -1,3 +1,22 @@ +/** @defgroup STM32F1xx_usart_file USART + +@ingroup STM32F_files + +@brief libopencm3 STM32F USART + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 30 August 2012 + +This library supports the USART/UART in the STM32F series +of ARM Cortex Microcontrollers by ST Microelectronics. + +Devices can have up to 3 USARTs and 2 UARTs. + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,6 +36,8 @@ * along with this library. If not, see . */ +/**@{*/ + #include #if defined(STM32F1) @@ -29,6 +50,20 @@ # error "stm32 family not defined." #endif +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Baudrate. + +The baud rate is computed from the APB high-speed prescaler clock (for USART1) +or the APB low-speed prescaler clock (for other USARTs). These values must +be correctly set before calling this function (refer to the rcc_clock_setup-* +functions in RCC). + +@todo Add support for USART6 and oversampling in F2/F4 + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] baud unsigned 32 bit. Baud rate specified in Hz. +*/ + void usart_set_baudrate(u32 usart, u32 baud) { u32 clock = rcc_ppre1_frequency; @@ -59,6 +94,16 @@ void usart_set_baudrate(u32 usart, u32 baud) USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Word Length. + +The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit +if parity is enabled, in which case the data length will be 7 or 8 bits respectively. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] bits unsigned 32 bit. Word length in bits 8 or 9. +*/ + void usart_set_databits(u32 usart, u32 bits) { if (bits == 8) @@ -67,6 +112,15 @@ void usart_set_databits(u32 usart, u32 bits) USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Stop Bit(s). + +The stop bits are specified as 0.5, 1, 1.5 or 2. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits. +*/ + void usart_set_stopbits(u32 usart, u32 stopbits) { u32 reg32; @@ -76,6 +130,15 @@ void usart_set_stopbits(u32 usart, u32 stopbits) USART_CR2(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Parity. + +The parity bit can be selected as none, even or odd. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity. +*/ + void usart_set_parity(u32 usart, u32 parity) { u32 reg32; @@ -85,6 +148,15 @@ void usart_set_parity(u32 usart, u32 parity) USART_CR1(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Rx/Tx Mode. + +The mode can be selected as Rx only, Tx only or Rx+Tx. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode. +*/ + void usart_set_mode(u32 usart, u32 mode) { u32 reg32; @@ -94,6 +166,15 @@ void usart_set_mode(u32 usart, u32 mode) USART_CR1(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Hardware Flow Control. + +The flow control bit can be selected as none, RTS, CTS or RTS+CTS. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol. +*/ + void usart_set_flow_control(u32 usart, u32 flowcontrol) { u32 reg32; @@ -103,46 +184,112 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol) USART_CR3(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable(u32 usart) { USART_CR1(usart) |= USART_CR1_UE; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Disable. + +At the end of the current frame, the USART is disabled to reduce power. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable(u32 usart) { USART_CR1(usart) &= ~USART_CR1_UE; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Send a Data Word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] data unsigned 16 bit. +*/ + void usart_send(u32 usart, u16 data) { /* Send data. */ USART_DR(usart) = (data & USART_DR_MASK); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Read a Received Data Word. + +If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@returns unsigned 16 bit data word. +*/ + u16 usart_recv(u32 usart) { /* Receive data. */ return USART_DR(usart) & USART_DR_MASK; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Wait for Transmit Data Buffer Empty + +Blocks until the transmit data buffer becomes empty and is ready to accept the +next data word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_wait_send_ready(u32 usart) { /* Wait until the data has been transferred into the shift register. */ while ((USART_SR(usart) & USART_SR_TXE) == 0); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Wait for Received Data Available + +Blocks until the receive data buffer holds a valid received data word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_wait_recv_ready(u32 usart) { /* Wait until the data is ready to be received. */ while ((USART_SR(usart) & USART_SR_RXNE) == 0); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Send Data Word with Blocking + +Blocks until the transmit data buffer becomes empty then writes the next data word +for transmission. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] data unsigned 16 bit. +*/ + void usart_send_blocking(u32 usart, u16 data) { usart_wait_send_ready(usart); usart_send(usart, data); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Read a Received Data Word with Blocking. + +Wait until a data word has been received then return the word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@returns unsigned 16 bit data word. +*/ + u16 usart_recv_blocking(u32 usart) { usart_wait_recv_ready(usart); @@ -150,22 +297,62 @@ u16 usart_recv_blocking(u32 usart) return usart_recv(usart); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver DMA Enable. + +DMA is available on: +@li USART1 Rx DMA1 channel 5. +@li USART2 Rx DMA1 channel 6. +@li USART3 Rx DMA1 channel 3. +@li UART4 Rx DMA2 channel 3. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable_rx_dma(u32 usart) { USART_CR3(usart) |= USART_CR3_DMAR; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver DMA Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable_rx_dma(u32 usart) { USART_CR3(usart) &= ~USART_CR3_DMAR; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter DMA Enable. + +DMA is available on: +@li USART1 Tx DMA1 channel 4. +@li USART2 Tx DMA1 channel 7. +@li USART3 Tx DMA1 channel 2. +@li UART4 Tx DMA2 channel 5. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable_tx_dma(u32 usart) { USART_CR3(usart) |= USART_CR3_DMAT; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter DMA Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable_tx_dma(u32 usart) { USART_CR3(usart) &= ~USART_CR3_DMAT; } + + +/**@}*/ + -- cgit v1.2.3 From c4b7e2a76a52a53e0ba6ccd1a6f9d699036bea48 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 10 Oct 2012 21:37:39 +1030 Subject: Additional stm32/usart.c functions to enable/disable Rx/Tx interrupts, return a status flag and check for interrupt source. --- include/libopencm3/stm32/usart.h | 6 +++ lib/stm32/usart.c | 86 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) (limited to 'lib') diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 911781b..088e67b 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -367,6 +367,12 @@ void usart_enable_rx_dma(u32 usart); void usart_disable_rx_dma(u32 usart); void usart_enable_tx_dma(u32 usart); void usart_disable_tx_dma(u32 usart); +void usart_enable_rx_interrupt(u32 usart); +void usart_disable_rx_interrupt(u32 usart); +void usart_enable_tx_interrupt(u32 usart); +void usart_disable_tx_interrupt(u32 usart); +bool usart_get_flag(u32 usart, u32 flag); +bool usart_get_interrupt_source(u32 usart, u32 flag); END_DECLS diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c index 2958d7c..5cf861b 100644 --- a/lib/stm32/usart.c +++ b/lib/stm32/usart.c @@ -353,6 +353,92 @@ void usart_disable_tx_dma(u32 usart) USART_CR3(usart) &= ~USART_CR3_DMAT; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver Interrupt Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_rx_interrupt(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_RXNEIE; +} + + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver Interrupt Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_rx_interrupt(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_RXNEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter Interrupt Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_tx_interrupt(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_TXEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter Interrupt Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_tx_interrupt(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_TXEIE; +} + + +/*---------------------------------------------------------------------------*/ +/** @brief USART Read a Status Flag. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. +@returns boolean: flag set. +*/ + +bool usart_get_flag(u32 usart, u32 flag) +{ + return ((USART_SR(usart) & flag) != 0); +} + +/*---------------------------------------------------------------------------*/ +/** @brief USART Return Interrupt Source. + +Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was +set and the interrupt was enabled. If the specified flag is not an interrupt +flag, the function returns false. + +@todo These are the most important interrupts likely to be used. Others +relating to LIN break, and error conditions in multibuffer communication, need +to be added for completeness. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. +@returns boolean: flag and interrupt enable both set. +*/ + +bool usart_get_interrupt_source(u32 usart, u32 flag) +{ +u32 flag_set = (USART_SR(usart) & flag); +/* IDLE, RXNE, TC, TXE interrupts */ + if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) + return ((flag_set & USART_CR1(usart)) != 0); +/* Overrun error */ + else if (flag == USART_SR_ORE) + return (flag_set && (USART_CR3(usart) & USART_CR3_CTSIE)); + return (false); +} /**@}*/ -- cgit v1.2.3 From 0c779512d6db7fd513c8982059b869df0be29210 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Mon, 15 Oct 2012 14:34:33 +1030 Subject: Initial documentation for SPI, I2C and CRC (no code changes) --- include/libopencm3/stm32/crc.h | 14 ++ include/libopencm3/stm32/i2c.h | 38 ++++ include/libopencm3/stm32/spi.h | 62 +++++++ lib/stm32/crc.c | 46 ++++- lib/stm32/i2c.c | 165 +++++++++++++++++ lib/stm32/spi.c | 408 ++++++++++++++++++++++++++++++++++++++++- 6 files changed, 730 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h index 3848191..aa30182 100644 --- a/include/libopencm3/stm32/crc.h +++ b/include/libopencm3/stm32/crc.h @@ -1,3 +1,17 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32F CRC Generator + +@ingroup STM32F_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h index 13257eb..a59c420 100644 --- a/include/libopencm3/stm32/i2c.h +++ b/include/libopencm3/stm32/i2c.h @@ -1,3 +1,19 @@ +/** @defgroup i2c_defines I2C Defines + +@ingroup STM32F_defines + +@brief libopencm3 Defined Constants and Types for the STM32 I2C + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * @@ -23,11 +39,19 @@ #include #include +/**@{*/ + /* --- Convenience macros -------------------------------------------------- */ /* I2C register base adresses (for convenience) */ +/****************************************************************************/ +/** @defgroup i2c_reg_base I2C register base address +@ingroup i2c_defines + +@{*/ #define I2C1 I2C1_BASE #define I2C2 I2C2_BASE +/**@}*/ /* --- I2C registers ------------------------------------------------------- */ @@ -146,6 +170,11 @@ /* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ /* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ +/****************************************************************************/ +/** @defgroup i2c_clock I2C clock frequency settings +@ingroup i2c_defines + +@{*/ #define I2C_CR2_FREQ_2MHZ 0x02 #define I2C_CR2_FREQ_3MHZ 0x03 #define I2C_CR2_FREQ_4MHZ 0x04 @@ -181,6 +210,7 @@ #define I2C_CR2_FREQ_34MHZ 0x22 #define I2C_CR2_FREQ_35MHZ 0x23 #define I2C_CR2_FREQ_36MHZ 0x24 +/**@}*/ /* --- I2Cx_OAR1 values ---------------------------------------------------- */ @@ -311,8 +341,14 @@ /* --- I2C const definitions ----------------------------------------------- */ +/****************************************************************************/ +/** @defgroup i2c_rw I2C Read/Write bit +@ingroup i2c_defines + +@{*/ #define I2C_WRITE 0 #define I2C_READ 1 +/**@}*/ /* --- I2C funtion prototypes----------------------------------------------- */ @@ -336,3 +372,5 @@ void i2c_send_data(u32 i2c, u8 data); END_DECLS #endif +/**@}*/ + diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h index 11ba820..f23df3a 100644 --- a/include/libopencm3/stm32/spi.h +++ b/include/libopencm3/stm32/spi.h @@ -1,3 +1,19 @@ +/** @defgroup spi_defines SPI Defines + +@ingroup STM32F_defines + +@brief libopencm3 Defined Constants and Types for the STM32 SPI + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * @@ -23,13 +39,21 @@ #include #include +/**@{*/ + /* Registers can be accessed as 16bit or 32bit values. */ /* --- Convenience macros -------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup spi_reg_base SPI Register base address +@ingroup spi_defines + +@{*/ #define SPI1 SPI1_BASE #define SPI2 SPI2_I2S_BASE #define SPI3 SPI3_I2S_BASE +/**@}*/ /* --- SPI registers ------------------------------------------------------- */ @@ -110,8 +134,14 @@ #define SPI_CR1_CRCNEXT (1 << 12) /* DFF: Data frame format */ +/****************************************************************************/ +/** @defgroup spi_dff SPI data frame format +@ingroup spi_defines + +@{*/ #define SPI_CR1_DFF_8BIT (0 << 11) #define SPI_CR1_DFF_16BIT (1 << 11) +/**@}*/ #define SPI_CR1_DFF (1 << 11) /* RXONLY: Receive only */ @@ -124,13 +154,24 @@ #define SPI_CR1_SSI (1 << 8) /* LSBFIRST: Frame format */ +/****************************************************************************/ +/** @defgroup spi_lsbfirst SPI lsb/msb first +@ingroup spi_defines + +@{*/ #define SPI_CR1_MSBFIRST (0 << 7) #define SPI_CR1_LSBFIRST (1 << 7) +/**@}*/ /* SPE: SPI enable */ #define SPI_CR1_SPE (1 << 6) /* BR[2:0]: Baud rate control */ +/****************************************************************************/ +/** @defgroup spi_baudrate SPI peripheral baud rates +@ingroup spi_defines + +@{*/ #define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) @@ -139,6 +180,12 @@ #define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) +/**@}*/ +/****************************************************************************/ +/** @defgroup spi_br_pre SPI peripheral baud rate prescale values +@ingroup spi_defines + +@{*/ #define SPI_CR1_BR_FPCLK_DIV_2 0x0 #define SPI_CR1_BR_FPCLK_DIV_4 0x1 #define SPI_CR1_BR_FPCLK_DIV_8 0x2 @@ -147,18 +194,31 @@ #define SPI_CR1_BR_FPCLK_DIV_64 0x5 #define SPI_CR1_BR_FPCLK_DIV_128 0x6 #define SPI_CR1_BR_FPCLK_DIV_256 0x7 +/**@}*/ /* MSTR: Master selection */ #define SPI_CR1_MSTR (1 << 2) /* CPOL: Clock polarity */ +/****************************************************************************/ +/** @defgroup spi_cpol SPI clock polarity +@ingroup spi_defines + +@{*/ #define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) #define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) +/**@}*/ #define SPI_CR1_CPOL (1 << 1) /* CPHA: Clock phase */ +/****************************************************************************/ +/** @defgroup spi_cpha SPI clock phase +@ingroup spi_defines + +@{*/ #define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) #define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) +/**@}*/ #define SPI_CR1_CPHA (1 << 0) /* --- SPI_CR2 values ------------------------------------------------------ */ @@ -347,4 +407,6 @@ void spi_disable_rx_dma(u32 spi); END_DECLS +/**@}*/ + #endif diff --git a/lib/stm32/crc.c b/lib/stm32/crc.c index bbbe1fd..bd9e8d2 100644 --- a/lib/stm32/crc.c +++ b/lib/stm32/crc.c @@ -1,3 +1,17 @@ +/** @defgroup crc_file CRC + +@ingroup STM32F_files + +@brief libopencm3 STM32Fxxx CRC + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Karl Palsson + +@date 15 October 2012 + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -19,11 +33,30 @@ #include +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Reset. + +Reset the CRC unit and forces the data register to all 1s. + +*/ + void crc_reset(void) { CRC_CR |= CRC_CR_RESET; } +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Calculate. + +Writes a data word to the register, the write operation stalling until the +computation is complete. + +@param[in] data Unsigned int32. +@returns int32 Computed CRC result +*/ + u32 crc_calculate(u32 data) { CRC_DR = data; @@ -31,6 +64,16 @@ u32 crc_calculate(u32 data) return CRC_DR; } +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Calculate of a Block of Data. + +Writes data words consecutively to the register, the write operation stalling +until the computation of each word is complete. + +@param[in] datap Unsigned int32. pointer to an array of 32 bit data words. +@returns int32 Final computed CRC result +*/ + u32 crc_calculate_block(u32 *datap, int size) { int i; @@ -39,6 +82,5 @@ u32 crc_calculate_block(u32 *datap, int size) } return CRC_DR; } - - +/**@}*/ diff --git a/lib/stm32/i2c.c b/lib/stm32/i2c.c index 87d9061..e1d3a09 100644 --- a/lib/stm32/i2c.c +++ b/lib/stm32/i2c.c @@ -1,3 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32F_files + +@brief libopencm3 STM32Fxxx I2C + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 15 October 2012 + +Devices can have up to two I2C peripherals. The peripherals support SMBus and +PMBus variants. + +A peripheral begins after reset in Slave mode. To become a Master a start +condition must be generated. The peripheral will remain in Master mode unless +a multimaster contention is lost or a stop condition is generated. + +@todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status +register access, Error conditions + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -20,6 +45,17 @@ #include #include +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Reset. + +The I2C peripheral and all its associated configuration registers are placed in the +reset condition. The reset is effected via the RCC peripheral reset system. + +@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. +*/ + void i2c_reset(u32 i2c) { switch (i2c) { @@ -34,26 +70,69 @@ void i2c_reset(u32 i2c) } } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Peripheral Enable. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_peripheral_enable(u32 i2c) { I2C_CR1(i2c) |= I2C_CR1_PE; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Peripheral Disable. + +This must not be reset while in Master mode until a communication has finished. +In Slave mode, the peripheral is disabled only after communication has ended. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_peripheral_disable(u32 i2c) { I2C_CR1(i2c) &= ~I2C_CR1_PE; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Start Condition. + +If in Master mode this will cause a restart condition to occur at the end of the +current transmission. If in Slave mode, this will initiate a start condition +when the current bus activity is completed. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_send_start(u32 i2c) { I2C_CR1(i2c) |= I2C_CR1_START; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Stop Condition. + +After the current byte transfer this will initiate a stop condition if in Master +mode, or simply release the bus if in Slave mode. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_send_stop(u32 i2c) { I2C_CR1(i2c) |= I2C_CR1_STOP; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the 7 bit Slave Address for the Peripheral. + +This sets an address for Slave mode operation, in 7 bit form. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int8. Slave address 0...127. +*/ + void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) { I2C_OAR1(i2c) = (u16)(slave << 1); @@ -61,21 +140,61 @@ void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the 10 bit Slave Address for the Peripheral. + +This sets an address for Slave mode operation, in 10 bit form. + +@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int16. Slave address 0...1023. +*/ + void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) { I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Fast Mode. + +Set the clock frequency to the high clock rate mode (up to 400kHz). The actual +clock frequency must be set with @ref i2c_set_clock_frequency + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_set_fast_mode(u32 i2c) { I2C_CCR(i2c) |= I2C_CCR_FS; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Standard Mode. + +Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual +clock frequency must be set with @ref i2c_set_clock_frequency + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_set_standard_mode(u32 i2c) { I2C_CCR(i2c) &= ~I2C_CCR_FS; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Peripheral Clock Frequency. + +Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that +this is not the I2C bus clock. This is set in conjunction with the Clock +Control register to generate the Master bus clock, see @ref i2c_set_ccr + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock. +*/ + void i2c_set_clock_frequency(u32 i2c, u8 freq) { u16 reg16; @@ -84,6 +203,21 @@ void i2c_set_clock_frequency(u32 i2c, u8 freq) I2C_CR2(i2c) = reg16; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Bus Clock Frequency. + +Set the bus clock frequency. This is a 12 bit number (0...4095) calculated +from the formulae given in the STM32F1 reference manual in the description +of the CCR field. It is a divisor of the peripheral clock frequency +@ref i2c_set_clock_frequency modified by the fast mode setting +@ref i2c_set_fast_mode + +@todo provide additional API assitance to set the clock, eg macros + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095. +*/ + void i2c_set_ccr(u32 i2c, u16 freq) { u16 reg16; @@ -92,17 +226,48 @@ void i2c_set_ccr(u32 i2c, u16 freq) I2C_CCR(i2c) = reg16; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the Rise Time. + +Set the maximum rise time on the bus according to the I2C specification, as 1 +more than the specified rise time in peripheral clock cycles. This is a 6 bit +number. + +@todo provide additional APIP assistance. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] trise Unsigned int16. Rise Time Setting 0...63. +*/ + void i2c_set_trise(u32 i2c, u16 trise) { I2C_TRISE(i2c) = trise; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send the 7-bit Slave Address. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int16. Slave address 0...1023. +@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw. +*/ + void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) { I2C_DR(i2c) = (u8)((slave << 1) | readwrite); } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Data. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] data Unsigned int8. Byte to send. +*/ + void i2c_send_data(u32 i2c, u8 data) { I2C_DR(i2c) = data; } + +/**@}*/ + diff --git a/lib/stm32/spi.c b/lib/stm32/spi.c index 828e123..90675b3 100644 --- a/lib/stm32/spi.c +++ b/lib/stm32/spi.c @@ -1,3 +1,43 @@ +/** @defgroup spi_file SPI + +@ingroup STM32F_files + +@brief libopencm3 STM32Fxxx SPI + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 15 October 2012 + +Devices can have up to three SPI peripherals. The common 4-wire full-duplex +mode of operation is supported, along with 3-wire variants using unidirectional +communication modes or half-duplex bidirectional communication. A variety of +options allows many of the SPI variants to be supported. Multimaster operation +is also supported. A CRC can be generated and checked in hardware. + +@note Some JTAG pins need to be remapped if SPI is to be used. + +@note The I2S protocol shares the SPI hardware so the two protocols cannot be +used at the same time on the same peripheral. + +Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, +LSB first. +@code + spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + SPI_CR1_LSBFIRST); + spi_write(SPI1, 0x55); // 8-bit write + spi_write(SPI1, 0xaa88); // 16-bit write + reg8 = spi_read(SPI1); // 8-bit read + reg16 = spi_read(SPI1); // 16-bit read +@endcode + +@todo need additional functions to aid ISRs in retrieving status + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -41,6 +81,17 @@ * reg16 = spi_read(SPI1); // 16-bit read */ +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Reset. + +The SPI peripheral and all its associated configuration registers are placed in the +reset condition. The reset is effected via the RCC peripheral reset system. + +@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_reset(u32 spi_peripheral) { switch (spi_peripheral) { @@ -59,6 +110,25 @@ void spi_reset(u32 spi_peripheral) } } +/*-----------------------------------------------------------------------------*/ +/** @brief Configure the SPI as Master. + +The SPI peripheral is configured as a master with communication parameters +baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity +and phase. The SPI enable, CRC enable and CRC next controls are not affected. +These must be controlled separately. + +@todo NSS pin handling. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] br Unsigned int32. Baudrate @ref spi_baudrate. +@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. +@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. +@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. +@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst. +@returns int. Error code. +*/ + int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) { u32 reg32 = SPI_CR1(spi); @@ -82,28 +152,66 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) } /* TODO: Error handling? */ +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable. + +The SPI peripheral is enabled. + +@todo Error handling? + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable(u32 spi) { SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */ } /* TODO: Error handling? */ +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable. + +The SPI peripheral is disabled. + +@todo Follow procedure from section 23.3.8 in the TRM. +(possibly create a "clean disable" function separately) + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable(u32 spi) { u32 reg32; - /* TODO: Follow procedure from section 23.3.8 in the TRM. */ reg32 = SPI_CR1(spi); reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ SPI_CR1(spi) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write. + +Data is written to the SPI interface. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +*/ + void spi_write(u32 spi, u16 data) { /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR(spi) = data; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write with Blocking. + +Data is written to the SPI interface after the previous write transfer has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +*/ + void spi_send(u32 spi, u16 data) { /* Wait for transfer finished. */ @@ -114,6 +222,15 @@ void spi_send(u32 spi, u16 data) SPI_DR(spi) = data; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Read. + +Data is read from the SPI interface after the incoming transfer has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@returns data Unsigned int16. 8 or 16 bit data. +*/ + u16 spi_read(u32 spi) { /* Wait for transfer finished. */ @@ -124,6 +241,17 @@ u16 spi_read(u32 spi) return SPI_DR(spi); } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write and Read Exchange. + +Data is written to the SPI interface, then a read is done after the incoming transfer +has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +@returns data Unsigned int16. 8 or 16 bit data. +*/ + u16 spi_xfer(u32 spi, u16 data) { spi_write(spi, data); @@ -136,98 +264,251 @@ u16 spi_xfer(u32 spi, u16 data) return SPI_DR(spi); } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire). + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_bidirectional_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Unidirectional Mode. + +The SPI peripheral is set for unidirectional transfers. This is used in full duplex +mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a +unidirectional data wire. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_unidirectional_mode(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Receive Only Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire), and is placed in a receive state. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_bidirectional_receive_only_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Receive Only Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire), and is placed in a transmit state. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_bidirectional_transmit_only_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; SPI_CR1(spi) |= SPI_CR1_BIDIOE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the CRC. + +The SPI peripheral is set to use a CRC field for transmit and receive. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_crc(u32 spi) { SPI_CR1(spi) |= SPI_CR1_CRCEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the CRC. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_crc(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_CRCEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Next Transmit is a Data Word + +The next transmission to take place is a data word from the transmit buffer. +This must be called before transmission to distinguish between sending +of a data or CRC word. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_next_tx_from_buffer(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Next Transmit is a CRC Word + +The next transmission to take place is a crc word from the hardware crc unit. +This must be called before transmission to distinguish between sending +of a data or CRC word. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_next_tx_from_crc(u32 spi) { SPI_CR1(spi) |= SPI_CR1_CRCNEXT; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Data Frame Format to 8 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_dff_8bit(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_DFF; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Data Frame Format to 16 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_dff_16bit(u32 spi) { SPI_CR1(spi) |= SPI_CR1_DFF; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Full Duplex (3-wire) Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_full_duplex_mode(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_RXONLY; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_receive_only_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_RXONLY; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Slave Management by Hardware + +In slave mode the NSS hardware input is used as a select enable for the slave. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_software_slave_management(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_SSM; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Slave Management by Software + +In slave mode the NSS hardware input is replaced by an internal software +enable/disable of the slave (@ref spi_set_nss_high). + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_software_slave_management(u32 spi) { SPI_CR1(spi) |= SPI_CR1_SSM; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Software NSS Signal High + +In slave mode, and only when software slave management is used, this replaces +the NSS signal with a slave select enable signal. + +@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_nss_high(u32 spi) { SPI_CR1(spi) |= SPI_CR1_SSI; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Software NSS Signal Low + +In slave mode, and only when software slave management is used, this replaces +the NSS signal with a slave select disable signal. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_nss_low(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_SSI; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Send LSB First + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_send_lsb_first(u32 spi) { SPI_CR1(spi) |= SPI_CR1_LSBFIRST; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Send MSB First + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_send_msb_first(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Baudrate Prescaler + +@todo Why is this specification different to the spi_init_master baudrate values? + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre. +*/ + void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) { u32 reg32; @@ -240,92 +521,217 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) SPI_CR1(spi) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Master Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_master_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_MSTR; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Slave Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_slave_mode(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_MSTR; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Polarity to High when Idle + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_clock_polarity_1(u32 spi) { SPI_CR1(spi) |= SPI_CR1_CPOL; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Polarity to Low when Idle + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_clock_polarity_0(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_CPOL; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Phase to Capture on Trailing Edge + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_clock_phase_1(u32 spi) { SPI_CR1(spi) |= SPI_CR1_CPHA; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Phase to Capture on Leading Edge + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_clock_phase_0(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_CPHA; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Transmit Buffer Empty Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_tx_buffer_empty_interrupt(u32 spi) { SPI_CR2(spi) |= SPI_CR2_TXEIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Transmit Buffer Empty Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_tx_buffer_empty_interrupt(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_TXEIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Receive Buffer Ready Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) { SPI_CR2(spi) |= SPI_CR2_RXNEIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Receive Buffer Ready Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Error Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_error_interrupt(u32 spi) { SPI_CR2(spi) |= SPI_CR2_ERRIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Error Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_error_interrupt(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_ERRIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the NSS Pin as an Output + +Normally used in master mode to allows the master to place all devices on the +SPI bus into slave mode. Multimaster mode is not possible. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_ss_output(u32 spi) { SPI_CR2(spi) |= SPI_CR2_SSOE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the NSS Pin as an Input + +In master mode this allows the master to sense the presence of other masters. If +NSS is then pulled low the master is placed into slave mode. In slave mode NSS +becomes a slave enable. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_ss_output(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_SSOE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Transmit Transfers via DMA + +This allows transmissions to proceed unattended using DMA to move data to the +transmit buffer as it becomes available. The DMA channels provided for each +SPI peripheral are given in the Technical Manual DMA section. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_tx_dma(u32 spi) { SPI_CR2(spi) |= SPI_CR2_TXDMAEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable Transmit Transfers via DMA + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_tx_dma(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Receive Transfers via DMA + +This allows received data streams to proceed unattended using DMA to move data from +the receive buffer as data becomes available. The DMA channels provided for each +SPI peripheral are given in the Technical Manual DMA section. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_rx_dma(u32 spi) { SPI_CR2(spi) |= SPI_CR2_RXDMAEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable Receive Transfers via DMA + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_rx_dma(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; } + +/**@}*/ -- cgit v1.2.3 From 9c13299f25c617974e7851283b51fbb0307d3e1c Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:20:56 +0200 Subject: unified nvic.c --- lib/cm3/nvic.c | 184 +++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/lpc43xx/nvic.c | 76 ---------------------- lib/stm32/nvic.c | 174 -------------------------------------------------- 3 files changed, 184 insertions(+), 250 deletions(-) create mode 100644 lib/cm3/nvic.c delete mode 100644 lib/lpc43xx/nvic.c delete mode 100644 lib/stm32/nvic.c (limited to 'lib') diff --git a/lib/cm3/nvic.c b/lib/cm3/nvic.c new file mode 100644 index 0000000..db187b3 --- /dev/null +++ b/lib/cm3/nvic.c @@ -0,0 +1,184 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Fergus Noble + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_nvic_file NVIC + +@ingroup CM3_files + +@brief libopencm3 Cortex Nested Vectored Interrupt Controller + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Fergus Noble + +@date 18 August 2012 + +Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults, +systicks etc.) and varying numbers of implementation defined interrupts +(typically peripherial interrupts and DMA). + +@see Cortex-M3 Devices Generic User Guide +@see STM32F10xxx Cortex-M3 programming manual + +LGPL License Terms @ref lgpl_license +*/ +/**@{*/ + +#include +#include + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Enable Interrupt + +Enables a user interrupt. + +@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint +*/ + +void nvic_enable_irq(u8 irqn) +{ + NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Disable Interrupt + +Disables a user interrupt. + +@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint +*/ + +void nvic_disable_irq(u8 irqn) +{ + NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Return Pending Interrupt + +True if the interrupt has occurred and is waiting for service. + +@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint +@return Boolean. Interrupt pending. +*/ + +u8 nvic_get_pending_irq(u8 irqn) +{ + return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Set Pending Interrupt + +Force a user interrupt to a pending state. This has no effect if the interrupt +is already pending. + +@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint +*/ + +void nvic_set_pending_irq(u8 irqn) +{ + NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Clear Pending Interrupt + +Force remove a user interrupt from a pending state. This has no effect if the +interrupt is actively being serviced. + +@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint +*/ + +void nvic_clear_pending_irq(u8 irqn) +{ + NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Return Active Interrupt + +Interrupt has occurred and is currently being serviced. + +@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint +@return Boolean. Interrupt active. +*/ + +u8 nvic_get_active_irq(u8 irqn) +{ + return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Return Enabled Interrupt + +@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint +@return Boolean. Interrupt enabled. +*/ + +u8 nvic_get_irq_enabled(u8 irqn) +{ + return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Set Interrupt Priority + +There are 16 priority levels only, given by the upper four bits of the priority +byte, as required by ARM standards. The priority levels are interpreted according +to the pre-emptive priority grouping set in the SCB Application Interrupt and Reset +Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping. + +@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint +@param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16) +*/ + +void nvic_set_priority(u8 irqn, u8 priority) +{ + /* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the + * negative interrupt numbers assigned to the system interrupts. better + * handling would mean signed integers. */ + if(irqn>=NVIC_IRQ_COUNT) + { + /* Cortex-M system interrupts */ + SCS_SHPR( (irqn&0xF)-4 ) = priority; + }else + { + /* Device specific interrupts */ + NVIC_IPR(irqn) = priority; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief NVIC Software Trigger Interrupt + +Generate an interrupt from software. This has no effect for unprivileged access +unless the privilege level has been elevated through the System Control Registers. + +@param[in] irqn Unsigned int16. Interrupt number (0 ... 239) +*/ + +void nvic_generate_software_interrupt(u16 irqn) +{ + if (irqn <= 239) + NVIC_STIR |= irqn; +} +/**@}*/ diff --git a/lib/lpc43xx/nvic.c b/lib/lpc43xx/nvic.c deleted file mode 100644 index 4793312..0000000 --- a/lib/lpc43xx/nvic.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Fergus Noble - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -#include -#include - -void nvic_enable_irq(u8 irqn) -{ - NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); -} - -void nvic_disable_irq(u8 irqn) -{ - NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); -} - -u8 nvic_get_pending_irq(u8 irqn) -{ - return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -void nvic_set_pending_irq(u8 irqn) -{ - NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); -} - -void nvic_clear_pending_irq(u8 irqn) -{ - NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); -} - -u8 nvic_get_active_irq(u8 irqn) -{ - return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -u8 nvic_get_irq_enabled(u8 irqn) -{ - return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -void nvic_set_priority(u8 irqn, u8 priority) -{ - if(irqn>NVIC_M4_QEI_IRQ) - { - /* Cortex-M system interrupts */ - SCS_SHPR( (irqn&0xF)-4 ) = priority; - }else - { - /* Device specific interrupts */ - NVIC_IPR(irqn) = priority; - } -} - -void nvic_generate_software_interrupt(u8 irqn) -{ - if (irqn <= 239) - NVIC_STIR |= irqn; -} diff --git a/lib/stm32/nvic.c b/lib/stm32/nvic.c deleted file mode 100644 index 84fa674..0000000 --- a/lib/stm32/nvic.c +++ /dev/null @@ -1,174 +0,0 @@ -/** @defgroup STM32F_nvic_file NVIC - -@ingroup STM32F_files - -@brief libopencm3 STM32F Nested Vectored Interrupt Controller - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto -@author @htmlonly © @endhtmlonly 2012 Fergus Noble - -@date 18 August 2012 - -The STM32F series provides up to 68 maskable user interrupts for the STM32F10x -series, and 87 for the STM32F2xx and STM32F4xx series. - -The NVIC registers are defined by the ARM standards but the STM32F series have some -additional limitations -@see Cortex-M3 Devices Generic User Guide -@see STM32F10xxx Cortex-M3 programming manual - -LGPL License Terms @ref lgpl_license -*/ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#include - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Enable Interrupt - -Enables a user interrupt. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -*/ - -void nvic_enable_irq(u8 irqn) -{ - NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Disable Interrupt - -Disables a user interrupt. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -*/ - -void nvic_disable_irq(u8 irqn) -{ - NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Return Pending Interrupt - -True if the interrupt has occurred and is waiting for service. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -@return Boolean. Interrupt pending. -*/ - -u8 nvic_get_pending_irq(u8 irqn) -{ - return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Set Pending Interrupt - -Force a user interrupt to a pending state. This has no effect if the interrupt -is already pending. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -*/ - -void nvic_set_pending_irq(u8 irqn) -{ - NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Clear Pending Interrupt - -Force remove a user interrupt from a pending state. This has no effect if the -interrupt is actively being serviced. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -*/ - -void nvic_clear_pending_irq(u8 irqn) -{ - NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Return Active Interrupt - -Interrupt has occurred and is currently being serviced. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -@return Boolean. Interrupt active. -*/ - -u8 nvic_get_active_irq(u8 irqn) -{ - return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Return Enabled Interrupt - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -@return Boolean. Interrupt enabled. -*/ - -u8 nvic_get_irq_enabled(u8 irqn) -{ - return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Set Interrupt Priority - -There are 16 priority levels only, given by the upper four bits of the priority -byte, as required by ARM standards. The priority levels are interpreted according -to the pre-emptive priority grouping set in the SCB Application Interrupt and Reset -Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -@param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16) -*/ - -void nvic_set_priority(u8 irqn, u8 priority) -{ - NVIC_IPR(irqn) = priority; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief NVIC Software Trigger Interrupt - -Generate an interrupt from software. This has no effect for unprivileged access -unless the privilege level has been elevated through the System Control Registers. - -@param[in] irqn Unsigned int16. Interrupt number (0 ... 239) -*/ - -void nvic_generate_software_interrupt(u16 irqn) -{ - if (irqn <= 239) - NVIC_STIR |= irqn; -} -/**@}*/ - -- cgit v1.2.3 From 5afa53f01abb3f19e1140d1a6407c43e8b3947cf Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 16:29:58 +0200 Subject: drop two-line vector.c dispatchers in favor of central dispatch --- lib/cm3/vector.c | 6 ++++++ lib/dispatch/vector.c | 11 +++++++++++ lib/efm32/tinygecko/vector.c | 2 -- lib/lm3s/vector.c | 2 -- lib/lpc17xx/vector.c | 2 -- lib/lpc43xx/vector.c | 8 +------- lib/stm32/f1/vector.c | 2 -- lib/stm32/f2/vector.c | 2 -- lib/stm32/f4/vector.c | 8 +------- 9 files changed, 19 insertions(+), 24 deletions(-) create mode 100644 lib/dispatch/vector.c delete mode 100644 lib/efm32/tinygecko/vector.c delete mode 100644 lib/lm3s/vector.c delete mode 100644 lib/lpc17xx/vector.c delete mode 100644 lib/stm32/f1/vector.c delete mode 100644 lib/stm32/f2/vector.c (limited to 'lib') diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index 200e8e5..7b660f9 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -20,6 +20,9 @@ #include +/* load optional platform dependent initialization routines */ +#include "../dispatch/vector.c" + #define WEAK __attribute__ ((weak)) /* Symbols exported by the linker script(s): */ @@ -70,6 +73,9 @@ void WEAK reset_handler(void) while (dest < &_ebss) *dest++ = 0; + /* might be provided by platform specific vector.c */ + pre_main(); + /* Call the application's entry point. */ main(); } diff --git a/lib/dispatch/vector.c b/lib/dispatch/vector.c new file mode 100644 index 0000000..baab436 --- /dev/null +++ b/lib/dispatch/vector.c @@ -0,0 +1,11 @@ +#if defined(STM32F4) +# include "../stm32/f4/vector.c" + +#elif defined(LPC43XX) +# include "../lpc43xx/vector.c" + +#else + +static void pre_main(void) {} + +#endif diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c deleted file mode 100644 index d6da5a2..0000000 --- a/lib/efm32/tinygecko/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../../cm3/vector.c" diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c deleted file mode 100644 index e9e7e06..0000000 --- a/lib/lm3s/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../cm3/vector.c" diff --git a/lib/lpc17xx/vector.c b/lib/lpc17xx/vector.c deleted file mode 100644 index 61342f4..0000000 --- a/lib/lpc17xx/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../cm3/vector.c" diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 66e9b63..0463a65 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -18,17 +18,13 @@ * along with this library. If not, see . */ -#include -#define reset_handler original_reset_handler -#include "../cm3/vector.c" -#undef reset_handler #include extern unsigned _etext_ram, _text_ram, _etext_rom; #define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) ) -void WEAK reset_handler(void) +static void pre_main(void) { volatile unsigned *src, *dest; @@ -49,6 +45,4 @@ void WEAK reset_handler(void) /* Continue Execution in RAM */ } - - original_reset_handler(); } diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c deleted file mode 100644 index 795773b..0000000 --- a/lib/stm32/f1/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../../cm3/vector.c" diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c deleted file mode 100644 index 24d1185..0000000 --- a/lib/stm32/f2/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../../cm3/vector.c" diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c index a5017b3..5304299 100644 --- a/lib/stm32/f4/vector.c +++ b/lib/stm32/f4/vector.c @@ -18,16 +18,10 @@ * along with this library. If not, see . */ -#include -#define reset_handler original_reset_handler -#include "../../cm3/vector.c" -#undef reset_handler #include -void WEAK reset_handler(void) +static void pre_main(void) { /* Enable access to Floating-Point coprocessor. */ SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); - - original_reset_handler(); } -- cgit v1.2.3 From ae832b4ee87f2cf94b29f790bc04d7b570109919 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 17:30:18 +0200 Subject: split irq.yaml output in nvic.h and vector_nvic.h the weak pragmas need to be used in the very compilation unit where their target is defined, requiring another dispatch --- include/libopencm3/dispatch/nvic.h | 1 - lib/cm3/vector.c | 2 ++ scripts/irq2nvic_h | 29 +++++++++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) (limited to 'lib') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 67ba544..d8e7889 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -15,6 +15,5 @@ # warning"no chipset defined; user interrupts are disabled" #define NVIC_IRQ_COUNT 0 -#define IRQ_HANDLERS #endif diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index 7b660f9..e0c2972 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -22,6 +22,8 @@ /* load optional platform dependent initialization routines */ #include "../dispatch/vector.c" +/* load the weak symbols for IRQ_HANDLERS */ +#include #define WEAK __attribute__ ((weak)) diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index 9346e9b..fc5e571 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -29,7 +29,7 @@ method to achive the same thing with C preprocessor is known to the author. import sys import yaml -template = '''\ +template_nvic_h = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. @@ -38,6 +38,8 @@ template = '''\ #ifndef {includeguard} #define {includeguard} +#include + /** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} @ingroup CM3_nvic_defines @@ -60,6 +62,19 @@ template = '''\ /**@}}*/ +#endif /* {includeguard} */ +''' + +template_vector_nvic_h = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + * + * This part needs to get included in the compilation unit where + * blocking_handler gets defined due to the way #pragma works. + */ + + /** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} @ingroup CM3_nvic_isrpragmas @@ -76,11 +91,9 @@ template = '''\ #define IRQ_HANDLERS \\ {vectortableinitialization} - -#endif /* {includeguard} */ ''' -def convert(infile, outfile): +def convert(infile, outfile_nvic, outfile_vectornvic): data = yaml.load(infile) irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) @@ -96,10 +109,14 @@ def convert(infile, outfile): data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) - outfile.write(template.format(**data)) + outfile_nvic.write(template_nvic_h.format(**data)) + # FIXME: the vector_nvic.h file could just as well be a vector_nvic.c file + # in lib/, but that'd spread this mechanism over the whole library; just + # needs some thingking over + outfile_vectornvic.write(template_vector_nvic_h.format(**data)) def main(): - convert(open('irq.yaml'), open('nvic.h', 'w')) + convert(open('irq.yaml'), open('nvic.h', 'w'), open('vector_nvic.h', 'w')) if __name__ == "__main__": main() -- cgit v1.2.3 From c69916ffb6d515b1dd644830ba27daef4fc75b58 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 17:57:59 +0200 Subject: integrate irq2nvic_h script in buildprocess --- Makefile | 8 +++++++- include/libopencm3/efm32/tinygecko/Makefile | 2 -- lib/cm3/vector.c | 2 +- lib/dispatch/vector_nvic.c | 19 +++++++++++++++++++ scripts/irq2nvic_h | 14 ++++++++------ 5 files changed, 35 insertions(+), 10 deletions(-) delete mode 100644 include/libopencm3/efm32/tinygecko/Makefile create mode 100644 lib/dispatch/vector_nvic.c (limited to 'lib') diff --git a/Makefile b/Makefile index 492b618..76c302d 100644 --- a/Makefile +++ b/Makefile @@ -39,7 +39,13 @@ all: build build: lib examples -lib: +generatedheaders: + @printf " UPDATING HEADERS\n" + $(Q)for yamlfile in `find -name 'irq.yaml'`; do \ + ./scripts/irq2nvic_h $$yamlfile ; \ + done + +lib: generatedheaders $(Q)for i in $(addprefix $@/,$(TARGETS)); do \ if [ -d $$i ]; then \ printf " BUILD $$i\n"; \ diff --git a/include/libopencm3/efm32/tinygecko/Makefile b/include/libopencm3/efm32/tinygecko/Makefile deleted file mode 100644 index 4ac5347..0000000 --- a/include/libopencm3/efm32/tinygecko/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -nvic.h: irq.yaml - ./irq2nvic_h diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index e0c2972..a6d2e93 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -23,7 +23,7 @@ /* load optional platform dependent initialization routines */ #include "../dispatch/vector.c" /* load the weak symbols for IRQ_HANDLERS */ -#include +#include "../dispatch/vector_nvic.c" #define WEAK __attribute__ ((weak)) diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c new file mode 100644 index 0000000..fc5fdd2 --- /dev/null +++ b/lib/dispatch/vector_nvic.c @@ -0,0 +1,19 @@ +#if defined(STM32F1) +# include "../stm32/f1/vector_nvic.c" +#elif defined(STM32F2) +# include "../stm32/f2/vector_nvic.c" +#elif defined(STM32F4) +# include "../stm32/f4/vector_nvic.c" + +#elif defined(TINYGECKO) +# include "../efm32/tinygecko/vector_nvic.c" + +#elif defined(LPC43XX) +# include "../lpc43xx/vector_nvic.c" + +#else +# warning"no chipset defined; user interrupts are disabled" + +#define IRQ_HANDLERS + +#endif diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index fc5e571..92d63b8 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -65,7 +65,7 @@ template_nvic_h = '''\ #endif /* {includeguard} */ ''' -template_vector_nvic_h = '''\ +template_vector_nvic_c = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. @@ -110,13 +110,15 @@ def convert(infile, outfile_nvic, outfile_vectornvic): data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) outfile_nvic.write(template_nvic_h.format(**data)) - # FIXME: the vector_nvic.h file could just as well be a vector_nvic.c file - # in lib/, but that'd spread this mechanism over the whole library; just - # needs some thingking over - outfile_vectornvic.write(template_vector_nvic_h.format(**data)) + outfile_vectornvic.write(template_vector_nvic_c.format(**data)) def main(): - convert(open('irq.yaml'), open('nvic.h', 'w'), open('vector_nvic.h', 'w')) + infile = sys.argv[1] + if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.yaml'): + raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml") + nvic_h = infile.replace('irq.yaml', 'nvic.h') + vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c') + convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w')) if __name__ == "__main__": main() -- cgit v1.2.3