From 6912cbe71fe1a4773a3ad0aa7ee04186422dd60d Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Wed, 14 Sep 2011 23:57:43 -0700 Subject: Some updates to the F2 GPIO header plus implementation of GPIO convenience functions. --- lib/stm32f2/gpio.c | 156 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 lib/stm32f2/gpio.c (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c new file mode 100644 index 0000000..f2ea55a --- /dev/null +++ b/lib/stm32f2/gpio.c @@ -0,0 +1,156 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Basic GPIO handling API. + * + * Examples: + * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); + * gpio_set(GPIOB, GPIO4); + * gpio_clear(GPIOG, GPIO2 | GPIO9); + * gpio_get(GPIOC, GPIO1); + * gpio_toggle(GPIOA, GPIO7 | GPIO8); + * reg16 = gpio_port_read(GPIOD); + * gpio_port_write(GPIOF, 0xc8fe); + * + * TODO: + * - GPIO remapping support + */ + +#include + +void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) +{ + u16 i; + u16 moder, pupd; + + /* + * We want to set the config only for the pins mentioned in gpios, + * but keeping the others, so read out the actual config first. + */ + moder = GPIO_MODER(gpioport); + pupd = GPIO_PUPDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + + moder &= ~GPIO_MODE_MASK(i); + moder |= GPIO_MODE(i, mode); + pupd &= ~GPIO_PUPD_MASK(i); + pupd |= GPIO_PUPD(i, pull_up_down); + } + + /* Set mode and pull up/down control registers. */ + GPIO_MODER(gpioport) = moder; + GPIO_PUPDR(gpioport) = pupd; +} + +void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) +{ + u16 i; + u16 ospeedr; + + if (otype == 0x1) + GPIO_OTYPER(gpioport) |= gpios; + else + GPIO_OTYPER(gpioport) &= ~gpios; + + ospeedr = GPIO_OSPEEDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue + ospeedr &= ~GPIO_OSPEEDR_MASK(i); + ospeedr |= GPIO_OSPEEDR(i, mode); + } + + GPIO_OSPEEDR(gpioport) = ospeedr; +} + +void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) +{ + u16 i; + u16 afrl, afrh; + + afrl = GPIO_AFRL(gpioport); + afrh = GPIO_AFRH(gpioport); + + for (i = 0; i < 8; i++) { + if (!((1 << i) & gpios)) + continue + afrl &= GPIO_AFR_MASK(i); + afrl |= GPIO_AFR(i, alt_func_num); + } + + for (i = 8; i < 16; i++) { + if (!((1 << i) & gpios)) + continue + afrl &= GPIO_AFR_MASK(i-8); + afrh |= GPIO_AFR(i-8, alt_func_num); + } + + GPIO_AFRL(gpioport) = afrl; + GPIO_AFRH(gpioport) = afrh; +} + +void gpio_set(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios; +} + +void gpio_clear(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios << 16; +} + +u16 gpio_get(u32 gpioport, u16 gpios) +{ + return gpio_port_read(gpioport) & gpios; +} + +void gpio_toggle(u32 gpioport, u16 gpios) +{ + GPIO_ODR(gpioport) = GPIO_IDR(gpioport) ^ gpios; +} + +u16 gpio_port_read(u32 gpioport) +{ + return (u16)GPIO_IDR(gpioport); +} + +void gpio_port_write(u32 gpioport, u16 data) +{ + GPIO_ODR(gpioport) = data; +} + +void gpio_port_config_lock(u32 gpioport, u16 gpios) +{ + u32 reg32; + + /* Special "Lock Key Writing Sequence", see datasheet. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ + + /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ +} -- cgit v1.2.3 From b5883df455c595c92f79ee7721e37ea808010cc2 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 00:07:14 -0700 Subject: Copying F1 linker script over to the F2 target, hopefully it should be the same! --- lib/stm32f2/libopencm3_stm32f2.ld | 63 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 lib/stm32f2/libopencm3_stm32f2.ld (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/libopencm3_stm32f2.ld b/lib/stm32f2/libopencm3_stm32f2.ld new file mode 100644 index 0000000..fda7d02 --- /dev/null +++ b/lib/stm32f2/libopencm3_stm32f2.ld @@ -0,0 +1,63 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Generic linker script for STM32 targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + *(.rodata*) /* Read-only data */ + _etext = .; + } >rom + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + _ebss = .; + } >ram AT >rom + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + end = .; +} + +PROVIDE(_stack = 0x20000800); + -- cgit v1.2.3 From 4366d5e60082b8be4ddb8926e6368f29fc363aab Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 00:59:30 -0700 Subject: Adding vector table for F2. --- lib/stm32f2/vector.c | 336 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 336 insertions(+) create mode 100644 lib/stm32f2/vector.c (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/vector.c b/lib/stm32f2/vector.c new file mode 100644 index 0000000..d6f70f8 --- /dev/null +++ b/lib/stm32f2/vector.c @@ -0,0 +1,336 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by linker script */ +extern unsigned _etext, _data, _edata, _ebss, _stack; + +void main(void); +void reset_handler(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK reset_handler(void); +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK usart4_isr(void); +void WEAK usart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +__attribute__ ((section(".vectors"))) +void (*const vector_table[]) (void) = { + (void*)&_stack, + reset_handler, + nmi_handler, + hard_fault_handler, + mem_manage_handler, + bus_fault_handler, + usage_fault_handler, + 0, 0, 0, 0, /* Reserved */ + sv_call_handler, + debug_monitor_handler, + 0, /* Reserved */ + pend_sv_handler, + sys_tick_handler, + wwdg_isr, + pvd_isr, + tamp_stamp_isr, + rtc_wkup_isr, + flash_isr, + rcc_isr, + exti0_isr, + exti1_isr, + exti2_isr, + exti3_isr, + exti4_isr, + dma1_stream0_isr, + dma1_stream1_isr, + dma1_stream2_isr, + dma1_stream3_isr, + dma1_stream4_isr, + dma1_stream5_isr, + dma1_stream6_isr, + adc_isr, + can1_tx_isr, + can1_rx0_isr, + can1_rx1_isr, + can1_sce_isr, + exti9_5_isr, + tim1_brk_tim9_isr, + tim1_up_tim10_isr, + tim1_trg_com_tim11_isr, + tim1_cc_isr, + tim2_isr, + tim3_isr, + tim4_isr, + i2c1_ev_isr, + i2c1_er_isr, + i2c2_ev_isr, + i2c2_er_isr, + spi1_isr, + spi2_isr, + usart1_isr, + usart2_isr, + usart3_isr, + exti15_10_isr, + rtc_alarm_isr, + usb_fs_wkup_isr, + tim8_brk_tim12_isr, + tim8_up_tim13_isr, + tim8_trg_com_tim14_isr, + tim8_cc_isr, + dma1_stream7_isr, + fsmc_isr, + sdio_isr, + tim5_isr, + spi3_isr, + usart4_isr, + usart5_isr, + tim6_dac_isr, + tim7_isr, + dma2_stream0_isr, + dma2_stream1_isr, + dma2_stream2_isr, + dma2_stream3_isr, + dma2_stream4_isr, + eth_isr, + eth_wkup_isr, + can2_tx_isr, + can2_rx0_isr, + can2_rx1_isr, + can2_sce_isr, + otg_fs_isr, + dma2_stream5_isr, + dma2_stream6_isr, + dma2_stream7_isr, + usart6_isr, + i2c3_ev_isr, + i2c3_er_isr, + otg_hs_ep1_out_isr, + otg_hs_ep1_in_isr, + otg_hs_wkup_isr, + otg_hs_isr, + dcmi_isr, + cryp_isr, + hash_rng_isr, +}; + +void reset_handler(void) +{ + volatile unsigned *src, *dest; + asm("MSR msp, %0" : : "r"(&_stack)); + + for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak usart4_isr = null_handler +#pragma weak usart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + -- cgit v1.2.3 From b546f9b5a92f592e0254ae3de94c609148a88018 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 01:18:26 -0700 Subject: Add family define for the F1 Makefile and add a Makefile for the F2. --- lib/stm32f1/Makefile | 2 +- lib/stm32f2/Makefile | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 lib/stm32f2/Makefile (limited to 'lib/stm32f2') diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile index fe2b129..1d6a3bc 100644 --- a/lib/stm32f1/Makefile +++ b/lib/stm32f1/Makefile @@ -25,7 +25,7 @@ CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD + -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile new file mode 100644 index 0000000..1f08089 --- /dev/null +++ b/lib/stm32f2/Makefile @@ -0,0 +1,58 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +LIBNAME = libopencm3_stm32f2 + +# PREFIX ?= arm-none-eabi +PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ + -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSTM32F2 +# ARFLAGS = rcsv +ARFLAGS = rcs +OBJS = vector.o gpio.o + +#VPATH += ../usb + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +endif + +all: $(LIBNAME).a + +$(LIBNAME).a: $(OBJS) + @printf " AR $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(AR) $(ARFLAGS) $@ $^ + +%.o: %.c + @printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + @printf " CLEAN lib/stm32f2\n" + $(Q)rm -f *.o *.d + $(Q)rm -f $(LIBNAME).a + +.PHONY: clean + +-include $(OBJS:.o=.d) + -- cgit v1.2.3 From 5b4cbe7d87409096e447951ba72b269e90cf12a7 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 01:18:49 -0700 Subject: Update F1 libs with new header file locations. --- lib/stm32f1/adc.c | 2 +- lib/stm32f1/can.c | 2 +- lib/stm32f1/dma.c | 2 +- lib/stm32f1/ethernet.c | 2 +- lib/stm32f1/exti.c | 2 +- lib/stm32f1/flash.c | 2 +- lib/stm32f1/gpio.c | 2 +- lib/stm32f1/nvic.c | 2 +- lib/stm32f1/rcc.c | 4 ++-- lib/stm32f1/rtc.c | 4 ++-- lib/stm32f1/systick.c | 2 +- lib/stm32f1/timer.c | 2 +- lib/stm32f1/usart.c | 2 +- lib/stm32f2/gpio.c | 10 +++++----- 14 files changed, 20 insertions(+), 20 deletions(-) (limited to 'lib/stm32f2') diff --git a/lib/stm32f1/adc.c b/lib/stm32f1/adc.c index 058837c..31e4cbf 100644 --- a/lib/stm32f1/adc.c +++ b/lib/stm32f1/adc.c @@ -31,7 +31,7 @@ * reg16 = adc_read(ADC1, ADC_CH_0); */ -#include +#include void rcc_set_adc_clk(u32 prescaler) { diff --git a/lib/stm32f1/can.c b/lib/stm32f1/can.c index e571f8a..8c5d7ec 100644 --- a/lib/stm32f1/can.c +++ b/lib/stm32f1/can.c @@ -18,7 +18,7 @@ */ #include -#include +#include void can_reset(u32 canport) { diff --git a/lib/stm32f1/dma.c b/lib/stm32f1/dma.c index 8feb2c9..4f0af6f 100644 --- a/lib/stm32f1/dma.c +++ b/lib/stm32f1/dma.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void dma_enable_mem2mem_mode(u32 dma, u8 channel) { diff --git a/lib/stm32f1/ethernet.c b/lib/stm32f1/ethernet.c index 4a4d080..fc65ec2 100644 --- a/lib/stm32f1/ethernet.c +++ b/lib/stm32f1/ethernet.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void eth_smi_write(u8 phy, u8 reg, u16 data) { diff --git a/lib/stm32f1/exti.c b/lib/stm32f1/exti.c index de037e7..969cae4 100644 --- a/lib/stm32f1/exti.c +++ b/lib/stm32f1/exti.c @@ -18,7 +18,7 @@ */ #include -#include +#include void exti_set_trigger(u32 extis, exti_trigger_type trig) { diff --git a/lib/stm32f1/flash.c b/lib/stm32f1/flash.c index 98f7777..b8b3d52 100644 --- a/lib/stm32f1/flash.c +++ b/lib/stm32f1/flash.c @@ -18,7 +18,7 @@ * along with this program. If not, see . */ -#include +#include void flash_prefetch_buffer_enable(void) { diff --git a/lib/stm32f1/gpio.c b/lib/stm32f1/gpio.c index 52c0c66..cd6be9b 100644 --- a/lib/stm32f1/gpio.c +++ b/lib/stm32f1/gpio.c @@ -34,7 +34,7 @@ * - GPIO remapping support */ -#include +#include void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios) { diff --git a/lib/stm32f1/nvic.c b/lib/stm32f1/nvic.c index cf77cc3..f45b601 100644 --- a/lib/stm32f1/nvic.c +++ b/lib/stm32f1/nvic.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void nvic_enable_irq(u8 irqn) { diff --git a/lib/stm32f1/rcc.c b/lib/stm32f1/rcc.c index f646168..689cabb 100644 --- a/lib/stm32f1/rcc.c +++ b/lib/stm32f1/rcc.c @@ -19,8 +19,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */ u32 rcc_ppre1_frequency = 8000000; diff --git a/lib/stm32f1/rtc.c b/lib/stm32f1/rtc.c index 4495641..c187be9 100644 --- a/lib/stm32f1/rtc.c +++ b/lib/stm32f1/rtc.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include void rtc_awake_from_off(osc_t clock_source) diff --git a/lib/stm32f1/systick.c b/lib/stm32f1/systick.c index 882601d..3308413 100644 --- a/lib/stm32f1/systick.c +++ b/lib/stm32f1/systick.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void systick_set_reload(u32 value) { diff --git a/lib/stm32f1/timer.c b/lib/stm32f1/timer.c index 32e240d..a61f67f 100644 --- a/lib/stm32f1/timer.c +++ b/lib/stm32f1/timer.c @@ -26,7 +26,7 @@ */ #include -#include +#include void timer_reset(u32 timer_peripheral) { diff --git a/lib/stm32f1/usart.c b/lib/stm32f1/usart.c index ead0ef7..73e450b 100644 --- a/lib/stm32f1/usart.c +++ b/lib/stm32f1/usart.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include #include diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index f2ea55a..2330628 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -77,9 +77,9 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) for (i = 0; i < 16; i++) { if (!((1 << i) & gpios)) - continue - ospeedr &= ~GPIO_OSPEEDR_MASK(i); - ospeedr |= GPIO_OSPEEDR(i, mode); + continue; + ospeedr &= ~GPIO_OSPEED_MASK(i); + ospeedr |= GPIO_OSPEED(i, speed); } GPIO_OSPEEDR(gpioport) = ospeedr; @@ -95,14 +95,14 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) for (i = 0; i < 8; i++) { if (!((1 << i) & gpios)) - continue + continue; afrl &= GPIO_AFR_MASK(i); afrl |= GPIO_AFR(i, alt_func_num); } for (i = 8; i < 16; i++) { if (!((1 << i) & gpios)) - continue + continue; afrl &= GPIO_AFR_MASK(i-8); afrh |= GPIO_AFR(i-8, alt_func_num); } -- cgit v1.2.3 From 7889cb66c77bbb921079097038ba0b179fcd5958 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 14:59:55 -0700 Subject: Move systick to stm32 common. --- include/libopencm3/stm32/f1/systick.h | 82 ----------------------------------- include/libopencm3/stm32/systick.h | 82 +++++++++++++++++++++++++++++++++++ lib/stm32_common/systick.c | 64 +++++++++++++++++++++++++++ lib/stm32f1/Makefile | 2 +- lib/stm32f1/systick.c | 64 --------------------------- lib/stm32f2/Makefile | 3 +- 6 files changed, 149 insertions(+), 148 deletions(-) delete mode 100644 include/libopencm3/stm32/f1/systick.h create mode 100644 include/libopencm3/stm32/systick.h create mode 100644 lib/stm32_common/systick.c delete mode 100644 lib/stm32f1/systick.c (limited to 'lib/stm32f2') diff --git a/include/libopencm3/stm32/f1/systick.h b/include/libopencm3/stm32/f1/systick.h deleted file mode 100644 index 7c2c9a3..0000000 --- a/include/libopencm3/stm32/f1/systick.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -#define STK_CTRL_CLKSOURCE_LSB 2 -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -#endif diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h new file mode 100644 index 0000000..7c2c9a3 --- /dev/null +++ b/include/libopencm3/stm32/systick.h @@ -0,0 +1,82 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +#define STK_CTRL_CLKSOURCE_LSB 2 +#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 +#define STK_CTRL_CLKSOURCE_AHB 1 +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +#endif diff --git a/lib/stm32_common/systick.c b/lib/stm32_common/systick.c new file mode 100644 index 0000000..882601d --- /dev/null +++ b/lib/stm32_common/systick.c @@ -0,0 +1,64 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +void systick_set_clocksource(u8 clocksource) +{ + if (clocksource < 2) + STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); +} + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile index 1d6a3bc..a6aed45 100644 --- a/lib/stm32f1/Makefile +++ b/lib/stm32f1/Makefile @@ -33,7 +33,7 @@ OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ timer.o usb_f107.o -VPATH += ../usb +VPATH += ../usb:../stm32_common # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) diff --git a/lib/stm32f1/systick.c b/lib/stm32f1/systick.c deleted file mode 100644 index 3308413..0000000 --- a/lib/stm32f1/systick.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -void systick_set_clocksource(u8 clocksource) -{ - if (clocksource < 2) - STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); -} - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index 1f08089..d52525b 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,9 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o +OBJS = vector.o gpio.o systick.o #VPATH += ../usb +VPATH += ../stm32_common # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) -- cgit v1.2.3 From 318deef8cb49cbf7d60788ad36f1fc4a41e1be4b Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 15:06:28 -0700 Subject: Moved I2C to stm32 common. --- lib/stm32_common/i2c.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/stm32f1/i2c.c | 93 -------------------------------------------------- lib/stm32f2/Makefile | 2 +- 3 files changed, 94 insertions(+), 94 deletions(-) create mode 100644 lib/stm32_common/i2c.c delete mode 100644 lib/stm32f1/i2c.c (limited to 'lib/stm32f2') diff --git a/lib/stm32_common/i2c.c b/lib/stm32_common/i2c.c new file mode 100644 index 0000000..e1a3b84 --- /dev/null +++ b/lib/stm32_common/i2c.c @@ -0,0 +1,93 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void i2c_peripheral_enable(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_PE; +} + +void i2c_peripheral_disable(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_PE; +} + +void i2c_send_start(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_START; +} + +void i2c_send_stop(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_STOP; +} + +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) +{ + I2C_OAR1(i2c) = (u16)(slave << 1); + I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; + I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ +} + +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) +{ + I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); +} + +void i2c_set_fast_mode(u32 i2c) +{ + I2C_CCR(i2c) |= I2C_CCR_FS; +} + +void i2c_set_standard_mode(u32 i2c) +{ + I2C_CCR(i2c) &= ~I2C_CCR_FS; +} + +void i2c_set_clock_frequency(u32 i2c, u8 freq) +{ + u16 reg16; + reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ + reg16 |= freq; + I2C_CR2(i2c) = reg16; +} + +void i2c_set_ccr(u32 i2c, u16 freq) +{ + u16 reg16; + reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ + reg16 |= freq; + I2C_CCR(i2c) = reg16; +} + +void i2c_set_trise(u32 i2c, u16 trise) +{ + I2C_TRISE(i2c) = trise; +} + +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) +{ + I2C_DR(i2c) = (u8)((slave << 1) | readwrite); +} + +void i2c_send_data(u32 i2c, u8 data) +{ + I2C_DR(i2c) = data; +} diff --git a/lib/stm32f1/i2c.c b/lib/stm32f1/i2c.c deleted file mode 100644 index e1a3b84..0000000 --- a/lib/stm32f1/i2c.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void i2c_peripheral_enable(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_PE; -} - -void i2c_peripheral_disable(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_PE; -} - -void i2c_send_start(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_START; -} - -void i2c_send_stop(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_STOP; -} - -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) -{ - I2C_OAR1(i2c) = (u16)(slave << 1); - I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; - I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ -} - -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) -{ - I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); -} - -void i2c_set_fast_mode(u32 i2c) -{ - I2C_CCR(i2c) |= I2C_CCR_FS; -} - -void i2c_set_standard_mode(u32 i2c) -{ - I2C_CCR(i2c) &= ~I2C_CCR_FS; -} - -void i2c_set_clock_frequency(u32 i2c, u8 freq) -{ - u16 reg16; - reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ - reg16 |= freq; - I2C_CR2(i2c) = reg16; -} - -void i2c_set_ccr(u32 i2c, u16 freq) -{ - u16 reg16; - reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ - reg16 |= freq; - I2C_CCR(i2c) = reg16; -} - -void i2c_set_trise(u32 i2c, u16 trise) -{ - I2C_TRISE(i2c) = trise; -} - -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) -{ - I2C_DR(i2c) = (u8)((slave << 1) | readwrite); -} - -void i2c_send_data(u32 i2c, u8 data) -{ - I2C_DR(i2c) = data; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index d52525b..f3d6ff7 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o +OBJS = vector.o gpio.o systick.o i2c.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 97413a83f8aecea15a79953703c8a2c320993bc4 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 15:07:07 -0700 Subject: Moved SPI to stm32 common. --- lib/stm32_common/spi.c | 290 +++++++++++++++++++++++++++++++++++++++++++++++++ lib/stm32f1/spi.c | 290 ------------------------------------------------- lib/stm32f2/Makefile | 2 +- 3 files changed, 291 insertions(+), 291 deletions(-) create mode 100644 lib/stm32_common/spi.c delete mode 100644 lib/stm32f1/spi.c (limited to 'lib/stm32f2') diff --git a/lib/stm32_common/spi.c b/lib/stm32_common/spi.c new file mode 100644 index 0000000..733a1bc --- /dev/null +++ b/lib/stm32_common/spi.c @@ -0,0 +1,290 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +/* + * SPI and I2S code. + * + * Examples: + * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + * SPI_CR1_LSBFIRST); + * spi_write(SPI1, 0x55); // 8-bit write + * spi_write(SPI1, 0xaa88); // 16-bit write + * reg8 = spi_read(SPI1); // 8-bit read + * reg16 = spi_read(SPI1); // 16-bit read + */ + +int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) +{ + u32 reg32 = 0; + + reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ + + reg32 |= br; /* Set BAUD rate bits. */ + reg32 |= cpol; /* Set CPOL value. */ + reg32 |= cpha; /* Set CPHA value. */ + reg32 |= dff; /* Set data format (8 or 16 bits). */ + reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ + + /* TODO: NSS pin handling. */ + + SPI_CR1(spi) = reg32; + + return 0; /* TODO */ +} + +/* TODO: Error handling? */ +void spi_enable(u32 spi) +{ + u32 reg32; + + reg32 = SPI_CR1(spi); + reg32 |= SPI_CR1_SPE; /* Enable SPI. */ + SPI_CR1(spi) = reg32; +} + +/* TODO: Error handling? */ +void spi_disable(u32 spi) +{ + u32 reg32; + + /* TODO: Follow procedure from section 23.3.8 in the techref manual. */ + reg32 = SPI_CR1(spi); + reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ + SPI_CR1(spi) = reg32; +} + +void spi_write(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; +} + +void spi_send(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; + + /* wait for transfer finished */ + while (SPI_SR(spi) & SPI_SR_BSY ) + { + } +} + +u16 spi_read(u32 spi) +{ + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR(spi); +} + +void spi_set_bidirectional_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; +} + +void spi_set_unidirectional_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; +} + +void spi_set_bidirectional_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; +} + +void spi_set_bidirectional_transmit_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) |= SPI_CR1_BIDIOE; +} + +void spi_enable_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCEN; +} + +void spi_disable_crc(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCEN; +} + +void spi_set_next_tx_from_buffer(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; +} + +void spi_set_next_tx_from_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCNEXT; +} + +void spi_set_dff_8bit(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_DFF; +} + +void spi_set_dff_16bit(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_DFF; +} + +void spi_set_full_duplex_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_RXONLY; +} + +void spi_set_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_RXONLY; +} + +void spi_disable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSM; +} + +void spi_enable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSM; +} + +void spi_set_nss_high(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSI; +} + +void spi_set_nss_low(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSI; +} + +void spi_send_lsb_first(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_LSBFIRST; +} + +void spi_send_msb_first(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; +} + +void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) +{ + u32 reg32; + + if (baudrate > 7) + return; + + reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ + reg32 |= (baudrate << 3); + SPI_CR1(spi) = reg32; +} + +void spi_set_master_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_MSTR; +} + +void spi_set_slave_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_MSTR; +} + +void spi_set_clock_polarity_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPOL; +} + +void spi_set_clock_polarity_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPOL; +} + +void spi_set_clock_phase_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPHA; +} + +void spi_set_clock_phase_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPHA; +} + +void spi_enable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXEIE; +} + +void spi_disable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXEIE; +} + +void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXNEIE; +} + +void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; +} + +void spi_enable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_ERRIE; +} + +void spi_disable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_ERRIE; +} + +void spi_enable_ss_output(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_SSOE; +} + +void spi_disable_ss_output(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_SSOE; +} + +void spi_enable_tx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXDMAEN; +} + +void spi_disable_tx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; +} + +void spi_enable_rx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXDMAEN; +} + +void spi_disable_rx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; +} diff --git a/lib/stm32f1/spi.c b/lib/stm32f1/spi.c deleted file mode 100644 index 733a1bc..0000000 --- a/lib/stm32f1/spi.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -/* - * SPI and I2S code. - * - * Examples: - * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, - * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, - * SPI_CR1_LSBFIRST); - * spi_write(SPI1, 0x55); // 8-bit write - * spi_write(SPI1, 0xaa88); // 16-bit write - * reg8 = spi_read(SPI1); // 8-bit read - * reg16 = spi_read(SPI1); // 16-bit read - */ - -int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) -{ - u32 reg32 = 0; - - reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ - - reg32 |= br; /* Set BAUD rate bits. */ - reg32 |= cpol; /* Set CPOL value. */ - reg32 |= cpha; /* Set CPHA value. */ - reg32 |= dff; /* Set data format (8 or 16 bits). */ - reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ - - /* TODO: NSS pin handling. */ - - SPI_CR1(spi) = reg32; - - return 0; /* TODO */ -} - -/* TODO: Error handling? */ -void spi_enable(u32 spi) -{ - u32 reg32; - - reg32 = SPI_CR1(spi); - reg32 |= SPI_CR1_SPE; /* Enable SPI. */ - SPI_CR1(spi) = reg32; -} - -/* TODO: Error handling? */ -void spi_disable(u32 spi) -{ - u32 reg32; - - /* TODO: Follow procedure from section 23.3.8 in the techref manual. */ - reg32 = SPI_CR1(spi); - reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ - SPI_CR1(spi) = reg32; -} - -void spi_write(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; -} - -void spi_send(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; - - /* wait for transfer finished */ - while (SPI_SR(spi) & SPI_SR_BSY ) - { - } -} - -u16 spi_read(u32 spi) -{ - /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ - return SPI_DR(spi); -} - -void spi_set_bidirectional_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; -} - -void spi_set_unidirectional_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; -} - -void spi_set_bidirectional_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; -} - -void spi_set_bidirectional_transmit_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) |= SPI_CR1_BIDIOE; -} - -void spi_enable_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCEN; -} - -void spi_disable_crc(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCEN; -} - -void spi_set_next_tx_from_buffer(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; -} - -void spi_set_next_tx_from_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCNEXT; -} - -void spi_set_dff_8bit(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_DFF; -} - -void spi_set_dff_16bit(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_DFF; -} - -void spi_set_full_duplex_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_RXONLY; -} - -void spi_set_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_RXONLY; -} - -void spi_disable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSM; -} - -void spi_enable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSM; -} - -void spi_set_nss_high(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSI; -} - -void spi_set_nss_low(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSI; -} - -void spi_send_lsb_first(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_LSBFIRST; -} - -void spi_send_msb_first(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; -} - -void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) -{ - u32 reg32; - - if (baudrate > 7) - return; - - reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ - reg32 |= (baudrate << 3); - SPI_CR1(spi) = reg32; -} - -void spi_set_master_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_MSTR; -} - -void spi_set_slave_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_MSTR; -} - -void spi_set_clock_polarity_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPOL; -} - -void spi_set_clock_polarity_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPOL; -} - -void spi_set_clock_phase_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPHA; -} - -void spi_set_clock_phase_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPHA; -} - -void spi_enable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXEIE; -} - -void spi_disable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXEIE; -} - -void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXNEIE; -} - -void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; -} - -void spi_enable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_ERRIE; -} - -void spi_disable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_ERRIE; -} - -void spi_enable_ss_output(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_SSOE; -} - -void spi_disable_ss_output(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_SSOE; -} - -void spi_enable_tx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXDMAEN; -} - -void spi_disable_tx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; -} - -void spi_enable_rx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXDMAEN; -} - -void spi_disable_rx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index f3d6ff7..ba0ae04 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 3a426b34aa38397aca3efc17f83a524fb05ea1ed Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 16:26:39 -0700 Subject: Moving nvic code to common, adding F1 and F2 specific user interrupt definition headers. --- include/libopencm3/stm32/f1/nvic.h | 162 ---------------------------------- include/libopencm3/stm32/f1/nvic_f1.h | 99 +++++++++++++++++++++ include/libopencm3/stm32/f2/nvic_f2.h | 112 +++++++++++++++++++++++ include/libopencm3/stm32/nvic.h | 108 +++++++++++++++++++++++ lib/stm32_common/nvic.c | 106 ++++++++++++++++++++++ lib/stm32f1/nvic.c | 106 ---------------------- lib/stm32f2/Makefile | 2 +- 7 files changed, 426 insertions(+), 269 deletions(-) delete mode 100644 include/libopencm3/stm32/f1/nvic.h create mode 100644 include/libopencm3/stm32/f1/nvic_f1.h create mode 100644 include/libopencm3/stm32/f2/nvic_f2.h create mode 100644 include/libopencm3/stm32/nvic.h create mode 100644 lib/stm32_common/nvic.c delete mode 100644 lib/stm32f1/nvic.c (limited to 'lib/stm32f2') diff --git a/include/libopencm3/stm32/f1/nvic.h b/include/libopencm3/stm32/f1/nvic.h deleted file mode 100644 index d29c425..0000000 --- a/include/libopencm3/stm32/f1/nvic.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 - -/* User Interrupts */ -#define NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMPER_IRQ 2 -#define NVIC_RTC_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_CHANNEL1_IRQ 11 -#define NVIC_DMA1_CHANNEL2_IRQ 12 -#define NVIC_DMA1_CHANNEL3_IRQ 13 -#define NVIC_DMA1_CHANNEL4_IRQ 14 -#define NVIC_DMA1_CHANNEL5_IRQ 15 -#define NVIC_DMA1_CHANNEL6_IRQ 16 -#define NVIC_DMA1_CHANNEL7_IRQ 17 -#define NVIC_ADC1_2_IRQ 18 -#define NVIC_USB_HP_CAN_TX_IRQ 19 -#define NVIC_USB_LP_CAN_RX0_IRQ 20 -#define NVIC_CAN_RX1_IRQ 21 -#define NVIC_CAN_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_IRQ 24 -#define NVIC_TIM1_UP_IRQ 25 -#define NVIC_TIM1_TRG_COM_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_WAKEUP_IRQ 42 -#define NVIC_TIM8_BRK_IRQ 43 -#define NVIC_TIM8_UP_IRQ 44 -#define NVIC_TIM8_TRG_COM_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_ADC3_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_USART4_IRQ 52 -#define NVIC_USART5_IRQ 53 -#define NVIC_TIM6_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_CHANNEL1_IRQ 56 -#define NVIC_DMA2_CHANNEL2_IRQ 57 -#define NVIC_DMA2_CHANNEL3_IRQ 58 -#define NVIC_DMA2_CHANNEL4_5_IRQ 59 -#define NVIC_DMA2_CHANNEL5_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 - -/* --- NVIC functions ------------------------------------------------------ */ - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -#endif diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h new file mode 100644 index 0000000..b0b32a0 --- /dev/null +++ b/include/libopencm3/stm32/f1/nvic_f1.h @@ -0,0 +1,99 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_F1_H +#define LIBOPENCM3_NVIC_F1_H + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Note: These F1 specific user interrupt definitions supplement the + * general NVIC definitions in ../nvic.h + */ + +/* User Interrupts */ +#define NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMPER_IRQ 2 +#define NVIC_RTC_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_CHANNEL1_IRQ 11 +#define NVIC_DMA1_CHANNEL2_IRQ 12 +#define NVIC_DMA1_CHANNEL3_IRQ 13 +#define NVIC_DMA1_CHANNEL4_IRQ 14 +#define NVIC_DMA1_CHANNEL5_IRQ 15 +#define NVIC_DMA1_CHANNEL6_IRQ 16 +#define NVIC_DMA1_CHANNEL7_IRQ 17 +#define NVIC_ADC1_2_IRQ 18 +#define NVIC_USB_HP_CAN_TX_IRQ 19 +#define NVIC_USB_LP_CAN_RX0_IRQ 20 +#define NVIC_CAN_RX1_IRQ 21 +#define NVIC_CAN_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_IRQ 24 +#define NVIC_TIM1_UP_IRQ 25 +#define NVIC_TIM1_TRG_COM_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_WAKEUP_IRQ 42 +#define NVIC_TIM8_BRK_IRQ 43 +#define NVIC_TIM8_UP_IRQ 44 +#define NVIC_TIM8_TRG_COM_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_ADC3_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_USART4_IRQ 52 +#define NVIC_USART5_IRQ 53 +#define NVIC_TIM6_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_CHANNEL1_IRQ 56 +#define NVIC_DMA2_CHANNEL2_IRQ 57 +#define NVIC_DMA2_CHANNEL3_IRQ 58 +#define NVIC_DMA2_CHANNEL4_5_IRQ 59 +#define NVIC_DMA2_CHANNEL5_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 + +#endif diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h new file mode 100644 index 0000000..2545f0a --- /dev/null +++ b/include/libopencm3/stm32/f2/nvic_f2.h @@ -0,0 +1,112 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_F2_H +#define LIBOPENCM3_NVIC_F2_H + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Note: These F2 specific user interrupt definitions supplement the + * general NVIC definitions in ../nvic.h + */ + +/* User Interrupts */ +#define NVIC_WWDG_IRQ 0 +#define PVD_IRQ 1 +#define TAMP_STAMP_IRQ 2 +#define RTC_WKUP_IRQ 3 +#define FLASH_IRQ 4 +#define RCC_IRQ 5 +#define EXTI0_IRQ 6 +#define EXTI1_IRQ 7 +#define EXTI2_IRQ 8 +#define EXTI3_IRQ 9 +#define EXTI4_IRQ 10 +#define DMA1_STREAM0_IRQ 11 +#define DMA1_STREAM1_IRQ 12 +#define DMA1_STREAM2_IRQ 13 +#define DMA1_STREAM3_IRQ 14 +#define DMA1_STREAM4_IRQ 15 +#define DMA1_STREAM5_IRQ 16 +#define DMA1_STREAM6_IRQ 17 +#define ADC_IRQ 18 +#define CAN1_TX_IRQ 19 +#define CAN1_RX0_IRQ 20 +#define CAN1_RX1_IRQ 21 +#define CAN1_SCE_IRQ 22 +#define EXTI9_5_IRQ 23 +#define TIM1_BRK_TIM9_IRQ 24 +#define TIM1_UP_TIM10_IRQ 25 +#define TIM1_TRG_COM_TIM11_IRQ 26 +#define TIM1_CC_IRQ 27 +#define TIM2_IRQ 28 +#define TIM3_IRQ 29 +#define TIM4_IRQ 30 +#define I2C1_EV_IRQ 31 +#define I2C1_ER_IRQ 32 +#define I2C2_EV_IRQ 33 +#define I2C2_ER_IRQ 34 +#define SPI1_IRQ 35 +#define SPI2_IRQ 36 +#define USART1_IRQ 37 +#define USART2_IRQ 38 +#define USART3_IRQ 39 +#define EXTI15_10_IRQ 40 +#define RTC_ALARM_IRQ 41 +#define USB_FS_WKUP_IRQ 42 +#define TIM8_BRK_TIM12_IRQ 43 +#define TIM8_UP_TIM13_IRQ 44 +#define TIM8_TRG_COM_TIM14_IRQ 45 +#define TIM8_CC_IRQ 46 +#define DMA1_STREAM7_IRQ 47 +#define FSMC_IRQ 48 +#define SDIO_IRQ 49 +#define TIM5_IRQ 50 +#define SPI3_IRQ 51 +#define USART4_IRQ 52 +#define USART5_IRQ 53 +#define TIM6_DAC_IRQ 54 +#define TIM7_IRQ 55 +#define DMA2_STREAM0_IRQ 56 +#define DMA2_STREAM1_IRQ 57 +#define DMA2_STREAM2_IRQ 58 +#define DMA2_STREAM3_IRQ 59 +#define DMA2_STREAM4_IRQ 60 +#define ETH_IRQ 61 +#define ETH_WKUP_IRQ 62 +#define CAN2_TX_IRQ 63 +#define CAN2_RX0_IRQ 64 +#define CAN2_RX1_IRQ 65 +#define CAN2_SCE_IRQ 66 +#define OTG_FS_IRQ 67 +#define DMA2_STREAM5_IRQ 68 +#define DMA2_STREAM6_IRQ 69 +#define DMA2_STREAM7_IRQ 70 +#define USART6_IRQ 71 +#define I2C3_EV_IRQ 72 +#define I2C3_ER_IRQ 73 +#define OTG_HS_EP1_OUT_IRQ 74 +#define OTG_HS_EP1_IN_IRQ 75 +#define OTG_HS_WKUP_IRQ 76 +#define OTG_HS_IRQ 77 +#define DCMI_IRQ 78 +#define CRYP_IRQ 79 +#define HASH_RNG_IRQ 80 + +#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h new file mode 100644 index 0000000..339a159 --- /dev/null +++ b/include/libopencm3/stm32/nvic.h @@ -0,0 +1,108 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 System Interrupts */ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 + + +/* Note: User interrupts are family specific and are defined in a familiy + * specific header file in the corresponding subfolder. + */ + +#ifdef STM32F1 +#include +#else +#ifdef STM32F2 +#include +#else +#error "stm32 family not defined." +#endif +#endif + + +/* --- NVIC functions ------------------------------------------------------ */ + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u8 irqn); + +#endif diff --git a/lib/stm32_common/nvic.c b/lib/stm32_common/nvic.c new file mode 100644 index 0000000..cf77cc3 --- /dev/null +++ b/lib/stm32_common/nvic.c @@ -0,0 +1,106 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void nvic_enable_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ISER(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ISER(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ISER(2) |= (1 << (irqn - 64)); +} + +void nvic_disable_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ICER(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ICER(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ICER(2) |= (1 << (irqn - 64)); +} + +u8 nvic_get_pending_irq(u8 irqn) +{ + if (irqn < 32) + return (NVIC_ISPR(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_ISPR(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_ISPR(2) & (1 << (irqn - 64))); + return 0; +} + +void nvic_set_pending_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ISPR(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ISPR(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ISPR(2) |= (1 << (irqn - 64)); +} + +void nvic_clear_pending_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ICPR(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ICPR(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ICPR(2) |= (1 << (irqn - 64)); +} + +u8 nvic_get_active_irq(u8 irqn) +{ + if (irqn < 32) + return (NVIC_IABR(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_IABR(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_IABR(2) & (1 << (irqn - 64))); + return 0; +} + +u8 nvic_get_irq_enabled(u8 irqn) +{ + if (irqn < 32) + return (NVIC_ISER(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_ISER(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_ISER(2) & (1 << (irqn - 64))); + return 0; +} + +void nvic_set_priority(u8 irqn, u8 priority) +{ + NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8)); +} + +void nvic_generate_software_interrupt(u8 irqn) +{ + if (irqn <= 239) + NVIC_STIR |= irqn; +} + + diff --git a/lib/stm32f1/nvic.c b/lib/stm32f1/nvic.c deleted file mode 100644 index f45b601..0000000 --- a/lib/stm32f1/nvic.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void nvic_enable_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ISER(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ISER(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ISER(2) |= (1 << (irqn - 64)); -} - -void nvic_disable_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ICER(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ICER(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ICER(2) |= (1 << (irqn - 64)); -} - -u8 nvic_get_pending_irq(u8 irqn) -{ - if (irqn < 32) - return (NVIC_ISPR(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_ISPR(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_ISPR(2) & (1 << (irqn - 64))); - return 0; -} - -void nvic_set_pending_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ISPR(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ISPR(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ISPR(2) |= (1 << (irqn - 64)); -} - -void nvic_clear_pending_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ICPR(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ICPR(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ICPR(2) |= (1 << (irqn - 64)); -} - -u8 nvic_get_active_irq(u8 irqn) -{ - if (irqn < 32) - return (NVIC_IABR(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_IABR(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_IABR(2) & (1 << (irqn - 64))); - return 0; -} - -u8 nvic_get_irq_enabled(u8 irqn) -{ - if (irqn < 32) - return (NVIC_ISER(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_ISER(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_ISER(2) & (1 << (irqn - 64))); - return 0; -} - -void nvic_set_priority(u8 irqn, u8 priority) -{ - NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8)); -} - -void nvic_generate_software_interrupt(u8 irqn) -{ - if (irqn <= 239) - NVIC_STIR |= irqn; -} - - diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index ba0ae04..cd50c4b 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o spi.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 551d069ed3e5fd5f2f25eae8bd0980905835002a Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 16 Sep 2011 23:14:07 -0700 Subject: Change default prefix in Makefiles to arm-none-eabi for compatability with summon toolchain out the box. --- examples/stm32f2/Makefile.include | 2 +- lib/lm3s/Makefile | 4 ++-- lib/lpc13xx/Makefile | 4 ++-- lib/stm32f1/Makefile | 4 ++-- lib/stm32f2/Makefile | 6 +++--- 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'lib/stm32f2') diff --git a/examples/stm32f2/Makefile.include b/examples/stm32f2/Makefile.include index 6ec9f65..9cec6e7 100644 --- a/examples/stm32f2/Makefile.include +++ b/examples/stm32f2/Makefile.include @@ -20,7 +20,7 @@ ## PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile index 2bdbd72..e2be89f 100644 --- a/lib/lm3s/Makefile +++ b/lib/lm3s/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_lm3s -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile index 7181a08..9b90316 100644 --- a/lib/lpc13xx/Makefile +++ b/lib/lpc13xx/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_lpc13xx -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile index a6aed45..f2f5382 100644 --- a/lib/stm32f1/Makefile +++ b/lib/stm32f1/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_stm32f1 -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index cd50c4b..5da64ab 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_stm32f2 -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 25ed4d5af0a31943fcc2d9d73ae4fce64e478bf8 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 22 Sep 2011 14:23:25 -0700 Subject: Fixed bug in F2 GPIO code. --- lib/stm32f2/gpio.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index 2330628..abb08c0 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -17,29 +17,12 @@ * along with this program. If not, see . */ -/* - * Basic GPIO handling API. - * - * Examples: - * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); - * gpio_set(GPIOB, GPIO4); - * gpio_clear(GPIOG, GPIO2 | GPIO9); - * gpio_get(GPIOC, GPIO1); - * gpio_toggle(GPIOA, GPIO7 | GPIO8); - * reg16 = gpio_port_read(GPIOD); - * gpio_port_write(GPIOF, 0xc8fe); - * - * TODO: - * - GPIO remapping support - */ - #include void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) { u16 i; - u16 moder, pupd; + u32 moder, pupd; /* * We want to set the config only for the pins mentioned in gpios, -- cgit v1.2.3 From d4d737096371fc489bed70684b13305af4785f82 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 23 Sep 2011 13:05:12 -0700 Subject: Some more silly bugs in GPIO fixed for F2. --- lib/stm32f2/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index abb08c0..6e1ef08 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -49,7 +49,7 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) { u16 i; - u16 ospeedr; + u32 ospeedr; if (otype == 0x1) GPIO_OTYPER(gpioport) |= gpios; @@ -71,7 +71,7 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) { u16 i; - u16 afrl, afrh; + u32 afrl, afrh; afrl = GPIO_AFRL(gpioport); afrh = GPIO_AFRH(gpioport); -- cgit v1.2.3 From 60dcacccb7ae8f80ca224e38abdfca1236d1871e Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Wed, 14 Sep 2011 23:57:43 -0700 Subject: Some updates to the F2 GPIO header plus implementation of GPIO convenience functions. --- include/libopencm3/stm32/f2/gpio.h | 14 ++-- lib/stm32f2/gpio.c | 156 +++++++++++++++++++++++++++++++++++++ 2 files changed, 165 insertions(+), 5 deletions(-) create mode 100644 lib/stm32f2/gpio.c (limited to 'lib/stm32f2') diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h index 3339311..b4fb4f3 100644 --- a/include/libopencm3/stm32/f2/gpio.h +++ b/include/libopencm3/stm32/f2/gpio.h @@ -179,7 +179,8 @@ /* --- GPIOx_MODER values -------------------------------------------------- */ -#define GPIO_MODE(n, mode) (mode << (2*n)) +#define GPIO_MODE(n, mode) (mode << (2*(n))) +#define GPIO_MODE_MASK(n) (0x3 << (2*(n))) #define GPIO_MODE_INPUT 0x0 #define GPIO_MODE_OUTPUT 0x1 #define GPIO_MODE_AF 0x2 @@ -192,7 +193,8 @@ /* --- GPIOx_OSPEEDR values ------------------------------------------------ */ -#define GPIO_OSPEED(n, speed) (speed << (2*n)) +#define GPIO_OSPEED(n, speed) (speed << (2*(n))) +#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n))) #define GPIO_OSPEED_2MHZ 0x0 #define GPIO_OSPEED_25MHZ 0x1 #define GPIO_OSPEED_50MHZ 0x2 @@ -200,7 +202,8 @@ /* --- GPIOx_PUPDR values -------------------------------------------------- */ -#define GPIO_PUPD(n, pupd) (pupd << (2*n)) +#define GPIO_PUPD(n, pupd) (pupd << (2*(n))) +#define GPIO_PUPD_MASK(n) (0x3 << (2*(n))) #define GPIO_PUPD_NONE 0x0 #define GPIO_PUPD_PULLUP 0x1 #define GPIO_PUPD_PULLDOWN 0x2 @@ -228,7 +231,8 @@ /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See Datasheet Table 6 (pg. 48) for alternate function mappings. */ -#define GPIO_AFR(n, af) (af << (n*4)) +#define GPIO_AFR(n, af) (af << ((n)*4)) +#define GPIO_AFR_MASK(n) (0xF << ((n)*4)) #define GPIO_AF0 0x0 #define GPIO_AF1 0x1 #define GPIO_AF2 0x2 @@ -262,7 +266,7 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios); void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios); void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios); -/* This part of the API is compatible with the F1 series */ +/* This part of the API is compatible with the F1 series ------------------- */ void gpio_set(u32 gpioport, u16 gpios); void gpio_clear(u32 gpioport, u16 gpios); u16 gpio_get(u32 gpioport, u16 gpios); diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c new file mode 100644 index 0000000..f2ea55a --- /dev/null +++ b/lib/stm32f2/gpio.c @@ -0,0 +1,156 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Basic GPIO handling API. + * + * Examples: + * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); + * gpio_set(GPIOB, GPIO4); + * gpio_clear(GPIOG, GPIO2 | GPIO9); + * gpio_get(GPIOC, GPIO1); + * gpio_toggle(GPIOA, GPIO7 | GPIO8); + * reg16 = gpio_port_read(GPIOD); + * gpio_port_write(GPIOF, 0xc8fe); + * + * TODO: + * - GPIO remapping support + */ + +#include + +void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) +{ + u16 i; + u16 moder, pupd; + + /* + * We want to set the config only for the pins mentioned in gpios, + * but keeping the others, so read out the actual config first. + */ + moder = GPIO_MODER(gpioport); + pupd = GPIO_PUPDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + + moder &= ~GPIO_MODE_MASK(i); + moder |= GPIO_MODE(i, mode); + pupd &= ~GPIO_PUPD_MASK(i); + pupd |= GPIO_PUPD(i, pull_up_down); + } + + /* Set mode and pull up/down control registers. */ + GPIO_MODER(gpioport) = moder; + GPIO_PUPDR(gpioport) = pupd; +} + +void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) +{ + u16 i; + u16 ospeedr; + + if (otype == 0x1) + GPIO_OTYPER(gpioport) |= gpios; + else + GPIO_OTYPER(gpioport) &= ~gpios; + + ospeedr = GPIO_OSPEEDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue + ospeedr &= ~GPIO_OSPEEDR_MASK(i); + ospeedr |= GPIO_OSPEEDR(i, mode); + } + + GPIO_OSPEEDR(gpioport) = ospeedr; +} + +void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) +{ + u16 i; + u16 afrl, afrh; + + afrl = GPIO_AFRL(gpioport); + afrh = GPIO_AFRH(gpioport); + + for (i = 0; i < 8; i++) { + if (!((1 << i) & gpios)) + continue + afrl &= GPIO_AFR_MASK(i); + afrl |= GPIO_AFR(i, alt_func_num); + } + + for (i = 8; i < 16; i++) { + if (!((1 << i) & gpios)) + continue + afrl &= GPIO_AFR_MASK(i-8); + afrh |= GPIO_AFR(i-8, alt_func_num); + } + + GPIO_AFRL(gpioport) = afrl; + GPIO_AFRH(gpioport) = afrh; +} + +void gpio_set(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios; +} + +void gpio_clear(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios << 16; +} + +u16 gpio_get(u32 gpioport, u16 gpios) +{ + return gpio_port_read(gpioport) & gpios; +} + +void gpio_toggle(u32 gpioport, u16 gpios) +{ + GPIO_ODR(gpioport) = GPIO_IDR(gpioport) ^ gpios; +} + +u16 gpio_port_read(u32 gpioport) +{ + return (u16)GPIO_IDR(gpioport); +} + +void gpio_port_write(u32 gpioport, u16 data) +{ + GPIO_ODR(gpioport) = data; +} + +void gpio_port_config_lock(u32 gpioport, u16 gpios) +{ + u32 reg32; + + /* Special "Lock Key Writing Sequence", see datasheet. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ + + /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ +} -- cgit v1.2.3 From 8a2cf9dd4b1ff3d14a67ee1545f1f58644170240 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 00:07:14 -0700 Subject: Copying F1 linker script over to the F2 target, hopefully it should be the same! --- lib/stm32f2/libopencm3_stm32f2.ld | 63 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 lib/stm32f2/libopencm3_stm32f2.ld (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/libopencm3_stm32f2.ld b/lib/stm32f2/libopencm3_stm32f2.ld new file mode 100644 index 0000000..fda7d02 --- /dev/null +++ b/lib/stm32f2/libopencm3_stm32f2.ld @@ -0,0 +1,63 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Generic linker script for STM32 targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + *(.rodata*) /* Read-only data */ + _etext = .; + } >rom + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + _ebss = .; + } >ram AT >rom + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + end = .; +} + +PROVIDE(_stack = 0x20000800); + -- cgit v1.2.3 From 7524b0f4c56e4b9785eac47ffe0fcbc4553d349e Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 00:59:30 -0700 Subject: Adding vector table for F2. --- lib/stm32f2/vector.c | 336 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 336 insertions(+) create mode 100644 lib/stm32f2/vector.c (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/vector.c b/lib/stm32f2/vector.c new file mode 100644 index 0000000..d6f70f8 --- /dev/null +++ b/lib/stm32f2/vector.c @@ -0,0 +1,336 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by linker script */ +extern unsigned _etext, _data, _edata, _ebss, _stack; + +void main(void); +void reset_handler(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK reset_handler(void); +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK usart4_isr(void); +void WEAK usart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +__attribute__ ((section(".vectors"))) +void (*const vector_table[]) (void) = { + (void*)&_stack, + reset_handler, + nmi_handler, + hard_fault_handler, + mem_manage_handler, + bus_fault_handler, + usage_fault_handler, + 0, 0, 0, 0, /* Reserved */ + sv_call_handler, + debug_monitor_handler, + 0, /* Reserved */ + pend_sv_handler, + sys_tick_handler, + wwdg_isr, + pvd_isr, + tamp_stamp_isr, + rtc_wkup_isr, + flash_isr, + rcc_isr, + exti0_isr, + exti1_isr, + exti2_isr, + exti3_isr, + exti4_isr, + dma1_stream0_isr, + dma1_stream1_isr, + dma1_stream2_isr, + dma1_stream3_isr, + dma1_stream4_isr, + dma1_stream5_isr, + dma1_stream6_isr, + adc_isr, + can1_tx_isr, + can1_rx0_isr, + can1_rx1_isr, + can1_sce_isr, + exti9_5_isr, + tim1_brk_tim9_isr, + tim1_up_tim10_isr, + tim1_trg_com_tim11_isr, + tim1_cc_isr, + tim2_isr, + tim3_isr, + tim4_isr, + i2c1_ev_isr, + i2c1_er_isr, + i2c2_ev_isr, + i2c2_er_isr, + spi1_isr, + spi2_isr, + usart1_isr, + usart2_isr, + usart3_isr, + exti15_10_isr, + rtc_alarm_isr, + usb_fs_wkup_isr, + tim8_brk_tim12_isr, + tim8_up_tim13_isr, + tim8_trg_com_tim14_isr, + tim8_cc_isr, + dma1_stream7_isr, + fsmc_isr, + sdio_isr, + tim5_isr, + spi3_isr, + usart4_isr, + usart5_isr, + tim6_dac_isr, + tim7_isr, + dma2_stream0_isr, + dma2_stream1_isr, + dma2_stream2_isr, + dma2_stream3_isr, + dma2_stream4_isr, + eth_isr, + eth_wkup_isr, + can2_tx_isr, + can2_rx0_isr, + can2_rx1_isr, + can2_sce_isr, + otg_fs_isr, + dma2_stream5_isr, + dma2_stream6_isr, + dma2_stream7_isr, + usart6_isr, + i2c3_ev_isr, + i2c3_er_isr, + otg_hs_ep1_out_isr, + otg_hs_ep1_in_isr, + otg_hs_wkup_isr, + otg_hs_isr, + dcmi_isr, + cryp_isr, + hash_rng_isr, +}; + +void reset_handler(void) +{ + volatile unsigned *src, *dest; + asm("MSR msp, %0" : : "r"(&_stack)); + + for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak usart4_isr = null_handler +#pragma weak usart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + -- cgit v1.2.3 From a4935eef571191f7c9170723943f1327d39656a1 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 01:18:26 -0700 Subject: Add family define for the F1 Makefile and add a Makefile for the F2. --- lib/stm32f1/Makefile | 2 +- lib/stm32f2/Makefile | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 lib/stm32f2/Makefile (limited to 'lib/stm32f2') diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile index 3d154aa..fa4dad1 100644 --- a/lib/stm32f1/Makefile +++ b/lib/stm32f1/Makefile @@ -25,7 +25,7 @@ CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD + -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile new file mode 100644 index 0000000..1f08089 --- /dev/null +++ b/lib/stm32f2/Makefile @@ -0,0 +1,58 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +LIBNAME = libopencm3_stm32f2 + +# PREFIX ?= arm-none-eabi +PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ + -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSTM32F2 +# ARFLAGS = rcsv +ARFLAGS = rcs +OBJS = vector.o gpio.o + +#VPATH += ../usb + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +endif + +all: $(LIBNAME).a + +$(LIBNAME).a: $(OBJS) + @printf " AR $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(AR) $(ARFLAGS) $@ $^ + +%.o: %.c + @printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + @printf " CLEAN lib/stm32f2\n" + $(Q)rm -f *.o *.d + $(Q)rm -f $(LIBNAME).a + +.PHONY: clean + +-include $(OBJS:.o=.d) + -- cgit v1.2.3 From ce7dd46aef9153c4f98a983977ce7bd2a905134d Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 01:18:49 -0700 Subject: Update F1 libs with new header file locations. --- lib/stm32f1/adc.c | 2 +- lib/stm32f1/can.c | 2 +- lib/stm32f1/dma.c | 2 +- lib/stm32f1/ethernet.c | 2 +- lib/stm32f1/exti.c | 2 +- lib/stm32f1/flash.c | 2 +- lib/stm32f1/gpio.c | 2 +- lib/stm32f1/nvic.c | 2 +- lib/stm32f1/rcc.c | 4 ++-- lib/stm32f1/rtc.c | 4 ++-- lib/stm32f1/systick.c | 2 +- lib/stm32f1/timer.c | 2 +- lib/stm32f1/usart.c | 2 +- lib/stm32f2/gpio.c | 10 +++++----- 14 files changed, 20 insertions(+), 20 deletions(-) (limited to 'lib/stm32f2') diff --git a/lib/stm32f1/adc.c b/lib/stm32f1/adc.c index 058837c..31e4cbf 100644 --- a/lib/stm32f1/adc.c +++ b/lib/stm32f1/adc.c @@ -31,7 +31,7 @@ * reg16 = adc_read(ADC1, ADC_CH_0); */ -#include +#include void rcc_set_adc_clk(u32 prescaler) { diff --git a/lib/stm32f1/can.c b/lib/stm32f1/can.c index e571f8a..8c5d7ec 100644 --- a/lib/stm32f1/can.c +++ b/lib/stm32f1/can.c @@ -18,7 +18,7 @@ */ #include -#include +#include void can_reset(u32 canport) { diff --git a/lib/stm32f1/dma.c b/lib/stm32f1/dma.c index 8feb2c9..4f0af6f 100644 --- a/lib/stm32f1/dma.c +++ b/lib/stm32f1/dma.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void dma_enable_mem2mem_mode(u32 dma, u8 channel) { diff --git a/lib/stm32f1/ethernet.c b/lib/stm32f1/ethernet.c index 4a4d080..fc65ec2 100644 --- a/lib/stm32f1/ethernet.c +++ b/lib/stm32f1/ethernet.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void eth_smi_write(u8 phy, u8 reg, u16 data) { diff --git a/lib/stm32f1/exti.c b/lib/stm32f1/exti.c index de037e7..969cae4 100644 --- a/lib/stm32f1/exti.c +++ b/lib/stm32f1/exti.c @@ -18,7 +18,7 @@ */ #include -#include +#include void exti_set_trigger(u32 extis, exti_trigger_type trig) { diff --git a/lib/stm32f1/flash.c b/lib/stm32f1/flash.c index 98f7777..b8b3d52 100644 --- a/lib/stm32f1/flash.c +++ b/lib/stm32f1/flash.c @@ -18,7 +18,7 @@ * along with this program. If not, see . */ -#include +#include void flash_prefetch_buffer_enable(void) { diff --git a/lib/stm32f1/gpio.c b/lib/stm32f1/gpio.c index 52c0c66..cd6be9b 100644 --- a/lib/stm32f1/gpio.c +++ b/lib/stm32f1/gpio.c @@ -34,7 +34,7 @@ * - GPIO remapping support */ -#include +#include void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios) { diff --git a/lib/stm32f1/nvic.c b/lib/stm32f1/nvic.c index cf77cc3..f45b601 100644 --- a/lib/stm32f1/nvic.c +++ b/lib/stm32f1/nvic.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void nvic_enable_irq(u8 irqn) { diff --git a/lib/stm32f1/rcc.c b/lib/stm32f1/rcc.c index f646168..689cabb 100644 --- a/lib/stm32f1/rcc.c +++ b/lib/stm32f1/rcc.c @@ -19,8 +19,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */ u32 rcc_ppre1_frequency = 8000000; diff --git a/lib/stm32f1/rtc.c b/lib/stm32f1/rtc.c index 4495641..c187be9 100644 --- a/lib/stm32f1/rtc.c +++ b/lib/stm32f1/rtc.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include void rtc_awake_from_off(osc_t clock_source) diff --git a/lib/stm32f1/systick.c b/lib/stm32f1/systick.c index 882601d..3308413 100644 --- a/lib/stm32f1/systick.c +++ b/lib/stm32f1/systick.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void systick_set_reload(u32 value) { diff --git a/lib/stm32f1/timer.c b/lib/stm32f1/timer.c index 32e240d..a61f67f 100644 --- a/lib/stm32f1/timer.c +++ b/lib/stm32f1/timer.c @@ -26,7 +26,7 @@ */ #include -#include +#include void timer_reset(u32 timer_peripheral) { diff --git a/lib/stm32f1/usart.c b/lib/stm32f1/usart.c index ead0ef7..73e450b 100644 --- a/lib/stm32f1/usart.c +++ b/lib/stm32f1/usart.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include #include diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index f2ea55a..2330628 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -77,9 +77,9 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) for (i = 0; i < 16; i++) { if (!((1 << i) & gpios)) - continue - ospeedr &= ~GPIO_OSPEEDR_MASK(i); - ospeedr |= GPIO_OSPEEDR(i, mode); + continue; + ospeedr &= ~GPIO_OSPEED_MASK(i); + ospeedr |= GPIO_OSPEED(i, speed); } GPIO_OSPEEDR(gpioport) = ospeedr; @@ -95,14 +95,14 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) for (i = 0; i < 8; i++) { if (!((1 << i) & gpios)) - continue + continue; afrl &= GPIO_AFR_MASK(i); afrl |= GPIO_AFR(i, alt_func_num); } for (i = 8; i < 16; i++) { if (!((1 << i) & gpios)) - continue + continue; afrl &= GPIO_AFR_MASK(i-8); afrh |= GPIO_AFR(i-8, alt_func_num); } -- cgit v1.2.3 From ca412a9ed2ab3bf5f4bdf54b7b300290931ab39b Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 14:59:55 -0700 Subject: Move systick to stm32 common. --- include/libopencm3/stm32/f1/systick.h | 82 ----------------------------------- include/libopencm3/stm32/systick.h | 82 +++++++++++++++++++++++++++++++++++ lib/stm32_common/systick.c | 64 +++++++++++++++++++++++++++ lib/stm32f1/Makefile | 2 +- lib/stm32f1/systick.c | 64 --------------------------- lib/stm32f2/Makefile | 3 +- 6 files changed, 149 insertions(+), 148 deletions(-) delete mode 100644 include/libopencm3/stm32/f1/systick.h create mode 100644 include/libopencm3/stm32/systick.h create mode 100644 lib/stm32_common/systick.c delete mode 100644 lib/stm32f1/systick.c (limited to 'lib/stm32f2') diff --git a/include/libopencm3/stm32/f1/systick.h b/include/libopencm3/stm32/f1/systick.h deleted file mode 100644 index 7c2c9a3..0000000 --- a/include/libopencm3/stm32/f1/systick.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -#define STK_CTRL_CLKSOURCE_LSB 2 -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -#endif diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h new file mode 100644 index 0000000..7c2c9a3 --- /dev/null +++ b/include/libopencm3/stm32/systick.h @@ -0,0 +1,82 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +#define STK_CTRL_CLKSOURCE_LSB 2 +#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 +#define STK_CTRL_CLKSOURCE_AHB 1 +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +#endif diff --git a/lib/stm32_common/systick.c b/lib/stm32_common/systick.c new file mode 100644 index 0000000..882601d --- /dev/null +++ b/lib/stm32_common/systick.c @@ -0,0 +1,64 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +void systick_set_clocksource(u8 clocksource) +{ + if (clocksource < 2) + STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); +} + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile index fa4dad1..bd9fca2 100644 --- a/lib/stm32f1/Makefile +++ b/lib/stm32f1/Makefile @@ -33,7 +33,7 @@ OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ timer.o usb_f107.o -VPATH += ../usb +VPATH += ../usb:../stm32_common # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) diff --git a/lib/stm32f1/systick.c b/lib/stm32f1/systick.c deleted file mode 100644 index 3308413..0000000 --- a/lib/stm32f1/systick.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -void systick_set_clocksource(u8 clocksource) -{ - if (clocksource < 2) - STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); -} - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index 1f08089..d52525b 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,9 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o +OBJS = vector.o gpio.o systick.o #VPATH += ../usb +VPATH += ../stm32_common # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) -- cgit v1.2.3 From 72baa300ab82c184e156e170cae0dcd1fd665d12 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 15:06:28 -0700 Subject: Moved I2C to stm32 common. --- lib/stm32_common/i2c.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/stm32f1/i2c.c | 93 -------------------------------------------------- lib/stm32f2/Makefile | 2 +- 3 files changed, 94 insertions(+), 94 deletions(-) create mode 100644 lib/stm32_common/i2c.c delete mode 100644 lib/stm32f1/i2c.c (limited to 'lib/stm32f2') diff --git a/lib/stm32_common/i2c.c b/lib/stm32_common/i2c.c new file mode 100644 index 0000000..e1a3b84 --- /dev/null +++ b/lib/stm32_common/i2c.c @@ -0,0 +1,93 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void i2c_peripheral_enable(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_PE; +} + +void i2c_peripheral_disable(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_PE; +} + +void i2c_send_start(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_START; +} + +void i2c_send_stop(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_STOP; +} + +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) +{ + I2C_OAR1(i2c) = (u16)(slave << 1); + I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; + I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ +} + +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) +{ + I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); +} + +void i2c_set_fast_mode(u32 i2c) +{ + I2C_CCR(i2c) |= I2C_CCR_FS; +} + +void i2c_set_standard_mode(u32 i2c) +{ + I2C_CCR(i2c) &= ~I2C_CCR_FS; +} + +void i2c_set_clock_frequency(u32 i2c, u8 freq) +{ + u16 reg16; + reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ + reg16 |= freq; + I2C_CR2(i2c) = reg16; +} + +void i2c_set_ccr(u32 i2c, u16 freq) +{ + u16 reg16; + reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ + reg16 |= freq; + I2C_CCR(i2c) = reg16; +} + +void i2c_set_trise(u32 i2c, u16 trise) +{ + I2C_TRISE(i2c) = trise; +} + +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) +{ + I2C_DR(i2c) = (u8)((slave << 1) | readwrite); +} + +void i2c_send_data(u32 i2c, u8 data) +{ + I2C_DR(i2c) = data; +} diff --git a/lib/stm32f1/i2c.c b/lib/stm32f1/i2c.c deleted file mode 100644 index e1a3b84..0000000 --- a/lib/stm32f1/i2c.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void i2c_peripheral_enable(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_PE; -} - -void i2c_peripheral_disable(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_PE; -} - -void i2c_send_start(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_START; -} - -void i2c_send_stop(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_STOP; -} - -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) -{ - I2C_OAR1(i2c) = (u16)(slave << 1); - I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; - I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ -} - -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) -{ - I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); -} - -void i2c_set_fast_mode(u32 i2c) -{ - I2C_CCR(i2c) |= I2C_CCR_FS; -} - -void i2c_set_standard_mode(u32 i2c) -{ - I2C_CCR(i2c) &= ~I2C_CCR_FS; -} - -void i2c_set_clock_frequency(u32 i2c, u8 freq) -{ - u16 reg16; - reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ - reg16 |= freq; - I2C_CR2(i2c) = reg16; -} - -void i2c_set_ccr(u32 i2c, u16 freq) -{ - u16 reg16; - reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ - reg16 |= freq; - I2C_CCR(i2c) = reg16; -} - -void i2c_set_trise(u32 i2c, u16 trise) -{ - I2C_TRISE(i2c) = trise; -} - -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) -{ - I2C_DR(i2c) = (u8)((slave << 1) | readwrite); -} - -void i2c_send_data(u32 i2c, u8 data) -{ - I2C_DR(i2c) = data; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index d52525b..f3d6ff7 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o +OBJS = vector.o gpio.o systick.o i2c.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 010ee532982ae8329f712967e7e3759fa432ce76 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 15:07:07 -0700 Subject: Moved SPI to stm32 common. --- lib/stm32_common/spi.c | 290 +++++++++++++++++++++++++++++++++++++++++++++++++ lib/stm32f1/spi.c | 290 ------------------------------------------------- lib/stm32f2/Makefile | 2 +- 3 files changed, 291 insertions(+), 291 deletions(-) create mode 100644 lib/stm32_common/spi.c delete mode 100644 lib/stm32f1/spi.c (limited to 'lib/stm32f2') diff --git a/lib/stm32_common/spi.c b/lib/stm32_common/spi.c new file mode 100644 index 0000000..733a1bc --- /dev/null +++ b/lib/stm32_common/spi.c @@ -0,0 +1,290 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +/* + * SPI and I2S code. + * + * Examples: + * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + * SPI_CR1_LSBFIRST); + * spi_write(SPI1, 0x55); // 8-bit write + * spi_write(SPI1, 0xaa88); // 16-bit write + * reg8 = spi_read(SPI1); // 8-bit read + * reg16 = spi_read(SPI1); // 16-bit read + */ + +int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) +{ + u32 reg32 = 0; + + reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ + + reg32 |= br; /* Set BAUD rate bits. */ + reg32 |= cpol; /* Set CPOL value. */ + reg32 |= cpha; /* Set CPHA value. */ + reg32 |= dff; /* Set data format (8 or 16 bits). */ + reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ + + /* TODO: NSS pin handling. */ + + SPI_CR1(spi) = reg32; + + return 0; /* TODO */ +} + +/* TODO: Error handling? */ +void spi_enable(u32 spi) +{ + u32 reg32; + + reg32 = SPI_CR1(spi); + reg32 |= SPI_CR1_SPE; /* Enable SPI. */ + SPI_CR1(spi) = reg32; +} + +/* TODO: Error handling? */ +void spi_disable(u32 spi) +{ + u32 reg32; + + /* TODO: Follow procedure from section 23.3.8 in the techref manual. */ + reg32 = SPI_CR1(spi); + reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ + SPI_CR1(spi) = reg32; +} + +void spi_write(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; +} + +void spi_send(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; + + /* wait for transfer finished */ + while (SPI_SR(spi) & SPI_SR_BSY ) + { + } +} + +u16 spi_read(u32 spi) +{ + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR(spi); +} + +void spi_set_bidirectional_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; +} + +void spi_set_unidirectional_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; +} + +void spi_set_bidirectional_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; +} + +void spi_set_bidirectional_transmit_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) |= SPI_CR1_BIDIOE; +} + +void spi_enable_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCEN; +} + +void spi_disable_crc(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCEN; +} + +void spi_set_next_tx_from_buffer(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; +} + +void spi_set_next_tx_from_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCNEXT; +} + +void spi_set_dff_8bit(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_DFF; +} + +void spi_set_dff_16bit(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_DFF; +} + +void spi_set_full_duplex_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_RXONLY; +} + +void spi_set_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_RXONLY; +} + +void spi_disable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSM; +} + +void spi_enable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSM; +} + +void spi_set_nss_high(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSI; +} + +void spi_set_nss_low(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSI; +} + +void spi_send_lsb_first(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_LSBFIRST; +} + +void spi_send_msb_first(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; +} + +void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) +{ + u32 reg32; + + if (baudrate > 7) + return; + + reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ + reg32 |= (baudrate << 3); + SPI_CR1(spi) = reg32; +} + +void spi_set_master_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_MSTR; +} + +void spi_set_slave_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_MSTR; +} + +void spi_set_clock_polarity_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPOL; +} + +void spi_set_clock_polarity_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPOL; +} + +void spi_set_clock_phase_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPHA; +} + +void spi_set_clock_phase_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPHA; +} + +void spi_enable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXEIE; +} + +void spi_disable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXEIE; +} + +void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXNEIE; +} + +void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; +} + +void spi_enable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_ERRIE; +} + +void spi_disable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_ERRIE; +} + +void spi_enable_ss_output(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_SSOE; +} + +void spi_disable_ss_output(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_SSOE; +} + +void spi_enable_tx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXDMAEN; +} + +void spi_disable_tx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; +} + +void spi_enable_rx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXDMAEN; +} + +void spi_disable_rx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; +} diff --git a/lib/stm32f1/spi.c b/lib/stm32f1/spi.c deleted file mode 100644 index 733a1bc..0000000 --- a/lib/stm32f1/spi.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -/* - * SPI and I2S code. - * - * Examples: - * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, - * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, - * SPI_CR1_LSBFIRST); - * spi_write(SPI1, 0x55); // 8-bit write - * spi_write(SPI1, 0xaa88); // 16-bit write - * reg8 = spi_read(SPI1); // 8-bit read - * reg16 = spi_read(SPI1); // 16-bit read - */ - -int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) -{ - u32 reg32 = 0; - - reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ - - reg32 |= br; /* Set BAUD rate bits. */ - reg32 |= cpol; /* Set CPOL value. */ - reg32 |= cpha; /* Set CPHA value. */ - reg32 |= dff; /* Set data format (8 or 16 bits). */ - reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ - - /* TODO: NSS pin handling. */ - - SPI_CR1(spi) = reg32; - - return 0; /* TODO */ -} - -/* TODO: Error handling? */ -void spi_enable(u32 spi) -{ - u32 reg32; - - reg32 = SPI_CR1(spi); - reg32 |= SPI_CR1_SPE; /* Enable SPI. */ - SPI_CR1(spi) = reg32; -} - -/* TODO: Error handling? */ -void spi_disable(u32 spi) -{ - u32 reg32; - - /* TODO: Follow procedure from section 23.3.8 in the techref manual. */ - reg32 = SPI_CR1(spi); - reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ - SPI_CR1(spi) = reg32; -} - -void spi_write(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; -} - -void spi_send(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; - - /* wait for transfer finished */ - while (SPI_SR(spi) & SPI_SR_BSY ) - { - } -} - -u16 spi_read(u32 spi) -{ - /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ - return SPI_DR(spi); -} - -void spi_set_bidirectional_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; -} - -void spi_set_unidirectional_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; -} - -void spi_set_bidirectional_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; -} - -void spi_set_bidirectional_transmit_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) |= SPI_CR1_BIDIOE; -} - -void spi_enable_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCEN; -} - -void spi_disable_crc(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCEN; -} - -void spi_set_next_tx_from_buffer(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; -} - -void spi_set_next_tx_from_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCNEXT; -} - -void spi_set_dff_8bit(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_DFF; -} - -void spi_set_dff_16bit(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_DFF; -} - -void spi_set_full_duplex_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_RXONLY; -} - -void spi_set_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_RXONLY; -} - -void spi_disable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSM; -} - -void spi_enable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSM; -} - -void spi_set_nss_high(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSI; -} - -void spi_set_nss_low(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSI; -} - -void spi_send_lsb_first(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_LSBFIRST; -} - -void spi_send_msb_first(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; -} - -void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) -{ - u32 reg32; - - if (baudrate > 7) - return; - - reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ - reg32 |= (baudrate << 3); - SPI_CR1(spi) = reg32; -} - -void spi_set_master_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_MSTR; -} - -void spi_set_slave_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_MSTR; -} - -void spi_set_clock_polarity_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPOL; -} - -void spi_set_clock_polarity_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPOL; -} - -void spi_set_clock_phase_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPHA; -} - -void spi_set_clock_phase_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPHA; -} - -void spi_enable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXEIE; -} - -void spi_disable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXEIE; -} - -void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXNEIE; -} - -void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; -} - -void spi_enable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_ERRIE; -} - -void spi_disable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_ERRIE; -} - -void spi_enable_ss_output(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_SSOE; -} - -void spi_disable_ss_output(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_SSOE; -} - -void spi_enable_tx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXDMAEN; -} - -void spi_disable_tx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; -} - -void spi_enable_rx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXDMAEN; -} - -void spi_disable_rx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index f3d6ff7..ba0ae04 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 4d02d36d6b16e96eda731c9adbbbadd694371700 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 16:26:39 -0700 Subject: Moving nvic code to common, adding F1 and F2 specific user interrupt definition headers. --- include/libopencm3/stm32/f1/nvic.h | 162 ---------------------------------- include/libopencm3/stm32/f1/nvic_f1.h | 99 +++++++++++++++++++++ include/libopencm3/stm32/f2/nvic_f2.h | 112 +++++++++++++++++++++++ include/libopencm3/stm32/nvic.h | 108 +++++++++++++++++++++++ lib/stm32_common/nvic.c | 106 ++++++++++++++++++++++ lib/stm32f1/nvic.c | 106 ---------------------- lib/stm32f2/Makefile | 2 +- 7 files changed, 426 insertions(+), 269 deletions(-) delete mode 100644 include/libopencm3/stm32/f1/nvic.h create mode 100644 include/libopencm3/stm32/f1/nvic_f1.h create mode 100644 include/libopencm3/stm32/f2/nvic_f2.h create mode 100644 include/libopencm3/stm32/nvic.h create mode 100644 lib/stm32_common/nvic.c delete mode 100644 lib/stm32f1/nvic.c (limited to 'lib/stm32f2') diff --git a/include/libopencm3/stm32/f1/nvic.h b/include/libopencm3/stm32/f1/nvic.h deleted file mode 100644 index d29c425..0000000 --- a/include/libopencm3/stm32/f1/nvic.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 - -/* User Interrupts */ -#define NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMPER_IRQ 2 -#define NVIC_RTC_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_CHANNEL1_IRQ 11 -#define NVIC_DMA1_CHANNEL2_IRQ 12 -#define NVIC_DMA1_CHANNEL3_IRQ 13 -#define NVIC_DMA1_CHANNEL4_IRQ 14 -#define NVIC_DMA1_CHANNEL5_IRQ 15 -#define NVIC_DMA1_CHANNEL6_IRQ 16 -#define NVIC_DMA1_CHANNEL7_IRQ 17 -#define NVIC_ADC1_2_IRQ 18 -#define NVIC_USB_HP_CAN_TX_IRQ 19 -#define NVIC_USB_LP_CAN_RX0_IRQ 20 -#define NVIC_CAN_RX1_IRQ 21 -#define NVIC_CAN_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_IRQ 24 -#define NVIC_TIM1_UP_IRQ 25 -#define NVIC_TIM1_TRG_COM_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_WAKEUP_IRQ 42 -#define NVIC_TIM8_BRK_IRQ 43 -#define NVIC_TIM8_UP_IRQ 44 -#define NVIC_TIM8_TRG_COM_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_ADC3_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_USART4_IRQ 52 -#define NVIC_USART5_IRQ 53 -#define NVIC_TIM6_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_CHANNEL1_IRQ 56 -#define NVIC_DMA2_CHANNEL2_IRQ 57 -#define NVIC_DMA2_CHANNEL3_IRQ 58 -#define NVIC_DMA2_CHANNEL4_5_IRQ 59 -#define NVIC_DMA2_CHANNEL5_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 - -/* --- NVIC functions ------------------------------------------------------ */ - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -#endif diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h new file mode 100644 index 0000000..b0b32a0 --- /dev/null +++ b/include/libopencm3/stm32/f1/nvic_f1.h @@ -0,0 +1,99 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_F1_H +#define LIBOPENCM3_NVIC_F1_H + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Note: These F1 specific user interrupt definitions supplement the + * general NVIC definitions in ../nvic.h + */ + +/* User Interrupts */ +#define NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMPER_IRQ 2 +#define NVIC_RTC_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_CHANNEL1_IRQ 11 +#define NVIC_DMA1_CHANNEL2_IRQ 12 +#define NVIC_DMA1_CHANNEL3_IRQ 13 +#define NVIC_DMA1_CHANNEL4_IRQ 14 +#define NVIC_DMA1_CHANNEL5_IRQ 15 +#define NVIC_DMA1_CHANNEL6_IRQ 16 +#define NVIC_DMA1_CHANNEL7_IRQ 17 +#define NVIC_ADC1_2_IRQ 18 +#define NVIC_USB_HP_CAN_TX_IRQ 19 +#define NVIC_USB_LP_CAN_RX0_IRQ 20 +#define NVIC_CAN_RX1_IRQ 21 +#define NVIC_CAN_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_IRQ 24 +#define NVIC_TIM1_UP_IRQ 25 +#define NVIC_TIM1_TRG_COM_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_WAKEUP_IRQ 42 +#define NVIC_TIM8_BRK_IRQ 43 +#define NVIC_TIM8_UP_IRQ 44 +#define NVIC_TIM8_TRG_COM_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_ADC3_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_USART4_IRQ 52 +#define NVIC_USART5_IRQ 53 +#define NVIC_TIM6_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_CHANNEL1_IRQ 56 +#define NVIC_DMA2_CHANNEL2_IRQ 57 +#define NVIC_DMA2_CHANNEL3_IRQ 58 +#define NVIC_DMA2_CHANNEL4_5_IRQ 59 +#define NVIC_DMA2_CHANNEL5_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 + +#endif diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h new file mode 100644 index 0000000..2545f0a --- /dev/null +++ b/include/libopencm3/stm32/f2/nvic_f2.h @@ -0,0 +1,112 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_F2_H +#define LIBOPENCM3_NVIC_F2_H + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Note: These F2 specific user interrupt definitions supplement the + * general NVIC definitions in ../nvic.h + */ + +/* User Interrupts */ +#define NVIC_WWDG_IRQ 0 +#define PVD_IRQ 1 +#define TAMP_STAMP_IRQ 2 +#define RTC_WKUP_IRQ 3 +#define FLASH_IRQ 4 +#define RCC_IRQ 5 +#define EXTI0_IRQ 6 +#define EXTI1_IRQ 7 +#define EXTI2_IRQ 8 +#define EXTI3_IRQ 9 +#define EXTI4_IRQ 10 +#define DMA1_STREAM0_IRQ 11 +#define DMA1_STREAM1_IRQ 12 +#define DMA1_STREAM2_IRQ 13 +#define DMA1_STREAM3_IRQ 14 +#define DMA1_STREAM4_IRQ 15 +#define DMA1_STREAM5_IRQ 16 +#define DMA1_STREAM6_IRQ 17 +#define ADC_IRQ 18 +#define CAN1_TX_IRQ 19 +#define CAN1_RX0_IRQ 20 +#define CAN1_RX1_IRQ 21 +#define CAN1_SCE_IRQ 22 +#define EXTI9_5_IRQ 23 +#define TIM1_BRK_TIM9_IRQ 24 +#define TIM1_UP_TIM10_IRQ 25 +#define TIM1_TRG_COM_TIM11_IRQ 26 +#define TIM1_CC_IRQ 27 +#define TIM2_IRQ 28 +#define TIM3_IRQ 29 +#define TIM4_IRQ 30 +#define I2C1_EV_IRQ 31 +#define I2C1_ER_IRQ 32 +#define I2C2_EV_IRQ 33 +#define I2C2_ER_IRQ 34 +#define SPI1_IRQ 35 +#define SPI2_IRQ 36 +#define USART1_IRQ 37 +#define USART2_IRQ 38 +#define USART3_IRQ 39 +#define EXTI15_10_IRQ 40 +#define RTC_ALARM_IRQ 41 +#define USB_FS_WKUP_IRQ 42 +#define TIM8_BRK_TIM12_IRQ 43 +#define TIM8_UP_TIM13_IRQ 44 +#define TIM8_TRG_COM_TIM14_IRQ 45 +#define TIM8_CC_IRQ 46 +#define DMA1_STREAM7_IRQ 47 +#define FSMC_IRQ 48 +#define SDIO_IRQ 49 +#define TIM5_IRQ 50 +#define SPI3_IRQ 51 +#define USART4_IRQ 52 +#define USART5_IRQ 53 +#define TIM6_DAC_IRQ 54 +#define TIM7_IRQ 55 +#define DMA2_STREAM0_IRQ 56 +#define DMA2_STREAM1_IRQ 57 +#define DMA2_STREAM2_IRQ 58 +#define DMA2_STREAM3_IRQ 59 +#define DMA2_STREAM4_IRQ 60 +#define ETH_IRQ 61 +#define ETH_WKUP_IRQ 62 +#define CAN2_TX_IRQ 63 +#define CAN2_RX0_IRQ 64 +#define CAN2_RX1_IRQ 65 +#define CAN2_SCE_IRQ 66 +#define OTG_FS_IRQ 67 +#define DMA2_STREAM5_IRQ 68 +#define DMA2_STREAM6_IRQ 69 +#define DMA2_STREAM7_IRQ 70 +#define USART6_IRQ 71 +#define I2C3_EV_IRQ 72 +#define I2C3_ER_IRQ 73 +#define OTG_HS_EP1_OUT_IRQ 74 +#define OTG_HS_EP1_IN_IRQ 75 +#define OTG_HS_WKUP_IRQ 76 +#define OTG_HS_IRQ 77 +#define DCMI_IRQ 78 +#define CRYP_IRQ 79 +#define HASH_RNG_IRQ 80 + +#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h new file mode 100644 index 0000000..339a159 --- /dev/null +++ b/include/libopencm3/stm32/nvic.h @@ -0,0 +1,108 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 System Interrupts */ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 + + +/* Note: User interrupts are family specific and are defined in a familiy + * specific header file in the corresponding subfolder. + */ + +#ifdef STM32F1 +#include +#else +#ifdef STM32F2 +#include +#else +#error "stm32 family not defined." +#endif +#endif + + +/* --- NVIC functions ------------------------------------------------------ */ + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u8 irqn); + +#endif diff --git a/lib/stm32_common/nvic.c b/lib/stm32_common/nvic.c new file mode 100644 index 0000000..cf77cc3 --- /dev/null +++ b/lib/stm32_common/nvic.c @@ -0,0 +1,106 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void nvic_enable_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ISER(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ISER(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ISER(2) |= (1 << (irqn - 64)); +} + +void nvic_disable_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ICER(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ICER(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ICER(2) |= (1 << (irqn - 64)); +} + +u8 nvic_get_pending_irq(u8 irqn) +{ + if (irqn < 32) + return (NVIC_ISPR(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_ISPR(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_ISPR(2) & (1 << (irqn - 64))); + return 0; +} + +void nvic_set_pending_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ISPR(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ISPR(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ISPR(2) |= (1 << (irqn - 64)); +} + +void nvic_clear_pending_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ICPR(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ICPR(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ICPR(2) |= (1 << (irqn - 64)); +} + +u8 nvic_get_active_irq(u8 irqn) +{ + if (irqn < 32) + return (NVIC_IABR(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_IABR(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_IABR(2) & (1 << (irqn - 64))); + return 0; +} + +u8 nvic_get_irq_enabled(u8 irqn) +{ + if (irqn < 32) + return (NVIC_ISER(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_ISER(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_ISER(2) & (1 << (irqn - 64))); + return 0; +} + +void nvic_set_priority(u8 irqn, u8 priority) +{ + NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8)); +} + +void nvic_generate_software_interrupt(u8 irqn) +{ + if (irqn <= 239) + NVIC_STIR |= irqn; +} + + diff --git a/lib/stm32f1/nvic.c b/lib/stm32f1/nvic.c deleted file mode 100644 index f45b601..0000000 --- a/lib/stm32f1/nvic.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void nvic_enable_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ISER(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ISER(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ISER(2) |= (1 << (irqn - 64)); -} - -void nvic_disable_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ICER(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ICER(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ICER(2) |= (1 << (irqn - 64)); -} - -u8 nvic_get_pending_irq(u8 irqn) -{ - if (irqn < 32) - return (NVIC_ISPR(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_ISPR(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_ISPR(2) & (1 << (irqn - 64))); - return 0; -} - -void nvic_set_pending_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ISPR(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ISPR(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ISPR(2) |= (1 << (irqn - 64)); -} - -void nvic_clear_pending_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ICPR(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ICPR(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ICPR(2) |= (1 << (irqn - 64)); -} - -u8 nvic_get_active_irq(u8 irqn) -{ - if (irqn < 32) - return (NVIC_IABR(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_IABR(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_IABR(2) & (1 << (irqn - 64))); - return 0; -} - -u8 nvic_get_irq_enabled(u8 irqn) -{ - if (irqn < 32) - return (NVIC_ISER(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_ISER(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_ISER(2) & (1 << (irqn - 64))); - return 0; -} - -void nvic_set_priority(u8 irqn, u8 priority) -{ - NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8)); -} - -void nvic_generate_software_interrupt(u8 irqn) -{ - if (irqn <= 239) - NVIC_STIR |= irqn; -} - - diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index ba0ae04..cd50c4b 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o spi.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 7133e792398b87695fa73bb344c8d3d0cb08bb23 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 16 Sep 2011 23:14:07 -0700 Subject: Change default prefix in Makefiles to arm-none-eabi for compatability with summon toolchain out the box. --- examples/stm32f2/Makefile.include | 2 +- lib/stm32f2/Makefile | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'lib/stm32f2') diff --git a/examples/stm32f2/Makefile.include b/examples/stm32f2/Makefile.include index 6ec9f65..9cec6e7 100644 --- a/examples/stm32f2/Makefile.include +++ b/examples/stm32f2/Makefile.include @@ -20,7 +20,7 @@ ## PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index cd50c4b..5da64ab 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_stm32f2 -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 53f1c75c53f856af7a46cebc3e68a68c0a89036d Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 22 Sep 2011 14:23:25 -0700 Subject: Fixed bug in F2 GPIO code. --- lib/stm32f2/gpio.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index 2330628..abb08c0 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -17,29 +17,12 @@ * along with this program. If not, see . */ -/* - * Basic GPIO handling API. - * - * Examples: - * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); - * gpio_set(GPIOB, GPIO4); - * gpio_clear(GPIOG, GPIO2 | GPIO9); - * gpio_get(GPIOC, GPIO1); - * gpio_toggle(GPIOA, GPIO7 | GPIO8); - * reg16 = gpio_port_read(GPIOD); - * gpio_port_write(GPIOF, 0xc8fe); - * - * TODO: - * - GPIO remapping support - */ - #include void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) { u16 i; - u16 moder, pupd; + u32 moder, pupd; /* * We want to set the config only for the pins mentioned in gpios, -- cgit v1.2.3 From e772992f4c56d79581e62607c27609e4eeaaae7e Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 23 Sep 2011 13:05:12 -0700 Subject: Some more silly bugs in GPIO fixed for F2. --- lib/stm32f2/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index abb08c0..6e1ef08 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -49,7 +49,7 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) { u16 i; - u16 ospeedr; + u32 ospeedr; if (otype == 0x1) GPIO_OTYPER(gpioport) |= gpios; @@ -71,7 +71,7 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) { u16 i; - u16 afrl, afrh; + u32 afrl, afrh; afrl = GPIO_AFRL(gpioport); afrh = GPIO_AFRH(gpioport); -- cgit v1.2.3 From 8974be743571e32cc6b7a6bc29615e24d4aafc89 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Wed, 26 Oct 2011 13:29:52 -0700 Subject: Added convenience function code for EXTI on F2. --- lib/stm32f2/exti.c | 146 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 lib/stm32f2/exti.c (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/exti.c b/lib/stm32f2/exti.c new file mode 100644 index 0000000..1db9ad7 --- /dev/null +++ b/lib/stm32f2/exti.c @@ -0,0 +1,146 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +void exti_set_trigger(u32 extis, exti_trigger_type trig) +{ + switch (trig) { + case EXTI_TRIGGER_RISING: + EXTI_RTSR |= extis; + EXTI_FTSR &= ~extis; + break; + case EXTI_TRIGGER_FALLING: + EXTI_RTSR &= ~extis; + EXTI_FTSR |= extis; + break; + case EXTI_TRIGGER_BOTH: + EXTI_RTSR |= extis; + EXTI_FTSR |= extis; + break; + } +} + +void exti_enable_request(u32 extis) +{ + /* Enable interrupts. */ + EXTI_IMR |= extis; + + /* Enable events. */ + EXTI_EMR |= extis; +} + +void exti_disable_request(u32 extis) +{ + /* Disable interrupts. */ + EXTI_IMR &= ~extis; + + /* Disable events. */ + EXTI_EMR &= ~extis; +} + +/* + * Reset the interrupt request by writing a 1 to the corresponding + * pending bit register. + */ +void exti_reset_request(u32 extis) +{ + EXTI_PR = extis; +} + +/* + * Remap an external interrupt line to the corresponding pin on the + * specified GPIO port. + * + * TODO: This could be rewritten in fewer lines of code. + */ +void exti_select_source(u32 exti, u32 gpioport) +{ + u8 shift, bits; + + shift = bits = 0; + + switch (exti) { + case EXTI0: + case EXTI4: + case EXTI8: + case EXTI12: + shift = 0; + break; + case EXTI1: + case EXTI5: + case EXTI9: + case EXTI13: + shift = 4; + break; + case EXTI2: + case EXTI6: + case EXTI10: + case EXTI14: + shift = 8; + break; + case EXTI3: + case EXTI7: + case EXTI11: + case EXTI15: + shift = 12; + break; + } + + switch (gpioport) { + case GPIOA: + bits = 0xf; + break; + case GPIOB: + bits = 0xe; + break; + case GPIOC: + bits = 0xd; + break; + case GPIOD: + bits = 0xc; + break; + case GPIOE: + bits = 0xb; + break; + case GPIOF: + bits = 0xa; + break; + case GPIOG: + bits = 0x9; + break; + } + + /* Ensure that only valid EXTI lines are used. */ + if (exti < EXTI4) { + SYSCFG_EXTICR1 &= ~(0x000F << shift); + SYSCFG_EXTICR1 |= (~bits << shift); + } else if (exti < EXTI8) { + SYSCFG_EXTICR2 &= ~(0x000F << shift); + SYSCFG_EXTICR2 |= (~bits << shift); + } else if (exti < EXTI12) { + SYSCFG_EXTICR3 &= ~(0x000F << shift); + SYSCFG_EXTICR3 |= (~bits << shift); + } else if (exti < EXTI16) { + SYSCFG_EXTICR4 &= ~(0x000F << shift); + SYSCFG_EXTICR4 |= (~bits << shift); + } +} -- cgit v1.2.3 From 869a0df701e6f937a7d350350aebe3772c51f7ba Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Wed, 26 Oct 2011 13:30:44 -0700 Subject: Adding new EXTI stuff to F2 makefile. --- lib/stm32f2/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/stm32f2') diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index 5da64ab..192c7b0 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o exti.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 36cff03af1b4ad08c72ccc21bbd3903113ef423a Mon Sep 17 00:00:00 2001 From: Stephen Caudle Date: Thu, 27 Oct 2011 23:34:52 -0400 Subject: Add RCC and FLASH support for STM32F2 --- include/libopencm3/cm3/common.h | 2 + include/libopencm3/stm32/f2/flash.h | 153 +++++++++++++ include/libopencm3/stm32/f2/rcc.h | 39 ++++ lib/stm32f2/Makefile | 2 +- lib/stm32f2/flash.c | 250 ++++++++++++++++++++++ lib/stm32f2/rcc.c | 412 ++++++++++++++++++++++++++++++++++++ 6 files changed, 857 insertions(+), 1 deletion(-) create mode 100644 include/libopencm3/stm32/f2/flash.h create mode 100644 lib/stm32f2/flash.c create mode 100644 lib/stm32f2/rcc.c (limited to 'lib/stm32f2') diff --git a/include/libopencm3/cm3/common.h b/include/libopencm3/cm3/common.h index bbd04cb..08f553f 100644 --- a/include/libopencm3/cm3/common.h +++ b/include/libopencm3/cm3/common.h @@ -30,10 +30,12 @@ typedef int32_t s32; typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; +typedef uint64_t u64; /* Generic memory-mapped I/O accessor functions */ #define MMIO8(addr) (*(volatile u8 *)(addr)) #define MMIO16(addr) (*(volatile u16 *)(addr)) #define MMIO32(addr) (*(volatile u32 *)(addr)) +#define MMIO64(addr) (*(volatile u64 *)(addr)) #endif diff --git a/include/libopencm3/stm32/f2/flash.h b/include/libopencm3/stm32/f2/flash.h new file mode 100644 index 0000000..15529ea --- /dev/null +++ b/include/libopencm3/stm32/f2/flash.h @@ -0,0 +1,153 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * For details see: + * PM0042 Programming manual: STM32F10xxx Flash programming + * October 2009, Doc ID 13259 Rev 7 + * http://www.st.com/stonline/products/literature/pm/13259.pdf + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include +#include + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_DCRST (1 << 12) +#define FLASH_ICRST (1 << 11) +#define FLASH_DCE (1 << 10) +#define FLASH_ICE (1 << 9) +#define FLASH_PRFTEN (1 << 8) +#define FLASH_LATENCY_0WS 0x00 +#define FLASH_LATENCY_1WS 0x01 +#define FLASH_LATENCY_2WS 0x02 +#define FLASH_LATENCY_3WS 0x03 +#define FLASH_LATENCY_4WS 0x04 +#define FLASH_LATENCY_5WS 0x05 +#define FLASH_LATENCY_6WS 0x06 +#define FLASH_LATENCY_7WS 0x07 + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_BSY (1 << 16) +#define FLASH_PGSERR (1 << 7) +#define FLASH_PGPERR (1 << 6) +#define FLASH_PGAERR (1 << 5) +#define FLASH_WRPERR (1 << 4) +#define FLASH_OPERR (1 << 1) +#define FLASH_EOP (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_LOCK (1 << 31) +#define FLASH_ERRIE (1 << 25) +#define FLASH_EOPIE (1 << 24) +#define FLASH_STRT (1 << 16) +#define FLASH_MER (1 << 2) +#define FLASH_SER (1 << 1) +#define FLASH_PG (1 << 0) +#define FLASH_SECTOR_0 (0x00 << 3) +#define FLASH_SECTOR_1 (0x01 << 3) +#define FLASH_SECTOR_2 (0x02 << 3) +#define FLASH_SECTOR_3 (0x03 << 3) +#define FLASH_SECTOR_4 (0x04 << 3) +#define FLASH_SECTOR_5 (0x05 << 3) +#define FLASH_SECTOR_6 (0x06 << 3) +#define FLASH_SECTOR_7 (0x07 << 3) +#define FLASH_SECTOR_8 (0x08 << 3) +#define FLASH_SECTOR_9 (0x09 << 3) +#define FLASH_SECTOR_10 (0x0a << 3) +#define FLASH_SECTOR_11 (0x0b << 3) +#define FLASH_PROGRAM_X8 (0x00 << 8) +#define FLASH_PROGRAM_X16 (0x01 << 8) +#define FLASH_PROGRAM_X32 (0x02 << 8) +#define FLASH_PROGRAM_X64 (0x03 << 8) + +/* --- FLASH_OPTCR values -------------------------------------------------- */ + +/* FLASH_OPTCR[27:16]: nWRP */ +/* FLASH_OBR[15:8]: RDP */ +#define FLASH_NRST_STDBY (1 << 7) +#define FLASH_NRST_STOP (1 << 6) +#define FLASH_WDG_SW (1 << 5) +#define FLASH_OPTSTRT (1 << 1) +#define FLASH_OPTLOCK (1 << 0) +#define FLASH_BOR_LEVEL_3 (0x00 << 2) +#define FLASH_BOR_LEVEL_2 (0x01 << 2) +#define FLASH_BOR_LEVEL_1 (0x02 << 2) +#define FLASH_BOR_OFF (0x03 << 2) + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define FLASH_KEY1 ((u32)0x45670123) +#define FLASH_KEY2 ((u32)0xcdef89ab) +#define FLASH_OPTKEY1 ((u32)0x08192a3b) +#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f) + +/* --- Function prototypes ------------------------------------------------- */ + +void flash_dcache_enable(void); +void flash_dcache_disable(void); +void flash_icache_enable(void); +void flash_icache_disable(void); +void flash_prefetch_enable(void); +void flash_prefetch_disable(void); +void flash_dcache_reset(void); +void flash_icache_reset(void); +void flash_set_ws(u32 ws); +void flash_unlock(void); +void flash_lock(void); +void flash_clear_pgserr_flag(void); +void flash_clear_pgperr_flag(void); +void flash_clear_pgaerr_flag(void); +void flash_clear_eop_flag(void); +void flash_clear_wrperr_flag(void); +void flash_clear_bsy_flag(void); +void flash_clear_status_flags(void); +void flash_unlock_option_bytes(void); +void flash_lock_option_bytes(void); +void flash_erase_all_sectors(u32 program_size); +void flash_erase_sector(u32 sector, u32 program_size); +void flash_program_double_word(u32 address, u64 data, u32 program_size); +void flash_program_word(u32 address, u32 data, u32 program_size); +void flash_program_half_word(u32 address, u16 data, u32 program_size); +void flash_program_byte(u32 address, u8 data, u32 program_size); +void flash_wait_for_last_operation(void); +void flash_program_option_bytes(u32 data); + +#if 0 +// TODO: Implement support for option bytes +void flash_erase_option_bytes(void); +void flash_program_option_bytes(u32 address, u16 data); +#endif + +#endif diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h index 430ce77..ba24c86 100644 --- a/include/libopencm3/stm32/f2/rcc.h +++ b/include/libopencm3/stm32/f2/rcc.h @@ -449,5 +449,44 @@ /* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ #define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 +/* --- Variable definitions ------------------------------------------------ */ +extern u32 rcc_ppre1_frequency; +extern u32 rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + PLL, HSE, HSI, LSE, LSI +} osc_t; + +void rcc_osc_ready_int_clear(osc_t osc); +void rcc_osc_ready_int_enable(osc_t osc); +void rcc_osc_ready_int_disable(osc_t osc); +int rcc_osc_ready_int_flag(osc_t osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(osc_t osc); +void rcc_wait_for_sysclk_status(osc_t osc); +void rcc_osc_on(osc_t osc); +void rcc_osc_off(osc_t osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(osc_t osc); +void rcc_osc_bypass_disable(osc_t osc); +void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en); +void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en); +void rcc_peripheral_reset(volatile u32 *reg, u32 reset); +void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset); +void rcc_set_sysclk_source(u32 clk); +void rcc_set_pll_source(u32 pllsrc); +void rcc_set_ppre2(u32 ppre2); +void rcc_set_ppre1(u32 ppre1); +void rcc_set_hpre(u32 hpre); +void rcc_set_rtcpre(u32 rtcpre); +void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq); +void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq); +u32 rcc_get_system_clock_source(int i); +void rcc_clock_setup_in_hse_8mhz_out_120mhz(void); +void rcc_backupdomain_reset(void); #endif diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index 5da64ab..98ba878 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o rcc.o flash.o #VPATH += ../usb VPATH += ../stm32_common diff --git a/lib/stm32f2/flash.c b/lib/stm32f2/flash.c new file mode 100644 index 0000000..e9bc73e --- /dev/null +++ b/lib/stm32f2/flash.c @@ -0,0 +1,250 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +static inline void flash_set_program_size(u32 psize) +{ + FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8); + FLASH_CR |= psize; +} + +void flash_data_cache_enable(void) +{ + FLASH_ACR |= FLASH_DCE; +} + +void flash_dcache_disable(void) +{ + FLASH_ACR &= ~FLASH_DCE; +} + +void flash_icache_enable(void) +{ + FLASH_ACR |= FLASH_ICE; +} + +void flash_icache_disable(void) +{ + FLASH_ACR &= ~FLASH_ICE; +} + +void flash_prefetch_enable(void) +{ + FLASH_ACR |= FLASH_PRFTEN; +} + +void flash_prefetch_disable(void) +{ + FLASH_ACR &= ~FLASH_PRFTEN; +} + +void flash_dcache_reset(void) +{ + FLASH_ACR |= FLASH_DCRST; +} + +void flash_icache_reset(void) +{ + FLASH_ACR |= FLASH_ICRST; +} + +void flash_set_ws(u32 ws) +{ + u32 reg32; + + reg32 = FLASH_ACR; + reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2)); + reg32 |= ws; + FLASH_ACR = reg32; +} + +void flash_unlock(void) +{ + /* Authorize the FPEC access. */ + FLASH_KEYR = FLASH_KEY1; + FLASH_KEYR = FLASH_KEY2; +} + +void flash_lock(void) +{ + FLASH_CR |= FLASH_LOCK; +} + +void flash_clear_pgserr_flag(void) +{ + FLASH_SR |= FLASH_PGSERR; +} + +void flash_clear_pgperr_flag(void) +{ + FLASH_SR |= FLASH_PGPERR; +} + +void flash_clear_pgaerr_flag(void) +{ + FLASH_SR |= FLASH_PGAERR; +} + +void flash_clear_eop_flag(void) +{ + FLASH_SR |= FLASH_EOP; +} + +void flash_clear_wrperr_flag(void) +{ + FLASH_SR |= FLASH_WRPERR; +} + +void flash_clear_bsy_flag(void) +{ + FLASH_SR &= ~FLASH_BSY; +} + +void flash_clear_status_flags(void) +{ + flash_clear_pgserr_flag(); + flash_clear_pgperr_flag(); + flash_clear_pgaerr_flag(); + flash_clear_eop_flag(); + flash_clear_wrperr_flag(); + flash_clear_bsy_flag(); +} + +void flash_unlock_option_bytes(void) +{ + FLASH_OPTKEYR = FLASH_OPTKEY1; + FLASH_OPTKEYR = FLASH_OPTKEY2; +} + +void flash_lock_option_bytes(void) +{ + FLASH_OPTCR |= FLASH_OPTLOCK; +} + +void flash_wait_for_last_operation(void) +{ + while ((FLASH_SR & FLASH_BSY) == FLASH_BSY) + ; +} + +void flash_program_double_word(u32 address, u64 data, u32 program_size) +{ + /* Ensure that all flash operations are complete. */ + flash_wait_for_last_operation(); + flash_set_program_size(program_size); + + /* Enable writes to flash. */ + FLASH_CR |= FLASH_PG; + + /* Program the first half of the word. */ + MMIO64(address) = data; + + /* Wait for the write to complete. */ + flash_wait_for_last_operation(); + + /* Disable writes to flash. */ + FLASH_CR &= ~FLASH_PG; +} + +void flash_program_word(u32 address, u32 data, u32 program_size) +{ + /* Ensure that all flash operations are complete. */ + flash_wait_for_last_operation(); + flash_set_program_size(program_size); + + /* Enable writes to flash. */ + FLASH_CR |= FLASH_PG; + + /* Program the first half of the word. */ + MMIO32(address) = data; + + /* Wait for the write to complete. */ + flash_wait_for_last_operation(); + + /* Disable writes to flash. */ + FLASH_CR &= ~FLASH_PG; +} + +void flash_program_half_word(u32 address, u16 data, u32 program_size) +{ + flash_wait_for_last_operation(); + flash_set_program_size(program_size); + + FLASH_CR |= FLASH_PG; + + MMIO16(address) = data; + + flash_wait_for_last_operation(); + + FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */ +} + +void flash_program_byte(u32 address, u8 data, u32 program_size) +{ + flash_wait_for_last_operation(); + flash_set_program_size(program_size); + + FLASH_CR |= FLASH_PG; + + MMIO8(address) = data; + + flash_wait_for_last_operation(); + + FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */ +} + +void flash_erase_sector(u32 sector, u32 program_size) +{ + flash_wait_for_last_operation(); + flash_set_program_size(program_size); + + FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3); + FLASH_CR |= sector; + FLASH_CR |= FLASH_STRT; + + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_SER; + FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3); +} + +void flash_erase_all_sectors(u32 program_size) +{ + flash_wait_for_last_operation(); + flash_set_program_size(program_size); + + FLASH_CR |= FLASH_MER; /* Enable mass erase. */ + FLASH_CR |= FLASH_STRT; /* Trigger the erase. */ + + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */ +} + +void flash_program_option_bytes(u32 data) +{ + flash_wait_for_last_operation(); + + if (FLASH_OPTCR & FLASH_OPTLOCK) + flash_unlock_option_bytes(); + + FLASH_OPTCR = data & ~0x3; + FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */ + flash_wait_for_last_operation(); +} diff --git a/lib/stm32f2/rcc.c b/lib/stm32f2/rcc.c new file mode 100644 index 0000000..048f0ff --- /dev/null +++ b/lib/stm32f2/rcc.c @@ -0,0 +1,412 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */ +u32 rcc_ppre1_frequency = 8000000; +u32 rcc_ppre2_frequency = 8000000; + +/* TODO: Create a table for these values */ +#define RCC_PLL_M 8 +#define RCC_PLL_N 336 +#define RCC_PLL_P 2 +#define RCC_PLL_Q 7 +#define RCC_PLLI2S_N 192 +#define RCC_PLLI2S_R 5 + +void rcc_osc_ready_int_clear(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYC; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYC; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYC; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYC; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYC; + break; + } +} + +void rcc_osc_ready_int_enable(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYIE; + break; + } +} + +void rcc_osc_ready_int_disable(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR &= ~RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR &= ~RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR &= ~RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR &= ~RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR &= ~RCC_CIR_LSIRDYIE; + break; + } +} + +int rcc_osc_ready_int_flag(osc_t osc) +{ + switch (osc) { + case PLL: + return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); + break; + case HSE: + return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); + break; + case HSI: + return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); + break; + case LSE: + return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); + break; + case LSI: + return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); + break; + } + + /* Shouldn't be reached. */ + return -1; +} + +void rcc_css_int_clear(void) +{ + RCC_CIR |= RCC_CIR_CSSC; +} + +int rcc_css_int_flag(void) +{ + return ((RCC_CIR & RCC_CIR_CSSF) != 0); +} + +void rcc_wait_for_osc_ready(osc_t osc) +{ + switch (osc) { + case PLL: + while ((RCC_CR & RCC_CR_PLLRDY) == 0); + break; + case HSE: + while ((RCC_CR & RCC_CR_HSERDY) == 0); + break; + case HSI: + while ((RCC_CR & RCC_CR_HSIRDY) == 0); + break; + case LSE: + while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); + break; + case LSI: + while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); + break; + } +} + +void rcc_wait_for_sysclk_status(osc_t osc) +{ + switch (osc) { + case PLL: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL); + break; + case HSE: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE); + break; + case HSI: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI); + break; + default: + /* Shouldn't be reached. */ + break; + } +} + +void rcc_osc_on(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case HSI: + RCC_CR |= RCC_CR_HSION; + break; + case LSE: + RCC_BDCR |= RCC_BDCR_LSEON; + break; + case LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + } +} + +void rcc_osc_off(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case LSE: + RCC_BDCR &= ~RCC_BDCR_LSEON; + break; + case LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + } +} + +void rcc_css_enable(void) +{ + RCC_CR |= RCC_CR_CSSON; +} + +void rcc_css_disable(void) +{ + RCC_CR &= ~RCC_CR_CSSON; +} + +void rcc_osc_bypass_enable(osc_t osc) +{ + switch (osc) { + case HSE: + RCC_CR |= RCC_CR_HSEBYP; + break; + case LSE: + RCC_BDCR |= RCC_BDCR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } +} + +void rcc_osc_bypass_disable(osc_t osc) +{ + switch (osc) { + case HSE: + RCC_CR &= ~RCC_CR_HSEBYP; + break; + case LSE: + RCC_BDCR &= ~RCC_BDCR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } +} + +void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) +{ + *reg |= en; +} + +void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en) +{ + *reg &= ~en; +} + +void rcc_peripheral_reset(volatile u32 *reg, u32 reset) +{ + *reg |= reset; +} + +void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset) +{ + *reg &= ~clear_reset; +} + +void rcc_set_sysclk_source(u32 clk) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR = (reg32 | clk); +} + +void rcc_set_pll_source(u32 pllsrc) +{ + u32 reg32; + + reg32 = RCC_PLLCFGR; + reg32 &= ~(1 << 22); + RCC_PLLCFGR = (reg32 | (pllsrc << 22)); +} + +void rcc_set_ppre2(u32 ppre2) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13)); + RCC_CFGR = (reg32 | (ppre2 << 11)); +} + +void rcc_set_ppre1(u32 ppre1) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10)); + RCC_CFGR = (reg32 | (ppre1 << 8)); +} + +void rcc_set_hpre(u32 hpre) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); + RCC_CFGR = (reg32 | (hpre << 4)); +} + +void rcc_set_rtcpre(u32 rtcpre) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); + RCC_CFGR = (reg32 | (rtcpre << 16)); +} + +void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq) +{ + RCC_PLLCFGR = pllm | + (plln << 6) | + (((pllp >> 1) - 1) << 16) | + (pllq << 24); +} + +void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq) +{ + RCC_PLLCFGR = pllm | + (plln << 6) | + (((pllp >> 1) - 1) << 16) | + RCC_PLLCFGR_PLLSRC | + (pllq << 24); +} + +u32 rcc_system_clock_source(void) +{ + /* Return the clock source which is used as system clock. */ + return ((RCC_CFGR & 0x000c) >> 2); +} + +void rcc_clock_setup_in_hse_8mhz_out_120mhz(void) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_HSI); + + /* Enable external high-speed oscillator 8MHz. */ + rcc_osc_on(HSE); + rcc_wait_for_osc_ready(HSE); + rcc_set_sysclk_source(RCC_CFGR_SW_HSE); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE); /* Set. 120MHz Max. 120MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_DIV_4); /* Set. 30MHz Max. 30MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_DIV_2); /* Set. 60MHz Max. 60MHz */ + + rcc_set_main_pll_hse(RCC_PLL_M, RCC_PLL_N, RCC_PLL_P, RCC_PLL_Q); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* + * @3.3V + * Sysclk runs with 120MHz -> 3 waitstates. + * 0WS from 0-30MHz + * 1WS from 30-60MHz + * 2WS from 60-90MHz + * 3WS from 90-120MHz + */ + flash_set_ws(FLASH_PRFTEN | FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_PLL); + + /* Wait for PLL clock to be selected. */ + rcc_wait_for_sysclk_status(PLL); + + /* Set the peripheral clock frequencies used */ + rcc_ppre1_frequency = 30000000; + rcc_ppre2_frequency = 60000000; +} + +void rcc_backupdomain_reset(void) +{ + /* Set the backup domain software reset. */ + RCC_BDCR |= RCC_BDCR_BDRST; + + /* Clear the backup domain software reset. */ + RCC_BDCR &= ~RCC_BDCR_BDRST; +} -- cgit v1.2.3