From 3c67ef7d07cfa4d2d041fa4f641a9f6f3c4a33bf Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 23 Sep 2011 13:04:54 -0700 Subject: Minor fixes to the SPI code, mainly you should check that the TX buffer is empty before rather than after sending. --- lib/stm32_common/spi.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'lib/stm32_common') diff --git a/lib/stm32_common/spi.c b/lib/stm32_common/spi.c index 733a1bc..7fb8711 100644 --- a/lib/stm32_common/spi.c +++ b/lib/stm32_common/spi.c @@ -54,11 +54,7 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) /* TODO: Error handling? */ void spi_enable(u32 spi) { - u32 reg32; - - reg32 = SPI_CR1(spi); - reg32 |= SPI_CR1_SPE; /* Enable SPI. */ - SPI_CR1(spi) = reg32; + SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */ } /* TODO: Error handling? */ @@ -80,13 +76,11 @@ void spi_write(u32 spi, u16 data) void spi_send(u32 spi, u16 data) { + /* wait for transfer finished */ + while (SPI_SR(spi) & SPI_SR_BSY ); + /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR(spi) = data; - - /* wait for transfer finished */ - while (SPI_SR(spi) & SPI_SR_BSY ) - { - } } u16 spi_read(u32 spi) -- cgit v1.2.3