From 7ec382c7d5dfdc868ab52501bebf02eb23a416a0 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 5 Dec 2012 15:36:44 +1030 Subject: STM32: Moved SPI code into the common area. Updated the documentation so that it appears in all families Also added it to the L1 area, but is untested. An addition to the memorymap allows commonality and a #ifdef added to the spi_common_all code to exclude the case of SPI3 for L1 and F0 as SPI3 doesn't exist in those. An rcc dispatch header was added to remove same code from the spi header. --- lib/stm32/common/spi_common_all.c | 727 +++++++++++++++++++++++++++++++++++++ lib/stm32/f1/Makefile | 4 +- lib/stm32/f1/spi.c | 28 ++ lib/stm32/f2/Makefile | 4 +- lib/stm32/f2/spi.c | 28 ++ lib/stm32/f4/Makefile | 4 +- lib/stm32/f4/spi.c | 28 ++ lib/stm32/l1/Makefile | 4 +- lib/stm32/l1/spi.c | 28 ++ lib/stm32/spi.c | 737 -------------------------------------- 10 files changed, 847 insertions(+), 745 deletions(-) create mode 100644 lib/stm32/common/spi_common_all.c create mode 100644 lib/stm32/f1/spi.c create mode 100644 lib/stm32/f2/spi.c create mode 100644 lib/stm32/f4/spi.c create mode 100644 lib/stm32/l1/spi.c delete mode 100644 lib/stm32/spi.c (limited to 'lib/stm32') diff --git a/lib/stm32/common/spi_common_all.c b/lib/stm32/common/spi_common_all.c new file mode 100644 index 0000000..3df3dcd --- /dev/null +++ b/lib/stm32/common/spi_common_all.c @@ -0,0 +1,727 @@ +/** @addtogroup gpio_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 15 October 2012 + +Devices can have up to three SPI peripherals. The common 4-wire full-duplex +mode of operation is supported, along with 3-wire variants using unidirectional +communication modes or half-duplex bidirectional communication. A variety of +options allows many of the SPI variants to be supported. Multimaster operation +is also supported. A CRC can be generated and checked in hardware. + +@note Some JTAG pins need to be remapped if SPI is to be used. + +@note The I2S protocol shares the SPI hardware so the two protocols cannot be +used at the same time on the same peripheral. + +Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, +LSB first. +@code + spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + SPI_CR1_LSBFIRST); + spi_write(SPI1, 0x55); // 8-bit write + spi_write(SPI1, 0xaa88); // 16-bit write + reg8 = spi_read(SPI1); // 8-bit read + reg16 = spi_read(SPI1); // 16-bit read +@endcode + +@todo need additional functions to aid ISRs in retrieving status + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +/* + * SPI and I2S code. + * + * Examples: + * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + * SPI_CR1_LSBFIRST); + * spi_write(SPI1, 0x55); // 8-bit write + * spi_write(SPI1, 0xaa88); // 16-bit write + * reg8 = spi_read(SPI1); // 8-bit read + * reg16 = spi_read(SPI1); // 16-bit read + */ + +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Reset. + +The SPI peripheral and all its associated configuration registers are placed in the +reset condition. The reset is effected via the RCC peripheral reset system. + +@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_reset(u32 spi_peripheral) +{ + switch (spi_peripheral) { + case SPI1: + rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST); + break; + case SPI2: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST); + break; +#if defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) + case SPI3: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST); + break; +#endif + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Configure the SPI as Master. + +The SPI peripheral is configured as a master with communication parameters +baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity +and phase. The SPI enable, CRC enable and CRC next controls are not affected. +These must be controlled separately. + +@todo NSS pin handling. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] br Unsigned int32. Baudrate @ref spi_baudrate. +@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. +@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. +@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. +@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst. +@returns int. Error code. +*/ + +int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) +{ + u32 reg32 = SPI_CR1(spi); + + /* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */ + reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT; + + reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ + + reg32 |= br; /* Set baud rate bits. */ + reg32 |= cpol; /* Set CPOL value. */ + reg32 |= cpha; /* Set CPHA value. */ + reg32 |= dff; /* Set data format (8 or 16 bits). */ + reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ + + /* TODO: NSS pin handling. */ + + SPI_CR1(spi) = reg32; + + return 0; /* TODO */ +} + +/* TODO: Error handling? */ +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable. + +The SPI peripheral is enabled. + +@todo Error handling? + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */ +} + +/* TODO: Error handling? */ +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable. + +The SPI peripheral is disabled. + +@todo Follow procedure from section 23.3.8 in the TRM. +(possibly create a "clean disable" function separately) + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable(u32 spi) +{ + u32 reg32; + + reg32 = SPI_CR1(spi); + reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ + SPI_CR1(spi) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write. + +Data is written to the SPI interface. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +*/ + +void spi_write(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write with Blocking. + +Data is written to the SPI interface after the previous write transfer has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +*/ + +void spi_send(u32 spi, u16 data) +{ + /* Wait for transfer finished. */ + while (!(SPI_SR(spi) & SPI_SR_TXE)) + ; + + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Read. + +Data is read from the SPI interface after the incoming transfer has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@returns data Unsigned int16. 8 or 16 bit data. +*/ + +u16 spi_read(u32 spi) +{ + /* Wait for transfer finished. */ + while (!(SPI_SR(spi) & SPI_SR_RXNE)) + ; + + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR(spi); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write and Read Exchange. + +Data is written to the SPI interface, then a read is done after the incoming transfer +has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +@returns data Unsigned int16. 8 or 16 bit data. +*/ + +u16 spi_xfer(u32 spi, u16 data) +{ + spi_write(spi, data); + + /* Wait for transfer finished. */ + while (!(SPI_SR(spi) & SPI_SR_RXNE)) + ; + + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR(spi); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire). + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_bidirectional_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Unidirectional Mode. + +The SPI peripheral is set for unidirectional transfers. This is used in full duplex +mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a +unidirectional data wire. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_unidirectional_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Receive Only Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire), and is placed in a receive state. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_bidirectional_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Receive Only Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire), and is placed in a transmit state. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_bidirectional_transmit_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) |= SPI_CR1_BIDIOE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the CRC. + +The SPI peripheral is set to use a CRC field for transmit and receive. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the CRC. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable_crc(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Next Transmit is a Data Word + +The next transmission to take place is a data word from the transmit buffer. +This must be called before transmission to distinguish between sending +of a data or CRC word. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_next_tx_from_buffer(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Next Transmit is a CRC Word + +The next transmission to take place is a crc word from the hardware crc unit. +This must be called before transmission to distinguish between sending +of a data or CRC word. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_next_tx_from_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCNEXT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Data Frame Format to 8 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_dff_8bit(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_DFF; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Data Frame Format to 16 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_dff_16bit(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_DFF; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Full Duplex (3-wire) Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_full_duplex_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_RXONLY; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_RXONLY; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Slave Management by Hardware + +In slave mode the NSS hardware input is used as a select enable for the slave. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSM; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Slave Management by Software + +In slave mode the NSS hardware input is replaced by an internal software +enable/disable of the slave (@ref spi_set_nss_high). + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSM; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Software NSS Signal High + +In slave mode, and only when software slave management is used, this replaces +the NSS signal with a slave select enable signal. + +@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_nss_high(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSI; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Software NSS Signal Low + +In slave mode, and only when software slave management is used, this replaces +the NSS signal with a slave select disable signal. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_nss_low(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSI; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Send LSB First + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_send_lsb_first(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_LSBFIRST; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Send MSB First + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_send_msb_first(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Baudrate Prescaler + +@todo Why is this specification different to the spi_init_master baudrate values? + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre. +*/ + +void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) +{ + u32 reg32; + + if (baudrate > 7) + return; + + reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */ + reg32 |= (baudrate << 3); + SPI_CR1(spi) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Master Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_master_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_MSTR; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Slave Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_slave_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_MSTR; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Polarity to High when Idle + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_clock_polarity_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPOL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Polarity to Low when Idle + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_clock_polarity_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPOL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Phase to Capture on Trailing Edge + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_clock_phase_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPHA; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Phase to Capture on Leading Edge + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_clock_phase_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPHA; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Transmit Buffer Empty Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Transmit Buffer Empty Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Receive Buffer Ready Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXNEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Receive Buffer Ready Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Error Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_ERRIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Error Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_ERRIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the NSS Pin as an Output + +Normally used in master mode to allows the master to place all devices on the +SPI bus into slave mode. Multimaster mode is not possible. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable_ss_output(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_SSOE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the NSS Pin as an Input + +In master mode this allows the master to sense the presence of other masters. If +NSS is then pulled low the master is placed into slave mode. In slave mode NSS +becomes a slave enable. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable_ss_output(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_SSOE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Transmit Transfers via DMA + +This allows transmissions to proceed unattended using DMA to move data to the +transmit buffer as it becomes available. The DMA channels provided for each +SPI peripheral are given in the Technical Manual DMA section. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable_tx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXDMAEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable Transmit Transfers via DMA + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable_tx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Receive Transfers via DMA + +This allows received data streams to proceed unattended using DMA to move data from +the receive buffer as data becomes available. The DMA channels provided for each +SPI peripheral are given in the Technical Manual DMA section. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_enable_rx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXDMAEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable Receive Transfers via DMA + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_disable_rx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; +} + +/**@}*/ diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 2572554..845ae0c 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -28,12 +28,12 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o \ +OBJS = rcc.o gpio.o usart.o adc.o flash.o \ rtc.o i2c.o dma.o exti.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o \ usb_fx07_common.o \ - gpio_common_all.o + gpio_common_all.o spi_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/spi.c b/lib/stm32/f1/spi.c new file mode 100644 index 0000000..3be5c23 --- /dev/null +++ b/lib/stm32/f1/spi.c @@ -0,0 +1,28 @@ +/** @defgroup spi_file SPI + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx SPI + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index b890fa4..174dbce 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -28,9 +28,9 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o usart.o spi.o flash.o \ +OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o timer.o \ - gpio_common_all.o gpio_common_f24.o + gpio_common_all.o gpio_common_f24.o spi_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/spi.c b/lib/stm32/f2/spi.c new file mode 100644 index 0000000..bc4a4ee --- /dev/null +++ b/lib/stm32/f2/spi.c @@ -0,0 +1,28 @@ +/** @defgroup spi_file SPI + +@ingroup STM32F2xx + +@brief libopencm3 STM32F2xx SPI + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index c9ad847..0bd9a10 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -29,11 +29,11 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F4 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o usart.o spi.o flash.o \ +OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ - gpio_common_all.o gpio_common_f24.o + gpio_common_all.o gpio_common_f24.o spi_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f4/spi.c b/lib/stm32/f4/spi.c new file mode 100644 index 0000000..40f5501 --- /dev/null +++ b/lib/stm32/f4/spi.c @@ -0,0 +1,28 @@ +/** @defgroup spi_file SPI + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx SPI + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index a3c8856..b533acf 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o desig.o crc.o usart.o exti2.o -OBJS += flash.o gpio_common_all.o gpio_common_f24.o +OBJS = rcc.o desig.o crc.o usart.o exti2.o +OBJS += flash.o gpio_common_all.o gpio_common_f24.o spi_common_all.o OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o OBJS += timer.o diff --git a/lib/stm32/l1/spi.c b/lib/stm32/l1/spi.c new file mode 100644 index 0000000..30c44dd --- /dev/null +++ b/lib/stm32/l1/spi.c @@ -0,0 +1,28 @@ +/** @defgroup spi_file SPI + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx SPI + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/spi.c b/lib/stm32/spi.c deleted file mode 100644 index 90675b3..0000000 --- a/lib/stm32/spi.c +++ /dev/null @@ -1,737 +0,0 @@ -/** @defgroup spi_file SPI - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxxx SPI - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies - -@date 15 October 2012 - -Devices can have up to three SPI peripherals. The common 4-wire full-duplex -mode of operation is supported, along with 3-wire variants using unidirectional -communication modes or half-duplex bidirectional communication. A variety of -options allows many of the SPI variants to be supported. Multimaster operation -is also supported. A CRC can be generated and checked in hardware. - -@note Some JTAG pins need to be remapped if SPI is to be used. - -@note The I2S protocol shares the SPI hardware so the two protocols cannot be -used at the same time on the same peripheral. - -Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, -LSB first. -@code - spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, - SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, - SPI_CR1_LSBFIRST); - spi_write(SPI1, 0x55); // 8-bit write - spi_write(SPI1, 0xaa88); // 16-bit write - reg8 = spi_read(SPI1); // 8-bit read - reg16 = spi_read(SPI1); // 16-bit read -@endcode - -@todo need additional functions to aid ISRs in retrieving status - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#if defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#else -# error "stm32 family not defined." -#endif - -/* - * SPI and I2S code. - * - * Examples: - * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, - * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, - * SPI_CR1_LSBFIRST); - * spi_write(SPI1, 0x55); // 8-bit write - * spi_write(SPI1, 0xaa88); // 16-bit write - * reg8 = spi_read(SPI1); // 8-bit read - * reg16 = spi_read(SPI1); // 16-bit read - */ - -/**@{*/ - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Reset. - -The SPI peripheral and all its associated configuration registers are placed in the -reset condition. The reset is effected via the RCC peripheral reset system. - -@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_reset(u32 spi_peripheral) -{ - switch (spi_peripheral) { - case SPI1: - rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST); - break; - case SPI2: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST); - break; - case SPI3: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Configure the SPI as Master. - -The SPI peripheral is configured as a master with communication parameters -baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity -and phase. The SPI enable, CRC enable and CRC next controls are not affected. -These must be controlled separately. - -@todo NSS pin handling. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -@param[in] br Unsigned int32. Baudrate @ref spi_baudrate. -@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. -@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. -@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. -@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst. -@returns int. Error code. -*/ - -int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) -{ - u32 reg32 = SPI_CR1(spi); - - /* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */ - reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT; - - reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ - - reg32 |= br; /* Set baud rate bits. */ - reg32 |= cpol; /* Set CPOL value. */ - reg32 |= cpha; /* Set CPHA value. */ - reg32 |= dff; /* Set data format (8 or 16 bits). */ - reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ - - /* TODO: NSS pin handling. */ - - SPI_CR1(spi) = reg32; - - return 0; /* TODO */ -} - -/* TODO: Error handling? */ -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable. - -The SPI peripheral is enabled. - -@todo Error handling? - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */ -} - -/* TODO: Error handling? */ -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Disable. - -The SPI peripheral is disabled. - -@todo Follow procedure from section 23.3.8 in the TRM. -(possibly create a "clean disable" function separately) - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable(u32 spi) -{ - u32 reg32; - - reg32 = SPI_CR1(spi); - reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ - SPI_CR1(spi) = reg32; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Data Write. - -Data is written to the SPI interface. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -@param[in] data Unsigned int16. 8 or 16 bit data to be written. -*/ - -void spi_write(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Data Write with Blocking. - -Data is written to the SPI interface after the previous write transfer has finished. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -@param[in] data Unsigned int16. 8 or 16 bit data to be written. -*/ - -void spi_send(u32 spi, u16 data) -{ - /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_TXE)) - ; - - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Data Read. - -Data is read from the SPI interface after the incoming transfer has finished. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -@returns data Unsigned int16. 8 or 16 bit data. -*/ - -u16 spi_read(u32 spi) -{ - /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_RXNE)) - ; - - /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ - return SPI_DR(spi); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Data Write and Read Exchange. - -Data is written to the SPI interface, then a read is done after the incoming transfer -has finished. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -@param[in] data Unsigned int16. 8 or 16 bit data to be written. -@returns data Unsigned int16. 8 or 16 bit data. -*/ - -u16 spi_xfer(u32 spi, u16 data) -{ - spi_write(spi, data); - - /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_RXNE)) - ; - - /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ - return SPI_DR(spi); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Bidirectional Simplex Mode. - -The SPI peripheral is set for bidirectional transfers in two-wire simplex mode -(using a clock wire and a bidirectional data wire). - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_bidirectional_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Unidirectional Mode. - -The SPI peripheral is set for unidirectional transfers. This is used in full duplex -mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a -unidirectional data wire. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_unidirectional_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Bidirectional Simplex Receive Only Mode. - -The SPI peripheral is set for bidirectional transfers in two-wire simplex mode -(using a clock wire and a bidirectional data wire), and is placed in a receive state. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_bidirectional_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Bidirectional Simplex Receive Only Mode. - -The SPI peripheral is set for bidirectional transfers in two-wire simplex mode -(using a clock wire and a bidirectional data wire), and is placed in a transmit state. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_bidirectional_transmit_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) |= SPI_CR1_BIDIOE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable the CRC. - -The SPI peripheral is set to use a CRC field for transmit and receive. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Disable the CRC. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable_crc(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Next Transmit is a Data Word - -The next transmission to take place is a data word from the transmit buffer. -This must be called before transmission to distinguish between sending -of a data or CRC word. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_next_tx_from_buffer(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Next Transmit is a CRC Word - -The next transmission to take place is a crc word from the hardware crc unit. -This must be called before transmission to distinguish between sending -of a data or CRC word. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_next_tx_from_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCNEXT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Data Frame Format to 8 bits - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_dff_8bit(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_DFF; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Data Frame Format to 16 bits - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_dff_16bit(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_DFF; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Full Duplex (3-wire) Mode - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_full_duplex_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_RXONLY; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_RXONLY; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable Slave Management by Hardware - -In slave mode the NSS hardware input is used as a select enable for the slave. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSM; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable Slave Management by Software - -In slave mode the NSS hardware input is replaced by an internal software -enable/disable of the slave (@ref spi_set_nss_high). - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSM; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the Software NSS Signal High - -In slave mode, and only when software slave management is used, this replaces -the NSS signal with a slave select enable signal. - -@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_nss_high(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSI; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the Software NSS Signal Low - -In slave mode, and only when software slave management is used, this replaces -the NSS signal with a slave select disable signal. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_nss_low(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSI; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set to Send LSB First - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_send_lsb_first(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_LSBFIRST; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set to Send MSB First - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_send_msb_first(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the Baudrate Prescaler - -@todo Why is this specification different to the spi_init_master baudrate values? - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre. -*/ - -void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) -{ - u32 reg32; - - if (baudrate > 7) - return; - - reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */ - reg32 |= (baudrate << 3); - SPI_CR1(spi) = reg32; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set to Master Mode - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_master_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_MSTR; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set to Slave Mode - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_slave_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_MSTR; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the Clock Polarity to High when Idle - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_clock_polarity_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPOL; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the Clock Polarity to Low when Idle - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_clock_polarity_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPOL; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the Clock Phase to Capture on Trailing Edge - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_clock_phase_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPHA; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the Clock Phase to Capture on Leading Edge - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_clock_phase_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPHA; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable the Transmit Buffer Empty Interrupt - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Disable the Transmit Buffer Empty Interrupt - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable the Receive Buffer Ready Interrupt - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXNEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Disable the Receive Buffer Ready Interrupt - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable the Error Interrupt - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_ERRIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Disable the Error Interrupt - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_ERRIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the NSS Pin as an Output - -Normally used in master mode to allows the master to place all devices on the -SPI bus into slave mode. Multimaster mode is not possible. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable_ss_output(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_SSOE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set the NSS Pin as an Input - -In master mode this allows the master to sense the presence of other masters. If -NSS is then pulled low the master is placed into slave mode. In slave mode NSS -becomes a slave enable. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable_ss_output(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_SSOE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable Transmit Transfers via DMA - -This allows transmissions to proceed unattended using DMA to move data to the -transmit buffer as it becomes available. The DMA channels provided for each -SPI peripheral are given in the Technical Manual DMA section. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable_tx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXDMAEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Disable Transmit Transfers via DMA - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable_tx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Enable Receive Transfers via DMA - -This allows received data streams to proceed unattended using DMA to move data from -the receive buffer as data becomes available. The DMA channels provided for each -SPI peripheral are given in the Technical Manual DMA section. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_enable_rx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXDMAEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Disable Receive Transfers via DMA - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_disable_rx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; -} - -/**@}*/ -- cgit v1.2.3 From 1029597e7034bc088179227efe84bc0c00391082 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 5 Dec 2012 16:05:40 +1030 Subject: Move DAC to common area (Note there are now dummy source files dac.c (and others) that are not compiled but are needed for documentation). --- include/libopencm3/stm32/common/dac_common_all.h | 403 ++++++++++++++++++ include/libopencm3/stm32/dac.h | 409 +----------------- include/libopencm3/stm32/f1/dac.h | 40 ++ include/libopencm3/stm32/f2/dac.h | 40 ++ include/libopencm3/stm32/f4/dac.h | 40 ++ include/libopencm3/stm32/l1/dac.h | 40 ++ lib/stm32/common/dac_common_all.c | 516 ++++++++++++++++++++++ lib/stm32/dac.c | 520 ----------------------- lib/stm32/f1/Makefile | 4 +- lib/stm32/f1/dac.c | 28 ++ lib/stm32/f2/Makefile | 2 +- lib/stm32/f2/dac.c | 28 ++ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/dac.c | 28 ++ lib/stm32/l1/Makefile | 7 +- lib/stm32/l1/dac.c | 28 ++ 16 files changed, 1209 insertions(+), 926 deletions(-) create mode 100644 include/libopencm3/stm32/common/dac_common_all.h create mode 100644 include/libopencm3/stm32/f1/dac.h create mode 100644 include/libopencm3/stm32/f2/dac.h create mode 100644 include/libopencm3/stm32/f4/dac.h create mode 100644 include/libopencm3/stm32/l1/dac.h create mode 100644 lib/stm32/common/dac_common_all.c delete mode 100644 lib/stm32/dac.c create mode 100644 lib/stm32/f1/dac.c create mode 100644 lib/stm32/f2/dac.c create mode 100644 lib/stm32/f4/dac.c create mode 100644 lib/stm32/l1/dac.c (limited to 'lib/stm32') diff --git a/include/libopencm3/stm32/common/dac_common_all.h b/include/libopencm3/stm32/common/dac_common_all.h new file mode 100644 index 0000000..c843c55 --- /dev/null +++ b/include/libopencm3/stm32/common/dac_common_all.h @@ -0,0 +1,403 @@ +/** @addtogroup dac_defines */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Felix Held + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_DAC_COMMON_ALL_H +#define LIBOPENCM3_DAC_COMMON_ALL_H + +#include + + +/* --- DAC registers ------------------------------------------------------- */ + +/* DAC control register (DAC_CR) */ +#define DAC_CR MMIO32(DAC_BASE + 0x00) + +/* DAC software trigger register (DAC_SWTRIGR) */ +#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) + +/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */ +#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) + +/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */ +#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) + +/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */ +#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) + +/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */ +#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) + +/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */ +#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) + +/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */ +#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) + +/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */ +#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) + +/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */ +#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) + +/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */ +#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) + +/* DAC channel1 data output register (DAC_DOR1) */ +#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) + +/* DAC channel2 data output register (DAC_DOR2) */ +#define DAC_DOR2 MMIO32(DAC_BASE + 0x30) + + +/* --- DAC_CR values ------------------------------------------------------- */ + +/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */ +/* doesn't exist in most members of the STM32F1 family */ +#define DAC_CR_DMAUDRIE2 (1 << 29) + +/* DMAEN2: DAC channel2 DMA enable */ +#define DAC_CR_DMAEN2 (1 << 28) + +/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */ +/* DAC_CR_MAMP2_n: + * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 + */ +#define DAC_CR_MAMP2_SHIFT 24 +/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values +@ingroup STM32F_dac_defines + +Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1 +@{*/ +#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT) +/**@}*/ + +/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */ +/* Legend: + * DIS: wave generation disabled + * NOISE: Noise wave generation enabled + * TRI: Triangle wave generation enabled + * + * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + */ +#define DAC_CR_WAVE2_SHIFT 22 +#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT) +/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable +@ingroup STM32F_dac_defines + +@li NOISE: Noise wave generation enabled +@li TRI: Triangle wave generation enabled + +@note: only used if bit TEN2 is set (DAC channel2 trigger enabled) +@{*/ +#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) +#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT) +/**@}*/ + +/* TSEL2[2:0]: DAC channel2 trigger selection */ +/* Legend: + * + * T6: Timer 6 TRGO event + * T3: Timer 3 TRGO event + * T8: Timer 8 TRGO event + * T7: Timer 7 TRGO event + * T5: Timer 5 TRGO event + * T15: Timer 15 TRGO event + * T2: Timer 2 TRGO event + * T4: Timer 4 TRGO event + * E9: External line9 + * SW: Software trigger + * + * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + * Note: T3 == T8; T5 == T15; not both present on one device + * Note: this is *not* valid for the STM32L1 family + */ +#define DAC_CR_TSEL2_SHIFT 19 +/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection +@ingroup STM32F_dac_defines + +@li T6: Timer 6 TRGO event +@li T3: Timer 3 TRGO event +@li T8: Timer 8 TRGO event +@li T7: Timer 7 TRGO event +@li T5: Timer 5 TRGO event +@li T15: Timer 15 TRGO event +@li T2: Timer 2 TRGO event +@li T4: Timer 4 TRGO event +@li E9: External line9 +@li SW: Software trigger + +@note: Refer to the timer documentation for details of the TRGO event. +@note: T3 replaced by T8 and T5 replaced by T15 in some devices. +@note: this is not valid for the STM32L1 family. +@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled) +@{*/ +#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT) +/**@}*/ + +/* TEN2: DAC channel2 trigger enable */ +#define DAC_CR_TEN2 (1 << 18) + +/* BOFF2: DAC channel2 output buffer disable */ +#define DAC_CR_BOFF2 (1 << 17) + +/* EN2: DAC channel2 enable */ +#define DAC_CR_EN2 (1 << 16) + +/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */ +/* doesn't exist in most members of the STM32F1 family */ +#define DAC_CR_DMAUDRIE1 (1 << 13) + +/* DMAEN1: DAC channel1 DMA enable */ +#define DAC_CR_DMAEN1 (1 << 12) + +/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */ +/* DAC_CR_MAMP1_n: + * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 + */ +#define DAC_CR_MAMP1_SHIFT 8 +/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values +@ingroup STM32F_dac_defines + +Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 +@{*/ +#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT) +/**@}*/ + +/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */ +/* Legend: + * DIS: wave generation disabled + * NOISE: Noise wave generation enabled + * TRI: Triangle wave generation enabled + * + * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) + */ +#define DAC_CR_WAVE1_SHIFT 6 +#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT) +/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable +@ingroup STM32F_dac_defines + +@li DIS: wave generation disabled +@li NOISE: Noise wave generation enabled +@li TRI: Triangle wave generation enabled + +@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) +@{*/ +#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) +#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT) +/**@}*/ + +/* TSEL1[2:0]: DAC channel1 trigger selection */ +/* Legend: + * + * T6: Timer 6 TRGO event + * T3: Timer 3 TRGO event in connectivity line devices + * T8: Timer 8 TRGO event in high-density and XL-density devices + * T7: Timer 7 TRGO event + * T5: Timer 5 TRGO event + * T15: Timer 15 TRGO event + * T2: Timer 2 TRGO event + * T4: Timer 4 TRGO event + * E9: External line9 + * SW: Software trigger + * + * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) + * Note: T3 == T8; T5 == T15; not both present on one device + * Note: this is *not* valid for the STM32L1 family + */ +#define DAC_CR_TSEL1_SHIFT 3 +/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection +@ingroup STM32F_dac_defines + +@li T6: Timer 6 TRGO event +@li T3: Timer 3 TRGO event +@li T8: Timer 8 TRGO event +@li T7: Timer 7 TRGO event +@li T5: Timer 5 TRGO event +@li T15: Timer 15 TRGO event +@li T2: Timer 2 TRGO event +@li T4: Timer 4 TRGO event +@li E9: External line 9 +@li SW: Software trigger + +@note: Refer to the timer documentation for details of the TRGO event. +@note: T3 replaced by T8 and T5 replaced by T15 in some devices. +@note: this is not valid for the STM32L1 family. +@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled). +@{*/ +#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT) +/**@}*/ + +/* TEN1: DAC channel1 trigger enable */ +#define DAC_CR_TEN1 (1 << 2) + +/* BOFF1: DAC channel1 output buffer disable */ +#define DAC_CR_BOFF1 (1 << 1) + +/* EN1: DAC channel1 enable */ +#define DAC_CR_EN1 (1 << 0) + + +/* --- DAC_SWTRIGR values -------------------------------------------------- */ + +/* SWTRIG2: DAC channel2 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) + +/* SWTRIG1: DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) + + +/* --- DAC_DHR12R1 values -------------------------------------------------- */ +#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0) + + +/* --- DAC_DHR12L1 values -------------------------------------------------- */ +#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4) +#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8R1 values --------------------------------------------------- */ +#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0) +#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0) + + +/* --- DAC_DHR12R2 values -------------------------------------------------- */ +#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0) +#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0) + + +/* --- DAC_DHR12L2 values -------------------------------------------------- */ +#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4) +#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8R2 values --------------------------------------------------- */ +#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0) +#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0) + + +/* --- DAC_DHR12RD values -------------------------------------------------- */ +#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16) +#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16) +#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0) + + +/* --- DAC_DHR12LD values -------------------------------------------------- */ +#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16) +#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20) +#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8RD values --------------------------------------------------- */ +#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8) +#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8) +#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0) + + +/* --- DAC_DOR1 values ----------------------------------------------------- */ +#define DAC_DOR1_DACC1DOR_LSB (1 << 0) +#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0) + + +/* --- DAC_DOR2 values ----------------------------------------------------- */ +#define DAC_DOR2_DACC2DOR_LSB (1 << 0) +#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) + +/** DAC channel identifier */ +typedef enum { + CHANNEL_1, CHANNEL_2, CHANNEL_D +} data_channel; + +/** DAC data size (8/12 bits), alignment (right/left) */ +typedef enum { + RIGHT8, RIGHT12, LEFT12 +} data_align; + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dac_enable(data_channel dac_channel); +void dac_disable(data_channel dac_channel); +void dac_buffer_enable(data_channel dac_channel); +void dac_buffer_disable(data_channel dac_channel); +void dac_dma_enable(data_channel dac_channel); +void dac_dma_disable(data_channel dac_channel); +void dac_trigger_enable(data_channel dac_channel); +void dac_trigger_disable(data_channel dac_channel); +void dac_set_trigger_source(u32 dac_trig_src); +void dac_set_waveform_generation(u32 dac_wave_ens); +void dac_disable_waveform_generation(data_channel dac_channel); +void dac_set_waveform_characteristics(u32 dac_mamp); +void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel); +void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format); +void dac_software_trigger(data_channel dac_channel); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h index 75d4edb..242ef89 100644 --- a/include/libopencm3/stm32/dac.h +++ b/include/libopencm3/stm32/dac.h @@ -1,24 +1,8 @@ -/** @defgroup STM32F_dac_defines DAC Defines - -@brief libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Felix Held -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ +/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2012 Felix Held - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -33,386 +17,15 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ -/**@{*/ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include -#include - - -/* --- DAC registers ------------------------------------------------------- */ - -/* DAC control register (DAC_CR) */ -#define DAC_CR MMIO32(DAC_BASE + 0x00) - -/* DAC software trigger register (DAC_SWTRIGR) */ -#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) - -/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */ -#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) - -/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */ -#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) - -/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */ -#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) - -/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */ -#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) - -/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */ -#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) - -/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */ -#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) - -/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */ -#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) - -/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */ -#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) - -/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */ -#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) - -/* DAC channel1 data output register (DAC_DOR1) */ -#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) - -/* DAC channel2 data output register (DAC_DOR2) */ -#define DAC_DOR2 MMIO32(DAC_BASE + 0x30) - - -/* --- DAC_CR values ------------------------------------------------------- */ - -/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */ -/* doesn't exist in most members of the STM32F1 family */ -#define DAC_CR_DMAUDRIE2 (1 << 29) - -/* DMAEN2: DAC channel2 DMA enable */ -#define DAC_CR_DMAEN2 (1 << 28) - -/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */ -/* DAC_CR_MAMP2_n: - * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 - */ -#define DAC_CR_MAMP2_SHIFT 24 -/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values -@ingroup STM32F_dac_defines - -Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1 -@{*/ -#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT) -/**@}*/ - -/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */ -/* Legend: - * DIS: wave generation disabled - * NOISE: Noise wave generation enabled - * TRI: Triangle wave generation enabled - * - * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) - */ -#define DAC_CR_WAVE2_SHIFT 22 -#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT) -/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable -@ingroup STM32F_dac_defines - -@li NOISE: Noise wave generation enabled -@li TRI: Triangle wave generation enabled - -@note: only used if bit TEN2 is set (DAC channel2 trigger enabled) -@{*/ -#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) -#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT) -/**@}*/ - -/* TSEL2[2:0]: DAC channel2 trigger selection */ -/* Legend: - * - * T6: Timer 6 TRGO event - * T3: Timer 3 TRGO event - * T8: Timer 8 TRGO event - * T7: Timer 7 TRGO event - * T5: Timer 5 TRGO event - * T15: Timer 15 TRGO event - * T2: Timer 2 TRGO event - * T4: Timer 4 TRGO event - * E9: External line9 - * SW: Software trigger - * - * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) - * Note: T3 == T8; T5 == T15; not both present on one device - * Note: this is *not* valid for the STM32L1 family - */ -#define DAC_CR_TSEL2_SHIFT 19 -/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection -@ingroup STM32F_dac_defines - -@li T6: Timer 6 TRGO event -@li T3: Timer 3 TRGO event -@li T8: Timer 8 TRGO event -@li T7: Timer 7 TRGO event -@li T5: Timer 5 TRGO event -@li T15: Timer 15 TRGO event -@li T2: Timer 2 TRGO event -@li T4: Timer 4 TRGO event -@li E9: External line9 -@li SW: Software trigger - -@note: Refer to the timer documentation for details of the TRGO event. -@note: T3 replaced by T8 and T5 replaced by T15 in some devices. -@note: this is not valid for the STM32L1 family. -@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled) -@{*/ -#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT) -/**@}*/ - -/* TEN2: DAC channel2 trigger enable */ -#define DAC_CR_TEN2 (1 << 18) - -/* BOFF2: DAC channel2 output buffer disable */ -#define DAC_CR_BOFF2 (1 << 17) - -/* EN2: DAC channel2 enable */ -#define DAC_CR_EN2 (1 << 16) - -/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */ -/* doesn't exist in most members of the STM32F1 family */ -#define DAC_CR_DMAUDRIE1 (1 << 13) - -/* DMAEN1: DAC channel1 DMA enable */ -#define DAC_CR_DMAEN1 (1 << 12) - -/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */ -/* DAC_CR_MAMP1_n: - * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 - */ -#define DAC_CR_MAMP1_SHIFT 8 -/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values -@ingroup STM32F_dac_defines - -Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 -@{*/ -#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT) -/**@}*/ - -/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */ -/* Legend: - * DIS: wave generation disabled - * NOISE: Noise wave generation enabled - * TRI: Triangle wave generation enabled - * - * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) - */ -#define DAC_CR_WAVE1_SHIFT 6 -#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT) -/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable -@ingroup STM32F_dac_defines - -@li DIS: wave generation disabled -@li NOISE: Noise wave generation enabled -@li TRI: Triangle wave generation enabled - -@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) -@{*/ -#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) -#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT) -/**@}*/ - -/* TSEL1[2:0]: DAC channel1 trigger selection */ -/* Legend: - * - * T6: Timer 6 TRGO event - * T3: Timer 3 TRGO event in connectivity line devices - * T8: Timer 8 TRGO event in high-density and XL-density devices - * T7: Timer 7 TRGO event - * T5: Timer 5 TRGO event - * T15: Timer 15 TRGO event - * T2: Timer 2 TRGO event - * T4: Timer 4 TRGO event - * E9: External line9 - * SW: Software trigger - * - * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) - * Note: T3 == T8; T5 == T15; not both present on one device - * Note: this is *not* valid for the STM32L1 family - */ -#define DAC_CR_TSEL1_SHIFT 3 -/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection -@ingroup STM32F_dac_defines - -@li T6: Timer 6 TRGO event -@li T3: Timer 3 TRGO event -@li T8: Timer 8 TRGO event -@li T7: Timer 7 TRGO event -@li T5: Timer 5 TRGO event -@li T15: Timer 15 TRGO event -@li T2: Timer 2 TRGO event -@li T4: Timer 4 TRGO event -@li E9: External line 9 -@li SW: Software trigger - -@note: Refer to the timer documentation for details of the TRGO event. -@note: T3 replaced by T8 and T5 replaced by T15 in some devices. -@note: this is not valid for the STM32L1 family. -@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled). -@{*/ -#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT) -/**@}*/ - -/* TEN1: DAC channel1 trigger enable */ -#define DAC_CR_TEN1 (1 << 2) - -/* BOFF1: DAC channel1 output buffer disable */ -#define DAC_CR_BOFF1 (1 << 1) - -/* EN1: DAC channel1 enable */ -#define DAC_CR_EN1 (1 << 0) - - -/* --- DAC_SWTRIGR values -------------------------------------------------- */ - -/* SWTRIG2: DAC channel2 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) - -/* SWTRIG1: DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) - - -/* --- DAC_DHR12R1 values -------------------------------------------------- */ -#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0) - - -/* --- DAC_DHR12L1 values -------------------------------------------------- */ -#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4) -#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8R1 values --------------------------------------------------- */ -#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0) -#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0) - - -/* --- DAC_DHR12R2 values -------------------------------------------------- */ -#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0) -#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0) - - -/* --- DAC_DHR12L2 values -------------------------------------------------- */ -#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4) -#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8R2 values --------------------------------------------------- */ -#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0) -#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0) - - -/* --- DAC_DHR12RD values -------------------------------------------------- */ -#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16) -#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16) -#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0) - - -/* --- DAC_DHR12LD values -------------------------------------------------- */ -#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16) -#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20) -#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8RD values --------------------------------------------------- */ -#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8) -#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8) -#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0) - - -/* --- DAC_DOR1 values ----------------------------------------------------- */ -#define DAC_DOR1_DACC1DOR_LSB (1 << 0) -#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0) - - -/* --- DAC_DOR2 values ----------------------------------------------------- */ -#define DAC_DOR2_DACC2DOR_LSB (1 << 0) -#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) - -/** DAC channel identifier */ -typedef enum { - CHANNEL_1, CHANNEL_2, CHANNEL_D -} data_channel; - -/** DAC data size (8/12 bits), alignment (right/left) */ -typedef enum { - RIGHT8, RIGHT12, LEFT12 -} data_align; - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void dac_enable(data_channel dac_channel); -void dac_disable(data_channel dac_channel); -void dac_buffer_enable(data_channel dac_channel); -void dac_buffer_disable(data_channel dac_channel); -void dac_dma_enable(data_channel dac_channel); -void dac_dma_disable(data_channel dac_channel); -void dac_trigger_enable(data_channel dac_channel); -void dac_trigger_disable(data_channel dac_channel); -void dac_set_trigger_source(u32 dac_trig_src); -void dac_set_waveform_generation(u32 dac_wave_ens); -void dac_disable_waveform_generation(data_channel dac_channel); -void dac_set_waveform_characteristics(u32 dac_mamp); -void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel); -void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format); -void dac_software_trigger(data_channel dac_channel); - -END_DECLS - +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." #endif -/**@}*/ diff --git a/include/libopencm3/stm32/f1/dac.h b/include/libopencm3/stm32/f1/dac.h new file mode 100644 index 0000000..a4e07aa --- /dev/null +++ b/include/libopencm3/stm32/f1/dac.h @@ -0,0 +1,40 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F1xx DAC + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f2/dac.h b/include/libopencm3/stm32/f2/dac.h new file mode 100644 index 0000000..87bd456 --- /dev/null +++ b/include/libopencm3/stm32/f2/dac.h @@ -0,0 +1,40 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F2xx DAC + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f4/dac.h b/include/libopencm3/stm32/f4/dac.h new file mode 100644 index 0000000..4c6b43f --- /dev/null +++ b/include/libopencm3/stm32/f4/dac.h @@ -0,0 +1,40 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F4xx DAC + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/l1/dac.h b/include/libopencm3/stm32/l1/dac.h new file mode 100644 index 0000000..9ec57ea --- /dev/null +++ b/include/libopencm3/stm32/l1/dac.h @@ -0,0 +1,40 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32L1xx DAC + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include +#include + +#endif + diff --git a/lib/stm32/common/dac_common_all.c b/lib/stm32/common/dac_common_all.c new file mode 100644 index 0000000..a6be233 --- /dev/null +++ b/lib/stm32/common/dac_common_all.c @@ -0,0 +1,516 @@ +/** @addtogroup dac_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 18 August 2012 + +This library supports the Digital to Analog Conversion System in the +STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. + +The DAC is present only in a limited set of devices, notably some +of the connection line, high density and XL devices. + +Two DAC channels are available, however unlike the ADC channels these +are separate DAC devices controlled by the same register block. + +The DAC is on APB1. Its clock must be enabled in RCC and the GPIO +ports set to alternate function output before it can be used. +The digital output driver is disabled so the output driver mode +(push-pull/open drain) is arbitrary. + +The DAC has a holding (buffer) register and an output register from +which the analog output is derived. The holding register must be +loaded first. If triggering is enabled the output register is loaded +from the holding register after a trigger occurs. If triggering is +not enabled the holding register contents are transferred directly +to the output register. + +@note To avoid nonlinearities, do not allow outputs to range close +to zero or V_analog. + +@section dac_api_dual Dual Channel Conversion + +There are dual modes in which both DACs are used to output data +simultaneously or independently on both channels. The data must be +presented according to the formats described in the datasheets. A +convenience function @ref dac_load_data_buffer_dual is provided +for software controlled use. + +A variety of modes are available depending on whether independent +or simultaneous output is desired, and whether waveforms are to be +superimposed. Refer to the datasheets. + +If DMA is used, only enable it for one of the channels. The DMA +requests will then serve data in dual format to the data register +dedicated to dual mode. The data will then be split and loaded to the +appropriate DAC following the next trigger. There are three registers +available, one for each of the formats: 12 bit right-aligned, 12 bit +left-aligned and 8 bit right-aligned. The desired format is determined +by specifying the appropriate register to the DMA controller. + +@section dac_api_basic_ex Basic DAC handling API. + +Set the DAC's GPIO port to any alternate function output mode. Enable the +DAC clock. Enable the DAC, set a trigger source and load the buffer +with the first value. After the DAC is triggered, load the buffer with +the next value. This example uses software triggering and added noise. +The trigger and further buffer load calls are made when data is to be +sent out. + +@code + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4); + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN); + dac_disable(CHANNEL_1); + dac_set_waveform_characteristics(DAC_CR_MAMP1_8); + dac_set_waveform_generation(DAC_CR_WAVE1_NOISE); + dac_enable(CHANNEL_1); + dac_set_trigger_source(DAC_CR_TSEL1_SW); + dac_load_data_buffer_single(0, RIGHT12, CHANNEL_1); + .... + dac_software_trigger(CHANNEL_1); + dac_load_data_buffer_single(value, RIGHT12, CHANNEL_1); +@endcode + +@section dac_api_dma_ex Simultaneous Dual DAC with DMA. + +This example in part sets up the DAC channel 1 DMA (DMA2 channel 3) to read +16 bit data from memory into the right-aligned 8 bit dual register DAC_DHR8RD. +Both DAC channels are enabled, and both triggers are set to the same timer +2 input as required for simultaneous operation. DMA is enabled for DAC channel +1 only to ensure that only one DMA request is generated. + +@code + dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT); + dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT); + dma_set_read_from_memory(DMA2,DMA_CHANNEL3); + dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(u32) &DAC_DHR8RD); + dma_enable_channel(DMA2,DMA_CHANNEL3); + ... + dac_trigger_enable(CHANNEL_D); + dac_set_trigger_source(DAC_CR_TSEL1_T2 | DAC_CR_TSEL2_T2); + dac_dma_enable(CHANNEL_1); + dac_enable(CHANNEL_D); +@endcode + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +#define MASK8 0xFF +#define MASK12 0xFFF + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Enable. + +Enable a digital to analog converter channel. After setting this enable, the DAC +requires a twakeup time typically around 10 microseconds before it +actually wakes up. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_enable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR |= DAC_CR_EN1; + break; + case CHANNEL_2: + DAC_CR |= DAC_CR_EN2; + break; + case CHANNEL_D: + DAC_CR |= (DAC_CR_EN1 | DAC_CR_EN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Disable. + +Disable a digital to analog converter channel. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_disable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_EN1; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_EN2; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_EN1 | DAC_CR_EN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Output Buffer Enable. + +Enable a digital to analog converter channel output drive buffer. This is an optional +amplifying buffer that provides additional drive for the output signal. The +buffer is enabled by default after a reset and needs to be explicitly disabled +if required. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_buffer_enable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR |= DAC_CR_BOFF1; + break; + case CHANNEL_2: + DAC_CR |= DAC_CR_BOFF2; + break; + case CHANNEL_D: + DAC_CR |= (DAC_CR_BOFF1 | DAC_CR_BOFF2); + break; + } +} +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Output Buffer Disable. + +Disable a digital to analog converter channel output drive buffer. Disabling this will +reduce power consumption slightly and will increase the output impedance of the DAC. +The buffers are enabled by default after a reset. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_buffer_disable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_BOFF1; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_BOFF2; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_BOFF1 | DAC_CR_BOFF2); + break; + } +} +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel DMA Enable. + +Enable a digital to analog converter channel DMA mode (connected to DMA2 channel +3 for DAC channel 1 and DMA2 channel 4 for DAC channel 2). A DMA request is +generated following an external trigger. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_dma_enable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR |= DAC_CR_DMAEN1; + break; + case CHANNEL_2: + DAC_CR |= DAC_CR_DMAEN2; + break; + case CHANNEL_D: + DAC_CR |= (DAC_CR_DMAEN1 | DAC_CR_DMAEN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel DMA Disable. + +Disable a digital to analog converter channel DMA mode. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_dma_disable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_DMAEN1; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_DMAEN2; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_DMAEN1 | DAC_CR_DMAEN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Trigger Enable. + +Enable a digital to analog converter channel external trigger mode. This allows an +external trigger to initiate register transfers from the buffer register to the DAC +output register, followed by a DMA transfer to the buffer register if DMA is enabled. +The trigger source must also be selected. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_trigger_enable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR |= DAC_CR_TEN1; + break; + case CHANNEL_2: + DAC_CR |= DAC_CR_TEN2; + break; + case CHANNEL_D: + DAC_CR |= (DAC_CR_TEN1 | DAC_CR_TEN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Trigger Disable. + +Disable a digital to analog converter channel external trigger. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_trigger_disable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_TEN1; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_TEN2; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_TEN1 | DAC_CR_TEN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Set DAC Channel Trigger Source. + +Sets the digital to analog converter trigger source, which can be taken from various +timers, an external trigger or a software trigger. + +@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or +a logical OR of one of each of these to set both channels simultaneously. +*/ + +void dac_set_trigger_source(u32 dac_trig_src) +{ + DAC_CR |= dac_trig_src; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Enable and Set DAC Channel Waveform Generation. + +Enable the digital to analog converter waveform generation as either pseudo-random +noise or triangular wave. These signals are superimposed on existing output values +in the DAC output registers. + +@note The DAC trigger must be enabled for this to work. + +@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en or +a logical OR of one of each of these to set both channels simultaneously. +*/ + +void dac_set_waveform_generation(u32 dac_wave_ens) +{ + DAC_CR |= dac_wave_ens; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Disable DAC Channel Waveform Generation. + +Disable a digital to analog converter channel superimposed waveform generation. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_disable_waveform_generation(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_WAVE1_DIS; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_WAVE2_DIS; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_WAVE1_DIS | DAC_CR_WAVE2_DIS); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude. + +Sets the digital to analog converter superimposed waveform generation characteristics. +@li If the noise generation mode is set, this sets the length of the PRBS sequence and +hence the amplitude of the output noise signal. Default setting is length 1. +@li If the triangle wave generation mode is set, this sets the amplitude of the +output signal as 2^(n)-1 where n is the parameter value. Default setting is 1. + +@note High amplitude levels of these waveforms can overload the DAC and distort the +signal output. +@note This must be called before enabling the DAC as the settings will then become read-only. +@note The DAC trigger must be enabled for this to work. + +@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR +of one of each of these to set both channels simultaneously. +*/ + +void dac_set_waveform_characteristics(u32 dac_mamp) +{ + DAC_CR |= dac_mamp; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Load DAC Data Register. + +Loads the appropriate digital to analog converter data register with 12 or 8 bit +data to be converted on a channel. The data can be aligned as follows: +@li right-aligned 8 bit data in bits 0-7 +@li right-aligned 12 bit data in bits 0-11 +@li left aligned 12 bit data in bits 4-15 + +This function can also be used to load the dual channel registers if the data is +formatted according to the datasheets: +@li right-aligned 8 bit data in bits 0-7 for channel 1 and 8-15 for channel 2 +@li right-aligned 12 bit data in bits 0-11 for channel 1 and 16-27 for channel 2 +@li left aligned 12 bit data in bits 4-15 for channel 1 and 20-31 for channel 2 + +@param[in] dac_data u32 with appropriate alignment. +@param[in] dac_data_format enum ::data_align. Alignment and size. +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel) +{ + if (dac_channel == CHANNEL_1) + { + switch (dac_data_format) { + case RIGHT8: + DAC_DHR8R1 = dac_data; + break; + case RIGHT12: + DAC_DHR12R1 = dac_data; + break; + case LEFT12: + DAC_DHR12L1 = dac_data; + break; + } + } + else if (dac_channel == CHANNEL_2) + { + switch (dac_data_format) { + case RIGHT8: + DAC_DHR8R2 = dac_data; + break; + case RIGHT12: + DAC_DHR12R2 = dac_data; + break; + case LEFT12: + DAC_DHR12L2 = dac_data; + break; + } + } + else + switch (dac_data_format) { + case RIGHT8: + DAC_DHR8RD = dac_data; + break; + case RIGHT12: + DAC_DHR12RD = dac_data; + break; + case LEFT12: + DAC_DHR12LD = dac_data; + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Load DAC Dual Data Register. + +Loads the appropriate digital to analog converter dual data register with 12 or +8 bit data to be converted for both channels. This allows high bandwidth +simultaneous or independent analog output. The data in both channels are aligned +identically. + +@param[in] dac_data1 u32 for channel 1 with appropriate alignment. +@param[in] dac_data2 u32 for channel 2 with appropriate alignment. +@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit. +*/ + +void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format) +{ + switch (dac_data_format) { + case RIGHT8: + DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8)); + break; + case RIGHT12: + DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 12)); + break; + case LEFT12: + DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16)); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Trigger the DAC by a Software Trigger. + +If the trigger source is set to be a software trigger, cause a trigger to occur. +The trigger is cleared by hardware after conversion. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_software_trigger(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG1; + break; + case CHANNEL_2: + DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG2; + break; + case CHANNEL_D: + DAC_SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2); + break; + } +} +/**@}*/ + diff --git a/lib/stm32/dac.c b/lib/stm32/dac.c deleted file mode 100644 index 55440bf..0000000 --- a/lib/stm32/dac.c +++ /dev/null @@ -1,520 +0,0 @@ -/** @defgroup STM32F_dac_file DAC - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxx Digital to Analog Converter - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies - -@date 18 August 2012 - -This library supports the Digital to Analog Conversion System in the -STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. - -The DAC is present only in a limited set of devices, notably some -of the connection line, high density and XL devices. - -Two DAC channels are available, however unlike the ADC channels these -are separate DAC devices controlled by the same register block. - -The DAC is on APB1. Its clock must be enabled in RCC and the GPIO -ports set to alternate function output before it can be used. -The digital output driver is disabled so the output driver mode -(push-pull/open drain) is arbitrary. - -The DAC has a holding (buffer) register and an output register from -which the analog output is derived. The holding register must be -loaded first. If triggering is enabled the output register is loaded -from the holding register after a trigger occurs. If triggering is -not enabled the holding register contents are transferred directly -to the output register. - -@note To avoid nonlinearities, do not allow outputs to range close -to zero or V_analog. - -@section dac_api_dual Dual Channel Conversion - -There are dual modes in which both DACs are used to output data -simultaneously or independently on both channels. The data must be -presented according to the formats described in the datasheets. A -convenience function @ref dac_load_data_buffer_dual is provided -for software controlled use. - -A variety of modes are available depending on whether independent -or simultaneous output is desired, and whether waveforms are to be -superimposed. Refer to the datasheets. - -If DMA is used, only enable it for one of the channels. The DMA -requests will then serve data in dual format to the data register -dedicated to dual mode. The data will then be split and loaded to the -appropriate DAC following the next trigger. There are three registers -available, one for each of the formats: 12 bit right-aligned, 12 bit -left-aligned and 8 bit right-aligned. The desired format is determined -by specifying the appropriate register to the DMA controller. - -@section dac_api_basic_ex Basic DAC handling API. - -Set the DAC's GPIO port to any alternate function output mode. Enable the -DAC clock. Enable the DAC, set a trigger source and load the buffer -with the first value. After the DAC is triggered, load the buffer with -the next value. This example uses software triggering and added noise. -The trigger and further buffer load calls are made when data is to be -sent out. - -@code - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4); - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN); - dac_disable(CHANNEL_1); - dac_set_waveform_characteristics(DAC_CR_MAMP1_8); - dac_set_waveform_generation(DAC_CR_WAVE1_NOISE); - dac_enable(CHANNEL_1); - dac_set_trigger_source(DAC_CR_TSEL1_SW); - dac_load_data_buffer_single(0, RIGHT12, CHANNEL_1); - .... - dac_software_trigger(CHANNEL_1); - dac_load_data_buffer_single(value, RIGHT12, CHANNEL_1); -@endcode - -@section dac_api_dma_ex Simultaneous Dual DAC with DMA. - -This example in part sets up the DAC channel 1 DMA (DMA2 channel 3) to read -16 bit data from memory into the right-aligned 8 bit dual register DAC_DHR8RD. -Both DAC channels are enabled, and both triggers are set to the same timer -2 input as required for simultaneous operation. DMA is enabled for DAC channel -1 only to ensure that only one DMA request is generated. - -@code - dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT); - dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT); - dma_set_read_from_memory(DMA2,DMA_CHANNEL3); - dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(u32) &DAC_DHR8RD); - dma_enable_channel(DMA2,DMA_CHANNEL3); - ... - dac_trigger_enable(CHANNEL_D); - dac_set_trigger_source(DAC_CR_TSEL1_T2 | DAC_CR_TSEL2_T2); - dac_dma_enable(CHANNEL_1); - dac_enable(CHANNEL_D); -@endcode - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#include - -#define MASK8 0xFF -#define MASK12 0xFFF - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Enable. - -Enable a digital to analog converter channel. After setting this enable, the DAC -requires a twakeup time typically around 10 microseconds before it -actually wakes up. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_enable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR |= DAC_CR_EN1; - break; - case CHANNEL_2: - DAC_CR |= DAC_CR_EN2; - break; - case CHANNEL_D: - DAC_CR |= (DAC_CR_EN1 | DAC_CR_EN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Disable. - -Disable a digital to analog converter channel. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_disable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_EN1; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_EN2; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_EN1 | DAC_CR_EN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Output Buffer Enable. - -Enable a digital to analog converter channel output drive buffer. This is an optional -amplifying buffer that provides additional drive for the output signal. The -buffer is enabled by default after a reset and needs to be explicitly disabled -if required. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_buffer_enable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR |= DAC_CR_BOFF1; - break; - case CHANNEL_2: - DAC_CR |= DAC_CR_BOFF2; - break; - case CHANNEL_D: - DAC_CR |= (DAC_CR_BOFF1 | DAC_CR_BOFF2); - break; - } -} -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Output Buffer Disable. - -Disable a digital to analog converter channel output drive buffer. Disabling this will -reduce power consumption slightly and will increase the output impedance of the DAC. -The buffers are enabled by default after a reset. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_buffer_disable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_BOFF1; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_BOFF2; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_BOFF1 | DAC_CR_BOFF2); - break; - } -} -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel DMA Enable. - -Enable a digital to analog converter channel DMA mode (connected to DMA2 channel -3 for DAC channel 1 and DMA2 channel 4 for DAC channel 2). A DMA request is -generated following an external trigger. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_dma_enable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR |= DAC_CR_DMAEN1; - break; - case CHANNEL_2: - DAC_CR |= DAC_CR_DMAEN2; - break; - case CHANNEL_D: - DAC_CR |= (DAC_CR_DMAEN1 | DAC_CR_DMAEN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel DMA Disable. - -Disable a digital to analog converter channel DMA mode. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_dma_disable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_DMAEN1; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_DMAEN2; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_DMAEN1 | DAC_CR_DMAEN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Trigger Enable. - -Enable a digital to analog converter channel external trigger mode. This allows an -external trigger to initiate register transfers from the buffer register to the DAC -output register, followed by a DMA transfer to the buffer register if DMA is enabled. -The trigger source must also be selected. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_trigger_enable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR |= DAC_CR_TEN1; - break; - case CHANNEL_2: - DAC_CR |= DAC_CR_TEN2; - break; - case CHANNEL_D: - DAC_CR |= (DAC_CR_TEN1 | DAC_CR_TEN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Trigger Disable. - -Disable a digital to analog converter channel external trigger. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_trigger_disable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_TEN1; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_TEN2; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_TEN1 | DAC_CR_TEN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Set DAC Channel Trigger Source. - -Sets the digital to analog converter trigger source, which can be taken from various -timers, an external trigger or a software trigger. - -@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or -a logical OR of one of each of these to set both channels simultaneously. -*/ - -void dac_set_trigger_source(u32 dac_trig_src) -{ - DAC_CR |= dac_trig_src; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Enable and Set DAC Channel Waveform Generation. - -Enable the digital to analog converter waveform generation as either pseudo-random -noise or triangular wave. These signals are superimposed on existing output values -in the DAC output registers. - -@note The DAC trigger must be enabled for this to work. - -@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en or -a logical OR of one of each of these to set both channels simultaneously. -*/ - -void dac_set_waveform_generation(u32 dac_wave_ens) -{ - DAC_CR |= dac_wave_ens; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Disable DAC Channel Waveform Generation. - -Disable a digital to analog converter channel superimposed waveform generation. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_disable_waveform_generation(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_WAVE1_DIS; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_WAVE2_DIS; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_WAVE1_DIS | DAC_CR_WAVE2_DIS); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude. - -Sets the digital to analog converter superimposed waveform generation characteristics. -@li If the noise generation mode is set, this sets the length of the PRBS sequence and -hence the amplitude of the output noise signal. Default setting is length 1. -@li If the triangle wave generation mode is set, this sets the amplitude of the -output signal as 2^(n)-1 where n is the parameter value. Default setting is 1. - -@note High amplitude levels of these waveforms can overload the DAC and distort the -signal output. -@note This must be called before enabling the DAC as the settings will then become read-only. -@note The DAC trigger must be enabled for this to work. - -@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR -of one of each of these to set both channels simultaneously. -*/ - -void dac_set_waveform_characteristics(u32 dac_mamp) -{ - DAC_CR |= dac_mamp; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Load DAC Data Register. - -Loads the appropriate digital to analog converter data register with 12 or 8 bit -data to be converted on a channel. The data can be aligned as follows: -@li right-aligned 8 bit data in bits 0-7 -@li right-aligned 12 bit data in bits 0-11 -@li left aligned 12 bit data in bits 4-15 - -This function can also be used to load the dual channel registers if the data is -formatted according to the datasheets: -@li right-aligned 8 bit data in bits 0-7 for channel 1 and 8-15 for channel 2 -@li right-aligned 12 bit data in bits 0-11 for channel 1 and 16-27 for channel 2 -@li left aligned 12 bit data in bits 4-15 for channel 1 and 20-31 for channel 2 - -@param[in] dac_data u32 with appropriate alignment. -@param[in] dac_data_format enum ::data_align. Alignment and size. -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel) -{ - if (dac_channel == CHANNEL_1) - { - switch (dac_data_format) { - case RIGHT8: - DAC_DHR8R1 = dac_data; - break; - case RIGHT12: - DAC_DHR12R1 = dac_data; - break; - case LEFT12: - DAC_DHR12L1 = dac_data; - break; - } - } - else if (dac_channel == CHANNEL_2) - { - switch (dac_data_format) { - case RIGHT8: - DAC_DHR8R2 = dac_data; - break; - case RIGHT12: - DAC_DHR12R2 = dac_data; - break; - case LEFT12: - DAC_DHR12L2 = dac_data; - break; - } - } - else - switch (dac_data_format) { - case RIGHT8: - DAC_DHR8RD = dac_data; - break; - case RIGHT12: - DAC_DHR12RD = dac_data; - break; - case LEFT12: - DAC_DHR12LD = dac_data; - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Load DAC Dual Data Register. - -Loads the appropriate digital to analog converter dual data register with 12 or -8 bit data to be converted for both channels. This allows high bandwidth -simultaneous or independent analog output. The data in both channels are aligned -identically. - -@param[in] dac_data1 u32 for channel 1 with appropriate alignment. -@param[in] dac_data2 u32 for channel 2 with appropriate alignment. -@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit. -*/ - -void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format) -{ - switch (dac_data_format) { - case RIGHT8: - DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8)); - break; - case RIGHT12: - DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 12)); - break; - case LEFT12: - DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16)); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Trigger the DAC by a Software Trigger. - -If the trigger source is set to be a software trigger, cause a trigger to occur. -The trigger is cleared by hardware after conversion. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_software_trigger(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG1; - break; - case CHANNEL_2: - DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG2; - break; - case CHANNEL_D: - DAC_SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2); - break; - } -} -/**@}*/ - diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 845ae0c..7da3449 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -31,9 +31,9 @@ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o adc.o flash.o \ rtc.o i2c.o dma.o exti.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o \ + timer.o usb_f107.o desig.o crc.o iwdg.o pwr.o \ usb_fx07_common.o \ - gpio_common_all.o spi_common_all.o + gpio_common_all.o spi_common_all.o dac_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/dac.c b/lib/stm32/f1/dac.c new file mode 100644 index 0000000..90dc029 --- /dev/null +++ b/lib/stm32/f1/dac.c @@ -0,0 +1,28 @@ +/** @defgroup dac_file DAC + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx DAC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 174dbce..190812c 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o timer.o \ - gpio_common_all.o gpio_common_f24.o spi_common_all.o + gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/dac.c b/lib/stm32/f2/dac.c new file mode 100644 index 0000000..5d20703 --- /dev/null +++ b/lib/stm32/f2/dac.c @@ -0,0 +1,28 @@ +/** @defgroup dac_file DAC + +@ingroup STM32F2xx + +@brief libopencm3 STM32F2xx DAC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 0bd9a10..282ed48 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -33,7 +33,7 @@ OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ - gpio_common_all.o gpio_common_f24.o spi_common_all.o + gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f4/dac.c b/lib/stm32/f4/dac.c new file mode 100644 index 0000000..4776c41 --- /dev/null +++ b/lib/stm32/f4/dac.c @@ -0,0 +1,28 @@ +/** @defgroup dac_file DAC + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx DAC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index b533acf..ee50b6c 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,10 +28,9 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o desig.o crc.o usart.o exti2.o -OBJS += flash.o gpio_common_all.o gpio_common_f24.o spi_common_all.o -OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o -OBJS += timer.o +OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o +OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o +OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/dac.c b/lib/stm32/l1/dac.c new file mode 100644 index 0000000..534f9f1 --- /dev/null +++ b/lib/stm32/l1/dac.c @@ -0,0 +1,28 @@ +/** @defgroup dac_file DAC + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx DAC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + -- cgit v1.2.3 From 0878a534cdd91b0d76e98d8cdb207bbe9f7d040a Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 5 Dec 2012 17:52:15 +1030 Subject: Move usart files to common area Again added to L1 which is similar to F1 --- include/libopencm3/stm32/common/usart_common_all.h | 369 ++++++++++++++++ include/libopencm3/stm32/common/usart_common_f24.h | 66 +++ include/libopencm3/stm32/f1/usart.h | 40 ++ include/libopencm3/stm32/f2/usart.h | 63 +-- include/libopencm3/stm32/f4/usart.h | 63 +-- include/libopencm3/stm32/l1/usart.h | 40 ++ include/libopencm3/stm32/usart.h | 31 +- lib/stm32/common/spi_common_all.c | 2 +- lib/stm32/common/usart_common_all.c | 452 ++++++++++++++++++++ lib/stm32/f1/Makefile | 3 +- lib/stm32/f1/usart.c | 28 ++ lib/stm32/f2/Makefile | 3 +- lib/stm32/f2/usart.c | 28 ++ lib/stm32/f4/Makefile | 3 +- lib/stm32/f4/usart.c | 28 ++ lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/usart.c | 28 ++ lib/stm32/usart.c | 467 --------------------- 18 files changed, 1141 insertions(+), 575 deletions(-) create mode 100644 include/libopencm3/stm32/common/usart_common_all.h create mode 100644 include/libopencm3/stm32/common/usart_common_f24.h create mode 100644 include/libopencm3/stm32/f1/usart.h create mode 100644 include/libopencm3/stm32/l1/usart.h create mode 100644 lib/stm32/common/usart_common_all.c create mode 100644 lib/stm32/f1/usart.c create mode 100644 lib/stm32/f2/usart.c create mode 100644 lib/stm32/f4/usart.c create mode 100644 lib/stm32/l1/usart.c delete mode 100644 lib/stm32/usart.c (limited to 'lib/stm32') diff --git a/include/libopencm3/stm32/common/usart_common_all.h b/include/libopencm3/stm32/common/usart_common_all.h new file mode 100644 index 0000000..1334420 --- /dev/null +++ b/include/libopencm3/stm32/common/usart_common_all.h @@ -0,0 +1,369 @@ +/** @addtogroup usart_defines */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */ + +#ifndef LIBOPENCM3_USART_COMMON_ALL_H +#define LIBOPENCM3_USART_COMMON_ALL_H + +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup usart_reg_base USART register base addresses +@ingroup STM32F_usart_defines + +@{*/ +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +/**@}*/ +#define UART4 UART4_BASE +#define UART5 UART5_BASE + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART_SR(usart_base) MMIO32(usart_base + 0x00) +#define USART1_SR USART_SR(USART1_BASE) +#define USART2_SR USART_SR(USART2_BASE) +#define USART3_SR USART_SR(USART3_BASE) +#define UART4_SR USART_SR(UART4_BASE) +#define UART5_SR USART_SR(UART5_BASE) + +/* Data register (USARTx_DR) */ +#define USART_DR(usart_base) MMIO32(usart_base + 0x04) +#define USART1_DR USART_DR(USART1_BASE) +#define USART2_DR USART_DR(USART2_BASE) +#define USART3_DR USART_DR(USART3_BASE) +#define UART4_DR USART_DR(UART4_BASE) +#define UART5_DR USART_DR(UART5_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define UART4_BRR USART_BRR(UART4_BASE) +#define UART5_BRR USART_BRR(UART5_BASE) + +/* Control register 1 (USARTx_CR1) */ +#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define UART4_CR1 USART_CR1(UART4_BASE) +#define UART5_CR1 USART_CR1(UART5_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define UART4_CR2 USART_CR2(UART4_BASE) +#define UART5_CR2 USART_CR2(UART5_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define UART4_CR3 USART_CR3(UART4_BASE) +#define UART5_CR3 USART_CR3(UART5_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define UART4_GTPR USART_GTPR(UART4_BASE) +#define UART5_GTPR USART_GTPR(UART5_BASE) + +/* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines + +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ +#define USART_SR_CTS (1 << 9) + +/** LBD: LIN break detection flag */ +#define USART_SR_LBD (1 << 8) + +/** TXE: Transmit data buffer empty */ +#define USART_SR_TXE (1 << 7) + +/** TC: Transmission complete */ +#define USART_SR_TC (1 << 6) + +/** RXNE: Read data register not empty */ +#define USART_SR_RXNE (1 << 5) + +/** IDLE: Idle line detected */ +#define USART_SR_IDLE (1 << 4) + +/** ORE: Overrun error */ +#define USART_SR_ORE (1 << 3) + +/** NE: Noise error flag */ +#define USART_SR_NE (1 << 2) + +/** FE: Framing error */ +#define USART_SR_FE (1 << 1) + +/** PE: Parity error */ +#define USART_SR_PE (1 << 0) +/**@}*/ + +/* --- USART_DR values ----------------------------------------------------- */ + +/* USART_DR[8:0]: DR[8:0]: Data value */ +#define USART_DR_MASK 0x1FF + +/* --- USART_BRR values ---------------------------------------------------- */ + +/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ +#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) +/* DIV_Fraction[3:0]: fraction of USARTDIV */ +#define USART_BRR_DIV_FRACTION_MASK 0xF + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* UE: USART enable */ +#define USART_CR1_UE (1 << 13) + +/* M: Word length */ +#define USART_CR1_M (1 << 12) + +/* WAKE: Wakeup method */ +#define USART_CR1_WAKE (1 << 11) + +/* PCE: Parity control enable */ +#define USART_CR1_PCE (1 << 10) + +/* PS: Parity selection */ +#define USART_CR1_PS (1 << 9) + +/* PEIE: PE interrupt enable */ +#define USART_CR1_PEIE (1 << 8) + +/* TXEIE: TXE interrupt enable */ +#define USART_CR1_TXEIE (1 << 7) + +/* TCIE: Transmission complete interrupt enable */ +#define USART_CR1_TCIE (1 << 6) + +/* RXNEIE: RXNE interrupt enable */ +#define USART_CR1_RXNEIE (1 << 5) + +/* IDLEIE: IDLE interrupt enable */ +#define USART_CR1_IDLEIE (1 << 4) + +/* TE: Transmitter enable */ +#define USART_CR1_TE (1 << 3) + +/* RE: Receiver enable */ +#define USART_CR1_RE (1 << 2) + +/* RWU: Receiver wakeup */ +#define USART_CR1_RWU (1 << 1) + +/* SBK: Send break */ +#define USART_CR1_SBK (1 << 0) + +/* --- USART_CR2 values ---------------------------------------------------- */ + +/* LINEN: LIN mode enable */ +#define USART_CR2_LINEN (1 << 14) + +/* STOP[13:12]: STOP bits */ +#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ +#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ +#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ +#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ +#define USART_CR2_STOPBITS_MASK (0x03 << 12) +#define USART_CR2_STOPBITS_SHIFT 12 + +/* CLKEN: Clock enable */ +#define USART_CR2_CLKEN (1 << 11) + +/* CPOL: Clock polarity */ +#define USART_CR2_CPOL (1 << 10) + +/* CPHA: Clock phase */ +#define USART_CR2_CPHA (1 << 9) + +/* LBCL: Last bit clock pulse */ +#define USART_CR2_LBCL (1 << 8) + +/* LBDIE: LIN break detection interrupt enable */ +#define USART_CR2_LBDIE (1 << 6) + +/* LBDL: LIN break detection length */ +#define USART_CR2_LBDL (1 << 5) + +/* ADD[3:0]: Addres of the usart node */ +#define USART_CR2_ADD_MASK 0xF + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* CTSIE: CTS interrupt enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSIE (1 << 10) + +/* CTSE: CTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSE (1 << 9) + +/* RTSE: RTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_RTSE (1 << 8) + +/* DMAT: DMA enable transmitter */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAT (1 << 7) + +/* DMAR: DMA enable receiver */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAR (1 << 6) + +/* SCEN: Smartcard mode enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_SCEN (1 << 5) + +/* NACK: Smartcard NACK enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_NACK (1 << 4) + +/* HDSEL: Half-duplex selection */ +#define USART_CR3_HDSEL (1 << 3) + +/* IRLP: IrDA low-power */ +#define USART_CR3_IRLP (1 << 2) + +/* IREN: IrDA mode enable */ +#define USART_CR3_IREN (1 << 1) + +/* EIE: Error interrupt enable */ +#define USART_CR3_EIE (1 << 0) + +/* --- USART_GTPR values --------------------------------------------------- */ + +/* GT[7:0]: Guard time value */ +/* Note: N/A on UART4 & UART5 */ +#define USART_GTPR_GT_MASK (0xFF << 8) + +/* PSC[7:0]: Prescaler value */ +/* Note: N/A on UART4/5 */ +#define USART_GTPR_PSC_MASK 0xFF + +/* TODO */ /* Note to Uwe: what needs to be done here? */ + +/* --- Convenience defines ------------------------------------------------- */ + +/* CR1_PCE / CR1_PS combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_parity USART Parity Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_PARITY_NONE 0x00 +#define USART_PARITY_EVEN USART_CR1_PCE +#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) +/**@}*/ +#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) + +/* CR1_TE/CR1_RE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_MODE_RX USART_CR1_RE +#define USART_MODE_TX USART_CR1_TE +#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +/**@}*/ +#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) + +/****************************************************************************/ +/** @defgroup usart_cr2_stopbits USART Stop Bit Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ +#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ +#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ +/**@}*/ + +/* CR3_CTSE/CR3_RTSE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_FLOWCONTROL_NONE 0x00 +#define USART_FLOWCONTROL_RTS USART_CR3_RTSE +#define USART_FLOWCONTROL_CTS USART_CR3_CTSE +#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +/**@}*/ +#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void usart_set_baudrate(u32 usart, u32 baud); +void usart_set_databits(u32 usart, u32 bits); +void usart_set_stopbits(u32 usart, u32 stopbits); +void usart_set_parity(u32 usart, u32 parity); +void usart_set_mode(u32 usart, u32 mode); +void usart_set_flow_control(u32 usart, u32 flowcontrol); +void usart_enable(u32 usart); +void usart_disable(u32 usart); +void usart_send(u32 usart, u16 data); +u16 usart_recv(u32 usart); +void usart_wait_send_ready(u32 usart); +void usart_wait_recv_ready(u32 usart); +void usart_send_blocking(u32 usart, u16 data); +u16 usart_recv_blocking(u32 usart); +void usart_enable_rx_dma(u32 usart); +void usart_disable_rx_dma(u32 usart); +void usart_enable_tx_dma(u32 usart); +void usart_disable_tx_dma(u32 usart); +void usart_enable_rx_interrupt(u32 usart); +void usart_disable_rx_interrupt(u32 usart); +void usart_enable_tx_interrupt(u32 usart); +void usart_disable_tx_interrupt(u32 usart); +bool usart_get_flag(u32 usart, u32 flag); +bool usart_get_interrupt_source(u32 usart, u32 flag); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/stm32/common/usart_common_f24.h b/include/libopencm3/stm32/common/usart_common_f24.h new file mode 100644 index 0000000..089a0c2 --- /dev/null +++ b/include/libopencm3/stm32/common/usart_common_f24.h @@ -0,0 +1,66 @@ +/** @addtogroup usart_defines */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2011 Stephen Caudle + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */ + +#ifndef LIBOPENCM3_USART_COMMON_F24_H +#define LIBOPENCM3_USART_COMMON_F24_H + +#include + +/* --- Convenience macros -------------------------------------------------- */ + +#define USART6 USART6_BASE + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART6_SR USART_SR(USART6_BASE) + +/* Data register (USARTx_DR) */ +#define USART6_DR USART_DR(USART6_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART6_BRR USART_BRR(USART6_BASE) + +/* Control register 1 (USARTx_CR1) */ +#define USART6_CR1 USART_CR1(USART6_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART6_CR2 USART_CR2(USART6_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART6_CR3 USART_CR3(USART6_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART6_GTPR USART_GTPR(USART6_BASE) + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* OVER8: Oversampling mode */ +#define USART_CR1_OVER8 (1 << 15) + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* ONEBIT: One sample bit method enable */ +#define USART_CR3_ONEBIT (1 << 11) + +#endif diff --git a/include/libopencm3/stm32/f1/usart.h b/include/libopencm3/stm32/f1/usart.h new file mode 100644 index 0000000..ba6762d --- /dev/null +++ b/include/libopencm3/stm32/f1/usart.h @@ -0,0 +1,40 @@ +/** @defgroup usart_defines USART Defines + +@brief Defined Constants and Types for the STM32F1xx USART + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f2/usart.h b/include/libopencm3/stm32/f2/usart.h index 1c007ab..135b493 100644 --- a/include/libopencm3/stm32/f2/usart.h +++ b/include/libopencm3/stm32/f2/usart.h @@ -1,9 +1,21 @@ +/** @defgroup usart_defines USART Defines + +@brief Defined Constants and Types for the STM32F2xx USART + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2011 Stephen Caudle - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -18,46 +30,11 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_USART_F2_H -#define LIBOPENCM3_USART_F2_H - -#include - -/* --- Convenience macros -------------------------------------------------- */ - -#define USART6 USART6_BASE +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H -/* --- USART registers ----------------------------------------------------- */ - -/* Status register (USARTx_SR) */ -#define USART6_SR USART_SR(USART6_BASE) - -/* Data register (USARTx_DR) */ -#define USART6_DR USART_DR(USART6_BASE) - -/* Baud rate register (USARTx_BRR) */ -#define USART6_BRR USART_BRR(USART6_BASE) - -/* Control register 1 (USARTx_CR1) */ -#define USART6_CR1 USART_CR1(USART6_BASE) - -/* Control register 2 (USARTx_CR2) */ -#define USART6_CR2 USART_CR2(USART6_BASE) - -/* Control register 3 (USARTx_CR3) */ -#define USART6_CR3 USART_CR3(USART6_BASE) - -/* Guard time and prescaler register (USARTx_GTPR) */ -#define USART6_GTPR USART_GTPR(USART6_BASE) - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* OVER8: Oversampling mode */ -#define USART_CR1_OVER8 (1 << 15) - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* ONEBIT: One sample bit method enable */ -#define USART_CR3_ONEBIT (1 << 11) +#include +#include #endif + diff --git a/include/libopencm3/stm32/f4/usart.h b/include/libopencm3/stm32/f4/usart.h index ac113da..461db50 100644 --- a/include/libopencm3/stm32/f4/usart.h +++ b/include/libopencm3/stm32/f4/usart.h @@ -1,9 +1,21 @@ +/** @defgroup usart_defines USART Defines + +@brief Defined Constants and Types for the STM32F4xx USART + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2011 Stephen Caudle - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -18,46 +30,11 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_USART_F4_H -#define LIBOPENCM3_USART_F4_H - -#include - -/* --- Convenience macros -------------------------------------------------- */ - -#define USART6 USART6_BASE +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H -/* --- USART registers ----------------------------------------------------- */ - -/* Status register (USARTx_SR) */ -#define USART6_SR USART_SR(USART6_BASE) - -/* Data register (USARTx_DR) */ -#define USART6_DR USART_DR(USART6_BASE) - -/* Baud rate register (USARTx_BRR) */ -#define USART6_BRR USART_BRR(USART6_BASE) - -/* Control register 1 (USARTx_CR1) */ -#define USART6_CR1 USART_CR1(USART6_BASE) - -/* Control register 2 (USARTx_CR2) */ -#define USART6_CR2 USART_CR2(USART6_BASE) - -/* Control register 3 (USARTx_CR3) */ -#define USART6_CR3 USART_CR3(USART6_BASE) - -/* Guard time and prescaler register (USARTx_GTPR) */ -#define USART6_GTPR USART_GTPR(USART6_BASE) - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* OVER8: Oversampling mode */ -#define USART_CR1_OVER8 (1 << 15) - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* ONEBIT: One sample bit method enable */ -#define USART_CR3_ONEBIT (1 << 11) +#include +#include #endif + diff --git a/include/libopencm3/stm32/l1/usart.h b/include/libopencm3/stm32/l1/usart.h new file mode 100644 index 0000000..e6124ad --- /dev/null +++ b/include/libopencm3/stm32/l1/usart.h @@ -0,0 +1,40 @@ +/** @defgroup usart_defines USART Defines + +@brief Defined Constants and Types for the STM32L1xx USART + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 9994002..c6ac545 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -1,23 +1,8 @@ -/** @defgroup STM32F_usart_defines USART Defines - -@brief libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann - -@date 1 September 2012 - -LGPL License Terms @ref lgpl_license - */ +/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2009 Uwe Hermann - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -32,6 +17,7 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ +<<<<<<< HEAD /**@{*/ #ifndef LIBOPENCM3_USART_H @@ -378,6 +364,17 @@ bool usart_get_interrupt_source(u32 usart, u32 flag); END_DECLS +======= +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +>>>>>>> Move usart files to common area #endif -/**@}*/ diff --git a/lib/stm32/common/spi_common_all.c b/lib/stm32/common/spi_common_all.c index 3df3dcd..2e6473d 100644 --- a/lib/stm32/common/spi_common_all.c +++ b/lib/stm32/common/spi_common_all.c @@ -1,4 +1,4 @@ -/** @addtogroup gpio_file +/** @addtogroup spi_file @version 1.0.0 diff --git a/lib/stm32/common/usart_common_all.c b/lib/stm32/common/usart_common_all.c new file mode 100644 index 0000000..0c3d302 --- /dev/null +++ b/lib/stm32/common/usart_common_all.c @@ -0,0 +1,452 @@ +/** @addtogroup usart_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 30 August 2012 + +This library supports the USART/UART in the STM32F series +of ARM Cortex Microcontrollers by ST Microelectronics. + +Devices can have up to 3 USARTs and 2 UARTs. + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include +#include + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Baudrate. + +The baud rate is computed from the APB high-speed prescaler clock (for USART1) +or the APB low-speed prescaler clock (for other USARTs). These values must +be correctly set before calling this function (refer to the rcc_clock_setup-* +functions in RCC). + +@todo Add support for USART6 and oversampling in F2/F4 + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] baud unsigned 32 bit. Baud rate specified in Hz. +*/ + +void usart_set_baudrate(u32 usart, u32 baud) +{ + u32 clock = rcc_ppre1_frequency; + +//#ifdef STM32F1 + if (usart == USART1) { + clock = rcc_ppre2_frequency; + } +/* This has to be added for F2 when it get's support for USART6 */ +/* +#else + if ((usart == USART1) || + (usart == USART6)) { + clock = rcc_ppre2_frequency; + } +#endif +*/ + + /* + * Yes it is as simple as that. The reference manual is + * talking about fractional calculation but it seems to be only + * marketting babble to sound awesome. It is nothing else but a + * simple divider to generate the correct baudrate. + * + * Note: We round() the value rather than floor()ing it, for more + * accurate divisor selection. + */ + USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Word Length. + +The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit +if parity is enabled, in which case the data length will be 7 or 8 bits respectively. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] bits unsigned 32 bit. Word length in bits 8 or 9. +*/ + +void usart_set_databits(u32 usart, u32 bits) +{ + if (bits == 8) + USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ + else + USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Stop Bit(s). + +The stop bits are specified as 0.5, 1, 1.5 or 2. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits. +*/ + +void usart_set_stopbits(u32 usart, u32 stopbits) +{ + u32 reg32; + + reg32 = USART_CR2(usart); + reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits; + USART_CR2(usart) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Parity. + +The parity bit can be selected as none, even or odd. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity. +*/ + +void usart_set_parity(u32 usart, u32 parity) +{ + u32 reg32; + + reg32 = USART_CR1(usart); + reg32 = (reg32 & ~USART_PARITY_MASK) | parity; + USART_CR1(usart) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Rx/Tx Mode. + +The mode can be selected as Rx only, Tx only or Rx+Tx. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode. +*/ + +void usart_set_mode(u32 usart, u32 mode) +{ + u32 reg32; + + reg32 = USART_CR1(usart); + reg32 = (reg32 & ~USART_MODE_MASK) | mode; + USART_CR1(usart) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Hardware Flow Control. + +The flow control bit can be selected as none, RTS, CTS or RTS+CTS. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol. +*/ + +void usart_set_flow_control(u32 usart, u32 flowcontrol) +{ + u32 reg32; + + reg32 = USART_CR3(usart); + reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; + USART_CR3(usart) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_UE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Disable. + +At the end of the current frame, the USART is disabled to reduce power. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_UE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Send a Data Word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] data unsigned 16 bit. +*/ + +void usart_send(u32 usart, u16 data) +{ + /* Send data. */ + USART_DR(usart) = (data & USART_DR_MASK); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Read a Received Data Word. + +If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@returns unsigned 16 bit data word. +*/ + +u16 usart_recv(u32 usart) +{ + /* Receive data. */ + return USART_DR(usart) & USART_DR_MASK; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Wait for Transmit Data Buffer Empty + +Blocks until the transmit data buffer becomes empty and is ready to accept the +next data word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_wait_send_ready(u32 usart) +{ + /* Wait until the data has been transferred into the shift register. */ + while ((USART_SR(usart) & USART_SR_TXE) == 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Wait for Received Data Available + +Blocks until the receive data buffer holds a valid received data word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_wait_recv_ready(u32 usart) +{ + /* Wait until the data is ready to be received. */ + while ((USART_SR(usart) & USART_SR_RXNE) == 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Send Data Word with Blocking + +Blocks until the transmit data buffer becomes empty then writes the next data word +for transmission. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] data unsigned 16 bit. +*/ + +void usart_send_blocking(u32 usart, u16 data) +{ + usart_wait_send_ready(usart); + usart_send(usart, data); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Read a Received Data Word with Blocking. + +Wait until a data word has been received then return the word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@returns unsigned 16 bit data word. +*/ + +u16 usart_recv_blocking(u32 usart) +{ + usart_wait_recv_ready(usart); + + return usart_recv(usart); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver DMA Enable. + +DMA is available on: +@li USART1 Rx DMA1 channel 5. +@li USART2 Rx DMA1 channel 6. +@li USART3 Rx DMA1 channel 3. +@li UART4 Rx DMA2 channel 3. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_rx_dma(u32 usart) +{ + USART_CR3(usart) |= USART_CR3_DMAR; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver DMA Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_rx_dma(u32 usart) +{ + USART_CR3(usart) &= ~USART_CR3_DMAR; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter DMA Enable. + +DMA is available on: +@li USART1 Tx DMA1 channel 4. +@li USART2 Tx DMA1 channel 7. +@li USART3 Tx DMA1 channel 2. +@li UART4 Tx DMA2 channel 5. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_tx_dma(u32 usart) +{ + USART_CR3(usart) |= USART_CR3_DMAT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter DMA Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_tx_dma(u32 usart) +{ + USART_CR3(usart) &= ~USART_CR3_DMAT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver Interrupt Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_rx_interrupt(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_RXNEIE; +} + + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver Interrupt Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_rx_interrupt(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_RXNEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter Interrupt Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_tx_interrupt(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_TXEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter Interrupt Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_tx_interrupt(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_TXEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Error Interrupt Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_error_interrupt(u32 usart) +{ + USART_CR3(usart) |= USART_CR3_EIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Error Interrupt Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_error_interrupt(u32 usart) +{ + USART_CR3(usart) &= ~USART_CR3_EIE; +} + +/*---------------------------------------------------------------------------*/ +/** @brief USART Read a Status Flag. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. +@returns boolean: flag set. +*/ + +bool usart_get_flag(u32 usart, u32 flag) +{ + return ((USART_SR(usart) & flag) != 0); +} + +/*---------------------------------------------------------------------------*/ +/** @brief USART Return Interrupt Source. + +Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was +set and the interrupt was enabled. If the specified flag is not an interrupt +flag, the function returns false. + +@todo These are the most important interrupts likely to be used. Others +relating to LIN break, and error conditions in multibuffer communication, need +to be added for completeness. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. +@returns boolean: flag and interrupt enable both set. +*/ + +bool usart_get_interrupt_source(u32 usart, u32 flag) +{ +u32 flag_set = (USART_SR(usart) & flag); +/* IDLE, RXNE, TC, TXE interrupts */ + if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) + return ((flag_set & USART_CR1(usart)) != 0); +/* Overrun error */ + else if (flag == USART_SR_ORE) + return (flag_set && (USART_CR3(usart) & USART_CR3_CTSIE)); + return (false); +} + +/**@}*/ + diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 7da3449..9daec73 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -33,7 +33,8 @@ OBJS = rcc.o gpio.o usart.o adc.o flash.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ timer.o usb_f107.o desig.o crc.o iwdg.o pwr.o \ usb_fx07_common.o \ - gpio_common_all.o spi_common_all.o dac_common_all.o + gpio_common_all.o spi_common_all.o dac_common_all.o \ + usart_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/usart.c b/lib/stm32/f1/usart.c new file mode 100644 index 0000000..ecf2b06 --- /dev/null +++ b/lib/stm32/f1/usart.c @@ -0,0 +1,28 @@ +/** @defgroup usart_file USART + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx USART + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 190812c..f1324f6 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -30,7 +30,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o timer.o \ - gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o + gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ + usart_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/usart.c b/lib/stm32/f2/usart.c new file mode 100644 index 0000000..225b706 --- /dev/null +++ b/lib/stm32/f2/usart.c @@ -0,0 +1,28 @@ +/** @defgroup usart_file USART + +@ingroup STM32F2xx + +@brief libopencm3 STM32F2xx USART + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 282ed48..aa43e1b 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -33,7 +33,8 @@ OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ - gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o + gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ + usart_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f4/usart.c b/lib/stm32/f4/usart.c new file mode 100644 index 0000000..e0f7be8 --- /dev/null +++ b/lib/stm32/f4/usart.c @@ -0,0 +1,28 @@ +/** @defgroup usart_file USART + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx USART + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index ee50b6c..6a2b898 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -29,7 +29,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o -OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o +OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o usart_common_all.o OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/usart.c b/lib/stm32/l1/usart.c new file mode 100644 index 0000000..67fd674 --- /dev/null +++ b/lib/stm32/l1/usart.c @@ -0,0 +1,28 @@ +/** @defgroup usart_file USART + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx USART + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c deleted file mode 100644 index cb46db8..0000000 --- a/lib/stm32/usart.c +++ /dev/null @@ -1,467 +0,0 @@ -/** @defgroup STM32F1xx_usart_file USART - -@ingroup STM32F_files - -@brief libopencm3 STM32F USART - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann - -@date 30 August 2012 - -This library supports the USART/UART in the STM32F series -of ARM Cortex Microcontrollers by ST Microelectronics. - -Devices can have up to 3 USARTs and 2 UARTs. - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#include - -#if defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32L1) -# include -#else -# error "stm32 family not defined." -#endif - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Set Baudrate. - -The baud rate is computed from the APB high-speed prescaler clock (for USART1) -or the APB low-speed prescaler clock (for other USARTs). These values must -be correctly set before calling this function (refer to the rcc_clock_setup-* -functions in RCC). - -@todo Add support for USART6 and oversampling in F2/F4 - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] baud unsigned 32 bit. Baud rate specified in Hz. -*/ - -void usart_set_baudrate(u32 usart, u32 baud) -{ - u32 clock = rcc_ppre1_frequency; - -//#ifdef STM32F1 - if (usart == USART1) { - clock = rcc_ppre2_frequency; - } -/* This has to be added for F2 when it get's support for USART6 */ -/* -#else - if ((usart == USART1) || - (usart == USART6)) { - clock = rcc_ppre2_frequency; - } -#endif -*/ - - /* - * Yes it is as simple as that. The reference manual is - * talking about fractional calculation but it seems to be only - * marketting babble to sound awesome. It is nothing else but a - * simple divider to generate the correct baudrate. - * - * Note: We round() the value rather than floor()ing it, for more - * accurate divisor selection. - */ - USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Set Word Length. - -The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit -if parity is enabled, in which case the data length will be 7 or 8 bits respectively. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] bits unsigned 32 bit. Word length in bits 8 or 9. -*/ - -void usart_set_databits(u32 usart, u32 bits) -{ - if (bits == 8) - USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ - else - USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Set Stop Bit(s). - -The stop bits are specified as 0.5, 1, 1.5 or 2. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits. -*/ - -void usart_set_stopbits(u32 usart, u32 stopbits) -{ - u32 reg32; - - reg32 = USART_CR2(usart); - reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits; - USART_CR2(usart) = reg32; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Set Parity. - -The parity bit can be selected as none, even or odd. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity. -*/ - -void usart_set_parity(u32 usart, u32 parity) -{ - u32 reg32; - - reg32 = USART_CR1(usart); - reg32 = (reg32 & ~USART_PARITY_MASK) | parity; - USART_CR1(usart) = reg32; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Set Rx/Tx Mode. - -The mode can be selected as Rx only, Tx only or Rx+Tx. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode. -*/ - -void usart_set_mode(u32 usart, u32 mode) -{ - u32 reg32; - - reg32 = USART_CR1(usart); - reg32 = (reg32 & ~USART_MODE_MASK) | mode; - USART_CR1(usart) = reg32; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Set Hardware Flow Control. - -The flow control bit can be selected as none, RTS, CTS or RTS+CTS. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol. -*/ - -void usart_set_flow_control(u32 usart, u32 flowcontrol) -{ - u32 reg32; - - reg32 = USART_CR3(usart); - reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; - USART_CR3(usart) = reg32; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Enable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_enable(u32 usart) -{ - USART_CR1(usart) |= USART_CR1_UE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Disable. - -At the end of the current frame, the USART is disabled to reduce power. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_disable(u32 usart) -{ - USART_CR1(usart) &= ~USART_CR1_UE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Send a Data Word. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] data unsigned 16 bit. -*/ - -void usart_send(u32 usart, u16 data) -{ - /* Send data. */ - USART_DR(usart) = (data & USART_DR_MASK); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Read a Received Data Word. - -If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@returns unsigned 16 bit data word. -*/ - -u16 usart_recv(u32 usart) -{ - /* Receive data. */ - return USART_DR(usart) & USART_DR_MASK; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Wait for Transmit Data Buffer Empty - -Blocks until the transmit data buffer becomes empty and is ready to accept the -next data word. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_wait_send_ready(u32 usart) -{ - /* Wait until the data has been transferred into the shift register. */ - while ((USART_SR(usart) & USART_SR_TXE) == 0); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Wait for Received Data Available - -Blocks until the receive data buffer holds a valid received data word. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_wait_recv_ready(u32 usart) -{ - /* Wait until the data is ready to be received. */ - while ((USART_SR(usart) & USART_SR_RXNE) == 0); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Send Data Word with Blocking - -Blocks until the transmit data buffer becomes empty then writes the next data word -for transmission. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] data unsigned 16 bit. -*/ - -void usart_send_blocking(u32 usart, u16 data) -{ - usart_wait_send_ready(usart); - usart_send(usart, data); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Read a Received Data Word with Blocking. - -Wait until a data word has been received then return the word. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@returns unsigned 16 bit data word. -*/ - -u16 usart_recv_blocking(u32 usart) -{ - usart_wait_recv_ready(usart); - - return usart_recv(usart); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Receiver DMA Enable. - -DMA is available on: -@li USART1 Rx DMA1 channel 5. -@li USART2 Rx DMA1 channel 6. -@li USART3 Rx DMA1 channel 3. -@li UART4 Rx DMA2 channel 3. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_enable_rx_dma(u32 usart) -{ - USART_CR3(usart) |= USART_CR3_DMAR; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Receiver DMA Disable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_disable_rx_dma(u32 usart) -{ - USART_CR3(usart) &= ~USART_CR3_DMAR; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Transmitter DMA Enable. - -DMA is available on: -@li USART1 Tx DMA1 channel 4. -@li USART2 Tx DMA1 channel 7. -@li USART3 Tx DMA1 channel 2. -@li UART4 Tx DMA2 channel 5. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_enable_tx_dma(u32 usart) -{ - USART_CR3(usart) |= USART_CR3_DMAT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Transmitter DMA Disable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_disable_tx_dma(u32 usart) -{ - USART_CR3(usart) &= ~USART_CR3_DMAT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Receiver Interrupt Enable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_enable_rx_interrupt(u32 usart) -{ - USART_CR1(usart) |= USART_CR1_RXNEIE; -} - - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Receiver Interrupt Disable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_disable_rx_interrupt(u32 usart) -{ - USART_CR1(usart) &= ~USART_CR1_RXNEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Transmitter Interrupt Enable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_enable_tx_interrupt(u32 usart) -{ - USART_CR1(usart) |= USART_CR1_TXEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Transmitter Interrupt Disable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_disable_tx_interrupt(u32 usart) -{ - USART_CR1(usart) &= ~USART_CR1_TXEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Error Interrupt Enable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_enable_error_interrupt(u32 usart) -{ - USART_CR3(usart) |= USART_CR3_EIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief USART Error Interrupt Disable. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -*/ - -void usart_disable_error_interrupt(u32 usart) -{ - USART_CR3(usart) &= ~USART_CR3_EIE; -} - -/*---------------------------------------------------------------------------*/ -/** @brief USART Read a Status Flag. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. -@returns boolean: flag set. -*/ - -bool usart_get_flag(u32 usart, u32 flag) -{ - return ((USART_SR(usart) & flag) != 0); -} - -/*---------------------------------------------------------------------------*/ -/** @brief USART Return Interrupt Source. - -Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was -set and the interrupt was enabled. If the specified flag is not an interrupt -flag, the function returns false. - -@todo These are the most important interrupts likely to be used. Others -relating to LIN break, and error conditions in multibuffer communication, need -to be added for completeness. - -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base -@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. -@returns boolean: flag and interrupt enable both set. -*/ - -bool usart_get_interrupt_source(u32 usart, u32 flag) -{ -u32 flag_set = (USART_SR(usart) & flag); -/* IDLE, RXNE, TC, TXE interrupts */ - if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) - return ((flag_set & USART_CR1(usart)) != 0); -/* Overrun error */ - else if (flag == USART_SR_ORE) - return (flag_set && (USART_CR3(usart) & USART_CR3_CTSIE)); - return (false); -} - -/**@}*/ - -- cgit v1.2.3 From 312d887825325daf7561046bd31e3ec449c7a01c Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Thu, 6 Dec 2012 02:45:17 +1030 Subject: IWDG moved to common area --- include/libopencm3/stm32/common/iwdg_common_all.h | 109 ++++++++++++++++ include/libopencm3/stm32/f1/iwdg.h | 41 ++++++ include/libopencm3/stm32/f2/iwdg.h | 41 ++++++ include/libopencm3/stm32/f4/iwdg.h | 41 ++++++ include/libopencm3/stm32/iwdg.h | 112 ++--------------- include/libopencm3/stm32/l1/iwdg.h | 41 ++++++ lib/stm32/common/iwdg_common_all.c | 140 +++++++++++++++++++++ lib/stm32/f1/Makefile | 4 +- lib/stm32/f1/iwdg.c | 28 +++++ lib/stm32/f2/Makefile | 2 +- lib/stm32/f2/iwdg.c | 28 +++++ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/iwdg.c | 28 +++++ lib/stm32/iwdg.c | 144 ---------------------- lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/iwdg.c | 28 +++++ 16 files changed, 541 insertions(+), 250 deletions(-) create mode 100644 include/libopencm3/stm32/common/iwdg_common_all.h create mode 100644 include/libopencm3/stm32/f1/iwdg.h create mode 100644 include/libopencm3/stm32/f2/iwdg.h create mode 100644 include/libopencm3/stm32/f4/iwdg.h create mode 100644 include/libopencm3/stm32/l1/iwdg.h create mode 100644 lib/stm32/common/iwdg_common_all.c create mode 100644 lib/stm32/f1/iwdg.c create mode 100644 lib/stm32/f2/iwdg.c create mode 100644 lib/stm32/f4/iwdg.c delete mode 100644 lib/stm32/iwdg.c create mode 100644 lib/stm32/l1/iwdg.c (limited to 'lib/stm32') diff --git a/include/libopencm3/stm32/common/iwdg_common_all.h b/include/libopencm3/stm32/common/iwdg_common_all.h new file mode 100644 index 0000000..ea2ad16 --- /dev/null +++ b/include/libopencm3/stm32/common/iwdg_common_all.h @@ -0,0 +1,109 @@ +/** @addtogroup iwdg_defines */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H */ + +#ifndef LIBOPENCM3_IWDG_COMMON_ALL_H +#define LIBOPENCM3_IWDG_COMMON_ALL_H + +#include + +/**@{*/ + +/* --- IWDG registers ------------------------------------------------------ */ + +/* Key Register (IWDG_KR) */ +#define IWDG_KR MMIO32(IWDG_BASE + 0x00) + +/* Prescaler register (IWDG_PR) */ +#define IWDG_PR MMIO32(IWDG_BASE + 0x04) + +/* Reload register (IWDG_RLR) */ +#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) + +/* Status register (IWDG_SR) */ +#define IWDG_SR MMIO32(IWDG_BASE + 0x0c) + +/* --- IWDG_KR values ------------------------------------------------------ */ + +/* Bits [31:16]: Reserved. */ + +/* KEY[15:0]: Key value (write-only, reads as 0x0000) */ +/** @defgroup iwdg_key IWDG Key Values +@ingroup STM32F_iwdg_defines + +@{*/ +#define IWDG_KR_RESET 0xaaaa +#define IWDG_KR_UNLOCK 0x5555 +#define IWDG_KR_START 0xcccc +/**@}*/ + +/* --- IWDG_PR values ------------------------------------------------------ */ + +/* Bits [31:3]: Reserved. */ + +/* PR[2:0]: Prescaler divider */ +#define IWDG_PR_LSB 0 +/** @defgroup iwdg_prediv IWDG Prescaler divider +@ingroup STM32F_iwdg_defines + +@{*/ +#define IWDG_PR_DIV4 0x0 +#define IWDG_PR_DIV8 0x1 +#define IWDG_PR_DIV16 0x2 +#define IWDG_PR_DIV32 0x3 +#define IWDG_PR_DIV64 0x4 +#define IWDG_PR_DIV128 0x5 +#define IWDG_PR_DIV256 0x6 +/**@}*/ +/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ +/* #define IWDG_PR_DIV256 0x7 */ + +/* --- IWDG_RLR values ----------------------------------------------------- */ + +/* Bits [31:12]: Reserved. */ + +/* RL[11:0]: Watchdog counter reload value */ + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* Bits [31:2]: Reserved. */ + +/* RVU: Watchdog counter reload value update */ +#define IWDG_SR_RVU (1 << 1) + +/* PVU: Watchdog prescaler value update */ +#define IWDG_SR_PVU (1 << 0) + +/* --- IWDG function prototypes---------------------------------------------- */ + +BEGIN_DECLS + +void iwdg_start(void); +void iwdg_set_period_ms(u32 period); +bool iwdg_reload_busy(void); +bool iwdg_prescaler_busy(void); +void iwdg_reset(void); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/stm32/f1/iwdg.h b/include/libopencm3/stm32/f1/iwdg.h new file mode 100644 index 0000000..c8a1e85 --- /dev/null +++ b/include/libopencm3/stm32/f1/iwdg.h @@ -0,0 +1,41 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief Defined Constants and Types for the STM32F1xx Independent Watchdog Timer + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f2/iwdg.h b/include/libopencm3/stm32/f2/iwdg.h new file mode 100644 index 0000000..d15f9a9 --- /dev/null +++ b/include/libopencm3/stm32/f2/iwdg.h @@ -0,0 +1,41 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief Defined Constants and Types for the STM32F2xx Independent Watchdog Timer + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f4/iwdg.h b/include/libopencm3/stm32/f4/iwdg.h new file mode 100644 index 0000000..d5baef4 --- /dev/null +++ b/include/libopencm3/stm32/f4/iwdg.h @@ -0,0 +1,41 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief Defined Constants and Types for the STM32F4xx Independent Watchdog Timer + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h index 4e44907..60bbd9e 100644 --- a/include/libopencm3/stm32/iwdg.h +++ b/include/libopencm3/stm32/iwdg.h @@ -1,22 +1,8 @@ -/** @defgroup STM32F_iwdg_defines IWDG Defines +/* This provides unification of code over STM32F subfamilies */ -@brief libopencm3 Defined Constants and Types for the STM32F Independent Watchdog Timer - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2010 Thomas Otto - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -31,91 +17,15 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ -/**@{*/ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include -#include - -/* --- IWDG registers ------------------------------------------------------ */ - -/* Key Register (IWDG_KR) */ -#define IWDG_KR MMIO32(IWDG_BASE + 0x00) - -/* Prescaler register (IWDG_PR) */ -#define IWDG_PR MMIO32(IWDG_BASE + 0x04) - -/* Reload register (IWDG_RLR) */ -#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) - -/* Status register (IWDG_SR) */ -#define IWDG_SR MMIO32(IWDG_BASE + 0x0c) - -/* --- IWDG_KR values ------------------------------------------------------ */ - -/* Bits [31:16]: Reserved. */ - -/* KEY[15:0]: Key value (write-only, reads as 0x0000) */ -/** @defgroup iwdg_key IWDG Key Values -@ingroup STM32F_iwdg_defines - -@{*/ -#define IWDG_KR_RESET 0xaaaa -#define IWDG_KR_UNLOCK 0x5555 -#define IWDG_KR_START 0xcccc -/**@}*/ - -/* --- IWDG_PR values ------------------------------------------------------ */ - -/* Bits [31:3]: Reserved. */ - -/* PR[2:0]: Prescaler divider */ -#define IWDG_PR_LSB 0 -/** @defgroup iwdg_prediv IWDG Prescaler divider -@ingroup STM32F_iwdg_defines - -@{*/ -#define IWDG_PR_DIV4 0x0 -#define IWDG_PR_DIV8 0x1 -#define IWDG_PR_DIV16 0x2 -#define IWDG_PR_DIV32 0x3 -#define IWDG_PR_DIV64 0x4 -#define IWDG_PR_DIV128 0x5 -#define IWDG_PR_DIV256 0x6 -/**@}*/ -/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ -/* #define IWDG_PR_DIV256 0x7 */ - -/* --- IWDG_RLR values ----------------------------------------------------- */ - -/* Bits [31:12]: Reserved. */ - -/* RL[11:0]: Watchdog counter reload value */ - -/* --- IWDG_SR values ------------------------------------------------------ */ - -/* Bits [31:2]: Reserved. */ - -/* RVU: Watchdog counter reload value update */ -#define IWDG_SR_RVU (1 << 1) - -/* PVU: Watchdog prescaler value update */ -#define IWDG_SR_PVU (1 << 0) - -/* --- IWDG function prototypes---------------------------------------------- */ - -BEGIN_DECLS - -void iwdg_start(void); -void iwdg_set_period_ms(u32 period); -bool iwdg_reload_busy(void); -bool iwdg_prescaler_busy(void); -void iwdg_reset(void); - -END_DECLS - +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." #endif -/**@}*/ diff --git a/include/libopencm3/stm32/l1/iwdg.h b/include/libopencm3/stm32/l1/iwdg.h new file mode 100644 index 0000000..8ba6c44 --- /dev/null +++ b/include/libopencm3/stm32/l1/iwdg.h @@ -0,0 +1,41 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief Defined Constants and Types for the STM32L1xx Independent Watchdog Timer + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include +#include + +#endif + diff --git a/lib/stm32/common/iwdg_common_all.c b/lib/stm32/common/iwdg_common_all.c new file mode 100644 index 0000000..d3d9364 --- /dev/null +++ b/lib/stm32/common/iwdg_common_all.c @@ -0,0 +1,140 @@ +/** @addtogroup iwdg_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net + +@date 18 August 2012 + +This library supports the Independent Watchdog Timer System in the STM32F1xx +series of ARM Cortex Microcontrollers by ST Microelectronics. + +The watchdog timer uses the LSI (low speed internal) clock which is low power +and continues to operate during stop and standby modes. Its frequency is +nominally 32kHz (40kHz for the STM32F1xx series) but can vary from as low +as 17kHz up to 60kHz (refer to datasheet electrical characteristics). + +Note that the User Configuration option byte provides a means of automatically +enabling the IWDG timer at power on (with counter value 0xFFF). If the +relevant bit is not set, the IWDG timer must be enabled by software. + +@note: Tested: CPU STM32F103RET6, Board ET-ARM Stamp STM32 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +#define LSI_FREQUENCY 32000 +#define COUNT_LENGTH 12 +#define COUNT_MASK ((1 << COUNT_LENGTH)-1) + +/*-----------------------------------------------------------------------------*/ +/** @brief IWDG Enable Watchdog Timer + +The watchdog timer is started. The timeout period defaults to 512 milliseconds +unless it has been previously defined. + +*/ + +void iwdg_start(void) +{ + IWDG_KR = IWDG_KR_START; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief IWDG Set Period in Milliseconds + +The countdown period is converted into count and prescale values. The maximum +period is 32.76 seconds; values above this are truncated. Periods less than 1ms +are not supported by this library. + +A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds) +can occasionally occur if the prescale or preload registers are currently busy +loading a previous value. + +@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset until +a system reset is issued. +*/ + +void iwdg_set_period_ms(u32 period) +{ +u32 count, prescale, reload, exponent; +/* Set the count to represent ticks of the 32kHz LSI clock */ + count = (period << 5); +/* Strip off the first 12 bits to get the prescale value required */ + prescale = (count >> 12); + if (prescale > 256) {exponent = IWDG_PR_DIV256; reload = COUNT_MASK;} + else if (prescale > 128) {exponent = IWDG_PR_DIV256; reload = (count >> 8);} + else if (prescale > 64) {exponent = IWDG_PR_DIV128; reload = (count >> 7);} + else if (prescale > 32) {exponent = IWDG_PR_DIV64; reload = (count >> 6);} + else if (prescale > 16) {exponent = IWDG_PR_DIV32; reload = (count >> 5);} + else if (prescale > 8) {exponent = IWDG_PR_DIV16; reload = (count >> 4);} + else if (prescale > 4) {exponent = IWDG_PR_DIV8; reload = (count >> 3);} + else {exponent = IWDG_PR_DIV4; reload = (count >> 2);} +/* Avoid the undefined situation of a zero count */ + if (count == 0) count = 1; + + while (iwdg_prescaler_busy()); + IWDG_KR = IWDG_KR_UNLOCK; + IWDG_PR = exponent; + while (iwdg_reload_busy()); + IWDG_KR = IWDG_KR_UNLOCK; + IWDG_RLR = (reload & COUNT_MASK); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief IWDG Get Reload Register Status + +@returns boolean: TRUE if the reload register is busy and unavailable for loading +a new count value. +*/ + +bool iwdg_reload_busy(void) +{ + return (IWDG_SR & IWDG_SR_RVU); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief IWDG Get Prescaler Register Status + +@returns boolean: TRUE if the prescaler register is busy and unavailable for loading +a new period value. +*/ + +bool iwdg_prescaler_busy(void) +{ + return (IWDG_SR & IWDG_SR_PVU); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief IWDG reset Watchdog Timer + +The watchdog timer is reset. The counter restarts from the value in the reload +register. +*/ + +void iwdg_reset(void) +{ + IWDG_KR = IWDG_KR_RESET; +} +/**@}*/ + diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 9daec73..e2c4284 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -31,10 +31,10 @@ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o adc.o flash.o \ rtc.o i2c.o dma.o exti.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o iwdg.o pwr.o \ + timer.o usb_f107.o desig.o crc.o pwr.o \ usb_fx07_common.o \ gpio_common_all.o spi_common_all.o dac_common_all.o \ - usart_common_all.o + usart_common_all.o iwdg_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/iwdg.c b/lib/stm32/f1/iwdg.c new file mode 100644 index 0000000..85cf18c --- /dev/null +++ b/lib/stm32/f1/iwdg.c @@ -0,0 +1,28 @@ +/** @defgroup iwdg_file IWDG + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx Independent Watchdog Timer + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index f1324f6..d0b1ac8 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -31,7 +31,7 @@ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o timer.o \ gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ - usart_common_all.o + usart_common_all.o iwdg_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/iwdg.c b/lib/stm32/f2/iwdg.c new file mode 100644 index 0000000..0440d88 --- /dev/null +++ b/lib/stm32/f2/iwdg.c @@ -0,0 +1,28 @@ +/** @defgroup iwdg_file IWDG + +@ingroup STM32F2xx + +@brief libopencm3 STM32F2xx Independent Watchdog Timer + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index aa43e1b..dc7db87 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -34,7 +34,7 @@ OBJS = rcc.o gpio.o usart.o flash.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ - usart_common_all.o + usart_common_all.o iwdg_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f4/iwdg.c b/lib/stm32/f4/iwdg.c new file mode 100644 index 0000000..9332fc4 --- /dev/null +++ b/lib/stm32/f4/iwdg.c @@ -0,0 +1,28 @@ +/** @defgroup iwdg_file IWDG + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx Independent Watchdog Timer + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/iwdg.c b/lib/stm32/iwdg.c deleted file mode 100644 index 251bec1..0000000 --- a/lib/stm32/iwdg.c +++ /dev/null @@ -1,144 +0,0 @@ -/** @defgroup STM32F_iwdg_file IWDG - -@ingroup STM32F_files - -@brief libopencm3 STM32F1xx Independent Watchdog Timer - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net - -@date 18 August 2012 - -This library supports the Independent Watchdog Timer System in the STM32F1xx -series of ARM Cortex Microcontrollers by ST Microelectronics. - -The watchdog timer uses the LSI (low speed internal) clock which is low power -and continues to operate during stop and standby modes. Its frequency is -nominally 32kHz (40kHz for the STM32F1xx series) but can vary from as low -as 17kHz up to 60kHz (refer to datasheet electrical characteristics). - -Note that the User Configuration option byte provides a means of automatically -enabling the IWDG timer at power on (with counter value 0xFFF). If the -relevant bit is not set, the IWDG timer must be enabled by software. - -@note: Tested: CPU STM32F103RET6, Board ET-ARM Stamp STM32 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#include - -#define LSI_FREQUENCY 32000 -#define COUNT_LENGTH 12 -#define COUNT_MASK ((1 << COUNT_LENGTH)-1) - -/*-----------------------------------------------------------------------------*/ -/** @brief IWDG Enable Watchdog Timer - -The watchdog timer is started. The timeout period defaults to 512 milliseconds -unless it has been previously defined. - -*/ - -void iwdg_start(void) -{ - IWDG_KR = IWDG_KR_START; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief IWDG Set Period in Milliseconds - -The countdown period is converted into count and prescale values. The maximum -period is 32.76 seconds; values above this are truncated. Periods less than 1ms -are not supported by this library. - -A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds) -can occasionally occur if the prescale or preload registers are currently busy -loading a previous value. - -@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset until -a system reset is issued. -*/ - -void iwdg_set_period_ms(u32 period) -{ -u32 count, prescale, reload, exponent; -/* Set the count to represent ticks of the 32kHz LSI clock */ - count = (period << 5); -/* Strip off the first 12 bits to get the prescale value required */ - prescale = (count >> 12); - if (prescale > 256) {exponent = IWDG_PR_DIV256; reload = COUNT_MASK;} - else if (prescale > 128) {exponent = IWDG_PR_DIV256; reload = (count >> 8);} - else if (prescale > 64) {exponent = IWDG_PR_DIV128; reload = (count >> 7);} - else if (prescale > 32) {exponent = IWDG_PR_DIV64; reload = (count >> 6);} - else if (prescale > 16) {exponent = IWDG_PR_DIV32; reload = (count >> 5);} - else if (prescale > 8) {exponent = IWDG_PR_DIV16; reload = (count >> 4);} - else if (prescale > 4) {exponent = IWDG_PR_DIV8; reload = (count >> 3);} - else {exponent = IWDG_PR_DIV4; reload = (count >> 2);} -/* Avoid the undefined situation of a zero count */ - if (count == 0) count = 1; - - while (iwdg_prescaler_busy()); - IWDG_KR = IWDG_KR_UNLOCK; - IWDG_PR = exponent; - while (iwdg_reload_busy()); - IWDG_KR = IWDG_KR_UNLOCK; - IWDG_RLR = (reload & COUNT_MASK); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief IWDG Get Reload Register Status - -@returns boolean: TRUE if the reload register is busy and unavailable for loading -a new count value. -*/ - -bool iwdg_reload_busy(void) -{ - return (IWDG_SR & IWDG_SR_RVU); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief IWDG Get Prescaler Register Status - -@returns boolean: TRUE if the prescaler register is busy and unavailable for loading -a new period value. -*/ - -bool iwdg_prescaler_busy(void) -{ - return (IWDG_SR & IWDG_SR_PVU); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief IWDG reset Watchdog Timer - -The watchdog timer is reset. The counter restarts from the value in the reload -register. -*/ - -void iwdg_reset(void) -{ - IWDG_KR = IWDG_KR_RESET; -} -/**@}*/ - diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index 6a2b898..c48f5b9 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -29,7 +29,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o -OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o usart_common_all.o +OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o usart_common_all.o iwdg_common_all.o OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/iwdg.c b/lib/stm32/l1/iwdg.c new file mode 100644 index 0000000..05ddf04 --- /dev/null +++ b/lib/stm32/l1/iwdg.c @@ -0,0 +1,28 @@ +/** @defgroup iwdg_file IWDG + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx Independent Watchdog Timer + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + -- cgit v1.2.3 From e831f4db51f9bd60654a38fd779cf1bf9613ee1a Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Thu, 6 Dec 2012 03:09:33 +1030 Subject: I2C to common area F2/4 has now I2C3 included --- include/libopencm3/stm32/common/i2c_common_all.h | 383 +++++++++++++++++++++ include/libopencm3/stm32/common/i2c_common_f24.h | 35 ++ include/libopencm3/stm32/f1/i2c.h | 41 +++ include/libopencm3/stm32/f2/i2c.h | 41 +++ include/libopencm3/stm32/f4/i2c.h | 41 +++ include/libopencm3/stm32/i2c.h | 387 +-------------------- include/libopencm3/stm32/l1/i2c.h | 41 +++ include/libopencm3/stm32/usart.h | 349 ------------------- lib/stm32/common/i2c_common_all.c | 411 ++++++++++++++++++++++ lib/stm32/f1/Makefile | 2 +- lib/stm32/f1/i2c.c | 28 ++ lib/stm32/f2/Makefile | 2 +- lib/stm32/f2/i2c.c | 28 ++ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/i2c.c | 28 ++ lib/stm32/i2c.c | 415 ----------------------- lib/stm32/l1/Makefile | 3 +- lib/stm32/l1/i2c.c | 28 ++ 18 files changed, 1121 insertions(+), 1144 deletions(-) create mode 100644 include/libopencm3/stm32/common/i2c_common_all.h create mode 100644 include/libopencm3/stm32/common/i2c_common_f24.h create mode 100644 include/libopencm3/stm32/f1/i2c.h create mode 100644 include/libopencm3/stm32/f2/i2c.h create mode 100644 include/libopencm3/stm32/f4/i2c.h create mode 100644 include/libopencm3/stm32/l1/i2c.h create mode 100644 lib/stm32/common/i2c_common_all.c create mode 100644 lib/stm32/f1/i2c.c create mode 100644 lib/stm32/f2/i2c.c create mode 100644 lib/stm32/f4/i2c.c delete mode 100644 lib/stm32/i2c.c create mode 100644 lib/stm32/l1/i2c.c (limited to 'lib/stm32') diff --git a/include/libopencm3/stm32/common/i2c_common_all.h b/include/libopencm3/stm32/common/i2c_common_all.h new file mode 100644 index 0000000..d5cc490 --- /dev/null +++ b/include/libopencm3/stm32/common/i2c_common_all.h @@ -0,0 +1,383 @@ +/** @addtogroup i2c_defines */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H */ + +#ifndef LIBOPENCM3_I2C_COMMON_ALL_H +#define LIBOPENCM3_I2C_COMMON_ALL_H + +#include + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C register base adresses (for convenience) */ +/****************************************************************************/ +/** @defgroup i2c_reg_base I2C register base address +@ingroup i2c_defines + +@{*/ +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE +/**@}*/ + +/* --- I2C registers ------------------------------------------------------- */ + +/* Control register 1 (I2Cx_CR1) */ +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +/* Control register 2 (I2Cx_CR2) */ +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +/* Own address register 1 (I2Cx_OAR1) */ +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +/* Own address register 2 (I2Cx_OAR2) */ +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +/* Data register (I2Cx_DR) */ +#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_DR I2C_DR(I2C1) +#define I2C2_DR I2C_DR(I2C2) + +/* Status register 1 (I2Cx_SR1) */ +#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_SR1 I2C_SR1(I2C1) +#define I2C2_SR1 I2C_SR1(I2C2) + +/* Status register 2 (I2Cx_SR2) */ +#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_SR2 I2C_SR2(I2C1) +#define I2C2_SR2 I2C_SR2(I2C2) + +/* Clock control register (I2Cx_CCR) */ +#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) +#define I2C1_CCR I2C_CCR(I2C1) +#define I2C2_CCR I2C_CCR(I2C2) + +/* TRISE register (I2Cx_CCR) */ +#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C1_TRISE I2C_TRISE(I2C1) +#define I2C2_TRISE I2C_TRISE(I2C2) + +/* --- I2Cx_CR1 values ----------------------------------------------------- */ + +/* SWRST: Software reset */ +#define I2C_CR1_SWRST (1 << 15) + +/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ + +/* ALERT: SMBus alert */ +#define I2C_CR1_ALERT (1 << 13) + +/* PEC: Packet error checking */ +#define I2C_CR1_PEC (1 << 12) + +/* POS: Acknowledge / PEC postition */ +#define I2C_CR1_POS (1 << 11) + +/* ACK: Acknowledge enable */ +#define I2C_CR1_ACK (1 << 10) + +/* STOP: STOP generation */ +#define I2C_CR1_STOP (1 << 9) + +/* START: START generation */ +#define I2C_CR1_START (1 << 8) + +/* NOSTRETCH: Clock stretching disable (slave mode) */ +#define I2C_CR1_NOSTRETCH (1 << 7) + +/* ENGC: General call enable */ +#define I2C_CR1_ENGC (1 << 6) + +/* ENPEC: Enable PEC */ +#define I2C_CR1_ENPEC (1 << 5) + +/* ENARP: ARP enable */ +#define I2C_CR1_ENARP (1 << 4) + +/* SMBTYPE: SMBus type */ +#define I2C_CR1_SMBTYPE (1 << 3) + +/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ + +/* SMBUS: SMBus mode */ +#define I2C_CR1_SMBUS (1 << 1) + +/* PE: Peripheral enable */ +#define I2C_CR1_PE (1 << 0) + +/* --- I2Cx_CR2 values ----------------------------------------------------- */ + +/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ + +/* LAST: DMA last transfer */ +#define I2C_CR2_LAST (1 << 12) + +/* DMAEN: DMA requests enable */ +#define I2C_CR2_DMAEN (1 << 11) + +/* ITBUFEN: Buffer interrupt enable */ +#define I2C_CR2_ITBUFEN (1 << 10) + +/* ITEVTEN: Event interrupt enable */ +#define I2C_CR2_ITEVTEN (1 << 9) + +/* ITERREN: Error interrupt enable */ +#define I2C_CR2_ITERREN (1 << 8) + +/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ + +/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ +/****************************************************************************/ +/** @defgroup i2c_clock I2C clock frequency settings +@ingroup i2c_defines + +@{*/ +#define I2C_CR2_FREQ_2MHZ 0x02 +#define I2C_CR2_FREQ_3MHZ 0x03 +#define I2C_CR2_FREQ_4MHZ 0x04 +#define I2C_CR2_FREQ_5MHZ 0x05 +#define I2C_CR2_FREQ_6MHZ 0x06 +#define I2C_CR2_FREQ_7MHZ 0x07 +#define I2C_CR2_FREQ_8MHZ 0x08 +#define I2C_CR2_FREQ_9MHZ 0x09 +#define I2C_CR2_FREQ_10MHZ 0x0a +#define I2C_CR2_FREQ_11MHZ 0x0b +#define I2C_CR2_FREQ_12MHZ 0x0c +#define I2C_CR2_FREQ_13MHZ 0x0d +#define I2C_CR2_FREQ_14MHZ 0x0e +#define I2C_CR2_FREQ_15MHZ 0x0f +#define I2C_CR2_FREQ_16MHZ 0x10 +#define I2C_CR2_FREQ_17MHZ 0x11 +#define I2C_CR2_FREQ_18MHZ 0x12 +#define I2C_CR2_FREQ_19MHZ 0x13 +#define I2C_CR2_FREQ_20MHZ 0x14 +#define I2C_CR2_FREQ_21MHZ 0x15 +#define I2C_CR2_FREQ_22MHZ 0x16 +#define I2C_CR2_FREQ_23MHZ 0x17 +#define I2C_CR2_FREQ_24MHZ 0x18 +#define I2C_CR2_FREQ_25MHZ 0x19 +#define I2C_CR2_FREQ_26MHZ 0x1a +#define I2C_CR2_FREQ_27MHZ 0x1b +#define I2C_CR2_FREQ_28MHZ 0x1c +#define I2C_CR2_FREQ_29MHZ 0x1d +#define I2C_CR2_FREQ_30MHZ 0x1e +#define I2C_CR2_FREQ_31MHZ 0x1f +#define I2C_CR2_FREQ_32MHZ 0x20 +#define I2C_CR2_FREQ_33MHZ 0x21 +#define I2C_CR2_FREQ_34MHZ 0x22 +#define I2C_CR2_FREQ_35MHZ 0x23 +#define I2C_CR2_FREQ_36MHZ 0x24 +/**@}*/ + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* ADDMODE: Addressing mode (slave mode) */ +#define I2C_OAR1_ADDMODE (1 << 15) +#define I2C_OAR1_ADDMODE_7BIT 0 +#define I2C_OAR1_ADDMODE_10BIT 1 + +/* Note: Bit 14 should always be kept at 1 by software! */ + +/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ + +/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ + +/* --- I2Cx_OAR2 values ---------------------------------------------------- */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ + +/* ENDUAL: Dual addressing mode enable */ +#define I2C_OAR2_ENDUAL (1 << 0) + +/* --- I2Cx_DR values ------------------------------------------------------ */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* DR[7:0] 8-bit data register */ + +/* --- I2Cx_SR1 values ----------------------------------------------------- */ + +/* SMBALERT: SMBus alert */ +#define I2C_SR1_SMBALERT (1 << 15) + +/* TIMEOUT: Timeout or Tlow Error */ +#define I2C_SR1_TIMEOUT (1 << 14) + +/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ + +/* PECERR: PEC Error in reception */ +#define I2C_SR1_PECERR (1 << 12) + +/* OVR: Overrun/Underrun */ +#define I2C_SR1_OVR (1 << 11) + +/* AF: Acknowledge failure */ +#define I2C_SR1_AF (1 << 10) + +/* ARLO: Arbitration lost (master mode) */ +#define I2C_SR1_ARLO (1 << 9) + +/* BERR: Bus error */ +#define I2C_SR1_BERR (1 << 8) + +/* TxE: Data register empty (transmitters) */ +#define I2C_SR1_TxE (1 << 7) + +/* RxNE: Data register not empty (receivers) */ +#define I2C_SR1_RxNE (1 << 6) + +/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ + +/* STOPF: STOP detection (slave mode) */ +#define I2C_SR1_STOPF (1 << 4) + +/* ADD10: 10-bit header sent (master mode) */ +#define I2C_SR1_ADD10 (1 << 3) + +/* BTF: Byte transfer finished */ +#define I2C_SR1_BTF (1 << 2) + +/* ADDR: Address sent (master mode) / address matched (slave mode) */ +#define I2C_SR1_ADDR (1 << 1) + +/* SB: Start bit (master mode) */ +#define I2C_SR1_SB (1 << 0) + +/* --- I2Cx_SR2 values ----------------------------------------------------- */ + +/* Bits [15:8]: PEC[7:0]: Packet error checking register */ + +/* DUALF: Dual flag (slave mode) */ +#define I2C_SR2_DUALF (1 << 7) + +/* SMBHOST: SMBus host header (slave mode) */ +#define I2C_SR2_SMBHOST (1 << 6) + +/* SMBDEFAULT: SMBus device default address (slave mode) */ +#define I2C_SR2_SMBDEFAULT (1 << 5) + +/* GENCALL: General call address (slave mode) */ +#define I2C_SR2_GENCALL (1 << 4) + +/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ + +/* TRA: Transmitter / receiver */ +#define I2C_SR2_TRA (1 << 2) + +/* BUSY: Bus busy */ +#define I2C_SR2_BUSY (1 << 1) + +/* MSL: Master / slave */ +#define I2C_SR2_MSL (1 << 0) + +/* --- I2Cx_CCR values ----------------------------------------------------- */ + +/* F/S: I2C Master mode selection (fast / standard) */ +#define I2C_CCR_FS (1 << 15) + +/* DUTY: Fast Mode Duty Cycle */ +/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles +@ingroup i2c_defines + +@{*/ +#define I2C_CCR_DUTY (1 << 14) +#define I2C_CCR_DUTY_DIV2 0 +#define I2C_CCR_DUTY_16_DIV_9 1 +/**@}*/ + +/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [11:0]: + * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) + */ + +/* --- I2Cx_TRISE values --------------------------------------------------- */ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [5:0]: + * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) + */ + +/* --- I2C const definitions ----------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup i2c_rw I2C Read/Write bit +@ingroup i2c_defines + +@{*/ +#define I2C_WRITE 0 +#define I2C_READ 1 +/**@}*/ + +/* --- I2C funtion prototypes----------------------------------------------- */ + +BEGIN_DECLS + +void i2c_reset(u32 i2c); +void i2c_peripheral_enable(u32 i2c); +void i2c_peripheral_disable(u32 i2c); +void i2c_send_start(u32 i2c); +void i2c_send_stop(u32 i2c); +void i2c_clear_stop(u32 i2c); +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave); +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave); +void i2c_set_fast_mode(u32 i2c); +void i2c_set_standard_mode(u32 i2c); +void i2c_set_clock_frequency(u32 i2c, u8 freq); +void i2c_set_ccr(u32 i2c, u16 freq); +void i2c_set_trise(u32 i2c, u16 trise); +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); +void i2c_send_data(u32 i2c, u8 data); +uint8_t i2c_get_data(u32 i2c); +void i2c_enable_interrupt(u32 i2c, u32 interrupt); +void i2c_disable_interrupt(u32 i2c, u32 interrupt); +void i2c_enable_ack(u32 i2c); +void i2c_disable_ack(u32 i2c); +void i2c_nack_next(u32 i2c); +void i2c_nack_current(u32 i2c); +void i2c_set_dutycycle(u32 i2c, u32 dutycycle); +void i2c_enable_dma(u32 i2c); +void i2c_disable_dma(u32 i2c); +void i2c_set_dma_last_transfer(u32 i2c); +void i2c_clear_dma_last_transfer(u32 i2c); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/stm32/common/i2c_common_f24.h b/include/libopencm3/stm32/common/i2c_common_f24.h new file mode 100644 index 0000000..22a5733 --- /dev/null +++ b/include/libopencm3/stm32/common/i2c_common_f24.h @@ -0,0 +1,35 @@ +/** @addtogroup i2c_defines */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H */ + +#ifndef LIBOPENCM3_I2C_COMMON_F24_H +#define LIBOPENCM3_I2C_COMMON_F24_H + +#include + +/**@{*/ + +#define I2C3 I2C3_BASE + +/**@}*/ + +#endif diff --git a/include/libopencm3/stm32/f1/i2c.h b/include/libopencm3/stm32/f1/i2c.h new file mode 100644 index 0000000..44d906a --- /dev/null +++ b/include/libopencm3/stm32/f1/i2c.h @@ -0,0 +1,41 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the STM32F1xx I2C + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f2/i2c.h b/include/libopencm3/stm32/f2/i2c.h new file mode 100644 index 0000000..3dc1652 --- /dev/null +++ b/include/libopencm3/stm32/f2/i2c.h @@ -0,0 +1,41 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the STM32F2xx I2C + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f4/i2c.h b/include/libopencm3/stm32/f4/i2c.h new file mode 100644 index 0000000..e1a41cf --- /dev/null +++ b/include/libopencm3/stm32/f4/i2c.h @@ -0,0 +1,41 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the STM32F4xx I2C + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h index 1b2dc0e..c1d0793 100644 --- a/include/libopencm3/stm32/i2c.h +++ b/include/libopencm3/stm32/i2c.h @@ -1,24 +1,8 @@ -/** @defgroup i2c_defines I2C Defines - -@ingroup STM32F_defines - -@brief libopencm3 Defined Constants and Types for the STM32 I2C - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies - -@date 12 October 2012 - -LGPL License Terms @ref lgpl_license - */ +/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2010 Thomas Otto - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -33,364 +17,15 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include -#include - -/**@{*/ - -/* --- Convenience macros -------------------------------------------------- */ - -/* I2C register base adresses (for convenience) */ -/****************************************************************************/ -/** @defgroup i2c_reg_base I2C register base address -@ingroup i2c_defines - -@{*/ -#define I2C1 I2C1_BASE -#define I2C2 I2C2_BASE -/**@}*/ - -/* --- I2C registers ------------------------------------------------------- */ - -/* Control register 1 (I2Cx_CR1) */ -#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) -#define I2C1_CR1 I2C_CR1(I2C1) -#define I2C2_CR1 I2C_CR1(I2C2) - -/* Control register 2 (I2Cx_CR2) */ -#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) -#define I2C1_CR2 I2C_CR2(I2C1) -#define I2C2_CR2 I2C_CR2(I2C2) - -/* Own address register 1 (I2Cx_OAR1) */ -#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) -#define I2C1_OAR1 I2C_OAR1(I2C1) -#define I2C2_OAR1 I2C_OAR1(I2C2) - -/* Own address register 2 (I2Cx_OAR2) */ -#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) -#define I2C1_OAR2 I2C_OAR2(I2C1) -#define I2C2_OAR2 I2C_OAR2(I2C2) - -/* Data register (I2Cx_DR) */ -#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) -#define I2C1_DR I2C_DR(I2C1) -#define I2C2_DR I2C_DR(I2C2) - -/* Status register 1 (I2Cx_SR1) */ -#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) -#define I2C1_SR1 I2C_SR1(I2C1) -#define I2C2_SR1 I2C_SR1(I2C2) - -/* Status register 2 (I2Cx_SR2) */ -#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) -#define I2C1_SR2 I2C_SR2(I2C1) -#define I2C2_SR2 I2C_SR2(I2C2) - -/* Clock control register (I2Cx_CCR) */ -#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) -#define I2C1_CCR I2C_CCR(I2C1) -#define I2C2_CCR I2C_CCR(I2C2) - -/* TRISE register (I2Cx_CCR) */ -#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) -#define I2C1_TRISE I2C_TRISE(I2C1) -#define I2C2_TRISE I2C_TRISE(I2C2) - -/* --- I2Cx_CR1 values ----------------------------------------------------- */ - -/* SWRST: Software reset */ -#define I2C_CR1_SWRST (1 << 15) - -/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ - -/* ALERT: SMBus alert */ -#define I2C_CR1_ALERT (1 << 13) - -/* PEC: Packet error checking */ -#define I2C_CR1_PEC (1 << 12) - -/* POS: Acknowledge / PEC postition */ -#define I2C_CR1_POS (1 << 11) - -/* ACK: Acknowledge enable */ -#define I2C_CR1_ACK (1 << 10) - -/* STOP: STOP generation */ -#define I2C_CR1_STOP (1 << 9) - -/* START: START generation */ -#define I2C_CR1_START (1 << 8) - -/* NOSTRETCH: Clock stretching disable (slave mode) */ -#define I2C_CR1_NOSTRETCH (1 << 7) - -/* ENGC: General call enable */ -#define I2C_CR1_ENGC (1 << 6) - -/* ENPEC: Enable PEC */ -#define I2C_CR1_ENPEC (1 << 5) - -/* ENARP: ARP enable */ -#define I2C_CR1_ENARP (1 << 4) - -/* SMBTYPE: SMBus type */ -#define I2C_CR1_SMBTYPE (1 << 3) - -/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ - -/* SMBUS: SMBus mode */ -#define I2C_CR1_SMBUS (1 << 1) - -/* PE: Peripheral enable */ -#define I2C_CR1_PE (1 << 0) - -/* --- I2Cx_CR2 values ----------------------------------------------------- */ - -/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ - -/* LAST: DMA last transfer */ -#define I2C_CR2_LAST (1 << 12) - -/* DMAEN: DMA requests enable */ -#define I2C_CR2_DMAEN (1 << 11) - -/* ITBUFEN: Buffer interrupt enable */ -#define I2C_CR2_ITBUFEN (1 << 10) - -/* ITEVTEN: Event interrupt enable */ -#define I2C_CR2_ITEVTEN (1 << 9) - -/* ITERREN: Error interrupt enable */ -#define I2C_CR2_ITERREN (1 << 8) - -/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ - -/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ -/****************************************************************************/ -/** @defgroup i2c_clock I2C clock frequency settings -@ingroup i2c_defines - -@{*/ -#define I2C_CR2_FREQ_2MHZ 0x02 -#define I2C_CR2_FREQ_3MHZ 0x03 -#define I2C_CR2_FREQ_4MHZ 0x04 -#define I2C_CR2_FREQ_5MHZ 0x05 -#define I2C_CR2_FREQ_6MHZ 0x06 -#define I2C_CR2_FREQ_7MHZ 0x07 -#define I2C_CR2_FREQ_8MHZ 0x08 -#define I2C_CR2_FREQ_9MHZ 0x09 -#define I2C_CR2_FREQ_10MHZ 0x0a -#define I2C_CR2_FREQ_11MHZ 0x0b -#define I2C_CR2_FREQ_12MHZ 0x0c -#define I2C_CR2_FREQ_13MHZ 0x0d -#define I2C_CR2_FREQ_14MHZ 0x0e -#define I2C_CR2_FREQ_15MHZ 0x0f -#define I2C_CR2_FREQ_16MHZ 0x10 -#define I2C_CR2_FREQ_17MHZ 0x11 -#define I2C_CR2_FREQ_18MHZ 0x12 -#define I2C_CR2_FREQ_19MHZ 0x13 -#define I2C_CR2_FREQ_20MHZ 0x14 -#define I2C_CR2_FREQ_21MHZ 0x15 -#define I2C_CR2_FREQ_22MHZ 0x16 -#define I2C_CR2_FREQ_23MHZ 0x17 -#define I2C_CR2_FREQ_24MHZ 0x18 -#define I2C_CR2_FREQ_25MHZ 0x19 -#define I2C_CR2_FREQ_26MHZ 0x1a -#define I2C_CR2_FREQ_27MHZ 0x1b -#define I2C_CR2_FREQ_28MHZ 0x1c -#define I2C_CR2_FREQ_29MHZ 0x1d -#define I2C_CR2_FREQ_30MHZ 0x1e -#define I2C_CR2_FREQ_31MHZ 0x1f -#define I2C_CR2_FREQ_32MHZ 0x20 -#define I2C_CR2_FREQ_33MHZ 0x21 -#define I2C_CR2_FREQ_34MHZ 0x22 -#define I2C_CR2_FREQ_35MHZ 0x23 -#define I2C_CR2_FREQ_36MHZ 0x24 -/**@}*/ - -/* --- I2Cx_OAR1 values ---------------------------------------------------- */ - -/* ADDMODE: Addressing mode (slave mode) */ -#define I2C_OAR1_ADDMODE (1 << 15) -#define I2C_OAR1_ADDMODE_7BIT 0 -#define I2C_OAR1_ADDMODE_10BIT 1 - -/* Note: Bit 14 should always be kept at 1 by software! */ - -/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ - -/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ - -/* --- I2Cx_OAR2 values ---------------------------------------------------- */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ - -/* ENDUAL: Dual addressing mode enable */ -#define I2C_OAR2_ENDUAL (1 << 0) - -/* --- I2Cx_DR values ------------------------------------------------------ */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* DR[7:0] 8-bit data register */ - -/* --- I2Cx_SR1 values ----------------------------------------------------- */ - -/* SMBALERT: SMBus alert */ -#define I2C_SR1_SMBALERT (1 << 15) - -/* TIMEOUT: Timeout or Tlow Error */ -#define I2C_SR1_TIMEOUT (1 << 14) - -/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ - -/* PECERR: PEC Error in reception */ -#define I2C_SR1_PECERR (1 << 12) - -/* OVR: Overrun/Underrun */ -#define I2C_SR1_OVR (1 << 11) - -/* AF: Acknowledge failure */ -#define I2C_SR1_AF (1 << 10) - -/* ARLO: Arbitration lost (master mode) */ -#define I2C_SR1_ARLO (1 << 9) - -/* BERR: Bus error */ -#define I2C_SR1_BERR (1 << 8) - -/* TxE: Data register empty (transmitters) */ -#define I2C_SR1_TxE (1 << 7) - -/* RxNE: Data register not empty (receivers) */ -#define I2C_SR1_RxNE (1 << 6) - -/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ - -/* STOPF: STOP detection (slave mode) */ -#define I2C_SR1_STOPF (1 << 4) - -/* ADD10: 10-bit header sent (master mode) */ -#define I2C_SR1_ADD10 (1 << 3) - -/* BTF: Byte transfer finished */ -#define I2C_SR1_BTF (1 << 2) - -/* ADDR: Address sent (master mode) / address matched (slave mode) */ -#define I2C_SR1_ADDR (1 << 1) - -/* SB: Start bit (master mode) */ -#define I2C_SR1_SB (1 << 0) - -/* --- I2Cx_SR2 values ----------------------------------------------------- */ - -/* Bits [15:8]: PEC[7:0]: Packet error checking register */ - -/* DUALF: Dual flag (slave mode) */ -#define I2C_SR2_DUALF (1 << 7) - -/* SMBHOST: SMBus host header (slave mode) */ -#define I2C_SR2_SMBHOST (1 << 6) - -/* SMBDEFAULT: SMBus device default address (slave mode) */ -#define I2C_SR2_SMBDEFAULT (1 << 5) - -/* GENCALL: General call address (slave mode) */ -#define I2C_SR2_GENCALL (1 << 4) - -/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ - -/* TRA: Transmitter / receiver */ -#define I2C_SR2_TRA (1 << 2) - -/* BUSY: Bus busy */ -#define I2C_SR2_BUSY (1 << 1) - -/* MSL: Master / slave */ -#define I2C_SR2_MSL (1 << 0) - -/* --- I2Cx_CCR values ----------------------------------------------------- */ - -/* F/S: I2C Master mode selection (fast / standard) */ -#define I2C_CCR_FS (1 << 15) - -/* DUTY: Fast Mode Duty Cycle */ -/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles -@ingroup i2c_defines - -@{*/ -#define I2C_CCR_DUTY (1 << 14) -#define I2C_CCR_DUTY_DIV2 0 -#define I2C_CCR_DUTY_16_DIV_9 1 -/**@}*/ - -/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [11:0]: - * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) - */ - -/* --- I2Cx_TRISE values --------------------------------------------------- */ - -/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [5:0]: - * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) - */ - -/* --- I2C const definitions ----------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup i2c_rw I2C Read/Write bit -@ingroup i2c_defines - -@{*/ -#define I2C_WRITE 0 -#define I2C_READ 1 -/**@}*/ - -/* --- I2C funtion prototypes----------------------------------------------- */ - -BEGIN_DECLS - -void i2c_reset(u32 i2c); -void i2c_peripheral_enable(u32 i2c); -void i2c_peripheral_disable(u32 i2c); -void i2c_send_start(u32 i2c); -void i2c_send_stop(u32 i2c); -void i2c_clear_stop(u32 i2c); -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave); -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave); -void i2c_set_fast_mode(u32 i2c); -void i2c_set_standard_mode(u32 i2c); -void i2c_set_clock_frequency(u32 i2c, u8 freq); -void i2c_set_ccr(u32 i2c, u16 freq); -void i2c_set_trise(u32 i2c, u16 trise); -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); -void i2c_send_data(u32 i2c, u8 data); -uint8_t i2c_get_data(u32 i2c); -void i2c_enable_interrupt(u32 i2c, u32 interrupt); -void i2c_disable_interrupt(u32 i2c, u32 interrupt); -void i2c_enable_ack(u32 i2c); -void i2c_disable_ack(u32 i2c); -void i2c_nack_next(u32 i2c); -void i2c_nack_current(u32 i2c); -void i2c_set_dutycycle(u32 i2c, u32 dutycycle); -void i2c_enable_dma(u32 i2c); -void i2c_disable_dma(u32 i2c); -void i2c_set_dma_last_transfer(u32 i2c); -void i2c_clear_dma_last_transfer(u32 i2c); - -END_DECLS - +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." #endif -/**@}*/ diff --git a/include/libopencm3/stm32/l1/i2c.h b/include/libopencm3/stm32/l1/i2c.h new file mode 100644 index 0000000..1fd419d --- /dev/null +++ b/include/libopencm3/stm32/l1/i2c.h @@ -0,0 +1,41 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the STM32L1xx I2C + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index c6ac545..fc6cbcb 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -17,354 +17,6 @@ * along with this library. If not, see . */ -<<<<<<< HEAD -/**@{*/ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup usart_reg_base USART register base addresses -@ingroup STM32F_usart_defines - -@{*/ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -/**@}*/ -#define UART4 UART4_BASE -#define UART5 UART5_BASE - -/* --- USART registers ----------------------------------------------------- */ - -/* Status register (USARTx_SR) */ -#define USART_SR(usart_base) MMIO32(usart_base + 0x00) -#define USART1_SR USART_SR(USART1_BASE) -#define USART2_SR USART_SR(USART2_BASE) -#define USART3_SR USART_SR(USART3_BASE) -#define UART4_SR USART_SR(UART4_BASE) -#define UART5_SR USART_SR(UART5_BASE) - -/* Data register (USARTx_DR) */ -#define USART_DR(usart_base) MMIO32(usart_base + 0x04) -#define USART1_DR USART_DR(USART1_BASE) -#define USART2_DR USART_DR(USART2_BASE) -#define USART3_DR USART_DR(USART3_BASE) -#define UART4_DR USART_DR(UART4_BASE) -#define UART5_DR USART_DR(UART5_BASE) - -/* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) -#define USART1_BRR USART_BRR(USART1_BASE) -#define USART2_BRR USART_BRR(USART2_BASE) -#define USART3_BRR USART_BRR(USART3_BASE) -#define UART4_BRR USART_BRR(UART4_BASE) -#define UART5_BRR USART_BRR(UART5_BASE) - -/* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) -#define USART1_CR1 USART_CR1(USART1_BASE) -#define USART2_CR1 USART_CR1(USART2_BASE) -#define USART3_CR1 USART_CR1(USART3_BASE) -#define UART4_CR1 USART_CR1(UART4_BASE) -#define UART5_CR1 USART_CR1(UART5_BASE) - -/* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) -#define USART1_CR2 USART_CR2(USART1_BASE) -#define USART2_CR2 USART_CR2(USART2_BASE) -#define USART3_CR2 USART_CR2(USART3_BASE) -#define UART4_CR2 USART_CR2(UART4_BASE) -#define UART5_CR2 USART_CR2(UART5_BASE) - -/* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) -#define USART1_CR3 USART_CR3(USART1_BASE) -#define USART2_CR3 USART_CR3(USART2_BASE) -#define USART3_CR3 USART_CR3(USART3_BASE) -#define UART4_CR3 USART_CR3(UART4_BASE) -#define UART5_CR3 USART_CR3(UART5_BASE) - -/* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) -#define USART1_GTPR USART_GTPR(USART1_BASE) -#define USART2_GTPR USART_GTPR(USART2_BASE) -#define USART3_GTPR USART_GTPR(USART3_BASE) -#define UART4_GTPR USART_GTPR(UART4_BASE) -#define UART5_GTPR USART_GTPR(UART5_BASE) - -/* --- USART_SR values ----------------------------------------------------- */ -/****************************************************************************/ -/** @defgroup usart_sr_flags USART Status register Flags -@ingroup STM32F_usart_defines - -@{*/ - -/** CTS: CTS flag */ -/** @note: undefined on UART4 and UART5 */ -#define USART_SR_CTS (1 << 9) - -/** LBD: LIN break detection flag */ -#define USART_SR_LBD (1 << 8) - -/** TXE: Transmit data buffer empty */ -#define USART_SR_TXE (1 << 7) - -/** TC: Transmission complete */ -#define USART_SR_TC (1 << 6) - -/** RXNE: Read data register not empty */ -#define USART_SR_RXNE (1 << 5) - -/** IDLE: Idle line detected */ -#define USART_SR_IDLE (1 << 4) - -/** ORE: Overrun error */ -#define USART_SR_ORE (1 << 3) - -/** NE: Noise error flag */ -#define USART_SR_NE (1 << 2) - -/** FE: Framing error */ -#define USART_SR_FE (1 << 1) - -/** PE: Parity error */ -#define USART_SR_PE (1 << 0) -/**@}*/ - -/* --- USART_DR values ----------------------------------------------------- */ - -/* USART_DR[8:0]: DR[8:0]: Data value */ -#define USART_DR_MASK 0x1FF - -/* --- USART_BRR values ---------------------------------------------------- */ - -/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ -#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) -/* DIV_Fraction[3:0]: fraction of USARTDIV */ -#define USART_BRR_DIV_FRACTION_MASK 0xF - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* UE: USART enable */ -#define USART_CR1_UE (1 << 13) - -/* M: Word length */ -#define USART_CR1_M (1 << 12) - -/* WAKE: Wakeup method */ -#define USART_CR1_WAKE (1 << 11) - -/* PCE: Parity control enable */ -#define USART_CR1_PCE (1 << 10) - -/* PS: Parity selection */ -#define USART_CR1_PS (1 << 9) - -/* PEIE: PE interrupt enable */ -#define USART_CR1_PEIE (1 << 8) - -/* TXEIE: TXE interrupt enable */ -#define USART_CR1_TXEIE (1 << 7) - -/* TCIE: Transmission complete interrupt enable */ -#define USART_CR1_TCIE (1 << 6) - -/* RXNEIE: RXNE interrupt enable */ -#define USART_CR1_RXNEIE (1 << 5) - -/* IDLEIE: IDLE interrupt enable */ -#define USART_CR1_IDLEIE (1 << 4) - -/* TE: Transmitter enable */ -#define USART_CR1_TE (1 << 3) - -/* RE: Receiver enable */ -#define USART_CR1_RE (1 << 2) - -/* RWU: Receiver wakeup */ -#define USART_CR1_RWU (1 << 1) - -/* SBK: Send break */ -#define USART_CR1_SBK (1 << 0) - -/* --- USART_CR2 values ---------------------------------------------------- */ - -/* LINEN: LIN mode enable */ -#define USART_CR2_LINEN (1 << 14) - -/* STOP[13:12]: STOP bits */ -#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ -#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ -#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ -#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ -#define USART_CR2_STOPBITS_MASK (0x03 << 12) -#define USART_CR2_STOPBITS_SHIFT 12 - -/* CLKEN: Clock enable */ -#define USART_CR2_CLKEN (1 << 11) - -/* CPOL: Clock polarity */ -#define USART_CR2_CPOL (1 << 10) - -/* CPHA: Clock phase */ -#define USART_CR2_CPHA (1 << 9) - -/* LBCL: Last bit clock pulse */ -#define USART_CR2_LBCL (1 << 8) - -/* LBDIE: LIN break detection interrupt enable */ -#define USART_CR2_LBDIE (1 << 6) - -/* LBDL: LIN break detection length */ -#define USART_CR2_LBDL (1 << 5) - -/* ADD[3:0]: Addres of the usart node */ -#define USART_CR2_ADD_MASK 0xF - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* CTSIE: CTS interrupt enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSIE (1 << 10) - -/* CTSE: CTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSE (1 << 9) - -/* RTSE: RTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_RTSE (1 << 8) - -/* DMAT: DMA enable transmitter */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAT (1 << 7) - -/* DMAR: DMA enable receiver */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAR (1 << 6) - -/* SCEN: Smartcard mode enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_SCEN (1 << 5) - -/* NACK: Smartcard NACK enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_NACK (1 << 4) - -/* HDSEL: Half-duplex selection */ -#define USART_CR3_HDSEL (1 << 3) - -/* IRLP: IrDA low-power */ -#define USART_CR3_IRLP (1 << 2) - -/* IREN: IrDA mode enable */ -#define USART_CR3_IREN (1 << 1) - -/* EIE: Error interrupt enable */ -#define USART_CR3_EIE (1 << 0) - -/* --- USART_GTPR values --------------------------------------------------- */ - -/* GT[7:0]: Guard time value */ -/* Note: N/A on UART4 & UART5 */ -#define USART_GTPR_GT_MASK (0xFF << 8) - -/* PSC[7:0]: Prescaler value */ -/* Note: N/A on UART4/5 */ -#define USART_GTPR_PSC_MASK 0xFF - -/* TODO */ /* Note to Uwe: what needs to be done here? */ - -/* --- Convenience defines ------------------------------------------------- */ - -/* CR1_PCE / CR1_PS combined values */ -/****************************************************************************/ -/** @defgroup usart_cr1_parity USART Parity Selection -@ingroup STM32F_usart_defines - -@{*/ -#define USART_PARITY_NONE 0x00 -#define USART_PARITY_EVEN USART_CR1_PCE -#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) -/**@}*/ -#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) - -/* CR1_TE/CR1_RE combined values */ -/****************************************************************************/ -/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection -@ingroup STM32F_usart_defines - -@{*/ -#define USART_MODE_RX USART_CR1_RE -#define USART_MODE_TX USART_CR1_TE -#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) -/**@}*/ -#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) - -/****************************************************************************/ -/** @defgroup usart_cr2_stopbits USART Stop Bit Selection -@ingroup STM32F_usart_defines - -@{*/ -#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ -#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ -#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ -/**@}*/ - -/* CR3_CTSE/CR3_RTSE combined values */ -/****************************************************************************/ -/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection -@ingroup STM32F_usart_defines - -@{*/ -#define USART_FLOWCONTROL_NONE 0x00 -#define USART_FLOWCONTROL_RTS USART_CR3_RTSE -#define USART_FLOWCONTROL_CTS USART_CR3_CTSE -#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -/**@}*/ -#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void usart_set_baudrate(u32 usart, u32 baud); -void usart_set_databits(u32 usart, u32 bits); -void usart_set_stopbits(u32 usart, u32 stopbits); -void usart_set_parity(u32 usart, u32 parity); -void usart_set_mode(u32 usart, u32 mode); -void usart_set_flow_control(u32 usart, u32 flowcontrol); -void usart_enable(u32 usart); -void usart_disable(u32 usart); -void usart_send(u32 usart, u16 data); -u16 usart_recv(u32 usart); -void usart_wait_send_ready(u32 usart); -void usart_wait_recv_ready(u32 usart); -void usart_send_blocking(u32 usart, u16 data); -u16 usart_recv_blocking(u32 usart); -void usart_enable_rx_dma(u32 usart); -void usart_disable_rx_dma(u32 usart); -void usart_enable_tx_dma(u32 usart); -void usart_disable_tx_dma(u32 usart); -void usart_enable_rx_interrupt(u32 usart); -void usart_disable_rx_interrupt(u32 usart); -void usart_enable_tx_interrupt(u32 usart); -void usart_disable_tx_interrupt(u32 usart); -void usart_enable_error_interrupt(u32 usart); -void usart_disable_error_interrupt(u32 usart); -bool usart_get_flag(u32 usart, u32 flag); -bool usart_get_interrupt_source(u32 usart, u32 flag); - -END_DECLS - -======= #if defined(STM32F1) # include #elif defined(STM32F2) @@ -375,6 +27,5 @@ END_DECLS # include #else # error "stm32 family not defined." ->>>>>>> Move usart files to common area #endif diff --git a/lib/stm32/common/i2c_common_all.c b/lib/stm32/common/i2c_common_all.c new file mode 100644 index 0000000..28ae199 --- /dev/null +++ b/lib/stm32/common/i2c_common_all.c @@ -0,0 +1,411 @@ +/** @addtogroup i2c_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 15 October 2012 + +Devices can have up to two I2C peripherals. The peripherals support SMBus and +PMBus variants. + +A peripheral begins after reset in Slave mode. To become a Master a start +condition must be generated. The peripheral will remain in Master mode unless +a multimaster contention is lost or a stop condition is generated. + +@todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status +register access, Error conditions + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Reset. + +The I2C peripheral and all its associated configuration registers are placed in the +reset condition. The reset is effected via the RCC peripheral reset system. + +@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. +*/ + +void i2c_reset(u32 i2c) +{ + switch (i2c) { + case I2C1: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); + break; + case I2C2: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Peripheral Enable. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_peripheral_enable(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_PE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Peripheral Disable. + +This must not be reset while in Master mode until a communication has finished. +In Slave mode, the peripheral is disabled only after communication has ended. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_peripheral_disable(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_PE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Start Condition. + +If in Master mode this will cause a restart condition to occur at the end of the +current transmission. If in Slave mode, this will initiate a start condition +when the current bus activity is completed. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_send_start(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_START; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Stop Condition. + +After the current byte transfer this will initiate a stop condition if in Master +mode, or simply release the bus if in Slave mode. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_send_stop(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_STOP; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Clear Stop Flag. + +Clear the "Send Stop" flag in the I2C config register + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_clear_stop(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_STOP; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the 7 bit Slave Address for the Peripheral. + +This sets an address for Slave mode operation, in 7 bit form. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int8. Slave address 0...127. +*/ + +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) +{ + I2C_OAR1(i2c) = (u16)(slave << 1); + I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; + I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the 10 bit Slave Address for the Peripheral. + +This sets an address for Slave mode operation, in 10 bit form. + +@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int16. Slave address 0...1023. +*/ + +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) +{ + I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Fast Mode. + +Set the clock frequency to the high clock rate mode (up to 400kHz). The actual +clock frequency must be set with @ref i2c_set_clock_frequency + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_set_fast_mode(u32 i2c) +{ + I2C_CCR(i2c) |= I2C_CCR_FS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Standard Mode. + +Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual +clock frequency must be set with @ref i2c_set_clock_frequency + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + +void i2c_set_standard_mode(u32 i2c) +{ + I2C_CCR(i2c) &= ~I2C_CCR_FS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Peripheral Clock Frequency. + +Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that +this is not the I2C bus clock. This is set in conjunction with the Clock +Control register to generate the Master bus clock, see @ref i2c_set_ccr + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock. +*/ + +void i2c_set_clock_frequency(u32 i2c, u8 freq) +{ + u16 reg16; + reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ + reg16 |= freq; + I2C_CR2(i2c) = reg16; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Bus Clock Frequency. + +Set the bus clock frequency. This is a 12 bit number (0...4095) calculated +from the formulae given in the STM32F1 reference manual in the description +of the CCR field. It is a divisor of the peripheral clock frequency +@ref i2c_set_clock_frequency modified by the fast mode setting +@ref i2c_set_fast_mode + +@todo provide additional API assitance to set the clock, eg macros + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095. +*/ + +void i2c_set_ccr(u32 i2c, u16 freq) +{ + u16 reg16; + reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ + reg16 |= freq; + I2C_CCR(i2c) = reg16; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the Rise Time. + +Set the maximum rise time on the bus according to the I2C specification, as 1 +more than the specified rise time in peripheral clock cycles. This is a 6 bit +number. + +@todo provide additional APIP assistance. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] trise Unsigned int16. Rise Time Setting 0...63. +*/ + +void i2c_set_trise(u32 i2c, u16 trise) +{ + I2C_TRISE(i2c) = trise; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send the 7-bit Slave Address. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int16. Slave address 0...1023. +@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw. +*/ + +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) +{ + I2C_DR(i2c) = (u8)((slave << 1) | readwrite); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Data. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] data Unsigned int8. Byte to send. +*/ + +void i2c_send_data(u32 i2c, u8 data) +{ + I2C_DR(i2c) = data; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Get Data. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +uint8_t i2c_get_data(u32 i2c) +{ + return I2C_DR(i2c) & 0xff; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Enable Interrupt + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] interrupt Unsigned int32. Interrupt to enable. +*/ +void i2c_enable_interrupt(u32 i2c, u32 interrupt) +{ + I2C_CR2(i2c) |= interrupt; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Disable Interrupt + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] interrupt Unsigned int32. Interrupt to disable. +*/ +void i2c_disable_interrupt(u32 i2c, u32 interrupt) +{ + I2C_CR2(i2c) &= ~interrupt; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Enable ACK + +Enables acking of own 7/10 bit address +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_enable_ack(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_ACK; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Disable ACK + +Disables acking of own 7/10 bit address +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_disable_ack(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_ACK; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C NACK Next Byte + +Causes the I2C controller to NACK the reception of the next byte +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_nack_next(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_POS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C NACK Next Byte + +Causes the I2C controller to NACK the reception of the current byte + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_nack_current(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_POS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set clock duty cycle + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle. +*/ +void i2c_set_dutycycle(u32 i2c, u32 dutycycle) +{ + if (dutycycle == I2C_CCR_DUTY_DIV2) + I2C_CCR(i2c) &= ~I2C_CCR_DUTY; + else + I2C_CCR(i2c) |= I2C_CCR_DUTY; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Enable DMA + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_enable_dma(u32 i2c) +{ + I2C_CR2(i2c) |= I2C_CR2_DMAEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Disable DMA + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_disable_dma(u32 i2c) +{ + I2C_CR2(i2c) &= ~I2C_CR2_DMAEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set DMA last transfer + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_set_dma_last_transfer(u32 i2c) +{ + I2C_CR2(i2c) |= I2C_CR2_LAST; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Clear DMA last transfer + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ +void i2c_clear_dma_last_transfer(u32 i2c) +{ + I2C_CR2(i2c) &= ~I2C_CR2_LAST; +} + +/**@}*/ diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index e2c4284..93cc3cf 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -34,7 +34,7 @@ OBJS = rcc.o gpio.o usart.o adc.o flash.o \ timer.o usb_f107.o desig.o crc.o pwr.o \ usb_fx07_common.o \ gpio_common_all.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/i2c.c b/lib/stm32/f1/i2c.c new file mode 100644 index 0000000..2d86bf3 --- /dev/null +++ b/lib/stm32/f1/i2c.c @@ -0,0 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx I2C + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index d0b1ac8..9a21857 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -31,7 +31,7 @@ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o timer.o \ gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/i2c.c b/lib/stm32/f2/i2c.c new file mode 100644 index 0000000..f20a840 --- /dev/null +++ b/lib/stm32/f2/i2c.c @@ -0,0 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32F2xx + +@brief libopencm3 STM32F2xx I2C + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index dc7db87..7d02d55 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -34,7 +34,7 @@ OBJS = rcc.o gpio.o usart.o flash.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f4/i2c.c b/lib/stm32/f4/i2c.c new file mode 100644 index 0000000..3250faa --- /dev/null +++ b/lib/stm32/f4/i2c.c @@ -0,0 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx I2C + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/i2c.c b/lib/stm32/i2c.c deleted file mode 100644 index a67bece..0000000 --- a/lib/stm32/i2c.c +++ /dev/null @@ -1,415 +0,0 @@ -/** @defgroup i2c_file I2C - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxxx I2C - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies - -@date 15 October 2012 - -Devices can have up to two I2C peripherals. The peripherals support SMBus and -PMBus variants. - -A peripheral begins after reset in Slave mode. To become a Master a start -condition must be generated. The peripheral will remain in Master mode unless -a multimaster contention is lost or a stop condition is generated. - -@todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status -register access, Error conditions - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -/**@{*/ - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Reset. - -The I2C peripheral and all its associated configuration registers are placed in the -reset condition. The reset is effected via the RCC peripheral reset system. - -@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. -*/ - -void i2c_reset(u32 i2c) -{ - switch (i2c) { - case I2C1: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); - break; - case I2C2: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Peripheral Enable. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_peripheral_enable(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_PE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Peripheral Disable. - -This must not be reset while in Master mode until a communication has finished. -In Slave mode, the peripheral is disabled only after communication has ended. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_peripheral_disable(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_PE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Send Start Condition. - -If in Master mode this will cause a restart condition to occur at the end of the -current transmission. If in Slave mode, this will initiate a start condition -when the current bus activity is completed. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_send_start(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_START; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Send Stop Condition. - -After the current byte transfer this will initiate a stop condition if in Master -mode, or simply release the bus if in Slave mode. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_send_stop(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_STOP; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Clear Stop Flag. - -Clear the "Send Stop" flag in the I2C config register - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_clear_stop(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_STOP; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set the 7 bit Slave Address for the Peripheral. - -This sets an address for Slave mode operation, in 7 bit form. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] slave Unsigned int8. Slave address 0...127. -*/ - -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) -{ - I2C_OAR1(i2c) = (u16)(slave << 1); - I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; - I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set the 10 bit Slave Address for the Peripheral. - -This sets an address for Slave mode operation, in 10 bit form. - -@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] slave Unsigned int16. Slave address 0...1023. -*/ - -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) -{ - I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set Fast Mode. - -Set the clock frequency to the high clock rate mode (up to 400kHz). The actual -clock frequency must be set with @ref i2c_set_clock_frequency - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_set_fast_mode(u32 i2c) -{ - I2C_CCR(i2c) |= I2C_CCR_FS; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set Standard Mode. - -Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual -clock frequency must be set with @ref i2c_set_clock_frequency - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ - -void i2c_set_standard_mode(u32 i2c) -{ - I2C_CCR(i2c) &= ~I2C_CCR_FS; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set Peripheral Clock Frequency. - -Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that -this is not the I2C bus clock. This is set in conjunction with the Clock -Control register to generate the Master bus clock, see @ref i2c_set_ccr - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock. -*/ - -void i2c_set_clock_frequency(u32 i2c, u8 freq) -{ - u16 reg16; - reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ - reg16 |= freq; - I2C_CR2(i2c) = reg16; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set Bus Clock Frequency. - -Set the bus clock frequency. This is a 12 bit number (0...4095) calculated -from the formulae given in the STM32F1 reference manual in the description -of the CCR field. It is a divisor of the peripheral clock frequency -@ref i2c_set_clock_frequency modified by the fast mode setting -@ref i2c_set_fast_mode - -@todo provide additional API assitance to set the clock, eg macros - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095. -*/ - -void i2c_set_ccr(u32 i2c, u16 freq) -{ - u16 reg16; - reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ - reg16 |= freq; - I2C_CCR(i2c) = reg16; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set the Rise Time. - -Set the maximum rise time on the bus according to the I2C specification, as 1 -more than the specified rise time in peripheral clock cycles. This is a 6 bit -number. - -@todo provide additional APIP assistance. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] trise Unsigned int16. Rise Time Setting 0...63. -*/ - -void i2c_set_trise(u32 i2c, u16 trise) -{ - I2C_TRISE(i2c) = trise; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Send the 7-bit Slave Address. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] slave Unsigned int16. Slave address 0...1023. -@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw. -*/ - -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) -{ - I2C_DR(i2c) = (u8)((slave << 1) | readwrite); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Send Data. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] data Unsigned int8. Byte to send. -*/ - -void i2c_send_data(u32 i2c, u8 data) -{ - I2C_DR(i2c) = data; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Get Data. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -uint8_t i2c_get_data(u32 i2c) -{ - return I2C_DR(i2c) & 0xff; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Enable Interrupt - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] interrupt Unsigned int32. Interrupt to enable. -*/ -void i2c_enable_interrupt(u32 i2c, u32 interrupt) -{ - I2C_CR2(i2c) |= interrupt; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Disable Interrupt - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] interrupt Unsigned int32. Interrupt to disable. -*/ -void i2c_disable_interrupt(u32 i2c, u32 interrupt) -{ - I2C_CR2(i2c) &= ~interrupt; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Enable ACK - -Enables acking of own 7/10 bit address -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_enable_ack(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_ACK; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Disable ACK - -Disables acking of own 7/10 bit address -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_disable_ack(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_ACK; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C NACK Next Byte - -Causes the I2C controller to NACK the reception of the next byte -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_nack_next(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_POS; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C NACK Next Byte - -Causes the I2C controller to NACK the reception of the current byte - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_nack_current(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_POS; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set clock duty cycle - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle. -*/ -void i2c_set_dutycycle(u32 i2c, u32 dutycycle) -{ - if (dutycycle == I2C_CCR_DUTY_DIV2) - I2C_CCR(i2c) &= ~I2C_CCR_DUTY; - else - I2C_CCR(i2c) |= I2C_CCR_DUTY; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Enable DMA - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_enable_dma(u32 i2c) -{ - I2C_CR2(i2c) |= I2C_CR2_DMAEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Disable DMA - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_disable_dma(u32 i2c) -{ - I2C_CR2(i2c) &= ~I2C_CR2_DMAEN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Set DMA last transfer - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_set_dma_last_transfer(u32 i2c) -{ - I2C_CR2(i2c) |= I2C_CR2_LAST; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief I2C Clear DMA last transfer - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ -void i2c_clear_dma_last_transfer(u32 i2c) -{ - I2C_CR2(i2c) &= ~I2C_CR2_LAST; -} - -/**@}*/ diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index c48f5b9..8578fe3 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -29,7 +29,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o -OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o usart_common_all.o iwdg_common_all.o +OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o +OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/i2c.c b/lib/stm32/l1/i2c.c new file mode 100644 index 0000000..7a6fe84 --- /dev/null +++ b/lib/stm32/l1/i2c.c @@ -0,0 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx I2C + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + -- cgit v1.2.3 From efee94901a3d587c3168f7340f3797336eb5f0dc Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Thu, 6 Dec 2012 03:25:51 +1030 Subject: CRC moved to common area --- include/libopencm3/stm32/common/crc_common_all.h | 85 ++++++++++++++++++++++ include/libopencm3/stm32/crc.h | 89 ++++-------------------- include/libopencm3/stm32/f1/crc.h | 40 +++++++++++ include/libopencm3/stm32/f2/crc.h | 40 +++++++++++ include/libopencm3/stm32/f4/crc.h | 40 +++++++++++ include/libopencm3/stm32/l1/crc.h | 40 +++++++++++ lib/stm32/common/crc_common_all.c | 82 ++++++++++++++++++++++ lib/stm32/crc.c | 86 ----------------------- lib/stm32/f1/Makefile | 8 +-- lib/stm32/f1/crc.c | 29 ++++++++ lib/stm32/f2/Makefile | 6 +- lib/stm32/f2/crc.c | 29 ++++++++ lib/stm32/f4/Makefile | 6 +- lib/stm32/f4/crc.c | 29 ++++++++ lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/crc.c | 29 ++++++++ 16 files changed, 466 insertions(+), 174 deletions(-) create mode 100644 include/libopencm3/stm32/common/crc_common_all.h create mode 100644 include/libopencm3/stm32/f1/crc.h create mode 100644 include/libopencm3/stm32/f2/crc.h create mode 100644 include/libopencm3/stm32/f4/crc.h create mode 100644 include/libopencm3/stm32/l1/crc.h create mode 100644 lib/stm32/common/crc_common_all.c delete mode 100644 lib/stm32/crc.c create mode 100644 lib/stm32/f1/crc.c create mode 100644 lib/stm32/f2/crc.c create mode 100644 lib/stm32/f4/crc.c create mode 100644 lib/stm32/l1/crc.c (limited to 'lib/stm32') diff --git a/include/libopencm3/stm32/common/crc_common_all.h b/include/libopencm3/stm32/common/crc_common_all.h new file mode 100644 index 0000000..892f41b --- /dev/null +++ b/include/libopencm3/stm32/common/crc_common_all.h @@ -0,0 +1,85 @@ +/** @addtogroup crc_defines */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */ + +#ifndef LIBOPENCM3_CRC_COMMON_ALL_H +#define LIBOPENCM3_CRC_COMMON_ALL_H + +#include + +/* --- CRC registers ------------------------------------------------------- */ + +/* Data register (CRC_DR) */ +#define CRC_DR MMIO32(CRC_BASE + 0x00) + +/* Independent data register (CRC_IDR) */ +#define CRC_IDR MMIO32(CRC_BASE + 0x04) + +/* Control register (CRC_CR) */ +#define CRC_CR MMIO32(CRC_BASE + 0x08) + +/* --- CRC_DR values ------------------------------------------------------- */ + +/* Bits [31:0]: Data register */ + +/* --- CRC_IDR values ------------------------------------------------------ */ + +/* Bits [31:8]: Reserved */ + +/* Bits [7:0]: General-purpose 8-bit data register bits */ + +/* --- CRC_CR values ------------------------------------------------------- */ + +/* Bits [31:1]: Reserved */ + +/* RESET bit */ +#define CRC_CR_RESET (1 << 0) + +/* --- CRC function prototypes --------------------------------------------- */ + +BEGIN_DECLS + +/* TODO */ + +/** + * Reset the CRC calculator to initial values. + */ +void crc_reset(void); + +/** + * Add a word to the crc calculator and return the result. + * @param data new word to add to the crc calculator + * @return final crc calculator value + */ +u32 crc_calculate(u32 data); + +/** + * Add a block of data to the CRC calculator and return the final result + * @param datap pointer to the start of a block of 32bit data words + * @param size length of data, in 32bit increments + * @return final CRC calculator value + */ +u32 crc_calculate_block(u32 *datap, int size); + +END_DECLS + +#endif diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h index aa30182..3d43061 100644 --- a/include/libopencm3/stm32/crc.h +++ b/include/libopencm3/stm32/crc.h @@ -1,22 +1,8 @@ -/** @defgroup crc_defines CRC Defines +/* This provides unification of code over STM32F subfamilies */ -@brief libopencm3 Defined Constants and Types for the STM32F CRC Generator - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2010 Thomas Otto - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -31,66 +17,15 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include -#include - -/* --- CRC registers ------------------------------------------------------- */ - -/* Data register (CRC_DR) */ -#define CRC_DR MMIO32(CRC_BASE + 0x00) - -/* Independent data register (CRC_IDR) */ -#define CRC_IDR MMIO32(CRC_BASE + 0x04) - -/* Control register (CRC_CR) */ -#define CRC_CR MMIO32(CRC_BASE + 0x08) - -/* --- CRC_DR values ------------------------------------------------------- */ - -/* Bits [31:0]: Data register */ - -/* --- CRC_IDR values ------------------------------------------------------ */ - -/* Bits [31:8]: Reserved */ - -/* Bits [7:0]: General-purpose 8-bit data register bits */ - -/* --- CRC_CR values ------------------------------------------------------- */ - -/* Bits [31:1]: Reserved */ - -/* RESET bit */ -#define CRC_CR_RESET (1 << 0) - -/* --- CRC function prototypes --------------------------------------------- */ - -BEGIN_DECLS - -/* TODO */ - -/** - * Reset the CRC calculator to initial values. - */ -void crc_reset(void); - -/** - * Add a word to the crc calculator and return the result. - * @param data new word to add to the crc calculator - * @return final crc calculator value - */ -u32 crc_calculate(u32 data); - -/** - * Add a block of data to the CRC calculator and return the final result - * @param datap pointer to the start of a block of 32bit data words - * @param size length of data, in 32bit increments - * @return final CRC calculator value - */ -u32 crc_calculate_block(u32 *datap, int size); - -END_DECLS - +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." #endif + diff --git a/include/libopencm3/stm32/f1/crc.h b/include/libopencm3/stm32/f1/crc.h new file mode 100644 index 0000000..c3b9939 --- /dev/null +++ b/include/libopencm3/stm32/f1/crc.h @@ -0,0 +1,40 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32F1xx CRC Generator + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include +#include + +#endif diff --git a/include/libopencm3/stm32/f2/crc.h b/include/libopencm3/stm32/f2/crc.h new file mode 100644 index 0000000..bf2d9fe --- /dev/null +++ b/include/libopencm3/stm32/f2/crc.h @@ -0,0 +1,40 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32F2xx CRC Generator + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include +#include + +#endif diff --git a/include/libopencm3/stm32/f4/crc.h b/include/libopencm3/stm32/f4/crc.h new file mode 100644 index 0000000..1c375fa --- /dev/null +++ b/include/libopencm3/stm32/f4/crc.h @@ -0,0 +1,40 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32F4xx CRC Generator + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include +#include + +#endif diff --git a/include/libopencm3/stm32/l1/crc.h b/include/libopencm3/stm32/l1/crc.h new file mode 100644 index 0000000..07370f2 --- /dev/null +++ b/include/libopencm3/stm32/l1/crc.h @@ -0,0 +1,40 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32L1xx CRC Generator + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include +#include + +#endif diff --git a/lib/stm32/common/crc_common_all.c b/lib/stm32/common/crc_common_all.c new file mode 100644 index 0000000..d65d1b7 --- /dev/null +++ b/lib/stm32/common/crc_common_all.c @@ -0,0 +1,82 @@ +/** @addtogroup crc_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Karl Palsson + +@date 15 October 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Reset. + +Reset the CRC unit and forces the data register to all 1s. + +*/ + +void crc_reset(void) +{ + CRC_CR |= CRC_CR_RESET; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Calculate. + +Writes a data word to the register, the write operation stalling until the +computation is complete. + +@param[in] data Unsigned int32. +@returns int32 Computed CRC result +*/ + +u32 crc_calculate(u32 data) +{ + CRC_DR = data; + // Data sheet says this blocks until it's ready.... + return CRC_DR; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Calculate of a Block of Data. + +Writes data words consecutively to the register, the write operation stalling +until the computation of each word is complete. + +@param[in] datap Unsigned int32. pointer to an array of 32 bit data words. +@returns int32 Final computed CRC result +*/ + +u32 crc_calculate_block(u32 *datap, int size) +{ + int i; + for (i = 0; i < size; i++) { + CRC_DR = datap[i]; + } + return CRC_DR; +} +/**@}*/ + diff --git a/lib/stm32/crc.c b/lib/stm32/crc.c deleted file mode 100644 index bd9e8d2..0000000 --- a/lib/stm32/crc.c +++ /dev/null @@ -1,86 +0,0 @@ -/** @defgroup crc_file CRC - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxxx CRC - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Karl Palsson - -@date 15 October 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -/**@{*/ - -/*-----------------------------------------------------------------------------*/ -/** @brief CRC Reset. - -Reset the CRC unit and forces the data register to all 1s. - -*/ - -void crc_reset(void) -{ - CRC_CR |= CRC_CR_RESET; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief CRC Calculate. - -Writes a data word to the register, the write operation stalling until the -computation is complete. - -@param[in] data Unsigned int32. -@returns int32 Computed CRC result -*/ - -u32 crc_calculate(u32 data) -{ - CRC_DR = data; - // Data sheet says this blocks until it's ready.... - return CRC_DR; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief CRC Calculate of a Block of Data. - -Writes data words consecutively to the register, the write operation stalling -until the computation of each word is complete. - -@param[in] datap Unsigned int32. pointer to an array of 32 bit data words. -@returns int32 Final computed CRC result -*/ - -u32 crc_calculate_block(u32 *datap, int size) -{ - int i; - for (i = 0; i < size; i++) { - CRC_DR = datap[i]; - } - return CRC_DR; -} -/**@}*/ - diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 93cc3cf..1f41e79 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -28,13 +28,13 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o usart.o adc.o flash.o \ - rtc.o i2c.o dma.o exti.o ethernet.o \ +OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o pwr.o \ + timer.o usb_f107.o desig.o pwr.o \ usb_fx07_common.o \ gpio_common_all.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o i2c_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o \ + crc_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/crc.c b/lib/stm32/f1/crc.c new file mode 100644 index 0000000..505fb79 --- /dev/null +++ b/lib/stm32/f1/crc.c @@ -0,0 +1,29 @@ +/** @defgroup crc_file CRC + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx CRC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + + diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 9a21857..b529697 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -28,10 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o usart.o flash.o \ - i2c.o exti2.o timer.o \ +OBJS = rcc.o gpio.o flash.o exti2.o timer.o \ gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o i2c_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o \ + crc_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/crc.c b/lib/stm32/f2/crc.c new file mode 100644 index 0000000..5437f7c --- /dev/null +++ b/lib/stm32/f2/crc.c @@ -0,0 +1,29 @@ +/** @defgroup crc_file CRC + +@ingroup STM32F2xx + +@brief libopencm3 STM32F2xx CRC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 7d02d55..9673d96 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -29,12 +29,12 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F4 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o usart.o flash.o \ - i2c.o exti2.o pwr.o timer.o \ +OBJS = rcc.o gpio.o flash.o exti2.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \ - usart_common_all.o iwdg_common_all.o i2c_common_all.o + usart_common_all.o iwdg_common_all.o i2c_common_all.o \ + crc_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f4/crc.c b/lib/stm32/f4/crc.c new file mode 100644 index 0000000..90e6782 --- /dev/null +++ b/lib/stm32/f4/crc.c @@ -0,0 +1,29 @@ +/** @defgroup crc_file CRC + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx CRC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + + diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index 8578fe3..32c8fd3 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -29,7 +29,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o -OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o +OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o crc_common_all.o OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o diff --git a/lib/stm32/l1/crc.c b/lib/stm32/l1/crc.c new file mode 100644 index 0000000..7d51341 --- /dev/null +++ b/lib/stm32/l1/crc.c @@ -0,0 +1,29 @@ +/** @defgroup crc_file CRC + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx CRC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + + -- cgit v1.2.3