From 1eb4e6ed29edc60598afc04e69b090a5ad3e9d80 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 23 Jan 2013 13:14:17 +0000 Subject: [flash] f1: use "proper" bit definition naming. Part 2 of 4: updated f1 to use flash__bit instead of just flash_bit --- lib/stm32/f1/rcc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'lib/stm32/f1/rcc.c') diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index 9cd8658..707c931 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -761,7 +761,7 @@ void rcc_clock_setup_in_hsi_out_64mhz(void) * 1WS from 24-48MHz * 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_2WS); + flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 16. @@ -814,7 +814,7 @@ void rcc_clock_setup_in_hsi_out_48mhz(void) * 1WS from 24-48MHz * 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_1WS); + flash_set_ws(FLASH_ACR_LATENCY_1WS); /* * Set the PLL multiplication factor to 12. @@ -865,7 +865,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) { * 1WS from 24-48MHz * 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_0WS); + flash_set_ws(FLASH_ACR_LATENCY_0WS); /* * Set the PLL multiplication factor to 6. @@ -922,7 +922,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) * 1WS from 24-48MHz * 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_0WS); + flash_set_ws(FLASH_ACR_LATENCY_0WS); /* * Set the PLL multiplication factor to 3. @@ -985,7 +985,7 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) * 1WS from 24-48MHz * 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_2WS); + flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. @@ -1048,7 +1048,7 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void) * 1WS from 24-48MHz * 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_2WS); + flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. @@ -1111,7 +1111,7 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void) * 1WS from 24-48MHz * 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_2WS); + flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. @@ -1158,7 +1158,7 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void) * 1WS from 24-48MHz * 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_2WS); + flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set prescalers for AHB, ADC, ABP1, ABP2. -- cgit v1.2.3