From 9439ce9d69afeb5e961cbc28ab581c3d4fc3fc60 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 22 May 2012 10:59:27 -0600 Subject: new lib/lpc43xx, starting with copy of lpc17xx --- lib/lpc43xx/Makefile | 58 ++++++++++++++++++++++++ lib/lpc43xx/gpio.c | 30 +++++++++++++ lib/lpc43xx/libopencm3_lpc17xx.ld | 73 ++++++++++++++++++++++++++++++ lib/lpc43xx/vector.c | 94 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 255 insertions(+) create mode 100644 lib/lpc43xx/Makefile create mode 100644 lib/lpc43xx/gpio.c create mode 100644 lib/lpc43xx/libopencm3_lpc17xx.ld create mode 100644 lib/lpc43xx/vector.c (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile new file mode 100644 index 0000000..c29f690 --- /dev/null +++ b/lib/lpc43xx/Makefile @@ -0,0 +1,58 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_lpc17xx + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \ + -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD +# ARFLAGS = rcsv +ARFLAGS = rcs +OBJS = gpio.o vector.o + +# VPATH += ../usb + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +endif + +all: $(LIBNAME).a + +$(LIBNAME).a: $(OBJS) + @printf " AR $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(AR) $(ARFLAGS) $@ $^ + +%.o: %.c + @printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + @printf " CLEAN lib/lpc17xx\n" + $(Q)rm -f *.o *.d + $(Q)rm -f $(LIBNAME).a + +.PHONY: clean + +-include $(OBJS:.o=.d) + diff --git a/lib/lpc43xx/gpio.c b/lib/lpc43xx/gpio.c new file mode 100644 index 0000000..6c44081 --- /dev/null +++ b/lib/lpc43xx/gpio.c @@ -0,0 +1,30 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void gpio_set(u32 gpioport, u32 gpios) +{ + GPIO_SET(gpioport) = gpios; +} + +void gpio_clear(u32 gpioport, u32 gpios) +{ + GPIO_CLR(gpioport) = gpios; +} diff --git a/lib/lpc43xx/libopencm3_lpc17xx.ld b/lib/lpc43xx/libopencm3_lpc17xx.ld new file mode 100644 index 0000000..30a2c0f --- /dev/null +++ b/lib/lpc43xx/libopencm3_lpc17xx.ld @@ -0,0 +1,73 @@ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Generic linker script for LPC13XX targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + *(.rodata*) /* Read-only data */ + _etext = .; + } >rom + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + _ebss = .; + } >ram AT >rom + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support - discard it for now. + */ + /DISCARD/ : { *(.ARM.exidx) } + + end = .; +} + +PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); + diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c new file mode 100644 index 0000000..016db7a --- /dev/null +++ b/lib/lpc43xx/vector.c @@ -0,0 +1,94 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by the linker script(s). */ +extern unsigned _etext, _data, _edata, _ebss, _stack; + +void main(void); +void reset_handler(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); + +/* TODO: Interrupt handler prototypes */ + +__attribute__ ((section(".vectors"))) +void (*const vector_table[]) (void) = { + (void*)&_stack, /* Addr: 0x0000_0000 */ + reset_handler, /* Addr: 0x0000_0004 */ + nmi_handler, /* Addr: 0x0000_0008 */ + hard_fault_handler, /* Addr: 0x0000_000C */ + mem_manage_handler, /* Addr: 0x0000_0010 */ + bus_fault_handler, /* Addr: 0x0000_0014 */ + usage_fault_handler, /* Addr: 0x0000_0018 */ + 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ + sv_call_handler, /* Addr: 0x0000_002C */ + debug_monitor_handler, /* Addr: 0x0000_0030 */ + 0, /* Reserved Addr: 0x0000_00034 */ + pend_sv_handler, /* Addr: 0x0000_0038 */ + sys_tick_handler, /* Addr: 0x0000_003C */ +}; + + +void reset_handler(void) +{ + volatile unsigned *src, *dest; + __asm__("MSR msp, %0" : : "r"(&_stack)); + + for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler +/* TODO: Interrupt handler weak aliases */ -- cgit v1.2.3 From 5e1bcaa5820ea3972e12319b4b5bd1ac09994f45 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 22 May 2012 13:55:50 -0600 Subject: gpio.c, vector.c updated for LPC43xx --- lib/lpc43xx/gpio.c | 2 +- lib/lpc43xx/vector.c | 181 ++++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 165 insertions(+), 18 deletions(-) (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/gpio.c b/lib/lpc43xx/gpio.c index 6c44081..9134f70 100644 --- a/lib/lpc43xx/gpio.c +++ b/lib/lpc43xx/gpio.c @@ -17,7 +17,7 @@ * along with this library. If not, see . */ -#include +#include void gpio_set(u32 gpioport, u32 gpios) { diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 016db7a..2d803a1 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -2,6 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -36,26 +37,126 @@ void WEAK sv_call_handler(void); void WEAK debug_monitor_handler(void); void WEAK pend_sv_handler(void); void WEAK sys_tick_handler(void); - -/* TODO: Interrupt handler prototypes */ +void WEAK dac_irqhandler(void) +void WEAK m0core_irqhandler(void) +void WEAK dma_irqhandler(void) +void WEAK ethernet_irqhandler(void) +void WEAK sdio_irqhandler(void) +void WEAK lcd_irqhandler(void) +void WEAK usb0_irqhandler(void) +void WEAK usb1_irqhandler(void) +void WEAK sct_irqhandler(void) +void WEAK ritimer_irqhandler(void) +void WEAK timer0_irqhandler(void) +void WEAK timer1_irqhandler(void) +void WEAK timer2_irqhandler(void) +void WEAK timer3_irqhandler(void) +void WEAK mcpwm_irqhandler(void) +void WEAK adc0_irqhandler(void) +void WEAK i2c0_irqhandler(void) +void WEAK i2c1_irqhandler(void) +void WEAK spi_irqhandler(void) +void WEAK adc1_irqhandler(void) +void WEAK ssp0_irqhandler(void) +void WEAK ssp1_irqhandler(void) +void WEAK usart0_irqhandler(void) +void WEAK uart1_irqhandler(void) +void WEAK usart2_irqhandler(void) +void WEAK usart3_irqhandler(void) +void WEAK i2s0_irqhandler(void) +void WEAK i2s1_irqhandler(void) +void WEAK spifi_irqhandler(void) +void WEAK sgpio_irqhandler(void) +void WEAK pin_int0_irqhandler(void) +void WEAK pin_int1_irqhandler(void) +void WEAK pin_int2_irqhandler(void) +void WEAK pin_int3_irqhandler(void) +void WEAK pin_int4_irqhandler(void) +void WEAK pin_int5_irqhandler(void) +void WEAK pin_int6_irqhandler(void) +void WEAK pin_int7_irqhandler(void) +void WEAK gint0_irqhandler(void) +void WEAK gint1_irqhandler(void) +void WEAK eventrouter_irqhandler(void) +void WEAK c_can1_irqhandler(void) +void WEAK atimer_irqhandler(void) +void WEAK rtc_irqhandler(void) +void WEAK wwdt_irqhandler(void) +void WEAK c_can0_irqhandler(void) +void WEAK qei_irqhandler(void) __attribute__ ((section(".vectors"))) void (*const vector_table[]) (void) = { - (void*)&_stack, /* Addr: 0x0000_0000 */ - reset_handler, /* Addr: 0x0000_0004 */ - nmi_handler, /* Addr: 0x0000_0008 */ - hard_fault_handler, /* Addr: 0x0000_000C */ - mem_manage_handler, /* Addr: 0x0000_0010 */ - bus_fault_handler, /* Addr: 0x0000_0014 */ - usage_fault_handler, /* Addr: 0x0000_0018 */ - 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ - sv_call_handler, /* Addr: 0x0000_002C */ - debug_monitor_handler, /* Addr: 0x0000_0030 */ - 0, /* Reserved Addr: 0x0000_00034 */ - pend_sv_handler, /* Addr: 0x0000_0038 */ - sys_tick_handler, /* Addr: 0x0000_003C */ -}; + /* Cortex-M4 interrupts */ + (void*)&_stack, + reset_handler, + nmi_handler, + hard_fault_handler, + mem_manage_handler, + bus_fault_handler, + usage_fault_handler, + 0, 0, 0, 0, /* reserved */ + sv_call_handler, + debug_monitor_handler, + 0, /* reserved */ + pend_sv_handler, + sys_tick_handler, + /* LPC43xx interrupts */ + dac_irqhandler, + m0core_irqhandler, + dma_irqhandler, + 0, /* reserved */ + 0, /* reserved */ + ethernet_irqhandler, + sdio_irqhandler, + lcd_irqhandler, + usb0_irqhandler, + usb1_irqhandler, + sct_irqhandler, + ritimer_irqhandler, + timer0_irqhandler, + timer1_irqhandler, + timer2_irqhandler, + timer3_irqhandler, + mcpwm_irqhandler, + adc0_irqhandler, + i2c0_irqhandler, + i2c1_irqhandler, + spi_irqhandler, + adc1_irqhandler, + ssp0_irqhandler, + ssp1_irqhandler, + usart0_irqhandler, + uart1_irqhandler, + usart2_irqhandler, + usart3_irqhandler, + i2s0_irqhandler, + i2s1_irqhandler, + spifi_irqhandler, + sgpio_irqhandler, + pin_int0_irqhandler, + pin_int1_irqhandler, + pin_int2_irqhandler, + pin_int3_irqhandler, + pin_int4_irqhandler, + pin_int5_irqhandler, + pin_int6_irqhandler, + pin_int7_irqhandler, + gint0_irqhandler, + gint1_irqhandler, + eventrouter_irqhandler, + c_can1_irqhandler, + 0, /* reserved */ + 0, /* reserved */ + atimer_irqhandler, + rtc_irqhandler, + 0, /* reserved */ + wwdt_irqhandler, + 0, /* reserved */ + c_can0_irqhandler, + qei_irqhandler, +}; void reset_handler(void) { @@ -91,4 +192,50 @@ void null_handler(void) #pragma weak debug_monitor_handler = null_handler #pragma weak pend_sv_handler = null_handler #pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#pragma weak dac_irqhandler = null_handler +#pragma weak m0core_irqhandler = null_handler +#pragma weak dma_irqhandler = null_handler +#pragma weak ethernet_irqhandler = null_handler +#pragma weak sdio_irqhandler = null_handler +#pragma weak lcd_irqhandler = null_handler +#pragma weak usb0_irqhandler = null_handler +#pragma weak usb1_irqhandler = null_handler +#pragma weak sct_irqhandler = null_handler +#pragma weak ritimer_irqhandler = null_handler +#pragma weak timer0_irqhandler = null_handler +#pragma weak timer1_irqhandler = null_handler +#pragma weak timer2_irqhandler = null_handler +#pragma weak timer3_irqhandler = null_handler +#pragma weak mcpwm_irqhandler = null_handler +#pragma weak adc0_irqhandler = null_handler +#pragma weak i2c0_irqhandler = null_handler +#pragma weak i2c1_irqhandler = null_handler +#pragma weak spi_irqhandler = null_handler +#pragma weak adc1_irqhandler = null_handler +#pragma weak ssp0_irqhandler = null_handler +#pragma weak ssp1_irqhandler = null_handler +#pragma weak usart0_irqhandler = null_handler +#pragma weak uart1_irqhandler = null_handler +#pragma weak usart2_irqhandler = null_handler +#pragma weak usart3_irqhandler = null_handler +#pragma weak i2s0_irqhandler = null_handler +#pragma weak i2s1_irqhandler = null_handler +#pragma weak spifi_irqhandler = null_handler +#pragma weak sgpio_irqhandler = null_handler +#pragma weak pin_int0_irqhandler = null_handler +#pragma weak pin_int1_irqhandler = null_handler +#pragma weak pin_int2_irqhandler = null_handler +#pragma weak pin_int3_irqhandler = null_handler +#pragma weak pin_int4_irqhandler = null_handler +#pragma weak pin_int5_irqhandler = null_handler +#pragma weak pin_int6_irqhandler = null_handler +#pragma weak pin_int7_irqhandler = null_handler +#pragma weak gint0_irqhandler = null_handler +#pragma weak gint1_irqhandler = null_handler +#pragma weak eventrouter_irqhandler = null_handler +#pragma weak c_can1_irqhandler = null_handler +#pragma weak atimer_irqhandler = null_handler +#pragma weak rtc_irqhandler = null_handler +#pragma weak wwdt_irqhandler = null_handler +#pragma weak c_can0_irqhandler = null_handler +#pragma weak qei_irqhandler = null_handler -- cgit v1.2.3 From ce14f4c0773008a726c8254a700cb57dd752306b Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 22 May 2012 14:15:20 -0600 Subject: updated linker script --- lib/lpc43xx/libopencm3_lpc17xx.ld | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/libopencm3_lpc17xx.ld b/lib/lpc43xx/libopencm3_lpc17xx.ld index 30a2c0f..5c3221b 100644 --- a/lib/lpc43xx/libopencm3_lpc17xx.ld +++ b/lib/lpc43xx/libopencm3_lpc17xx.ld @@ -1,8 +1,8 @@ - /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -18,7 +18,7 @@ * along with this library. If not, see . */ -/* Generic linker script for LPC13XX targets using libopencm3. */ +/* Generic linker script for LPC43XX targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ @@ -34,25 +34,43 @@ SECTIONS . = ORIGIN(rom); .text : { + . = ALIGN(0x400); *(.vectors) /* Vector table */ *(.text*) /* Program code */ + . = ALIGN(4); *(.rodata*) /* Read-only data */ - _etext = .; + . = ALIGN(4); } >rom + /* exception index - required due to libgcc.a issuing /0 exceptions */ + __exidx_start = .; + .ARM.exidx : { + *(.ARM.exidx*) + } > rom + __exidx_end = .; + + _etext = .; + . = ORIGIN(ram); .data : { _data = .; *(.data*) /* Read-write initialized data */ + . = ALIGN(4); _edata = .; } >ram AT >rom .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) + . = ALIGN(4); _ebss = .; - } >ram AT >rom + } >ram + + /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ + .ARM.extab : { + *(.ARM.extab*) + } >ram /* * The .eh_frame section appears to be used for C++ exception handling. @@ -67,7 +85,8 @@ SECTIONS /DISCARD/ : { *(.ARM.exidx) } end = .; -} - -PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); + /* Leave room above stack for IAP to run. */ + __StackTop = ORIGIN(ram) + LENGTH(ram) - 32; + PROVIDE(_stack = __StackTop); +} -- cgit v1.2.3 From 61e162e3d218f45f77121fd784b459a53803dc3a Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 22 May 2012 14:20:39 -0600 Subject: Makefile updates --- lib/lpc43xx/Makefile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index c29f690..4b8eae4 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -2,6 +2,7 @@ ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2012 Michael Ossmann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by @@ -17,15 +18,16 @@ ## along with this library. If not, see . ## -LIBNAME = libopencm3_lpc17xx +LIBNAME = libopencm3_lpc43xx PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \ - -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD + -mcpu=cortex-m4 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD \ + -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs OBJS = gpio.o vector.o -- cgit v1.2.3 From 3a9d48923a9417e9e34cad2fe546dc6e7c2b5553 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 22 May 2012 14:21:11 -0600 Subject: semicolons might help --- lib/lpc43xx/vector.c | 94 ++++++++++++++++++++++++++-------------------------- 1 file changed, 47 insertions(+), 47 deletions(-) (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 2d803a1..33eee4a 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -37,53 +37,53 @@ void WEAK sv_call_handler(void); void WEAK debug_monitor_handler(void); void WEAK pend_sv_handler(void); void WEAK sys_tick_handler(void); -void WEAK dac_irqhandler(void) -void WEAK m0core_irqhandler(void) -void WEAK dma_irqhandler(void) -void WEAK ethernet_irqhandler(void) -void WEAK sdio_irqhandler(void) -void WEAK lcd_irqhandler(void) -void WEAK usb0_irqhandler(void) -void WEAK usb1_irqhandler(void) -void WEAK sct_irqhandler(void) -void WEAK ritimer_irqhandler(void) -void WEAK timer0_irqhandler(void) -void WEAK timer1_irqhandler(void) -void WEAK timer2_irqhandler(void) -void WEAK timer3_irqhandler(void) -void WEAK mcpwm_irqhandler(void) -void WEAK adc0_irqhandler(void) -void WEAK i2c0_irqhandler(void) -void WEAK i2c1_irqhandler(void) -void WEAK spi_irqhandler(void) -void WEAK adc1_irqhandler(void) -void WEAK ssp0_irqhandler(void) -void WEAK ssp1_irqhandler(void) -void WEAK usart0_irqhandler(void) -void WEAK uart1_irqhandler(void) -void WEAK usart2_irqhandler(void) -void WEAK usart3_irqhandler(void) -void WEAK i2s0_irqhandler(void) -void WEAK i2s1_irqhandler(void) -void WEAK spifi_irqhandler(void) -void WEAK sgpio_irqhandler(void) -void WEAK pin_int0_irqhandler(void) -void WEAK pin_int1_irqhandler(void) -void WEAK pin_int2_irqhandler(void) -void WEAK pin_int3_irqhandler(void) -void WEAK pin_int4_irqhandler(void) -void WEAK pin_int5_irqhandler(void) -void WEAK pin_int6_irqhandler(void) -void WEAK pin_int7_irqhandler(void) -void WEAK gint0_irqhandler(void) -void WEAK gint1_irqhandler(void) -void WEAK eventrouter_irqhandler(void) -void WEAK c_can1_irqhandler(void) -void WEAK atimer_irqhandler(void) -void WEAK rtc_irqhandler(void) -void WEAK wwdt_irqhandler(void) -void WEAK c_can0_irqhandler(void) -void WEAK qei_irqhandler(void) +void WEAK dac_irqhandler(void); +void WEAK m0core_irqhandler(void); +void WEAK dma_irqhandler(void); +void WEAK ethernet_irqhandler(void); +void WEAK sdio_irqhandler(void); +void WEAK lcd_irqhandler(void); +void WEAK usb0_irqhandler(void); +void WEAK usb1_irqhandler(void); +void WEAK sct_irqhandler(void); +void WEAK ritimer_irqhandler(void); +void WEAK timer0_irqhandler(void); +void WEAK timer1_irqhandler(void); +void WEAK timer2_irqhandler(void); +void WEAK timer3_irqhandler(void); +void WEAK mcpwm_irqhandler(void); +void WEAK adc0_irqhandler(void); +void WEAK i2c0_irqhandler(void); +void WEAK i2c1_irqhandler(void); +void WEAK spi_irqhandler(void); +void WEAK adc1_irqhandler(void); +void WEAK ssp0_irqhandler(void); +void WEAK ssp1_irqhandler(void); +void WEAK usart0_irqhandler(void); +void WEAK uart1_irqhandler(void); +void WEAK usart2_irqhandler(void); +void WEAK usart3_irqhandler(void); +void WEAK i2s0_irqhandler(void); +void WEAK i2s1_irqhandler(void); +void WEAK spifi_irqhandler(void); +void WEAK sgpio_irqhandler(void); +void WEAK pin_int0_irqhandler(void); +void WEAK pin_int1_irqhandler(void); +void WEAK pin_int2_irqhandler(void); +void WEAK pin_int3_irqhandler(void); +void WEAK pin_int4_irqhandler(void); +void WEAK pin_int5_irqhandler(void); +void WEAK pin_int6_irqhandler(void); +void WEAK pin_int7_irqhandler(void); +void WEAK gint0_irqhandler(void); +void WEAK gint1_irqhandler(void); +void WEAK eventrouter_irqhandler(void); +void WEAK c_can1_irqhandler(void); +void WEAK atimer_irqhandler(void); +void WEAK rtc_irqhandler(void); +void WEAK wwdt_irqhandler(void); +void WEAK c_can0_irqhandler(void); +void WEAK qei_irqhandler(void); __attribute__ ((section(".vectors"))) void (*const vector_table[]) (void) = { -- cgit v1.2.3 From 4c37af55f455e3c404aff8acf45b3544156076a1 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 22 May 2012 14:46:05 -0600 Subject: renamed linker script --- lib/lpc43xx/libopencm3_lpc43xx.ld | 92 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 lib/lpc43xx/libopencm3_lpc43xx.ld (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld new file mode 100644 index 0000000..5c3221b --- /dev/null +++ b/lib/lpc43xx/libopencm3_lpc43xx.ld @@ -0,0 +1,92 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Generic linker script for LPC43XX targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + . = ALIGN(0x400); + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + } >rom + + /* exception index - required due to libgcc.a issuing /0 exceptions */ + __exidx_start = .; + .ARM.exidx : { + *(.ARM.exidx*) + } > rom + __exidx_end = .; + + _etext = .; + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + . = ALIGN(4); + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram + + /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ + .ARM.extab : { + *(.ARM.extab*) + } >ram + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support - discard it for now. + */ + /DISCARD/ : { *(.ARM.exidx) } + + end = .; + + /* Leave room above stack for IAP to run. */ + __StackTop = ORIGIN(ram) + LENGTH(ram) - 32; + PROVIDE(_stack = __StackTop); +} -- cgit v1.2.3 From 27b1597c1aaf8869472c90a2935dd8cdbfe85c79 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Sun, 27 May 2012 20:33:18 -0600 Subject: rm renamed file --- lib/lpc43xx/libopencm3_lpc43xx.ld | 92 --------------------------------------- 1 file changed, 92 deletions(-) delete mode 100644 lib/lpc43xx/libopencm3_lpc43xx.ld (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld deleted file mode 100644 index 5c3221b..0000000 --- a/lib/lpc43xx/libopencm3_lpc43xx.ld +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* Generic linker script for LPC43XX targets using libopencm3. */ - -/* Memory regions must be defined in the ld script which includes this one. */ - -/* Enforce emmition of the vector table. */ -EXTERN (vector_table) - -/* Define the entry point of the output file. */ -ENTRY(reset_handler) - -/* Define sections. */ -SECTIONS -{ - . = ORIGIN(rom); - - .text : { - . = ALIGN(0x400); - *(.vectors) /* Vector table */ - *(.text*) /* Program code */ - . = ALIGN(4); - *(.rodata*) /* Read-only data */ - . = ALIGN(4); - } >rom - - /* exception index - required due to libgcc.a issuing /0 exceptions */ - __exidx_start = .; - .ARM.exidx : { - *(.ARM.exidx*) - } > rom - __exidx_end = .; - - _etext = .; - - . = ORIGIN(ram); - - .data : { - _data = .; - *(.data*) /* Read-write initialized data */ - . = ALIGN(4); - _edata = .; - } >ram AT >rom - - .bss : { - *(.bss*) /* Read-write zero initialized data */ - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >ram - - /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ - .ARM.extab : { - *(.ARM.extab*) - } >ram - - /* - * The .eh_frame section appears to be used for C++ exception handling. - * You may need to fix this if you're using C++. - */ - /DISCARD/ : { *(.eh_frame) } - - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - discard it for now. - */ - /DISCARD/ : { *(.ARM.exidx) } - - end = .; - - /* Leave room above stack for IAP to run. */ - __StackTop = ORIGIN(ram) + LENGTH(ram) - 32; - PROVIDE(_stack = __StackTop); -} -- cgit v1.2.3 From 82181c2cdac29b11c2fd3c985320ded2877c902e Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Sun, 27 May 2012 23:02:18 -0600 Subject: trying to rm again --- lib/lpc43xx/libopencm3_lpc17xx.ld | 92 --------------------------------------- 1 file changed, 92 deletions(-) delete mode 100644 lib/lpc43xx/libopencm3_lpc17xx.ld (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/libopencm3_lpc17xx.ld b/lib/lpc43xx/libopencm3_lpc17xx.ld deleted file mode 100644 index 5c3221b..0000000 --- a/lib/lpc43xx/libopencm3_lpc17xx.ld +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* Generic linker script for LPC43XX targets using libopencm3. */ - -/* Memory regions must be defined in the ld script which includes this one. */ - -/* Enforce emmition of the vector table. */ -EXTERN (vector_table) - -/* Define the entry point of the output file. */ -ENTRY(reset_handler) - -/* Define sections. */ -SECTIONS -{ - . = ORIGIN(rom); - - .text : { - . = ALIGN(0x400); - *(.vectors) /* Vector table */ - *(.text*) /* Program code */ - . = ALIGN(4); - *(.rodata*) /* Read-only data */ - . = ALIGN(4); - } >rom - - /* exception index - required due to libgcc.a issuing /0 exceptions */ - __exidx_start = .; - .ARM.exidx : { - *(.ARM.exidx*) - } > rom - __exidx_end = .; - - _etext = .; - - . = ORIGIN(ram); - - .data : { - _data = .; - *(.data*) /* Read-write initialized data */ - . = ALIGN(4); - _edata = .; - } >ram AT >rom - - .bss : { - *(.bss*) /* Read-write zero initialized data */ - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >ram - - /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ - .ARM.extab : { - *(.ARM.extab*) - } >ram - - /* - * The .eh_frame section appears to be used for C++ exception handling. - * You may need to fix this if you're using C++. - */ - /DISCARD/ : { *(.eh_frame) } - - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - discard it for now. - */ - /DISCARD/ : { *(.ARM.exidx) } - - end = .; - - /* Leave room above stack for IAP to run. */ - __StackTop = ORIGIN(ram) + LENGTH(ram) - 32; - PROVIDE(_stack = __StackTop); -} -- cgit v1.2.3 From 38abe9f01f185cb0451b0d60b6b246718c0b49c3 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Sun, 27 May 2012 23:07:13 -0600 Subject: replaced linker script I accidentally deleted --- lib/lpc43xx/libopencm3_lpc43xx.ld | 92 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 lib/lpc43xx/libopencm3_lpc43xx.ld (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld new file mode 100644 index 0000000..5c3221b --- /dev/null +++ b/lib/lpc43xx/libopencm3_lpc43xx.ld @@ -0,0 +1,92 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Generic linker script for LPC43XX targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + . = ALIGN(0x400); + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + } >rom + + /* exception index - required due to libgcc.a issuing /0 exceptions */ + __exidx_start = .; + .ARM.exidx : { + *(.ARM.exidx*) + } > rom + __exidx_end = .; + + _etext = .; + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + . = ALIGN(4); + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram + + /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ + .ARM.extab : { + *(.ARM.extab*) + } >ram + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support - discard it for now. + */ + /DISCARD/ : { *(.ARM.exidx) } + + end = .; + + /* Leave room above stack for IAP to run. */ + __StackTop = ORIGIN(ram) + LENGTH(ram) - 32; + PROVIDE(_stack = __StackTop); +} -- cgit v1.2.3 From e7fbc2220b23b1d50fc0285c260a8787694328fe Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Sat, 2 Jun 2012 09:45:03 +0200 Subject: Added JellyBean Configuration for PinMux, GPIO In/Out (work in progress). Added scu driver file scu.c. Modified Makefile/Makefile.include to generate .map file and use -O2 as optimization. Modified hackrf-jellybean miniblink.c to enable 1V8 and blink LED1,2&3 with configuration of PinMux and GPIO. --- examples/lpc43xx/Makefile.include | 5 +- examples/lpc43xx/hackrf-jellybean/jellybean_conf.h | 80 +++++ .../lpc43xx/hackrf-jellybean/miniblink/miniblink.c | 54 +++- include/libopencm3/cm3/common.h | 34 +++ include/libopencm3/lpc43xx/scu.h | 323 ++++++++++++++++++++- lib/lpc43xx/Makefile | 5 +- lib/lpc43xx/scu.c | 30 ++ 7 files changed, 516 insertions(+), 15 deletions(-) create mode 100644 examples/lpc43xx/hackrf-jellybean/jellybean_conf.h create mode 100644 lib/lpc43xx/scu.c (limited to 'lib/lpc43xx') diff --git a/examples/lpc43xx/Makefile.include b/examples/lpc43xx/Makefile.include index 6b0b8b9..89e356d 100644 --- a/examples/lpc43xx/Makefile.include +++ b/examples/lpc43xx/Makefile.include @@ -4,6 +4,7 @@ ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2010 Piotr Esden-Tempski ## Copyright (C) 2012 Michael Ossmann +## Copyright (C) 2012 Benjamin Vernoux ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by @@ -29,12 +30,12 @@ GDB = $(PREFIX)-gdb # Uncomment this line if you want to use the installed (not local) library. # TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) TOOLCHAIN_DIR = ../../../.. -CFLAGS += -O0 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ +CFLAGS += -O2 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m4 -mthumb -MD \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 LDSCRIPT ?= $(BINARY).ld LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/lpc43xx \ - -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections + -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections -Xlinker -Map=$(BINARY).map OBJS += $(BINARY).o OOCD ?= openocd diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h b/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h new file mode 100644 index 0000000..a5ad8d0 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h @@ -0,0 +1,80 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef __JELLYBEAN_CONF_H +#define __JELLYBEAN_CONF_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/************************/ +/* JellyBean SCU PinMux */ +/************************/ + +/* GPIO Output PinMux */ +#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */ +#define SCU_PINMUX_LED2 (P4_2) /* GPIO2[2] on P4_2 */ +#define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */ + +#define SCU_PINMUX_EN1V8 (P6_10) /* GPIO3[6] on P6_10 */ + +/* GPIO Input PinMux */ +#define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */ +#define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */ +#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */ +#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */ + +/* TODO add other Pins */ + +/**********************/ +/* JellyBean GPIO Pin */ +/**********************/ + +/* GPIO Output */ +#define PIN_LED1 (BIT1) /* GPIO2[1] on P4_1 */ +#define PIN_LED2 (BIT2) /* GPIO2[2] on P4_2 */ +#define PIN_LED3 (BIT8) /* GPIO2[8] on P6_12 */ +#define PORT_LED1_3 (GPIO2) /* PORT for LED1, 2 & 3 */ + +#define PIN_EN1V8 (BIT6) /* GPIO3[6] on P6_10 */ +#define PORT_EN1V8 (GPIO3) + +/* GPIO Input */ +#define PIN_BOOT0 (BIT8) /* GPIO0[8] on P1_1 */ +#define PIN_BOOT1 (BIT9) /* GPIO0[9] on P1_2 */ +#define PIN_BOOT2 (BIT7) /* GPIO5[7] on P2_8 */ +#define PIN_BOOT3 (BIT10) /* GPIO1[10] on P2_9 */ + +/* Read GPIO Pin */ +#define BOOT0_STATE ( (GPIO0_PIN & PIN_BOOT0)==PIN_BOOT0 ) +#define BOOT1_STATE ( (GPIO0_PIN & PIN_BOOT1)==PIN_BOOT1 ) +#define BOOT2_STATE ( (GPIO5_PIN & PIN_BOOT2)==PIN_BOOT2 ) +#define BOOT3_STATE ( (GPIO1_PIN & PIN_BOOT3)==PIN_BOOT3 ) + +/* TODO add other Pins */ + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c index 6d8a9bc..567d9dc 100644 --- a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c +++ b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c @@ -19,26 +19,62 @@ */ #include +#include + +#include "../jellybean_conf.h" void gpio_setup(void) { - GPIO2_DIR |= (1 << 1); /* Configure GPIO2[1] (P4_1) as output. */ + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ } +u32 boot0, boot1, boot2, boot3; + int main(void) { int i; - gpio_setup(); - /* Blink LED1 on the board. */ - while (1) { - - gpio_set(GPIO2, GPIOPIN1); /* LED on */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ + /* Set 1V8 */ + gpio_set(PORT_EN1V8, PIN_EN1V8); + + /* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */ + while (1) + { + boot0 = BOOT0_STATE; + boot1 = BOOT1_STATE; + boot2 = BOOT2_STATE; + boot3 = BOOT3_STATE; + + gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ __asm__("nop"); - gpio_clear(GPIO2, GPIOPIN1); /* LED off */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ + gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ __asm__("nop"); } diff --git a/include/libopencm3/cm3/common.h b/include/libopencm3/cm3/common.h index dc3e433..7947017 100644 --- a/include/libopencm3/cm3/common.h +++ b/include/libopencm3/cm3/common.h @@ -38,6 +38,40 @@ typedef uint64_t u64; #define MMIO32(addr) (*(volatile u32 *)(addr)) #define MMIO64(addr) (*(volatile u64 *)(addr)) +/* Generic bit definition */ +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + /* Main page for the doxygen-generated documentation: */ /** diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index 83688e2..146aafc 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -288,7 +288,6 @@ #define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) #define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) - /* ADC pin select registers */ /* ADC0 function select register */ @@ -311,6 +310,326 @@ #define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) /* Pin interrupt select register for pin interrupts 4 to 7 */ -#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE00) +#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) + +/* +SCU PIN Normal Drive: +The pin configuration registers for normal-drive pins control the following pins: +- P0_0 and P0_1 +- P1_0 to P1_16 and P1_18 to P1_20 +- P2_0 to P2_2 and P2_6 to P2_13 +- P3_0 to P3_2 and P3_4 to P3_8 +- P4_0 to P4_10 +- P5_0 to P5_7 +- P6_0 to P6_12 +- P7_0 to P7_7 +- P8_3 to P8_8 +- P9_0 to P9_6 +- PA_0 and PA_4 +- PB_0 to PB_6 +- PC_0 to PC_14 +- PE_0 to PE_15 +- PF_0 to PF_11 + +Pin configuration registers for High-Drive pins. +The pin configuration registers for high-drive pins control the following pins: +• P1_17 +• P2_3 to P2_5 +• P8_0 to P8_2 +• PA_1 to PA_3 + +Pin configuration registers for High-Speed pins. +This register controls the following pins: +P3_3 and pins CLK0 to CLK3. +*/ +typedef enum { + /* Group Port 0 */ + P0_0 = (PIN_GROUP0+PIN0), + P0_1 = (PIN_GROUP0+PIN1), + + /* Group Port 1 */ + P1_0 = (PIN_GROUP1+PIN0), + P1_1 = (PIN_GROUP1+PIN1), + P1_2 = (PIN_GROUP1+PIN2), + P1_3 = (PIN_GROUP1+PIN3), + P1_4 = (PIN_GROUP1+PIN4), + P1_5 = (PIN_GROUP1+PIN5), + P1_6 = (PIN_GROUP1+PIN6), + P1_7 = (PIN_GROUP1+PIN7), + P1_8 = (PIN_GROUP1+PIN8), + P1_9 = (PIN_GROUP1+PIN9), + P1_10 = (PIN_GROUP1+PIN10), + P1_11 = (PIN_GROUP1+PIN11), + P1_12 = (PIN_GROUP1+PIN12), + P1_13 = (PIN_GROUP1+PIN13), + P1_14 = (PIN_GROUP1+PIN14), + P1_15 = (PIN_GROUP1+PIN15), + P1_16 = (PIN_GROUP1+PIN16), + + /* P1_17 is High-Drive pin */ + P1_17 = (PIN_GROUP1+PIN17), + + P1_18 = (PIN_GROUP1+PIN18), + P1_19 = (PIN_GROUP1+PIN19), + P1_20 = (PIN_GROUP1+PIN20), + + /* Group Port 2 */ + P2_0 = (PIN_GROUP2+PIN0), + P2_1 = (PIN_GROUP2+PIN1), + P2_2 = (PIN_GROUP2+PIN2), + + /* P2_3 to P2_5 are High-Drive pins */ + P2_3 = (PIN_GROUP2+PIN3), + P2_4 = (PIN_GROUP2+PIN4), + P2_5 = (PIN_GROUP2+PIN5), + + P2_6 = (PIN_GROUP2+PIN6), + P2_7 = (PIN_GROUP2+PIN7), + P2_8 = (PIN_GROUP2+PIN8), + P2_9 = (PIN_GROUP2+PIN9), + P2_10 = (PIN_GROUP2+PIN10), + P2_11 = (PIN_GROUP2+PIN11), + P2_12 = (PIN_GROUP2+PIN12), + P2_13 = (PIN_GROUP2+PIN13), + + /* Group Port 3 */ + P3_0 = (PIN_GROUP3+PIN0), + P3_1 = (PIN_GROUP3+PIN1), + P3_2 = (PIN_GROUP3+PIN2), + + /* P3_3 is High-Speed pin */ + P3_3 = (PIN_GROUP3+PIN3), + + P3_4 = (PIN_GROUP3+PIN4), + P3_5 = (PIN_GROUP3+PIN5), + P3_6 = (PIN_GROUP3+PIN6), + P3_7 = (PIN_GROUP3+PIN7), + P3_8 = (PIN_GROUP3+PIN8), + + /* Group Port 4 */ + P4_0 = (PIN_GROUP4+PIN0), + P4_1 = (PIN_GROUP4+PIN1), + P4_2 = (PIN_GROUP4+PIN2), + P4_3 = (PIN_GROUP4+PIN3), + P4_4 = (PIN_GROUP4+PIN4), + P4_5 = (PIN_GROUP4+PIN5), + P4_6 = (PIN_GROUP4+PIN6), + P4_7 = (PIN_GROUP4+PIN7), + P4_8 = (PIN_GROUP4+PIN8), + P4_9 = (PIN_GROUP4+PIN9), + P4_10 = (PIN_GROUP4+PIN10), + + /* Group Port 5 */ + P5_0 = (PIN_GROUP5+PIN0), + P5_1 = (PIN_GROUP5+PIN1), + P5_2 = (PIN_GROUP5+PIN2), + P5_3 = (PIN_GROUP5+PIN3), + P5_4 = (PIN_GROUP5+PIN4), + P5_5 = (PIN_GROUP5+PIN5), + P5_6 = (PIN_GROUP5+PIN6), + P5_7 = (PIN_GROUP5+PIN7), + + /* Group Port 6 */ + P6_0 = (PIN_GROUP6+PIN0), + P6_1 = (PIN_GROUP6+PIN1), + P6_2 = (PIN_GROUP6+PIN2), + P6_3 = (PIN_GROUP6+PIN3), + P6_4 = (PIN_GROUP6+PIN4), + P6_5 = (PIN_GROUP6+PIN5), + P6_6 = (PIN_GROUP6+PIN6), + P6_7 = (PIN_GROUP6+PIN7), + P6_8 = (PIN_GROUP6+PIN8), + P6_9 = (PIN_GROUP6+PIN9), + P6_10 = (PIN_GROUP6+PIN10), + P6_11 = (PIN_GROUP6+PIN11), + P6_12 = (PIN_GROUP6+PIN12), + + /* Group Port 7 */ + P7_0 = (PIN_GROUP7+PIN0), + P7_1 = (PIN_GROUP7+PIN1), + P7_2 = (PIN_GROUP7+PIN2), + P7_3 = (PIN_GROUP7+PIN3), + P7_4 = (PIN_GROUP7+PIN4), + P7_5 = (PIN_GROUP7+PIN5), + P7_6 = (PIN_GROUP7+PIN6), + P7_7 = (PIN_GROUP7+PIN7), + + /* Group Port 8 */ + /* P8_0 to P8_2 are High-Drive pins */ + P8_0 = (PIN_GROUP8+PIN0), + P8_1 = (PIN_GROUP8+PIN1), + P8_2 = (PIN_GROUP8+PIN2), + + P8_3 = (PIN_GROUP8+PIN3), + P8_4 = (PIN_GROUP8+PIN4), + P8_5 = (PIN_GROUP8+PIN5), + P8_6 = (PIN_GROUP8+PIN6), + P8_7 = (PIN_GROUP8+PIN7), + P8_8 = (PIN_GROUP8+PIN8), + + /* Group Port 9 */ + P9_0 = (PIN_GROUP9+PIN0), + P9_1 = (PIN_GROUP9+PIN1), + P9_2 = (PIN_GROUP9+PIN2), + P9_3 = (PIN_GROUP9+PIN3), + P9_4 = (PIN_GROUP9+PIN4), + P9_5 = (PIN_GROUP9+PIN5), + P9_6 = (PIN_GROUP9+PIN6), + + /* Group Port A */ + PA_0 = (PIN_GROUPA+PIN0), + /* PA_1 to PA_3 are Normal & High-Drive Pins */ + PA_1 = (PIN_GROUPA+PIN1), + PA_2 = (PIN_GROUPA+PIN2), + PA_3 = (PIN_GROUPA+PIN3), + PA_4 = (PIN_GROUPA+PIN4), + + /* Group Port B */ + PB_0 = (PIN_GROUPB+PIN0), + PB_1 = (PIN_GROUPB+PIN1), + PB_2 = (PIN_GROUPB+PIN2), + PB_3 = (PIN_GROUPB+PIN3), + PB_4 = (PIN_GROUPB+PIN4), + PB_5 = (PIN_GROUPB+PIN5), + PB_6 = (PIN_GROUPB+PIN6), + + /* Group Port C */ + PC_0 = (PIN_GROUPC+PIN0), + PC_1 = (PIN_GROUPC+PIN1), + PC_2 = (PIN_GROUPC+PIN2), + PC_3 = (PIN_GROUPC+PIN3), + PC_4 = (PIN_GROUPC+PIN4), + PC_5 = (PIN_GROUPC+PIN5), + PC_6 = (PIN_GROUPC+PIN6), + PC_7 = (PIN_GROUPC+PIN7), + PC_8 = (PIN_GROUPC+PIN8), + PC_9 = (PIN_GROUPC+PIN9), + PC_10 = (PIN_GROUPC+PIN10), + PC_11 = (PIN_GROUPC+PIN11), + PC_12 = (PIN_GROUPC+PIN12), + PC_13 = (PIN_GROUPC+PIN13), + PC_14 = (PIN_GROUPC+PIN14), + + /* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */ + PD_0 = (PIN_GROUPD+PIN0), + PD_1 = (PIN_GROUPD+PIN1), + PD_2 = (PIN_GROUPD+PIN2), + PD_3 = (PIN_GROUPD+PIN3), + PD_4 = (PIN_GROUPD+PIN4), + PD_5 = (PIN_GROUPD+PIN5), + PD_6 = (PIN_GROUPD+PIN6), + PD_7 = (PIN_GROUPD+PIN7), + PD_8 = (PIN_GROUPD+PIN8), + PD_9 = (PIN_GROUPD+PIN9), + PD_10 = (PIN_GROUPD+PIN10), + PD_11 = (PIN_GROUPD+PIN11), + PD_12 = (PIN_GROUPD+PIN12), + PD_13 = (PIN_GROUPD+PIN13), + PD_14 = (PIN_GROUPD+PIN14), + PD_15 = (PIN_GROUPD+PIN15), + PD_16 = (PIN_GROUPD+PIN16), + + /* Group Port E */ + PE_0 = (PIN_GROUPE+PIN0), + PE_1 = (PIN_GROUPE+PIN1), + PE_2 = (PIN_GROUPE+PIN2), + PE_3 = (PIN_GROUPE+PIN3), + PE_4 = (PIN_GROUPE+PIN4), + PE_5 = (PIN_GROUPE+PIN5), + PE_6 = (PIN_GROUPE+PIN6), + PE_7 = (PIN_GROUPE+PIN7), + PE_8 = (PIN_GROUPE+PIN8), + PE_9 = (PIN_GROUPE+PIN9), + PE_10 = (PIN_GROUPE+PIN10), + PE_11 = (PIN_GROUPE+PIN11), + PE_12 = (PIN_GROUPE+PIN12), + PE_13 = (PIN_GROUPE+PIN13), + PE_14 = (PIN_GROUPE+PIN14), + PE_15 = (PIN_GROUPE+PIN15), + + /* Group Port F */ + PF_0 = (PIN_GROUPF+PIN0), + PF_1 = (PIN_GROUPF+PIN1), + PF_2 = (PIN_GROUPF+PIN2), + PF_3 = (PIN_GROUPF+PIN3), + PF_4 = (PIN_GROUPF+PIN4), + PF_5 = (PIN_GROUPF+PIN5), + PF_6 = (PIN_GROUPF+PIN6), + PF_7 = (PIN_GROUPF+PIN7), + PF_8 = (PIN_GROUPF+PIN8), + PF_9 = (PIN_GROUPF+PIN9), + PF_10 = (PIN_GROUPF+PIN10), + PF_11 = (PIN_GROUPF+PIN11), + + /* Group Clock 0 to 3 High-Speed pins */ + CLK0 = (SCU_BASE + 0xC00), + CLK1 = (SCU_BASE + 0xC04), + CLK2 = (SCU_BASE + 0xC08), + CLK3 = (SCU_BASE + 0xC0C) + +} scu_grp_pin_t; + +/******************************************************************/ +/* Pin Configuration to be used for scu_pinmux() parameter scu_conf + For normal-drive pins, high-drive pins, high-speed pins */ +/******************************************************************/ +/* Function BIT0 to 2. +Common to normal-drive pins, high-drive pins, high-speed pins. */ +#define SCU_CONF_FUNCTION0 (0x0) +#define SCU_CONF_FUNCTION1 (0x1) +#define SCU_CONF_FUNCTION2 (0x2) +#define SCU_CONF_FUNCTION3 (0x3) +#define SCU_CONF_FUNCTION4 (0x4) +#define SCU_CONF_FUNCTION5 (0x5) +#define SCU_CONF_FUNCTION6 (0x6) +#define SCU_CONF_FUNCTION7 (0x7) + +/* Enable pull-down resistor at pad +By default=0 Disable pull-down. +Available to normal-drive pins, high-drive pins, high-speed pins */ +#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) + +/* Disable pull-up resistor at pad. +By default=0 the pull-up resistor is enabled at reset. +Available to normal-drive pins, high-drive pins, high-speed pins */ +#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) + +/* Select Slew Rate. +By Default=0 Slow. +Available to normal-drive pins and high-speed pins, reserved for high-drive pins. */ +#define SCU_CONF_EHS_FAST (BIT5) + +/* Input buffer enable. +By Default=0 Disable Input Buffer. +The input buffer is disabled by default at reset and must be enabled +for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins). +Available to normal-drive pins, high-drive pins, high-speed pins */ +#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) + +/* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. +Available to normal-drive pins, high-drive pins, high-speed pins */ +#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) + +/* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9) +Available to high-drive pins, reserved for others. */ +#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) +#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) +#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) + +/* BIT10 to 31 are Reserved */ + +/* Configuration for different I/O pins types */ +#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) + +void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf); #endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 4b8eae4..dd6f1cd 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -3,6 +3,7 @@ ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 Michael Ossmann +## Copyright (C) 2012 Benjamin Vernoux ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by @@ -24,13 +25,13 @@ PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar -CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \ +CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mcpu=cortex-m4 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o +OBJS = gpio.o vector.o scu.o # VPATH += ../usb diff --git a/lib/lpc43xx/scu.c b/lib/lpc43xx/scu.c new file mode 100644 index 0000000..bc495cd --- /dev/null +++ b/lib/lpc43xx/scu.c @@ -0,0 +1,30 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */ +void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf) +{ + MMIO32(group_pin) = scu_conf; +} + +/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */ + +/* For Pin interrupt select register see scu.h SCU_PINTSEL0 & SCU_PINTSEL1 */ -- cgit v1.2.3 From 686c0cf0502fe8e72aaa69206a67ff13eec94b96 Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Mon, 4 Jun 2012 19:13:53 +0200 Subject: Minor fix --- lib/lpc43xx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index dd6f1cd..041e3bc 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -51,7 +51,7 @@ $(LIBNAME).a: $(OBJS) $(Q)$(CC) $(CFLAGS) -o $@ -c $< clean: - @printf " CLEAN lib/lpc17xx\n" + @printf " CLEAN lib/lpc43xx\n" $(Q)rm -f *.o *.d $(Q)rm -f $(LIBNAME).a -- cgit v1.2.3 From 569801687744d5f4f4157ea186a8a6c1d159d285 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Mon, 4 Jun 2012 17:30:08 -0600 Subject: moved stuff out of i2cdemo.c and into drivers/headers --- examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c | 113 ------------------------ include/libopencm3/lpc43xx/cgu.h | 23 +++++ include/libopencm3/lpc43xx/i2c.h | 29 +++++- lib/lpc43xx/Makefile | 2 +- 4 files changed, 52 insertions(+), 115 deletions(-) (limited to 'lib/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c index 7198bb3..102365b 100644 --- a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c @@ -19,8 +19,6 @@ */ #include -#include -#include #include #include "../jellybean_conf.h" @@ -39,9 +37,6 @@ void gpio_setup(void) scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); - /* Configure SCU I2C0 Peripheral */ - SCU_SFSI2C0 = SCU_I2C0_NOMINAL; - /* Configure all GPIO as Input (safe state) */ GPIO0_DIR = 0; GPIO1_DIR = 0; @@ -57,115 +52,7 @@ void gpio_setup(void) GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ } -//FIXME generalize and move to drivers - -#define SCU_SFSI2C0_SCL_EFP (1 << 1) /* 3 ns glitch filter */ -#define SCU_SFSI2C0_SCL_EHD (1 << 2) /* Fast-mode Plus transmit */ -#define SCU_SFSI2C0_SCL_EZI (1 << 3) /* Enable the input receiver */ -#define SCU_SFSI2C0_SCL_ZIF (1 << 7) /* Disable input glitch filter */ -#define SCU_SFSI2C0_SDA_EFP (1 << 8) /* 3 ns glitch filter */ -#define SCU_SFSI2C0_SDA_EHD (1 << 10) /* Fast-mode Plus transmit */ -#define SCU_SFSI2C0_SDA_EZI (1 << 11) /* Enable the input receiver */ -#define SCU_SFSI2C0_SDA_ZIF (1 << 15) /* Disable input glitch filter */ - -#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ -#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ -#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ -#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ - -#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ -#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ -#define I2C_CONSET_STO (1 << 4) /* STOP flag */ -#define I2C_CONSET_STA (1 << 5) /* START flag */ -#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ - -#define CGU_SRC_32K 0x00 -#define CGU_SRC_IRC 0x01 -#define CGU_SRC_ENET_RX 0x02 -#define CGU_SRC_ENET_TX 0x03 -#define CGU_SRC_GP_CLKIN 0x04 -#define CGU_SRC_XTAL 0x06 -#define CGU_SRC_PLL0USB 0x07 -#define CGU_SRC_PLL0AUDIO 0x08 -#define CGU_SRC_PLL1 0x09 -#define CGU_SRC_IDIVA 0x0C -#define CGU_SRC_IDIVB 0x0D -#define CGU_SRC_IDIVC 0x0E -#define CGU_SRC_IDIVD 0x0F -#define CGU_SRC_IDIVE 0x10 - -#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */ -#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */ -#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ - -void i2c0_init() -{ - /* enable input on SCL and SDA pins */ - SCU_SFSI2C0 = (SCU_SFSI2C0_SCL_EZI | SCU_SFSI2C0_SDA_EZI); - - /* use PLL1 as clock source for APB1 (including I2C0) */ - CGU_BASE_APB1_CLK = (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT); - - //FIXME assuming we're on IRC at 96 MHz - - /* 400 kHz I2C */ - //I2C0_SCLH = 120; - //I2C0_SCLL = 120; - - /* 100 kHz I2C */ - I2C0_SCLH = 480; - I2C0_SCLL = 480; - //FIXME not sure why this appears to run at about 290 kHz - - /* clear the control bits */ - I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC - | I2C_CONCLR_STAC | I2C_CONCLR_I2ENC); - - /* enable I2C0 */ - I2C0_CONSET = I2C_CONSET_I2EN; -} - -/* transmit start bit */ -void i2c0_tx_start() -{ - I2C0_CONCLR = I2C_CONCLR_SIC; - I2C0_CONSET = I2C_CONSET_STA; - while (!(I2C0_CONSET & I2C_CONSET_SI)); - I2C0_CONCLR = I2C_CONCLR_STAC; -} - -/* transmit data byte */ -void i2c0_tx_byte(u8 byte) -{ - if (I2C0_CONSET & I2C_CONSET_STA) - I2C0_CONCLR = I2C_CONCLR_STAC; - I2C0_DAT = byte; - I2C0_CONCLR = I2C_CONCLR_SIC; - while (!(I2C0_CONSET & I2C_CONSET_SI)); -} - -/* receive data byte */ -u8 i2c0_rx_byte() -{ - if (I2C0_CONSET & I2C_CONSET_STA) - I2C0_CONCLR = I2C_CONCLR_STAC; - I2C0_CONCLR = I2C_CONCLR_SIC; - while (!(I2C0_CONSET & I2C_CONSET_SI)); - return I2C0_DAT; -} - -/* transmit stop bit */ -void i2c0_stop() -{ - if (I2C0_CONSET & I2C_CONSET_STA) - I2C0_CONCLR = I2C_CONCLR_STAC; - I2C0_CONSET = I2C_CONSET_STO; - I2C0_CONCLR = I2C_CONCLR_SIC; -} - #define SI5351C_I2C_ADDR (0x60 << 1) -#define I2C_WRITE 0 -#define I2C_READ 1 /* write to single register */ void si5351c_write_reg(uint8_t reg, uint8_t val) diff --git a/include/libopencm3/lpc43xx/cgu.h b/include/libopencm3/lpc43xx/cgu.h index 1234834..48eb9cb 100644 --- a/include/libopencm3/lpc43xx/cgu.h +++ b/include/libopencm3/lpc43xx/cgu.h @@ -163,4 +163,27 @@ /* Output stage 27 control CLK register for base clock */ #define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8) +/* --- CGU_BASE_x_CLK values ----------------------------------------------- */ + +#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */ +#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */ +#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ + +/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */ + +#define CGU_SRC_32K 0x00 +#define CGU_SRC_IRC 0x01 +#define CGU_SRC_ENET_RX 0x02 +#define CGU_SRC_ENET_TX 0x03 +#define CGU_SRC_GP_CLKIN 0x04 +#define CGU_SRC_XTAL 0x06 +#define CGU_SRC_PLL0USB 0x07 +#define CGU_SRC_PLL0AUDIO 0x08 +#define CGU_SRC_PLL1 0x09 +#define CGU_SRC_IDIVA 0x0C +#define CGU_SRC_IDIVB 0x0D +#define CGU_SRC_IDIVC 0x0E +#define CGU_SRC_IDIVD 0x0F +#define CGU_SRC_IDIVE 0x10 + #endif diff --git a/include/libopencm3/lpc43xx/i2c.h b/include/libopencm3/lpc43xx/i2c.h index 1fe7655..249962c 100644 --- a/include/libopencm3/lpc43xx/i2c.h +++ b/include/libopencm3/lpc43xx/i2c.h @@ -29,7 +29,6 @@ #define I2C0 I2C0_BASE #define I2C1 I2C1_BASE - /* --- I2C registers ------------------------------------------------------- */ /* I2C Control Set Register */ @@ -112,4 +111,32 @@ #define I2C0_MASK3 I2C_MASK3(I2C0) #define I2C1_MASK3 I2C_MASK3(I2C1) +/* --- I2Cx_CONCLR values -------------------------------------------------- */ + +#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ +#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ +#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ +#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ + +/* --- I2Cx_CONSET values -------------------------------------------------- */ + +#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ + +/* --- I2C const definitions ----------------------------------------------- */ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +/* --- I2C funtion prototypes----------------------------------------------- */ + +void i2c0_init(void); +void i2c0_tx_start(void); +void i2c0_tx_byte(u8 byte); +u8 i2c0_rx_byte(void); +void i2c0_stop(void); + #endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 041e3bc..6df4b29 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o +OBJS = gpio.o vector.o scu.o i2c.o # VPATH += ../usb -- cgit v1.2.3 From d7a7fd9d3037a5e490be3e73027a11f779d7d35c Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Tue, 5 Jun 2012 01:41:54 +0200 Subject: * Added SSP Driver (Not Tested). * Replaced leading space by tabulations. --- examples/lpc43xx/Makefile.include | 1 + examples/lpc43xx/hackrf-jellybean/jellybean_conf.h | 19 +- .../lpc43xx/hackrf-jellybean/miniblink/miniblink.c | 98 +- examples/lpc43xx/hackrf-jellybean/ssp/Makefile | 24 + examples/lpc43xx/hackrf-jellybean/ssp/README | 20 + examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c | 99 ++ include/libopencm3/lpc43xx/scu.h | 1228 ++++++++++---------- include/libopencm3/lpc43xx/ssp.h | 188 ++- lib/lpc43xx/Makefile | 2 +- lib/lpc43xx/scu.c | 36 +- lib/lpc43xx/ssp.c | 132 +++ 11 files changed, 1112 insertions(+), 735 deletions(-) create mode 100644 examples/lpc43xx/hackrf-jellybean/ssp/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/ssp/README create mode 100644 examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c create mode 100644 lib/lpc43xx/ssp.c (limited to 'lib/lpc43xx') diff --git a/examples/lpc43xx/Makefile.include b/examples/lpc43xx/Makefile.include index 89e356d..588ddee 100644 --- a/examples/lpc43xx/Makefile.include +++ b/examples/lpc43xx/Makefile.include @@ -94,6 +94,7 @@ clean: $(Q)rm -f *.hex $(Q)rm -f *.srec $(Q)rm -f *.list + $(Q)rm -f *.map # FIXME: Replace STM32 stuff with proper LPC43XX OpenOCD support later. ifeq ($(OOCD_SERIAL),) diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h b/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h index a5ad8d0..dc791b3 100644 --- a/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h +++ b/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h @@ -27,9 +27,9 @@ extern "C" #include -/************************/ -/* JellyBean SCU PinMux */ -/************************/ +/* + * JellyBean SCU PinMux + */ /* GPIO Output PinMux */ #define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */ @@ -44,12 +44,17 @@ extern "C" #define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */ #define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */ -/* TODO add other Pins */ +/* SSP1 Peripheral PinMux */ +#define SCU_SSP1_MISO (P1_3) /* P1_3 */ +#define SCU_SSP1_MOSI (P1_4) /* P1_4 */ +#define SCU_SSP1_SCK (P1_19) /* P1_19 */ +#define SCU_SSP1_SSEL (P1_20) /* P1_20 */ -/**********************/ -/* JellyBean GPIO Pin */ -/**********************/ +/* TODO add other Pins */ +/* + * JellyBean GPIO Pin + */ /* GPIO Output */ #define PIN_LED1 (BIT1) /* GPIO2[1] on P4_1 */ #define PIN_LED2 (BIT2) /* GPIO2[2] on P4_2 */ diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c index 2826126..b1a22fa 100644 --- a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c +++ b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c @@ -1,22 +1,22 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +* This file is part of the libopencm3 project. +* +* Copyright (C) 2010 Uwe Hermann +* Copyright (C) 2012 Michael Ossmann +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ #include #include @@ -25,32 +25,38 @@ void gpio_setup(void) { - /* Configure SCU Pin Mux as GPIO */ - scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); - /* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */ - SCU_SFSI2C0 = SCU_I2C0_NOMINAL; + /* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */ + SCU_SFSI2C0 = SCU_I2C0_NOMINAL; - /* Configure all GPIO as Input (safe state) */ - GPIO0_DIR = 0; - GPIO1_DIR = 0; - GPIO2_DIR = 0; - GPIO3_DIR = 0; - GPIO4_DIR = 0; - GPIO5_DIR = 0; - GPIO6_DIR = 0; - GPIO7_DIR = 0; + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); - /* Configure GPIO as Output */ + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ } @@ -62,16 +68,16 @@ int main(void) int i; gpio_setup(); - /* Set 1V8 */ - gpio_set(PORT_EN1V8, PIN_EN1V8); + /* Set 1V8 */ + gpio_set(PORT_EN1V8, PIN_EN1V8); /* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */ while (1) - { - boot0 = BOOT0_STATE; - boot1 = BOOT1_STATE; - boot2 = BOOT2_STATE; - boot3 = BOOT3_STATE; + { + boot0 = BOOT0_STATE; + boot1 = BOOT1_STATE; + boot2 = BOOT2_STATE; + boot3 = BOOT3_STATE; gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ for (i = 0; i < 2000000; i++) /* Wait a bit. */ diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/Makefile b/examples/lpc43xx/hackrf-jellybean/ssp/Makefile new file mode 100644 index 0000000..8a3b1cc --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/ssp/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2010 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = sspdemo + +LDSCRIPT = ../jellybean-lpc4330.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/README b/examples/lpc43xx/hackrf-jellybean/ssp/README new file mode 100644 index 0000000..9b43214 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/ssp/README @@ -0,0 +1,20 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This program exercises the SSP1 peripheral on Jellybean's LPC43xx. + + Jellybean (connector) + P9 SPI + |-----------------| + | Pin2 Pin4 Pin6 | +||------| | +|| Pin1 |Pin3 Pin5 | +||------|----------| +|-------| + +SSP1_MISO: Jellybean P9 SPI Pin6 +SSP1_MOSI: Jellybean P9 SPI Pin4 +SSP1_SCK: Jellybean P9 SPI Pin2 +SSP1_SSEL: Jellybean P9 SPI Pin3 +GND: Can be connected to P12 SD Pin1 diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c new file mode 100644 index 0000000..388afc8 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c @@ -0,0 +1,99 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include + +#include "../jellybean_conf.h" + +void gpio_setup(void) +{ + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ +} + +int main(void) +{ + int i; + u8 ssp_val; + u8 serial_clock_rate; + + gpio_setup(); + + /* FIX Me freq */ + serial_clock_rate = 128; + + ssp_init(SSP1_NUM, + SSP_DATA_8BITS, + SSP_FRAME_SPI, + SSP_CPOL_0_CPHA_0, + serial_clock_rate, + SSP_MODE_NORMAL, + SSP_MASTER, + SSP_SLAVE_OUT_ENABLE); + + ssp_val = 0x0; + + while (1) { + + ssp_write(SSP1_NUM, (u16)ssp_val); + + gpio_set(GPIO2, GPIOPIN1); /* LED on */ + + for (i = 0; i < 1000; i++) /* Wait a bit. */ + __asm__("nop"); + + gpio_clear(GPIO2, GPIOPIN1); /* LED off */ + + ssp_val++; + } + + return 0; +} diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index c61918a..b9be79f 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -1,22 +1,22 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Michael Ossmann +* Copyright (C) 2012 Benjamin Vernoux +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ #ifndef LPC43XX_SCU_H #define LPC43XX_SCU_H @@ -27,703 +27,703 @@ /* --- Convenience macros -------------------------------------------------- */ /* Pin group base addresses */ -#define PIN_GROUP0 (SCU_BASE + 0x000) -#define PIN_GROUP1 (SCU_BASE + 0x080) -#define PIN_GROUP2 (SCU_BASE + 0x100) -#define PIN_GROUP3 (SCU_BASE + 0x180) -#define PIN_GROUP4 (SCU_BASE + 0x200) -#define PIN_GROUP5 (SCU_BASE + 0x280) -#define PIN_GROUP6 (SCU_BASE + 0x300) -#define PIN_GROUP7 (SCU_BASE + 0x380) -#define PIN_GROUP8 (SCU_BASE + 0x400) -#define PIN_GROUP9 (SCU_BASE + 0x480) -#define PIN_GROUPA (SCU_BASE + 0x500) -#define PIN_GROUPB (SCU_BASE + 0x580) -#define PIN_GROUPC (SCU_BASE + 0x600) -#define PIN_GROUPD (SCU_BASE + 0x680) -#define PIN_GROUPE (SCU_BASE + 0x700) -#define PIN_GROUPF (SCU_BASE + 0x780) - -#define PIN0 0x000 -#define PIN1 0x004 -#define PIN2 0x008 -#define PIN3 0x00C -#define PIN4 0x010 -#define PIN5 0x014 -#define PIN6 0x018 -#define PIN7 0x01C -#define PIN8 0x020 -#define PIN9 0x024 -#define PIN10 0x028 -#define PIN11 0x02C -#define PIN12 0x030 -#define PIN13 0x034 -#define PIN14 0x038 -#define PIN15 0x03C -#define PIN16 0x040 -#define PIN17 0x044 -#define PIN18 0x048 -#define PIN19 0x04C -#define PIN20 0x050 +#define PIN_GROUP0 (SCU_BASE + 0x000) +#define PIN_GROUP1 (SCU_BASE + 0x080) +#define PIN_GROUP2 (SCU_BASE + 0x100) +#define PIN_GROUP3 (SCU_BASE + 0x180) +#define PIN_GROUP4 (SCU_BASE + 0x200) +#define PIN_GROUP5 (SCU_BASE + 0x280) +#define PIN_GROUP6 (SCU_BASE + 0x300) +#define PIN_GROUP7 (SCU_BASE + 0x380) +#define PIN_GROUP8 (SCU_BASE + 0x400) +#define PIN_GROUP9 (SCU_BASE + 0x480) +#define PIN_GROUPA (SCU_BASE + 0x500) +#define PIN_GROUPB (SCU_BASE + 0x580) +#define PIN_GROUPC (SCU_BASE + 0x600) +#define PIN_GROUPD (SCU_BASE + 0x680) +#define PIN_GROUPE (SCU_BASE + 0x700) +#define PIN_GROUPF (SCU_BASE + 0x780) + +#define PIN0 0x000 +#define PIN1 0x004 +#define PIN2 0x008 +#define PIN3 0x00C +#define PIN4 0x010 +#define PIN5 0x014 +#define PIN6 0x018 +#define PIN7 0x01C +#define PIN8 0x020 +#define PIN9 0x024 +#define PIN10 0x028 +#define PIN11 0x02C +#define PIN12 0x030 +#define PIN13 0x034 +#define PIN14 0x038 +#define PIN15 0x03C +#define PIN16 0x040 +#define PIN17 0x044 +#define PIN18 0x048 +#define PIN19 0x04C +#define PIN20 0x050 /* --- SCU registers ------------------------------------------------------- */ /* Pin configuration registers */ -#define SCU_SFS(group, pin) MMIO32(group + pin) +#define SCU_SFS(group, pin) MMIO32(group + pin) /* Pins P0_n */ -#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) -#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1) +#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) +#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1) /* Pins P1_n */ -#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0) -#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1) -#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2) -#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3) -#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4) -#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5) -#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6) -#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7) -#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8) -#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9) -#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10) -#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11) -#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12) -#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13) -#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14) -#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15) -#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16) -#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17) -#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18) -#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19) -#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20) +#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0) +#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1) +#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2) +#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3) +#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4) +#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5) +#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6) +#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7) +#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8) +#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9) +#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10) +#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11) +#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12) +#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13) +#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14) +#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15) +#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16) +#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17) +#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18) +#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19) +#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20) /* Pins P2_n */ -#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0) -#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1) -#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2) -#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3) -#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4) -#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5) -#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6) -#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7) -#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8) -#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9) -#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10) -#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11) -#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12) -#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13) +#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0) +#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1) +#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2) +#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3) +#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4) +#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5) +#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6) +#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7) +#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8) +#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9) +#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10) +#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11) +#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12) +#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13) /* Pins P3_n */ -#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0) -#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1) -#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2) -#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3) -#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4) -#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5) -#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6) -#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7) -#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8) +#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0) +#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1) +#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2) +#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3) +#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4) +#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5) +#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6) +#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7) +#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8) /* Pins P4_n */ -#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0) -#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1) -#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2) -#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3) -#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4) -#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5) -#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6) -#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7) -#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8) -#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9) -#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10) +#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0) +#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1) +#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2) +#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3) +#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4) +#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5) +#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6) +#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7) +#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8) +#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9) +#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10) /* Pins P5_n */ -#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0) -#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1) -#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2) -#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3) -#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4) -#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5) -#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6) -#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7) +#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0) +#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1) +#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2) +#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3) +#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4) +#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5) +#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6) +#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7) /* Pins P6_n */ -#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0) -#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1) -#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2) -#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3) -#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4) -#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5) -#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6) -#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7) -#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8) -#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9) -#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10) -#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11) -#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12) +#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0) +#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1) +#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2) +#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3) +#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4) +#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5) +#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6) +#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7) +#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8) +#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9) +#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10) +#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11) +#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12) /* Pins P7_n */ -#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0) -#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1) -#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2) -#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3) -#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4) -#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5) -#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6) -#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7) +#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0) +#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1) +#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2) +#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3) +#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4) +#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5) +#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6) +#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7) /* Pins P8_n */ -#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0) -#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1) -#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2) -#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3) -#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4) -#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5) -#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6) -#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7) -#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8) +#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0) +#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1) +#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2) +#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3) +#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4) +#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5) +#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6) +#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7) +#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8) /* Pins P9_n */ -#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0) -#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1) -#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2) -#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3) -#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4) -#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5) -#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6) +#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0) +#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1) +#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2) +#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3) +#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4) +#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5) +#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6) /* Pins PA_n */ -#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0) -#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1) -#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2) -#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3) -#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4) +#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0) +#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1) +#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2) +#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3) +#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4) /* Pins PB_n */ -#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0) -#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1) -#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2) -#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3) -#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4) -#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5) -#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6) +#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0) +#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1) +#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2) +#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3) +#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4) +#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5) +#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6) /* Pins PC_n */ -#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0) -#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1) -#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2) -#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3) -#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4) -#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5) -#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6) -#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7) -#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8) -#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9) -#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10) -#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11) -#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12) -#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13) -#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14) +#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0) +#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1) +#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2) +#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3) +#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4) +#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5) +#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6) +#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7) +#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8) +#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9) +#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10) +#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11) +#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12) +#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13) +#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14) /* Pins PD_n */ -#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0) -#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1) -#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2) -#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3) -#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4) -#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5) -#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6) -#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7) -#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8) -#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9) -#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10) -#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11) -#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12) -#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13) -#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14) -#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15) -#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16) +#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0) +#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1) +#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2) +#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3) +#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4) +#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5) +#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6) +#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7) +#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8) +#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9) +#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10) +#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11) +#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12) +#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13) +#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14) +#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15) +#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16) /* Pins PE_n */ -#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0) -#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1) -#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2) -#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3) -#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4) -#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5) -#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6) -#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7) -#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8) -#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9) -#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10) -#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11) -#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12) -#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13) -#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14) -#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15) +#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0) +#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1) +#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2) +#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3) +#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4) +#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5) +#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6) +#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7) +#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8) +#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9) +#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10) +#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11) +#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12) +#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13) +#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14) +#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15) /* Pins PF_n */ -#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0) -#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1) -#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2) -#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3) -#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4) -#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5) -#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6) -#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7) -#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8) -#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9) -#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10) -#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11) +#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0) +#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1) +#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2) +#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3) +#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4) +#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5) +#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6) +#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7) +#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8) +#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9) +#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10) +#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11) /* CLKn pins */ -#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00) -#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04) -#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08) -#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C) +#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00) +#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04) +#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08) +#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C) /* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ -#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) -#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) +#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) +#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) /* ADC pin select registers */ /* ADC0 function select register */ -#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88) +#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88) /* ADC1 function select register */ -#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C) +#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C) /* Analog function select register */ -#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90) +#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90) /* EMC clock delay register */ -#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00) +#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00) /* Pin interrupt select registers */ /* Pin interrupt select register for pin interrupts 0 to 3 */ -#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) +#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) /* Pin interrupt select register for pin interrupts 4 to 7 */ -#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) +#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) /**************************/ /* SCU I2C0 Configuration */ /**************************/ -/* - * Select input glitch filter time constant for the SCL pin. - * 0 = 50 ns glitch filter. - * 1 = 3ns glitch filter. - */ -#define SCU_SCL_EFP (BIT0) +/* +* Select input glitch filter time constant for the SCL pin. +* 0 = 50 ns glitch filter. +* 1 = 3ns glitch filter. +*/ +#define SCU_SCL_EFP (BIT0) /* BIT1 Reserved. Always write a 0 to this bit. */ /* - * Select I2C mode for the SCL pin. - * 0 = Standard/Fast mode transmit. - * 1 = Fast-mode Plus transmit. - */ -#define SCU_SCL_EHD (BIT2) +* Select I2C mode for the SCL pin. +* 0 = Standard/Fast mode transmit. +* 1 = Fast-mode Plus transmit. +*/ +#define SCU_SCL_EHD (BIT2) /* - * Enable the input receiver for the SCL pin. - * Always write a 1 to this bit when using the - * I2C0. - * 0 = Disabled. - * 1 = Enabled. - */ -#define SCU_SCL_EZI_EN (BIT3) +* Enable the input receiver for the SCL pin. +* Always write a 1 to this bit when using the +* I2C0. +* 0 = Disabled. +* 1 = Enabled. +*/ +#define SCU_SCL_EZI_EN (BIT3) /* BIT4-6 Reserved. */ -/* - * Enable or disable input glitch filter for the - * SCL pin. The filter time constant is - * determined by bit EFP. - * 0 = Enable input filter. - * 1 = Disable input filter. - */ -#define SCU_SCL_ZIF_DIS (BIT7) +/* +* Enable or disable input glitch filter for the +* SCL pin. The filter time constant is +* determined by bit EFP. +* 0 = Enable input filter. +* 1 = Disable input filter. +*/ +#define SCU_SCL_ZIF_DIS (BIT7) /* - * Select input glitch filter time constant for the SDA pin. - * 0 = 50 ns glitch filter. - * 1 = 3ns glitch filter. - */ -#define SCU_SDA_EFP (BIT8) +* Select input glitch filter time constant for the SDA pin. +* 0 = 50 ns glitch filter. +* 1 = 3ns glitch filter. +*/ +#define SCU_SDA_EFP (BIT8) /* BIT9 Reserved. Always write a 0 to this bit. */ -/* - * Select I2C mode for the SDA pin. - * 0 = Standard/Fast mode transmit. - * 1 = Fast-mode Plus transmit. - */ -#define SCU_SDA_EHD (BIT10) +/* +* Select I2C mode for the SDA pin. +* 0 = Standard/Fast mode transmit. +* 1 = Fast-mode Plus transmit. +*/ +#define SCU_SDA_EHD (BIT10) /* - * Enable the input receiver for the SDA pin. - * Always write a 1 to this bit when using the - * I2C0. - * 0 = Disabled. - * 1 = Enabled. - */ -#define SCU_SDA_EZI_EN (BIT11) +* Enable the input receiver for the SDA pin. +* Always write a 1 to this bit when using the +* I2C0. +* 0 = Disabled. +* 1 = Enabled. +*/ +#define SCU_SDA_EZI_EN (BIT11) /* BIT 12-14 - Reserved */ /* - * Enable or disable input glitch filter for the - * SDA pin. The filter time constant is - * determined by bit SDA_EFP. - * 0 = Enable input filter. - * 1 = Disable input filter. - */ -#define SCU_SDA_ZIF_DIS (BIT15) +* Enable or disable input glitch filter for the +* SDA pin. The filter time constant is +* determined by bit SDA_EFP. +* 0 = Enable input filter. +* 1 = Disable input filter. +*/ +#define SCU_SDA_ZIF_DIS (BIT15) /* Standard mode for I2C SCL/SDA Standard/Fast mode */ -#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) +#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) /* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */ -#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \ - SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN) - -/* - * SCU PIN Normal Drive: - * The pin configuration registers for normal-drive pins control the following pins: - * - P0_0 and P0_1 - * - P1_0 to P1_16 and P1_18 to P1_20 - * - P2_0 to P2_2 and P2_6 to P2_13 - * - P3_0 to P3_2 and P3_4 to P3_8 - * - P4_0 to P4_10 - * - P5_0 to P5_7 - * - P6_0 to P6_12 - * - P7_0 to P7_7 - * - P8_3 to P8_8 - * - P9_0 to P9_6 - * - PA_0 and PA_4 - * - PB_0 to PB_6 - * - PC_0 to PC_14 - * - PE_0 to PE_15 - * - PF_0 to PF_11 - * - * Pin configuration registers for High-Drive pins. - * The pin configuration registers for high-drive pins control the following pins: - * - P1_17 - * - P2_3 to P2_5 - * - P8_0 to P8_2 - * - PA_1 to PA_3 - * - * Pin configuration registers for High-Speed pins. - * This register controls the following pins: - * - P3_3 and pins CLK0 to CLK3. - */ +#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \ + SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN) + +/* +* SCU PIN Normal Drive: +* The pin configuration registers for normal-drive pins control the following pins: +* - P0_0 and P0_1 +* - P1_0 to P1_16 and P1_18 to P1_20 +* - P2_0 to P2_2 and P2_6 to P2_13 +* - P3_0 to P3_2 and P3_4 to P3_8 +* - P4_0 to P4_10 +* - P5_0 to P5_7 +* - P6_0 to P6_12 +* - P7_0 to P7_7 +* - P8_3 to P8_8 +* - P9_0 to P9_6 +* - PA_0 and PA_4 +* - PB_0 to PB_6 +* - PC_0 to PC_14 +* - PE_0 to PE_15 +* - PF_0 to PF_11 +* +* Pin configuration registers for High-Drive pins. +* The pin configuration registers for high-drive pins control the following pins: +* - P1_17 +* - P2_3 to P2_5 +* - P8_0 to P8_2 +* - PA_1 to PA_3 +* +* Pin configuration registers for High-Speed pins. +* This register controls the following pins: +* - P3_3 and pins CLK0 to CLK3. +*/ typedef enum { - /* Group Port 0 */ + /* Group Port 0 */ P0_0 = (PIN_GROUP0+PIN0), - P0_1 = (PIN_GROUP0+PIN1), - - /* Group Port 1 */ - P1_0 = (PIN_GROUP1+PIN0), - P1_1 = (PIN_GROUP1+PIN1), - P1_2 = (PIN_GROUP1+PIN2), - P1_3 = (PIN_GROUP1+PIN3), - P1_4 = (PIN_GROUP1+PIN4), - P1_5 = (PIN_GROUP1+PIN5), - P1_6 = (PIN_GROUP1+PIN6), - P1_7 = (PIN_GROUP1+PIN7), - P1_8 = (PIN_GROUP1+PIN8), - P1_9 = (PIN_GROUP1+PIN9), - P1_10 = (PIN_GROUP1+PIN10), - P1_11 = (PIN_GROUP1+PIN11), - P1_12 = (PIN_GROUP1+PIN12), - P1_13 = (PIN_GROUP1+PIN13), - P1_14 = (PIN_GROUP1+PIN14), - P1_15 = (PIN_GROUP1+PIN15), - P1_16 = (PIN_GROUP1+PIN16), - - /* P1_17 is High-Drive pin */ - P1_17 = (PIN_GROUP1+PIN17), - - P1_18 = (PIN_GROUP1+PIN18), - P1_19 = (PIN_GROUP1+PIN19), - P1_20 = (PIN_GROUP1+PIN20), - - /* Group Port 2 */ - P2_0 = (PIN_GROUP2+PIN0), - P2_1 = (PIN_GROUP2+PIN1), - P2_2 = (PIN_GROUP2+PIN2), - - /* P2_3 to P2_5 are High-Drive pins */ - P2_3 = (PIN_GROUP2+PIN3), - P2_4 = (PIN_GROUP2+PIN4), - P2_5 = (PIN_GROUP2+PIN5), - - P2_6 = (PIN_GROUP2+PIN6), - P2_7 = (PIN_GROUP2+PIN7), - P2_8 = (PIN_GROUP2+PIN8), - P2_9 = (PIN_GROUP2+PIN9), - P2_10 = (PIN_GROUP2+PIN10), - P2_11 = (PIN_GROUP2+PIN11), - P2_12 = (PIN_GROUP2+PIN12), - P2_13 = (PIN_GROUP2+PIN13), - - /* Group Port 3 */ - P3_0 = (PIN_GROUP3+PIN0), - P3_1 = (PIN_GROUP3+PIN1), - P3_2 = (PIN_GROUP3+PIN2), - - /* P3_3 is High-Speed pin */ - P3_3 = (PIN_GROUP3+PIN3), - - P3_4 = (PIN_GROUP3+PIN4), - P3_5 = (PIN_GROUP3+PIN5), - P3_6 = (PIN_GROUP3+PIN6), - P3_7 = (PIN_GROUP3+PIN7), - P3_8 = (PIN_GROUP3+PIN8), - - /* Group Port 4 */ - P4_0 = (PIN_GROUP4+PIN0), - P4_1 = (PIN_GROUP4+PIN1), - P4_2 = (PIN_GROUP4+PIN2), - P4_3 = (PIN_GROUP4+PIN3), - P4_4 = (PIN_GROUP4+PIN4), - P4_5 = (PIN_GROUP4+PIN5), - P4_6 = (PIN_GROUP4+PIN6), - P4_7 = (PIN_GROUP4+PIN7), - P4_8 = (PIN_GROUP4+PIN8), - P4_9 = (PIN_GROUP4+PIN9), - P4_10 = (PIN_GROUP4+PIN10), - - /* Group Port 5 */ - P5_0 = (PIN_GROUP5+PIN0), - P5_1 = (PIN_GROUP5+PIN1), - P5_2 = (PIN_GROUP5+PIN2), - P5_3 = (PIN_GROUP5+PIN3), - P5_4 = (PIN_GROUP5+PIN4), - P5_5 = (PIN_GROUP5+PIN5), - P5_6 = (PIN_GROUP5+PIN6), - P5_7 = (PIN_GROUP5+PIN7), - - /* Group Port 6 */ - P6_0 = (PIN_GROUP6+PIN0), - P6_1 = (PIN_GROUP6+PIN1), - P6_2 = (PIN_GROUP6+PIN2), - P6_3 = (PIN_GROUP6+PIN3), - P6_4 = (PIN_GROUP6+PIN4), - P6_5 = (PIN_GROUP6+PIN5), - P6_6 = (PIN_GROUP6+PIN6), - P6_7 = (PIN_GROUP6+PIN7), - P6_8 = (PIN_GROUP6+PIN8), - P6_9 = (PIN_GROUP6+PIN9), - P6_10 = (PIN_GROUP6+PIN10), - P6_11 = (PIN_GROUP6+PIN11), - P6_12 = (PIN_GROUP6+PIN12), - - /* Group Port 7 */ - P7_0 = (PIN_GROUP7+PIN0), - P7_1 = (PIN_GROUP7+PIN1), - P7_2 = (PIN_GROUP7+PIN2), - P7_3 = (PIN_GROUP7+PIN3), - P7_4 = (PIN_GROUP7+PIN4), - P7_5 = (PIN_GROUP7+PIN5), - P7_6 = (PIN_GROUP7+PIN6), - P7_7 = (PIN_GROUP7+PIN7), - - /* Group Port 8 */ - /* P8_0 to P8_2 are High-Drive pins */ - P8_0 = (PIN_GROUP8+PIN0), - P8_1 = (PIN_GROUP8+PIN1), - P8_2 = (PIN_GROUP8+PIN2), - - P8_3 = (PIN_GROUP8+PIN3), - P8_4 = (PIN_GROUP8+PIN4), - P8_5 = (PIN_GROUP8+PIN5), - P8_6 = (PIN_GROUP8+PIN6), - P8_7 = (PIN_GROUP8+PIN7), - P8_8 = (PIN_GROUP8+PIN8), - - /* Group Port 9 */ - P9_0 = (PIN_GROUP9+PIN0), - P9_1 = (PIN_GROUP9+PIN1), - P9_2 = (PIN_GROUP9+PIN2), - P9_3 = (PIN_GROUP9+PIN3), - P9_4 = (PIN_GROUP9+PIN4), - P9_5 = (PIN_GROUP9+PIN5), - P9_6 = (PIN_GROUP9+PIN6), - - /* Group Port A */ - PA_0 = (PIN_GROUPA+PIN0), - /* PA_1 to PA_3 are Normal & High-Drive Pins */ - PA_1 = (PIN_GROUPA+PIN1), - PA_2 = (PIN_GROUPA+PIN2), - PA_3 = (PIN_GROUPA+PIN3), - PA_4 = (PIN_GROUPA+PIN4), - - /* Group Port B */ - PB_0 = (PIN_GROUPB+PIN0), - PB_1 = (PIN_GROUPB+PIN1), - PB_2 = (PIN_GROUPB+PIN2), - PB_3 = (PIN_GROUPB+PIN3), - PB_4 = (PIN_GROUPB+PIN4), - PB_5 = (PIN_GROUPB+PIN5), - PB_6 = (PIN_GROUPB+PIN6), - - /* Group Port C */ - PC_0 = (PIN_GROUPC+PIN0), - PC_1 = (PIN_GROUPC+PIN1), - PC_2 = (PIN_GROUPC+PIN2), - PC_3 = (PIN_GROUPC+PIN3), - PC_4 = (PIN_GROUPC+PIN4), - PC_5 = (PIN_GROUPC+PIN5), - PC_6 = (PIN_GROUPC+PIN6), - PC_7 = (PIN_GROUPC+PIN7), - PC_8 = (PIN_GROUPC+PIN8), - PC_9 = (PIN_GROUPC+PIN9), - PC_10 = (PIN_GROUPC+PIN10), - PC_11 = (PIN_GROUPC+PIN11), - PC_12 = (PIN_GROUPC+PIN12), - PC_13 = (PIN_GROUPC+PIN13), - PC_14 = (PIN_GROUPC+PIN14), - - /* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */ - PD_0 = (PIN_GROUPD+PIN0), - PD_1 = (PIN_GROUPD+PIN1), - PD_2 = (PIN_GROUPD+PIN2), - PD_3 = (PIN_GROUPD+PIN3), - PD_4 = (PIN_GROUPD+PIN4), - PD_5 = (PIN_GROUPD+PIN5), - PD_6 = (PIN_GROUPD+PIN6), - PD_7 = (PIN_GROUPD+PIN7), - PD_8 = (PIN_GROUPD+PIN8), - PD_9 = (PIN_GROUPD+PIN9), - PD_10 = (PIN_GROUPD+PIN10), - PD_11 = (PIN_GROUPD+PIN11), - PD_12 = (PIN_GROUPD+PIN12), - PD_13 = (PIN_GROUPD+PIN13), - PD_14 = (PIN_GROUPD+PIN14), - PD_15 = (PIN_GROUPD+PIN15), - PD_16 = (PIN_GROUPD+PIN16), - - /* Group Port E */ - PE_0 = (PIN_GROUPE+PIN0), - PE_1 = (PIN_GROUPE+PIN1), - PE_2 = (PIN_GROUPE+PIN2), - PE_3 = (PIN_GROUPE+PIN3), - PE_4 = (PIN_GROUPE+PIN4), - PE_5 = (PIN_GROUPE+PIN5), - PE_6 = (PIN_GROUPE+PIN6), - PE_7 = (PIN_GROUPE+PIN7), - PE_8 = (PIN_GROUPE+PIN8), - PE_9 = (PIN_GROUPE+PIN9), - PE_10 = (PIN_GROUPE+PIN10), - PE_11 = (PIN_GROUPE+PIN11), - PE_12 = (PIN_GROUPE+PIN12), - PE_13 = (PIN_GROUPE+PIN13), - PE_14 = (PIN_GROUPE+PIN14), - PE_15 = (PIN_GROUPE+PIN15), - - /* Group Port F */ - PF_0 = (PIN_GROUPF+PIN0), - PF_1 = (PIN_GROUPF+PIN1), - PF_2 = (PIN_GROUPF+PIN2), - PF_3 = (PIN_GROUPF+PIN3), - PF_4 = (PIN_GROUPF+PIN4), - PF_5 = (PIN_GROUPF+PIN5), - PF_6 = (PIN_GROUPF+PIN6), - PF_7 = (PIN_GROUPF+PIN7), - PF_8 = (PIN_GROUPF+PIN8), - PF_9 = (PIN_GROUPF+PIN9), - PF_10 = (PIN_GROUPF+PIN10), - PF_11 = (PIN_GROUPF+PIN11), - - /* Group Clock 0 to 3 High-Speed pins */ - CLK0 = (SCU_BASE + 0xC00), - CLK1 = (SCU_BASE + 0xC04), - CLK2 = (SCU_BASE + 0xC08), - CLK3 = (SCU_BASE + 0xC0C) + P0_1 = (PIN_GROUP0+PIN1), + + /* Group Port 1 */ + P1_0 = (PIN_GROUP1+PIN0), + P1_1 = (PIN_GROUP1+PIN1), + P1_2 = (PIN_GROUP1+PIN2), + P1_3 = (PIN_GROUP1+PIN3), + P1_4 = (PIN_GROUP1+PIN4), + P1_5 = (PIN_GROUP1+PIN5), + P1_6 = (PIN_GROUP1+PIN6), + P1_7 = (PIN_GROUP1+PIN7), + P1_8 = (PIN_GROUP1+PIN8), + P1_9 = (PIN_GROUP1+PIN9), + P1_10 = (PIN_GROUP1+PIN10), + P1_11 = (PIN_GROUP1+PIN11), + P1_12 = (PIN_GROUP1+PIN12), + P1_13 = (PIN_GROUP1+PIN13), + P1_14 = (PIN_GROUP1+PIN14), + P1_15 = (PIN_GROUP1+PIN15), + P1_16 = (PIN_GROUP1+PIN16), + + /* P1_17 is High-Drive pin */ + P1_17 = (PIN_GROUP1+PIN17), + + P1_18 = (PIN_GROUP1+PIN18), + P1_19 = (PIN_GROUP1+PIN19), + P1_20 = (PIN_GROUP1+PIN20), + + /* Group Port 2 */ + P2_0 = (PIN_GROUP2+PIN0), + P2_1 = (PIN_GROUP2+PIN1), + P2_2 = (PIN_GROUP2+PIN2), + + /* P2_3 to P2_5 are High-Drive pins */ + P2_3 = (PIN_GROUP2+PIN3), + P2_4 = (PIN_GROUP2+PIN4), + P2_5 = (PIN_GROUP2+PIN5), + + P2_6 = (PIN_GROUP2+PIN6), + P2_7 = (PIN_GROUP2+PIN7), + P2_8 = (PIN_GROUP2+PIN8), + P2_9 = (PIN_GROUP2+PIN9), + P2_10 = (PIN_GROUP2+PIN10), + P2_11 = (PIN_GROUP2+PIN11), + P2_12 = (PIN_GROUP2+PIN12), + P2_13 = (PIN_GROUP2+PIN13), + + /* Group Port 3 */ + P3_0 = (PIN_GROUP3+PIN0), + P3_1 = (PIN_GROUP3+PIN1), + P3_2 = (PIN_GROUP3+PIN2), + + /* P3_3 is High-Speed pin */ + P3_3 = (PIN_GROUP3+PIN3), + + P3_4 = (PIN_GROUP3+PIN4), + P3_5 = (PIN_GROUP3+PIN5), + P3_6 = (PIN_GROUP3+PIN6), + P3_7 = (PIN_GROUP3+PIN7), + P3_8 = (PIN_GROUP3+PIN8), + + /* Group Port 4 */ + P4_0 = (PIN_GROUP4+PIN0), + P4_1 = (PIN_GROUP4+PIN1), + P4_2 = (PIN_GROUP4+PIN2), + P4_3 = (PIN_GROUP4+PIN3), + P4_4 = (PIN_GROUP4+PIN4), + P4_5 = (PIN_GROUP4+PIN5), + P4_6 = (PIN_GROUP4+PIN6), + P4_7 = (PIN_GROUP4+PIN7), + P4_8 = (PIN_GROUP4+PIN8), + P4_9 = (PIN_GROUP4+PIN9), + P4_10 = (PIN_GROUP4+PIN10), + + /* Group Port 5 */ + P5_0 = (PIN_GROUP5+PIN0), + P5_1 = (PIN_GROUP5+PIN1), + P5_2 = (PIN_GROUP5+PIN2), + P5_3 = (PIN_GROUP5+PIN3), + P5_4 = (PIN_GROUP5+PIN4), + P5_5 = (PIN_GROUP5+PIN5), + P5_6 = (PIN_GROUP5+PIN6), + P5_7 = (PIN_GROUP5+PIN7), + + /* Group Port 6 */ + P6_0 = (PIN_GROUP6+PIN0), + P6_1 = (PIN_GROUP6+PIN1), + P6_2 = (PIN_GROUP6+PIN2), + P6_3 = (PIN_GROUP6+PIN3), + P6_4 = (PIN_GROUP6+PIN4), + P6_5 = (PIN_GROUP6+PIN5), + P6_6 = (PIN_GROUP6+PIN6), + P6_7 = (PIN_GROUP6+PIN7), + P6_8 = (PIN_GROUP6+PIN8), + P6_9 = (PIN_GROUP6+PIN9), + P6_10 = (PIN_GROUP6+PIN10), + P6_11 = (PIN_GROUP6+PIN11), + P6_12 = (PIN_GROUP6+PIN12), + + /* Group Port 7 */ + P7_0 = (PIN_GROUP7+PIN0), + P7_1 = (PIN_GROUP7+PIN1), + P7_2 = (PIN_GROUP7+PIN2), + P7_3 = (PIN_GROUP7+PIN3), + P7_4 = (PIN_GROUP7+PIN4), + P7_5 = (PIN_GROUP7+PIN5), + P7_6 = (PIN_GROUP7+PIN6), + P7_7 = (PIN_GROUP7+PIN7), + + /* Group Port 8 */ + /* P8_0 to P8_2 are High-Drive pins */ + P8_0 = (PIN_GROUP8+PIN0), + P8_1 = (PIN_GROUP8+PIN1), + P8_2 = (PIN_GROUP8+PIN2), + + P8_3 = (PIN_GROUP8+PIN3), + P8_4 = (PIN_GROUP8+PIN4), + P8_5 = (PIN_GROUP8+PIN5), + P8_6 = (PIN_GROUP8+PIN6), + P8_7 = (PIN_GROUP8+PIN7), + P8_8 = (PIN_GROUP8+PIN8), + + /* Group Port 9 */ + P9_0 = (PIN_GROUP9+PIN0), + P9_1 = (PIN_GROUP9+PIN1), + P9_2 = (PIN_GROUP9+PIN2), + P9_3 = (PIN_GROUP9+PIN3), + P9_4 = (PIN_GROUP9+PIN4), + P9_5 = (PIN_GROUP9+PIN5), + P9_6 = (PIN_GROUP9+PIN6), + + /* Group Port A */ + PA_0 = (PIN_GROUPA+PIN0), + /* PA_1 to PA_3 are Normal & High-Drive Pins */ + PA_1 = (PIN_GROUPA+PIN1), + PA_2 = (PIN_GROUPA+PIN2), + PA_3 = (PIN_GROUPA+PIN3), + PA_4 = (PIN_GROUPA+PIN4), + + /* Group Port B */ + PB_0 = (PIN_GROUPB+PIN0), + PB_1 = (PIN_GROUPB+PIN1), + PB_2 = (PIN_GROUPB+PIN2), + PB_3 = (PIN_GROUPB+PIN3), + PB_4 = (PIN_GROUPB+PIN4), + PB_5 = (PIN_GROUPB+PIN5), + PB_6 = (PIN_GROUPB+PIN6), + + /* Group Port C */ + PC_0 = (PIN_GROUPC+PIN0), + PC_1 = (PIN_GROUPC+PIN1), + PC_2 = (PIN_GROUPC+PIN2), + PC_3 = (PIN_GROUPC+PIN3), + PC_4 = (PIN_GROUPC+PIN4), + PC_5 = (PIN_GROUPC+PIN5), + PC_6 = (PIN_GROUPC+PIN6), + PC_7 = (PIN_GROUPC+PIN7), + PC_8 = (PIN_GROUPC+PIN8), + PC_9 = (PIN_GROUPC+PIN9), + PC_10 = (PIN_GROUPC+PIN10), + PC_11 = (PIN_GROUPC+PIN11), + PC_12 = (PIN_GROUPC+PIN12), + PC_13 = (PIN_GROUPC+PIN13), + PC_14 = (PIN_GROUPC+PIN14), + + /* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */ + PD_0 = (PIN_GROUPD+PIN0), + PD_1 = (PIN_GROUPD+PIN1), + PD_2 = (PIN_GROUPD+PIN2), + PD_3 = (PIN_GROUPD+PIN3), + PD_4 = (PIN_GROUPD+PIN4), + PD_5 = (PIN_GROUPD+PIN5), + PD_6 = (PIN_GROUPD+PIN6), + PD_7 = (PIN_GROUPD+PIN7), + PD_8 = (PIN_GROUPD+PIN8), + PD_9 = (PIN_GROUPD+PIN9), + PD_10 = (PIN_GROUPD+PIN10), + PD_11 = (PIN_GROUPD+PIN11), + PD_12 = (PIN_GROUPD+PIN12), + PD_13 = (PIN_GROUPD+PIN13), + PD_14 = (PIN_GROUPD+PIN14), + PD_15 = (PIN_GROUPD+PIN15), + PD_16 = (PIN_GROUPD+PIN16), + + /* Group Port E */ + PE_0 = (PIN_GROUPE+PIN0), + PE_1 = (PIN_GROUPE+PIN1), + PE_2 = (PIN_GROUPE+PIN2), + PE_3 = (PIN_GROUPE+PIN3), + PE_4 = (PIN_GROUPE+PIN4), + PE_5 = (PIN_GROUPE+PIN5), + PE_6 = (PIN_GROUPE+PIN6), + PE_7 = (PIN_GROUPE+PIN7), + PE_8 = (PIN_GROUPE+PIN8), + PE_9 = (PIN_GROUPE+PIN9), + PE_10 = (PIN_GROUPE+PIN10), + PE_11 = (PIN_GROUPE+PIN11), + PE_12 = (PIN_GROUPE+PIN12), + PE_13 = (PIN_GROUPE+PIN13), + PE_14 = (PIN_GROUPE+PIN14), + PE_15 = (PIN_GROUPE+PIN15), + + /* Group Port F */ + PF_0 = (PIN_GROUPF+PIN0), + PF_1 = (PIN_GROUPF+PIN1), + PF_2 = (PIN_GROUPF+PIN2), + PF_3 = (PIN_GROUPF+PIN3), + PF_4 = (PIN_GROUPF+PIN4), + PF_5 = (PIN_GROUPF+PIN5), + PF_6 = (PIN_GROUPF+PIN6), + PF_7 = (PIN_GROUPF+PIN7), + PF_8 = (PIN_GROUPF+PIN8), + PF_9 = (PIN_GROUPF+PIN9), + PF_10 = (PIN_GROUPF+PIN10), + PF_11 = (PIN_GROUPF+PIN11), + + /* Group Clock 0 to 3 High-Speed pins */ + CLK0 = (SCU_BASE + 0xC00), + CLK1 = (SCU_BASE + 0xC04), + CLK2 = (SCU_BASE + 0xC08), + CLK3 = (SCU_BASE + 0xC0C) } scu_grp_pin_t; -/* - * Pin Configuration to be used for scu_pinmux() parameter scu_conf - * For normal-drive pins, high-drive pins, high-speed pins - */ -/* - * Function BIT0 to 2. - * Common to normal-drive pins, high-drive pins, high-speed pins. - */ -#define SCU_CONF_FUNCTION0 (0x0) -#define SCU_CONF_FUNCTION1 (0x1) -#define SCU_CONF_FUNCTION2 (0x2) -#define SCU_CONF_FUNCTION3 (0x3) -#define SCU_CONF_FUNCTION4 (0x4) -#define SCU_CONF_FUNCTION5 (0x5) -#define SCU_CONF_FUNCTION6 (0x6) -#define SCU_CONF_FUNCTION7 (0x7) - -/* - * Enable pull-down resistor at pad - * By default=0 Disable pull-down. - * Available to normal-drive pins, high-drive pins, high-speed pins - */ -#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) - -/* - * Disable pull-up resistor at pad. - * By default=0 the pull-up resistor is enabled at reset. - * Available to normal-drive pins, high-drive pins, high-speed pins - */ -#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) - -/* - * Select Slew Rate. - * By Default=0 Slow. - * Available to normal-drive pins and high-speed pins, reserved for high-drive pins. - */ -#define SCU_CONF_EHS_FAST (BIT5) +/* +* Pin Configuration to be used for scu_pinmux() parameter scu_conf +* For normal-drive pins, high-drive pins, high-speed pins +*/ +/* +* Function BIT0 to 2. +* Common to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_FUNCTION0 (0x0) +#define SCU_CONF_FUNCTION1 (0x1) +#define SCU_CONF_FUNCTION2 (0x2) +#define SCU_CONF_FUNCTION3 (0x3) +#define SCU_CONF_FUNCTION4 (0x4) +#define SCU_CONF_FUNCTION5 (0x5) +#define SCU_CONF_FUNCTION6 (0x6) +#define SCU_CONF_FUNCTION7 (0x7) + +/* +* Enable pull-down resistor at pad +* By default=0 Disable pull-down. +* Available to normal-drive pins, high-drive pins, high-speed pins +*/ +#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) + +/* +* Disable pull-up resistor at pad. +* By default=0 the pull-up resistor is enabled at reset. +* Available to normal-drive pins, high-drive pins, high-speed pins +*/ +#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) + +/* +* Select Slew Rate. +* By Default=0 Slow. +* Available to normal-drive pins and high-speed pins, reserved for high-drive pins. +*/ +#define SCU_CONF_EHS_FAST (BIT5) /* - * Input buffer enable. - * By Default=0 Disable Input Buffer. - * The input buffer is disabled by default at reset and must be enabled. - * for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins). - * Available to normal-drive pins, high-drive pins, high-speed pins. - */ -#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) +* Input buffer enable. +* By Default=0 Disable Input Buffer. +* The input buffer is disabled by default at reset and must be enabled. +* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins). +* Available to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) /* - * Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. - * Available to normal-drive pins, high-drive pins, high-speed pins. - */ -#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) +* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. +* Available to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) /* - * Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9). - * Available to high-drive pins, reserved for others. - */ -#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) -#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) -#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) +* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9). +* Available to high-drive pins, reserved for others. +*/ +#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) +#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) +#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) /* BIT10 to 31 are Reserved */ /* Configuration for different I/O pins types */ -#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf); diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h index f645e4c..6a1510c 100644 --- a/include/libopencm3/lpc43xx/ssp.h +++ b/include/libopencm3/lpc43xx/ssp.h @@ -1,21 +1,21 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Michael Ossmann +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ #ifndef LPC43XX_SSP_H #define LPC43XX_SSP_H @@ -26,60 +26,150 @@ /* --- Convenience macros -------------------------------------------------- */ /* SSP port base addresses (for convenience) */ -#define SSP0 SSP0_BASE -#define SSP1 SSP1_BASE +#define SSP0 SSP0_BASE +#define SSP1 SSP1_BASE /* --- SSP registers ------------------------------------------------------- */ /* Control Register 0 */ -#define SSP_CR0(port) MMIO32(port + 0x000) -#define SSP0_CR0 SSP_CR0(SSP0) -#define SSP1_CR0 SSP_CR0(SSP1) +#define SSP_CR0(port) MMIO32(port + 0x000) +#define SSP0_CR0 SSP_CR0(SSP0) +#define SSP1_CR0 SSP_CR0(SSP1) /* Control Register 1 */ -#define SSP_CR1(port) MMIO32(port + 0x004) -#define SSP0_CR1 SSP_CR1(SSP0) -#define SSP1_CR1 SSP_CR1(SSP1) +#define SSP_CR1(port) MMIO32(port + 0x004) +#define SSP0_CR1 SSP_CR1(SSP0) +#define SSP1_CR1 SSP_CR1(SSP1) /* Data Register */ -#define SSP_DR(port) MMIO32(port + 0x008) -#define SSP0_DR SSP_DR(SSP0) -#define SSP1_DR SSP_DR(SSP1) +#define SSP_DR(port) MMIO32(port + 0x008) +#define SSP0_DR SSP_DR(SSP0) +#define SSP1_DR SSP_DR(SSP1) /* Status Register */ -#define SSP_SR(port) MMIO32(port + 0x00C) -#define SSP0_SR SSP_SR(SSP0) -#define SSP1_SR SSP_SR(SSP1) +#define SSP_SR(port) MMIO32(port + 0x00C) +#define SSP0_SR SSP_SR(SSP0) +#define SSP1_SR SSP_SR(SSP1) + +#define SSP_SR_TFE BIT0 +#define SSP_SR_TNF BIT1 +#define SSP_SR_RNE BIT2 +#define SSP_SR_RFF BIT3 +#define SSP_SR_BSY BIT4 /* Clock Prescale Register */ -#define SSP_CPSR(port) MMIO32(port + 0x010) -#define SSP0_CPSR SSP_CPSR(SSP0) -#define SSP1_CPSR SSP_CPSR(SSP1) +#define SSP_CPSR(port) MMIO32(port + 0x010) +#define SSP0_CPSR SSP_CPSR(SSP0) +#define SSP1_CPSR SSP_CPSR(SSP1) /* Interrupt Mask Set and Clear Register */ -#define SSP_IMSC(port) MMIO32(port + 0x014) -#define SSP0_IMSC SSP_IMSC(SSP0) -#define SSP1_IMSC SSP_IMSC(SSP1) +#define SSP_IMSC(port) MMIO32(port + 0x014) +#define SSP0_IMSC SSP_IMSC(SSP0) +#define SSP1_IMSC SSP_IMSC(SSP1) /* Raw Interrupt Status Register */ -#define SSP_RIS(port) MMIO32(port + 0x018) -#define SSP0_RIS SSP_RIS(SSP0) -#define SSP1_RIS SSP_RIS(SSP1) +#define SSP_RIS(port) MMIO32(port + 0x018) +#define SSP0_RIS SSP_RIS(SSP0) +#define SSP1_RIS SSP_RIS(SSP1) /* Masked Interrupt Status Register */ -#define SSP_MIS(port) MMIO32(port + 0x01C) -#define SSP0_MIS SSP_MIS(SSP0) -#define SSP1_MIS SSP_MIS(SSP1) +#define SSP_MIS(port) MMIO32(port + 0x01C) +#define SSP0_MIS SSP_MIS(SSP0) +#define SSP1_MIS SSP_MIS(SSP1) /* SSPICR Interrupt Clear Register */ -#define SSP_ICR(port) MMIO32(port + 0x020) -#define SSP0_ICR SSP_ICR(SSP0) -#define SSP1_ICR SSP_ICR(SSP1) +#define SSP_ICR(port) MMIO32(port + 0x020) +#define SSP0_ICR SSP_ICR(SSP0) +#define SSP1_ICR SSP_ICR(SSP1) /* SSP1 DMA control register */ -#define SSP_DMACR(port) MMIO32(port + 0x024) -#define SSP0_DMACR SSP_DMACR(SSP0) -#define SSP1_DMACR SSP_DMACR(SSP1) +#define SSP_DMACR(port) MMIO32(port + 0x024) +#define SSP0_DMACR SSP_DMACR(SSP0) +#define SSP1_DMACR SSP_DMACR(SSP1) + +typedef enum { + SSP0_NUM = 0x0, + SSP1_NUM = 0x1 +} ssp_num_t; + +/* +* SSP Control Register 0 +*/ +/* SSP Data Size Bits 0 to 3 */ +typedef enum { + SSP_DATA_4BITS = 0x3, + SSP_DATA_5BITS = 0x4, + SSP_DATA_6BITS = 0x5, + SSP_DATA_7BITS = 0x6, + SSP_DATA_8BITS = 0x7, + SSP_DATA_9BITS = 0x8, + SSP_DATA_10BITS = 0x9, + SSP_DATA_11BITS = 0xA, + SSP_DATA_12BITS = 0xB, + SSP_DATA_13BITS = 0xC, + SSP_DATA_14BITS = 0xD, + SSP_DATA_15BITS = 0xE, + SSP_DATA_16BITS = 0xF +} ssp_datasize_t; + +/* SSP Frame Format/Type Bits 4 & 5 */ +typedef enum { + SSP_FRAME_SPI = 0x00, + SSP_FRAME_TI = BIT4, + SSP_FRAM_MICROWIRE = BIT5 +} ssp_frame_format_t; + +/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */ +typedef enum { + SSP_CPOL_0_CPHA_0 = 0x0, + SSP_CPOL_1_CPHA_0 = BIT6, + SSP_CPOL_0_CPHA_1 = BIT7, + SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) +} ssp_cpol_cpha_t; + +/* +* SSP Control Register 1 +*/ +/* SSP Mode Bit0 */ +typedef enum { + SSP_MODE_NORMAL = 0x0, + SSP_MODE_LOOPBACK = BIT0 +} ssp_mode_t; + +/* SSP Enable Bit1 */ +#define SSP_ENABLE BIT1 + +/* SSP Master/Slave Mode Bit2 */ +typedef enum { + SSP_MASTER = 0x0, + SSP_SLAVE = BIT2 +} ssp_master_slave_t; + +/* +* SSP Slave Output Disable Bit3 +* Slave Output Disable. This bit is relevant only in slave mode +* (MS = 1). If it is 1, this blocks this SSP controller from driving the +* transmit data line (MISO). +*/ +typedef enum { + SSP_SLAVE_OUT_ENABLE = 0x0, + SSP_SLAVE_OUT_DISABLE = BIT3 +} ssp_slave_option_t; /* This option is relevant only in slave mode */ + +void ssp_disable(ssp_num_t ssp_num); + +void ssp_init( ssp_num_t ssp_num, + ssp_datasize_t data_size, + ssp_frame_format_t frame_format, + ssp_cpol_cpha_t cpol_cpha_format, + u8 serial_clock_rate, + ssp_mode_t mode, + ssp_master_slave_t master_slave, + ssp_slave_option_t slave_option); + +u16 ssp_read(ssp_num_t ssp_num); + +void ssp_write(ssp_num_t ssp_num, u16 data); #endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 041e3bc..54c788b 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o +OBJS = gpio.o vector.o scu.o ssp.o # VPATH += ../usb diff --git a/lib/lpc43xx/scu.c b/lib/lpc43xx/scu.c index bc495cd..addf5e2 100644 --- a/lib/lpc43xx/scu.c +++ b/lib/lpc43xx/scu.c @@ -1,28 +1,28 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Benjamin Vernoux +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ #include /* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */ void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf) { - MMIO32(group_pin) = scu_conf; + MMIO32(group_pin) = scu_conf; } /* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */ diff --git a/lib/lpc43xx/ssp.c b/lib/lpc43xx/ssp.c new file mode 100644 index 0000000..ba7026e --- /dev/null +++ b/lib/lpc43xx/ssp.c @@ -0,0 +1,132 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#define CGU_SRC_32K 0x00 +#define CGU_SRC_IRC 0x01 +#define CGU_SRC_ENET_RX 0x02 +#define CGU_SRC_ENET_TX 0x03 +#define CGU_SRC_GP_CLKIN 0x04 +#define CGU_SRC_XTAL 0x06 +#define CGU_SRC_PLL0USB 0x07 +#define CGU_SRC_PLL0AUDIO 0x08 +#define CGU_SRC_PLL1 0x09 +#define CGU_SRC_IDIVA 0x0C +#define CGU_SRC_IDIVB 0x0D +#define CGU_SRC_IDIVC 0x0E +#define CGU_SRC_IDIVD 0x0F +#define CGU_SRC_IDIVE 0x10 + +#define CGU_AUTOBLOCK_CLOCK_BIT 11 +#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ + +/* Disable SSP */ +void ssp_disable(ssp_num_t ssp_num) +{ + u32 ssp_port; + + if(ssp_num == SSP0_NUM) + { + ssp_port = SSP0; + }else + { + ssp_port = SSP1; + } + /* Disable SSP */ + SSP_CR1(ssp_port) = 0x0; +} + +/* +* SSP Init function +*/ +void ssp_init(ssp_num_t ssp_num, + ssp_datasize_t data_size, + ssp_frame_format_t frame_format, + ssp_cpol_cpha_t cpol_cpha_format, + u8 serial_clock_rate, + ssp_mode_t mode, + ssp_master_slave_t master_slave, + ssp_slave_option_t slave_option) +{ + u32 ssp_port; + u32 clock; + + if(ssp_num == SSP0_NUM) + { + ssp_port = SSP0; + }else + { + ssp_port = SSP1; + } + + /* use PLL1 as clock source for SSP1 */ + CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1< + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * This is a very minimal I2C driver just to make sure we can get the + * peripheral working. + */ + +#include +#include +#include + +void i2c0_init(void) +{ + /* enable input on SCL and SDA pins */ + SCU_SFSI2C0 = SCU_I2C0_NOMINAL; + + /* use PLL1 as clock source for APB1 (including I2C0) */ + CGU_BASE_APB1_CLK = (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT); + + /* FIXME assuming we're on IRC at 96 MHz */ + + /* 400 kHz I2C */ + /* + I2C0_SCLH = 120; + I2C0_SCLL = 120; + */ + + /* 100 kHz I2C */ + I2C0_SCLH = 480; + I2C0_SCLL = 480; + /* FIXME not sure why this appears to run at about 290 kHz */ + + /* clear the control bits */ + I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC + | I2C_CONCLR_STAC | I2C_CONCLR_I2ENC); + + /* enable I2C0 */ + I2C0_CONSET = I2C_CONSET_I2EN; +} + +/* transmit start bit */ +void i2c0_tx_start(void) +{ + I2C0_CONCLR = I2C_CONCLR_SIC; + I2C0_CONSET = I2C_CONSET_STA; + while (!(I2C0_CONSET & I2C_CONSET_SI)); + I2C0_CONCLR = I2C_CONCLR_STAC; +} + +/* transmit data byte */ +void i2c0_tx_byte(u8 byte) +{ + if (I2C0_CONSET & I2C_CONSET_STA) + I2C0_CONCLR = I2C_CONCLR_STAC; + I2C0_DAT = byte; + I2C0_CONCLR = I2C_CONCLR_SIC; + while (!(I2C0_CONSET & I2C_CONSET_SI)); +} + +/* receive data byte */ +u8 i2c0_rx_byte(void) +{ + if (I2C0_CONSET & I2C_CONSET_STA) + I2C0_CONCLR = I2C_CONCLR_STAC; + I2C0_CONCLR = I2C_CONCLR_SIC; + while (!(I2C0_CONSET & I2C_CONSET_SI)); + return I2C0_DAT; +} + +/* transmit stop bit */ +void i2c0_stop(void) +{ + if (I2C0_CONSET & I2C_CONSET_STA) + I2C0_CONCLR = I2C_CONCLR_STAC; + I2C0_CONSET = I2C_CONSET_STO; + I2C0_CONCLR = I2C_CONCLR_SIC; +} -- cgit v1.2.3 From 8adc873e843ea8599e7e658d00b66bebe86c2f62 Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Wed, 6 Jun 2012 00:30:25 +0200 Subject: Fixed SSP, tested with Oscilloscope Write work fine (tested SPI Mode). For more details on tests see ssp/README. --- examples/lpc43xx/hackrf-jellybean/ssp/README | 28 +++++++++++++++++++++++++ examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c | 25 ++++++++++++---------- include/libopencm3/lpc43xx/scu.h | 2 +- include/libopencm3/lpc43xx/ssp.h | 6 ++++++ lib/lpc43xx/ssp.c | 2 ++ 5 files changed, 51 insertions(+), 12 deletions(-) (limited to 'lib/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/README b/examples/lpc43xx/hackrf-jellybean/ssp/README index 9b43214..5354a53 100644 --- a/examples/lpc43xx/hackrf-jellybean/ssp/README +++ b/examples/lpc43xx/hackrf-jellybean/ssp/README @@ -18,3 +18,31 @@ SSP1_MOSI: Jellybean P9 SPI Pin4 SSP1_SCK: Jellybean P9 SPI Pin2 SSP1_SSEL: Jellybean P9 SPI Pin3 GND: Can be connected to P12 SD Pin1 + +PCLK clock source is PLL1 288MHz (from IRC 96MHz boot from SPIFI) +Freq = PCLK / (CPSDVSR * [SCR+1]). + +By default (CPSDVSR=0 => Means MAX Divisor) +SSP1->CR0->SCR = 0x00 => CLK Freq 1.126MHz +SSP1->CR0->SCR = 0x01 => MOSI Freq 566.9KHz +... + +Test Oscilloscpe: +SCR=0, CPSDVSR=32 => CLK 9.025MHz +SCR=1, CPSDVSR=2 => CLK 73MHz +SCR=2, CPSDVSR=2 => CLK 49MHz +SCR=4, CPSDVSR=2 => CLK 29MHz +SCR=8, CPSDVSR=2 => CLK 16MHz +SCR=16, CPSDVSR=2 => CLK 8.5MHz +SCR=32, CPSDVSR=2 => CLK 4.386MHz +SCR=64, CPSDVSR=2 => CLK 2.227MHz +SCR=1, CPSDVSR=64 => CLK 2.262MHz + +Theory: +SCR=0, CPSDVSR=32 => 288MHz / (32*(0+1) = 9MHz +SCR=1, CPSDVSR=2 => 288MHz / (2*(1+1) = 72MHz +SCR=4, CPSDVSR=2 => 288MHz / (2*(4+1) = 28.8MHz +SCR=32, CPSDVSR=2 => 288MHz / (2*(32+1) = 4.364MHz +SCR=64, CPSDVSR=2 => 288MHz / (2*(64+1)) = 2.2154MHz +SCR=128, CPSDVSR=2 => 288MHz / (2*(128+1)) = 1.116MHz +SCR=1, CPSDVSR=64 => 288MHz / (64*(1+1)) = 2.25MHz diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c index 388afc8..cdb3702 100644 --- a/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c @@ -26,6 +26,16 @@ void gpio_setup(void) { + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + /* Configure SCU Pin Mux as GPIO */ scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); @@ -44,16 +54,6 @@ void gpio_setup(void) scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); - /* Configure all GPIO as Input (safe state) */ - GPIO0_DIR = 0; - GPIO1_DIR = 0; - GPIO2_DIR = 0; - GPIO3_DIR = 0; - GPIO4_DIR = 0; - GPIO5_DIR = 0; - GPIO6_DIR = 0; - GPIO7_DIR = 0; - /* Configure GPIO as Output */ GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ @@ -64,10 +64,12 @@ int main(void) int i; u8 ssp_val; u8 serial_clock_rate; + u8 clock_prescale_rate; gpio_setup(); - /* FIX Me freq */ + /* Freq About 1.12MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=288MHz */ + clock_prescale_rate = 2; serial_clock_rate = 128; ssp_init(SSP1_NUM, @@ -75,6 +77,7 @@ int main(void) SSP_FRAME_SPI, SSP_CPOL_0_CPHA_0, serial_clock_rate, + clock_prescale_rate, SSP_MODE_NORMAL, SSP_MASTER, SSP_SLAVE_OUT_ENABLE); diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index 641331a..6e1be7f 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -723,7 +723,7 @@ typedef enum { #define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) #define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) #define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf); diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h index 338fd88..ed69668 100644 --- a/include/libopencm3/lpc43xx/ssp.h +++ b/include/libopencm3/lpc43xx/ssp.h @@ -159,11 +159,17 @@ typedef enum { void ssp_disable(ssp_num_t ssp_num); +/* + * SSP Init + * clk_prescale shall be in range 2 to 254 (even number only). + * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, SCR=serial_clock_rate + */ void ssp_init(ssp_num_t ssp_num, ssp_datasize_t data_size, ssp_frame_format_t frame_format, ssp_cpol_cpha_t cpol_cpha_format, u8 serial_clock_rate, + u8 clk_prescale, ssp_mode_t mode, ssp_master_slave_t master_slave, ssp_slave_option_t slave_option); diff --git a/lib/lpc43xx/ssp.c b/lib/lpc43xx/ssp.c index ba7026e..592b5d8 100644 --- a/lib/lpc43xx/ssp.c +++ b/lib/lpc43xx/ssp.c @@ -62,6 +62,7 @@ void ssp_init(ssp_num_t ssp_num, ssp_frame_format_t frame_format, ssp_cpol_cpha_t cpol_cpha_format, u8 serial_clock_rate, + u8 clk_prescale, ssp_mode_t mode, ssp_master_slave_t master_slave, ssp_slave_option_t slave_option) @@ -85,6 +86,7 @@ void ssp_init(ssp_num_t ssp_num, /* Configure SSP */ clock = serial_clock_rate; + SSP_CPSR(ssp_port) = clk_prescale; SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8) ); /* Enable SSP */ -- cgit v1.2.3 From 251687fe37af0c2869c46f27e52d35c2a4679fcf Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Wed, 6 Jun 2012 22:05:03 -0600 Subject: changed I2C to run directly from IRC --- lib/lpc43xx/i2c.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/i2c.c b/lib/lpc43xx/i2c.c index 9d742e0..f006615 100644 --- a/lib/lpc43xx/i2c.c +++ b/lib/lpc43xx/i2c.c @@ -31,21 +31,20 @@ void i2c0_init(void) /* enable input on SCL and SDA pins */ SCU_SFSI2C0 = SCU_I2C0_NOMINAL; - /* use PLL1 as clock source for APB1 (including I2C0) */ - CGU_BASE_APB1_CLK = (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT); + /* use IRC as clock source for APB1 (including I2C0) */ + CGU_BASE_APB1_CLK = (CGU_SRC_IRC << CGU_BASE_CLK_SEL_SHIFT); - /* FIXME assuming we're on IRC at 96 MHz */ + /* FIXME assuming we're on IRC at 12 MHz */ /* 400 kHz I2C */ - /* - I2C0_SCLH = 120; - I2C0_SCLL = 120; - */ + I2C0_SCLH = 15; + I2C0_SCLL = 15; /* 100 kHz I2C */ - I2C0_SCLH = 480; - I2C0_SCLL = 480; - /* FIXME not sure why this appears to run at about 290 kHz */ + /* + I2C0_SCLH = 60; + I2C0_SCLL = 60; + */ /* clear the control bits */ I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC -- cgit v1.2.3 From 8d97dbc7c31d814e521ad9792fcf1914543288bf Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Sat, 9 Jun 2012 18:27:42 +0200 Subject: Work on scs.h register and also nvic.h. ARM Interrupt API (see nvic.h). ARM SysTick API (see systick.h). Example using both Interrupt and SysTick and blink LED1/2/3 see systickdemo.c. --- examples/lpc43xx/hackrf-jellybean/systick/Makefile | 24 ++ examples/lpc43xx/hackrf-jellybean/systick/README | 8 + .../lpc43xx/hackrf-jellybean/systick/systickdemo.c | 184 ++++++++++++++++ include/libopencm3/cm3/scs.h | 242 +++++++++++++++++++++ include/libopencm3/lpc43xx/nvic.h | 53 +++++ include/libopencm3/lpc43xx/systick.h | 84 +++++++ lib/lpc43xx/Makefile | 2 +- lib/lpc43xx/nvic.c | 76 +++++++ lib/lpc43xx/systick.c | 69 ++++++ 9 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/README create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c create mode 100644 include/libopencm3/lpc43xx/systick.h create mode 100644 lib/lpc43xx/nvic.c create mode 100644 lib/lpc43xx/systick.c (limited to 'lib/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/systick/Makefile b/examples/lpc43xx/hackrf-jellybean/systick/Makefile new file mode 100644 index 0000000..93b471e --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2012 Benjamin Vernoux +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = systickdemo + +LDSCRIPT = ../jellybean-lpc4330.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/systick/README b/examples/lpc43xx/hackrf-jellybean/systick/README new file mode 100644 index 0000000..8c32cdc --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/README @@ -0,0 +1,8 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This program exercises the SysTick Interrupt of ARM CortexM4 on Jellybean's LPC43xx. +It also enable Cycle Counter to be used for accurate delay independant from Clock Frequency. +The Demo Use Cycle Counter and SysTick Interrupt to compute number of cycles executed per second. +The result is LED1/2 & 3 Blink with an accurate 1s Period (using SysTick) (Checked visualy and with Oscilloscope). diff --git a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c new file mode 100644 index 0000000..66c8e06 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c @@ -0,0 +1,184 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include "../jellybean_conf.h" + +/* Global counter incremented by SysTick Interrupt each millisecond */ +volatile u32 g_ulSysTickCount; +u32 g_NbCyclePerSecond; + +void gpio_setup(void) +{ + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ +} + +void systick_setup(void) +{ + u32 systick_reload_val; + g_ulSysTickCount = 0; + + /* Disable IRQ globally */ + asm volatile ("cpsid i"); + + /* Set processor Clock as Source Clock */ + systick_set_clocksource(STK_CTRL_CLKSOURCE); + + /* Get SysTick calibration value to obtain by default 1 tick = 10ms */ + systick_reload_val = systick_get_calib(); + /* + * Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*8=96MHz + * Fix the Calibration value bu multiplication by 8 + */ + systick_reload_val = (systick_reload_val*8); + + /* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */ + systick_reload_val = systick_reload_val/10; + systick_set_reload(systick_reload_val); + + systick_interrupt_enable(); + + /* Start counting. */ + systick_counter_enable(); + + /* Set SysTick Priority to maximum */ + nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF); + + /* Enable IRQ globally */ + asm volatile ("cpsie i"); +} + +void scs_dwt_cycle_counter_enabled(void) +{ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA; +} + +u32 sys_tick_get_time_ms(void) +{ + return g_ulSysTickCount; +} + +u32 sys_tick_delta_time_ms(u32 start, u32 end) +{ + #define MAX_T_U32 ((2^32)-1) + u32 diff; + + if(end > start) + { + diff=end-start; + }else + { + diff=MAX_T_U32-(start-end)+1; + } + + return diff; +} + +void sys_tick_wait_time_ms(u32 wait_ms) +{ + u32 start, end; + u32 tickms; + + start = sys_tick_get_time_ms(); + + do + { + end = sys_tick_get_time_ms(); + tickms = sys_tick_delta_time_ms(start, end); + }while(tickms < wait_ms); +} + +/* Called each 1ms/1000Hz by interrupt + 1) Count the number of cycle per second. + 2) Increment g_ulSysTickCount counter. +*/ +void sys_tick_handler(void) +{ + if(g_ulSysTickCount==0) + { + /* Clear Cycle Counter*/ + SCS_DWT_CYCCNT = 0; + }else if(g_ulSysTickCount==1000) + { + /* Capture number of cycle elapsed during 1 second */ + g_NbCyclePerSecond = SCS_DWT_CYCCNT; + } + + g_ulSysTickCount++; +} + +int main(void) +{ + systick_setup(); + + gpio_setup(); + + /* SCS & Cycle Counter enabled (used to count number of cycles executed per second see g_NbCyclePerSecond */ + scs_dwt_cycle_counter_enabled(); + + while (1) + { + gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ + + sys_tick_wait_time_ms(500); + + gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */ + + sys_tick_wait_time_ms(500); + } + + return 0; +} diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h index 033ec73..fff4a1b 100644 --- a/include/libopencm3/cm3/scs.h +++ b/include/libopencm3/cm3/scs.h @@ -2,6 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -20,9 +21,85 @@ #ifndef LIBOPENCM3_CM3_SCS_H #define LIBOPENCM3_CM3_SCS_H +/* + * All the definition hereafter are generic for CortexMx ARMv7-M + * See ARM document "ARMv7-M Architecture Reference Manual" for more details. + * See also ARM document "ARM Compiler toolchain Developing Software for ARM Processors" for details on System Timer/SysTick. + */ + +/* + * The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for + * configuration, status reporting and control. The SCS registers divide into the following groups: + * - system control and identification + * - the CPUID processor identification space + * - system configuration and status + * - fault reporting + * - a system timer, SysTick + * - a Nested Vectored Interrupt Controller (NVIC) + * - a Protected Memory System Architecture (PMSA) + * - system debug. + */ + +/* System Handler Priority 8 bits Registers, SHPR1/2/3 */ +/* Note: 12 8bit Registers */ +#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id) + +/* + * Debug Halting Control and Status Register (DHCSR). + * + * Purpose Controls halting debug. + * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when the system + * is running with halting debug enabled is UNPREDICTABLE. + * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running when S_HALT is set to 0. + * - When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this register. + * - For more information about the use of DHCSR see Debug stepping on + * page C1-824. + * Configurations Always implemented. + */ +/* SCS_DHCSR register */ #define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0) +/* + * Debug Core Register Selector Register (DCRSR). + * + * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core registers, + * special-purpose registers, and Floating-point extension registers. A write to DCRSR + * specifies the register to transfer, whether the transfer is a read or a write, and starts + * the transfer. + * Usage constraints: Only accessible in Debug state. + * Configurations Always implemented. + * + */ +/* SCS_DCRS register */ #define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4) +/* + * Debug Core Register Data Register (DCRDR) + * + * Purpose With the DCRSR, see Debug Core Register Selector Register, + * the DCRDR provides debug access to the ARM core registers, + * special-purpose registers, and Floating-point extension registers. The + * DCRDR is the data register for these accesses. + * - Used on its own, the DCRDR provides a message passing resource between + * an external debugger and a debug agent running on the processor. + * Note: + * The architecture does not define any handshaking mechanism for this use of DCRDR. + * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to + * particular transfers using the DCRSR and DCRDR. + * Configurations Always implemented. + * + */ +/* SCS_DCRDR register */ #define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8) +/* + * Debug Exception and Monitor Control Register (DEMCR). + * + * Purpose Manages vector catch behavior and DebugMonitor handling when debugging. + * Usage constraints: + * - Bits [23:16] provide DebugMonitor exception control. + * - Bits [15:0] provide Debug state, halting debug, control. + * Configurations Always implemented. + * + */ +/* SCS_DEMCR register */ #define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC) /* Debug Halting Control and Status Register (DHCSR) */ @@ -64,4 +141,169 @@ /* Bits 3:1 - Reserved */ #define SCS_DEMCR_VC_CORERESET (1 << 0) +/* + * System Control Space (SCS) => System timer register support in the SCS. + * To configure SysTick, load the interval required between SysTick events to the SysTick Reload + * Value register. The timer interrupt, or COUNTFLAG bit in the SysTick Control and Status + * register, is activated on the transition from 1 to 0, therefore it activates every n+1 clock ticks. + * If you require a period of 100, write 99 to the SysTick Reload Value register. The SysTick Reload + * Value register supports values between 0x1 and 0x00FFFFFF. + * + * If you want to use SysTick to generate an event at a timed interval, for example 1ms, you can + * use the SysTick Calibration Value Register to scale your value for the Reload register. The + * SysTick Calibration Value Register is a read-only register that contains the number of pulses for + * a period of 10ms, in the TENMS field, bits[23:0]. + * + * This register also has a SKEW bit. Bit[30] == 1 indicates that the calibration for 10ms in the + * TENMS section is not exactly 10ms due to clock frequency. Bit[31] == 1 indicates that the + * reference clock is not provided. + */ +/* + * SysTick Control and Status Register (CSR). + * Purpose Controls the system timer and provides status data. + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. +*/ +#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10) + +/* SysTick Reload Value Register (CVR). + * Purpose Reads or clears the current counter value. + * Usage constraints: + * - Any write to the register clears the register to zero. + * - The counter does not provide read-modify-write protection. + * - Unsupported bits are read as zero + * Configurations Always implemented. + */ +#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14) + +/* SysTick Current Value Register (RVR). + * Purpose Holds the reload value of the SYST_CVR. + * Usage constraints There are no usage constraints. + * Configurations Always implemented. + */ +#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18) + +/* + * SysTick Calibration value Register(Read Only) (CALIB) + * Purpose Reads the calibration value and parameters for SysTick. + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. + */ +#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C) + +/* --- SCS_SYST_CSR values ----------------------------------------------- */ +/* Counter is operating. */ +#define SCS_SYST_CSR_ENABLE (BIT0) +/* Count to 0 changes the SysTick exception status to pending. */ +#define SCS_SYST_CSR_TICKINT (BIT1) +/* SysTick uses the processor clock. */ +#define SCS_SYST_CSR_CLKSOURCE (BIT2) +/* + * Indicates whether the counter has counted to 0 since the last read of this register: + * 0 = Timer has not counted to 0 + * 1 = Timer has counted to 0. + */ +#define SCS_SYST_CSR_COUNTFLAG (BIT16) + +/* --- CM_SCS_SYST_RVR values ----------------------------------------------- */ +/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter reaches 0. */ +/* Bit 24 to 31 are Reserved */ + +/* --- CM_SCS_SYST_CVR values ----------------------------------------------- */ +/* Bit0 to 31 => Reads or clears the current counter value. */ + +/* --- CM_SCS_SYST_CALIB values ----------------------------------------------- */ +/* + * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock + * skew errors. If this field is zero, the calibration value is not known. + */ +#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1) + +/* + * Bit30 => SKEW Indicates whether the 10ms calibration value is exact: + * 0 = 10ms calibration value is exact. + * 1 = 10ms calibration value is inexact, because of the clock frequency + */ +#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30) +/* + * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented: + * 0 = The reference clock is implemented. + * 1 = The reference clock is not implemented. + * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot + * be cleared to 0. + */ +#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31) + +/* + * System Control Space (SCS) => Data Watchpoint and Trace (DWT). + * See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html (ARMv7-M Architecture Reference Manual) + * The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling + * for the processor. + */ +/* + * DWT Control register + * Purpose Provides configuration and status information for the DWT block, and used to control features of the block + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. + */ +#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00) +/* + * DWT_CYCCNT register + * Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT) + * When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero. + * + * Purpose Shows or sets the value of the processor cycle counter, CYCCNT. + * Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state. + * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL. + * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP. +*/ +#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04) + +/* DWT_CPICNT register + * Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls. + * Usage constraints: The counter initializes to 0 when software enables its counter overflow event by + * setting the DWT_CTRL.CPIEVTENA bit to 1. + * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL. + * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not + * include the profiling counters, this register is UNK/SBZP. + */ +#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08) + +/* DWT_EXCCNT register */ +#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C) + +/* DWT_EXCCNT register */ +#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10) + +/* DWT_EXCCNT register */ +#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14) + +/* DWT_EXCCNT register */ +#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18) + +/* DWT_PCSR register */ +#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18) + +/* --- SCS_DWT_CTRL values ----------------------------------------------- */ +/* + * Enables CYCCNT: + * 0 = Disabled, 1 = Enabled + * This bit is UNK/SBZP if the NOCYCCNT bit is RAO. + */ +#define SCS_DWT_CTRL_CYCCNTENA (BIT0) + +/* TODO bit definition values for other DWT_XXX register */ + +/* Macro to be called at startup to enable SCS & Cycle Counter */ +#define SCS_DWT_CYCLE_COUNTER_ENABLED() ( (SCS_DEMCR |= SCS_DEMCR_TRCENA)\ + (SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA) ) + +#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR=0) + +/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not enabled) */ +#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE)) + +/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */ +#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE | SCS_SYST_CSR_TICKINT)) + #endif diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index 336eab8..b996ab8 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -3,6 +3,7 @@ * * Copyright (C) 2010 Piotr Esden-Tempski * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -22,8 +23,48 @@ #define LPC43XX_NVIC_H #include +#include #include +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M4 System Interrupts */ @@ -91,4 +132,16 @@ /* LPC43xx M0 specific user interrupts */ //TODO +/* --- NVIC functions ------------------------------------------------------ */ + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u8 irqn); + #endif diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h new file mode 100644 index 0000000..9f8b38d --- /dev/null +++ b/include/libopencm3/lpc43xx/systick.h @@ -0,0 +1,84 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ +/* See also libopencm3\cm3\scs.h for details on SysTicks registers */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +u32 systick_get_calib(void); + +#endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 38d5bf7..e8bd8fc 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o i2c.o ssp.o +OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o # VPATH += ../usb diff --git a/lib/lpc43xx/nvic.c b/lib/lpc43xx/nvic.c new file mode 100644 index 0000000..4793312 --- /dev/null +++ b/lib/lpc43xx/nvic.c @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Fergus Noble + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +#include +#include + +void nvic_enable_irq(u8 irqn) +{ + NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); +} + +void nvic_disable_irq(u8 irqn) +{ + NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); +} + +u8 nvic_get_pending_irq(u8 irqn) +{ + return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +void nvic_set_pending_irq(u8 irqn) +{ + NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); +} + +void nvic_clear_pending_irq(u8 irqn) +{ + NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); +} + +u8 nvic_get_active_irq(u8 irqn) +{ + return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +u8 nvic_get_irq_enabled(u8 irqn) +{ + return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +void nvic_set_priority(u8 irqn, u8 priority) +{ + if(irqn>NVIC_M4_QEI_IRQ) + { + /* Cortex-M system interrupts */ + SCS_SHPR( (irqn&0xF)-4 ) = priority; + }else + { + /* Device specific interrupts */ + NVIC_IPR(irqn) = priority; + } +} + +void nvic_generate_software_interrupt(u8 irqn) +{ + if (irqn <= 239) + NVIC_STIR |= irqn; +} diff --git a/lib/lpc43xx/systick.c b/lib/lpc43xx/systick.c new file mode 100644 index 0000000..82345a9 --- /dev/null +++ b/lib/lpc43xx/systick.c @@ -0,0 +1,69 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +void systick_set_clocksource(u8 clocksource) +{ + STK_CTRL |= clocksource; +} + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} + +u32 systick_get_calib(void) +{ + return (STK_CALIB&0x00FFFFFF); +} -- cgit v1.2.3 From 3c8e76f679158d2a5cb1a16a7da1c4f48066ddfc Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Sun, 10 Jun 2012 11:44:36 +0200 Subject: Added ROM to RAM code copy & exec with example of how to use it (miniblink_rom_to_ram). --- .../jellybean-lpc4330_rom_to_ram.ld | 35 ++++++++ .../hackrf-jellybean/miniblink_rom_to_ram/Makefile | 24 ++++++ .../hackrf-jellybean/miniblink_rom_to_ram/README | 12 +++ .../miniblink_rom_to_ram/miniblink.c | 82 ++++++++++++++++++ lib/lpc43xx/libopencm3_lpc43xx.ld | 4 + lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld | 97 ++++++++++++++++++++++ lib/lpc43xx/vector.c | 19 +++++ 7 files changed, 273 insertions(+) create mode 100644 examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/README create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/miniblink.c create mode 100644 lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld (limited to 'lib/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld new file mode 100644 index 0000000..385b081 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 264K SRAM). */ + +/* Define memory regions. */ +MEMORY +{ + /* Physical address in Flash used to copy Code from Flash to RAM */ + rom_flash (rx) : ORIGIN = 0x80000000, LENGTH = 1M + /* rom is really the shadow region that points to SPI flash or elsewhere */ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M + ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K + /* there are some additional RAM regions */ +} + +/* Include the common ld script. */ +INCLUDE libopencm3_lpc43xx_rom_to_ram.ld diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/Makefile b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/Makefile new file mode 100644 index 0000000..56cb540 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2010 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = miniblink + +LDSCRIPT = ../jellybean-lpc4330_rom_to_ram.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/README b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/README new file mode 100644 index 0000000..02960fa --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/README @@ -0,0 +1,12 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + +It's intended for the Jellybean development board from the HackRF project: + +https://github.com/mossmann/hackrf + +It should blink LED1 on the board. +This example copy the Code from ROM to RAM and execute code from RAM. diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/miniblink.c new file mode 100644 index 0000000..3b3919b --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/miniblink.c @@ -0,0 +1,82 @@ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2010 Uwe Hermann +* Copyright (C) 2012 Michael Ossmann +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ + +#include +#include + +#include "../jellybean_conf.h" + +void gpio_setup(void) +{ + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ +} + +u32 boot0, boot1, boot2, boot3; + +int main(void) +{ + int i; + gpio_setup(); + + /* Set 1V8 */ + gpio_set(PORT_EN1V8, PIN_EN1V8); + + /* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */ + while (1) + { + boot0 = BOOT0_STATE; + boot1 = BOOT1_STATE; + boot2 = BOOT2_STATE; + boot3 = BOOT3_STATE; + + gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld index 5c3221b..47b403b 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -35,6 +36,7 @@ SECTIONS .text : { . = ALIGN(0x400); + _text_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); @@ -50,6 +52,8 @@ SECTIONS __exidx_end = .; _etext = .; + _etext_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ + _etext_rom = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ . = ORIGIN(ram); diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld new file mode 100644 index 0000000..f833aaf --- /dev/null +++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld @@ -0,0 +1,97 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Generic linker script for LPC43XX targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + . = ALIGN(0x400); + _text_ram = . + ORIGIN(ram); /* Start of Code in RAM */ + + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + } >rom + + /* exception index - required due to libgcc.a issuing /0 exceptions */ + __exidx_start = .; + .ARM.exidx : { + *(.ARM.exidx*) + } > rom + __exidx_end = .; + + _etext = .; + _etext_ram = . + ORIGIN(ram); + _etext_rom = . + ORIGIN(rom_flash); + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + . = ALIGN(4); + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram + + /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ + .ARM.extab : { + *(.ARM.extab*) + } >ram + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support - discard it for now. + */ + /DISCARD/ : { *(.ARM.exidx) } + + end = .; + + /* Leave room above stack for IAP to run. */ + __StackTop = ORIGIN(ram) + LENGTH(ram) - 32; + PROVIDE(_stack = __StackTop); +} diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 33eee4a..631e54e 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -22,6 +22,7 @@ /* Symbols exported by the linker script(s). */ extern unsigned _etext, _data, _edata, _ebss, _stack; +extern unsigned _etext_ram, _text_ram, _etext_rom; void main(void); void reset_handler(void); @@ -158,11 +159,29 @@ void (*const vector_table[]) (void) = { qei_irqhandler, }; +#define MMIO32(addr) (*(volatile unsigned long*)(addr)) +#define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) ) + void reset_handler(void) { volatile unsigned *src, *dest; __asm__("MSR msp, %0" : : "r"(&_stack)); + /* Copy the code from ROM to Real RAM (if enabled) */ + if( (&_etext_ram-&_text_ram) > 0 ) + { + src = &_etext_rom-(&_etext_ram-&_text_ram); + for(dest = &_text_ram; dest < &_etext_ram; ) + { + *dest++ = *src++; + } + + /* Change Shadow memory to Real RAM */ + CREG_M4MEMMAP = (unsigned long)&_text_ram; + + /* Continue Execution in RAM */ + } + for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; -- cgit v1.2.3 From c65ca01044495774ad51c26c16ea97cf60798ecb Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Wed, 13 Jun 2012 01:05:49 +0200 Subject: Fix Linker bug copy ROM to RAM & exec from RAM (need more test). --- .../lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld | 3 ++- lib/lpc43xx/Makefile | 2 +- lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld | 10 +++++----- lib/lpc43xx/vector.c | 3 +++ 4 files changed, 11 insertions(+), 7 deletions(-) (limited to 'lib/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld index 385b081..fb3d8f6 100644 --- a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld +++ b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld @@ -28,7 +28,8 @@ MEMORY /* rom is really the shadow region that points to SPI flash or elsewhere */ rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K - /* there are some additional RAM regions */ + /* there are some additional RAM regions for data */ + ram_data (rw) : ORIGIN = 0x10080000, LENGTH = 72K } /* Include the common ld script. */ diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index e8bd8fc..91169d4 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -25,7 +25,7 @@ PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar -CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ +CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \ -mcpu=cortex-m4 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld index f833aaf..850218b 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld @@ -56,26 +56,26 @@ SECTIONS _etext_ram = . + ORIGIN(ram); _etext_rom = . + ORIGIN(rom_flash); - . = ORIGIN(ram); - .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; - } >ram AT >rom + } >ram_data AT >rom .bss : { + . = _edata; *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; - } >ram + } >ram_data /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ .ARM.extab : { + . = _ebss; *(.ARM.extab*) - } >ram + } >ram_data /* * The .eh_frame section appears to be used for C++ exception handling. diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 631e54e..daef5a9 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -171,6 +171,9 @@ void reset_handler(void) if( (&_etext_ram-&_text_ram) > 0 ) { src = &_etext_rom-(&_etext_ram-&_text_ram); + /* Change Shadow memory to ROM (for Debug Purpose in case Boot has not set correctly the M4MEMMAP because of debug) */ + CREG_M4MEMMAP = (unsigned long)src; + for(dest = &_text_ram; dest < &_etext_ram; ) { *dest++ = *src++; -- cgit v1.2.3 From 536c92257755487710088df6ac4932ea25005e3e Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Fri, 15 Jun 2012 17:20:50 -0700 Subject: Modified SSP driver to wait for data to be sent before returning. This is critical when controlling device CS# pins via GPIO. Long-term, it might be better to have a different API that permits this level of control. --- lib/lpc43xx/ssp.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'lib/lpc43xx') diff --git a/lib/lpc43xx/ssp.c b/lib/lpc43xx/ssp.c index 592b5d8..e9cf5b0 100644 --- a/lib/lpc43xx/ssp.c +++ b/lib/lpc43xx/ssp.c @@ -113,6 +113,21 @@ u16 ssp_read(ssp_num_t ssp_num) return SSP_DR(ssp_port); } +void ssp_wait_until_not_busy(ssp_num_t ssp_num) +{ + u32 ssp_port; + + if(ssp_num == SSP0_NUM) + { + ssp_port = SSP0; + }else + { + ssp_port = SSP1; + } + + while( (SSP_SR(ssp_port) & SSP_SR_BSY) ); +} + /* This Function Wait Data TX Ready, and Write Data to SSP */ void ssp_write(ssp_num_t ssp_num, u16 data) { @@ -130,5 +145,16 @@ void ssp_write(ssp_num_t ssp_num, u16 data) while( (SSP_SR(ssp_port) & SSP_SR_TNF) == 0); SSP_DR(ssp_port) = data; + + /* Wait for not busy, since we're controlling CS# of + * devices manually and need to wait for the data to + * be sent. It may also be important to wait here + * in case we're configuring devices via SPI and also + * with GPIO control -- we need to know when SPI + * commands are effective before altering a device's + * state with GPIO. I'm thinking the MAX2837, for + * example... + */ + ssp_wait_until_not_busy(ssp_num); } -- cgit v1.2.3 From 81317c02ab3c33e820fe4852c053476a33c6f834 Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Mon, 25 Jun 2012 22:12:00 +0200 Subject: * Updated GPIO added gpio_toggle() function. * Fixed ROM to RAM Linker script (libopencm3_lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld). --- include/libopencm3/lpc43xx/gpio.h | 1 + lib/lpc43xx/gpio.c | 7 ++++++- lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld | 6 +++--- 3 files changed, 10 insertions(+), 4 deletions(-) (limited to 'lib/lpc43xx') diff --git a/include/libopencm3/lpc43xx/gpio.h b/include/libopencm3/lpc43xx/gpio.h index 6052887..8abd546 100644 --- a/include/libopencm3/lpc43xx/gpio.h +++ b/include/libopencm3/lpc43xx/gpio.h @@ -155,5 +155,6 @@ void gpio_set(u32 gpioport, u32 gpios); void gpio_clear(u32 gpioport, u32 gpios); +void gpio_toggle(u32 gpioport, u32 gpios); #endif diff --git a/lib/lpc43xx/gpio.c b/lib/lpc43xx/gpio.c index 9134f70..1256fd0 100644 --- a/lib/lpc43xx/gpio.c +++ b/lib/lpc43xx/gpio.c @@ -26,5 +26,10 @@ void gpio_set(u32 gpioport, u32 gpios) void gpio_clear(u32 gpioport, u32 gpios) { - GPIO_CLR(gpioport) = gpios; + GPIO_CLR(gpioport) = gpios; } + +void gpio_toggle(u32 gpioport, u32 gpios) +{ + GPIO_NOT(gpioport) = gpios; +} \ No newline at end of file diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld index 850218b..0270ea8 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld @@ -36,7 +36,7 @@ SECTIONS .text : { . = ALIGN(0x400); - _text_ram = . + ORIGIN(ram); /* Start of Code in RAM */ + _text_ram = (. - ORIGIN(rom)) + ORIGIN(ram); /* Start of Code in RAM */ *(.vectors) /* Vector table */ *(.text*) /* Program code */ @@ -53,8 +53,8 @@ SECTIONS __exidx_end = .; _etext = .; - _etext_ram = . + ORIGIN(ram); - _etext_rom = . + ORIGIN(rom_flash); + _etext_ram = (. - ORIGIN(rom)) + ORIGIN(ram); + _etext_rom = (. - ORIGIN(rom)) + ORIGIN(rom_flash); .data : { _data = .; -- cgit v1.2.3 From 3441bba1c4fc2710bef73402f58b5499cea20b42 Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Mon, 13 Aug 2012 14:37:07 -0700 Subject: Changed local build target for library and linker files. - The library files are now being built into the lib subdirectory of the source. - The linker files for each library are being copied into the lib source subdirectory. Motivation: The relative locations of files in the source directory after make are now the same as after make install now. This makes it easier to reuse examples with their makefiles outside of the libopencm3 sourcecode directory. --- Makefile | 11 ++++----- examples/lm3s/Makefile.include | 4 ++-- examples/lpc13xx/Makefile.include | 4 ++-- examples/lpc17xx/Makefile.include | 4 ++-- examples/lpc43xx/Makefile.include | 4 ++-- examples/stm32/f1/Makefile.include | 4 ++-- lib/Makefile.include | 48 ++++++++++++++++++++++++++++++++++++++ lib/lm3s/Makefile | 24 +------------------ lib/lpc13xx/Makefile | 25 +------------------- lib/lpc17xx/Makefile | 25 +------------------- lib/lpc43xx/Makefile | 25 +------------------- lib/stm32/f1/Makefile | 24 +------------------ lib/stm32/f2/Makefile | 25 +------------------- lib/stm32/f4/Makefile | 25 +------------------- 14 files changed, 70 insertions(+), 182 deletions(-) create mode 100644 lib/Makefile.include (limited to 'lib/lpc43xx') diff --git a/Makefile b/Makefile index 092efbd..d4abe2f 100644 --- a/Makefile +++ b/Makefile @@ -25,6 +25,7 @@ LIBDIR = $(DESTDIR)/$(PREFIX)/lib SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL = install +SRCLIBDIR = $(shell pwd)/lib TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lpc43xx lm3s # Be silent per default, but 'make V=1' will show all compiler calls. @@ -42,7 +43,7 @@ lib: $(Q)for i in $(addprefix $@/,$(TARGETS)); do \ if [ -d $$i ]; then \ printf " BUILD $$i\n"; \ - $(MAKE) -C $$i || exit $?; \ + $(MAKE) -C $$i SRCLIBDIR=$(SRCLIBDIR) || exit $?; \ fi; \ done @@ -61,11 +62,9 @@ install: lib $(Q)$(INSTALL) -d $(SHAREDIR) $(Q)cp -r include/libopencm3/* $(INCDIR)/libopencm3 @printf " INSTALL libs\n" - $(Q)$(INSTALL) -m 0644 lib/*/*/*.a $(LIBDIR) - $(Q)$(INSTALL) -m 0644 lib/*/*.a $(LIBDIR) + $(Q)$(INSTALL) -m 0644 lib/*.a $(LIBDIR) @printf " INSTALL ldscripts\n" - $(Q)$(INSTALL) -m 0644 lib/*/*/*.ld $(LIBDIR) - $(Q)$(INSTALL) -m 0644 lib/*/*.ld $(LIBDIR) + $(Q)$(INSTALL) -m 0644 lib/*.ld $(LIBDIR) @printf " INSTALL scripts\n" $(Q)$(INSTALL) -m 0644 scripts/* $(SHAREDIR) @@ -77,7 +76,7 @@ clean: $(addsuffix /*/*,$(addprefix examples/,$(TARGETS))); do \ if [ -d $$i ]; then \ printf " CLEAN $$i\n"; \ - $(MAKE) -C $$i clean || exit $?; \ + $(MAKE) -C $$i clean SRCLIBDIR=$(SRCLIBDIR) || exit $?; \ fi; \ done @printf " CLEAN doxygen\n" diff --git a/examples/lm3s/Makefile.include b/examples/lm3s/Makefile.include index b850d57..c119846 100644 --- a/examples/lm3s/Makefile.include +++ b/examples/lm3s/Makefile.include @@ -30,7 +30,7 @@ TOOLCHAIN_DIR = ../../../.. CFLAGS += -O0 -g3 -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m3 -mthumb -MD LDSCRIPT ?= $(BINARY).ld -LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/lm3s \ +LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections OBJS += $(BINARY).o @@ -75,7 +75,7 @@ flash: $(BINARY).flash @#printf " OBJDUMP $(*).list\n" $(Q)$(OBJDUMP) -S $(*).elf > $(*).list -%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/lm3s/libopencm3_lm3s.a +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_lm3s.a @#printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) $(LDFLAGS) -o $(*).elf $(OBJS) -lopencm3_lm3s diff --git a/examples/lpc13xx/Makefile.include b/examples/lpc13xx/Makefile.include index 1db02e9..47d906c 100644 --- a/examples/lpc13xx/Makefile.include +++ b/examples/lpc13xx/Makefile.include @@ -30,7 +30,7 @@ TOOLCHAIN_DIR = ../../../.. CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m3 -mthumb -MD LDSCRIPT ?= $(BINARY).ld -LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/lpc13xx \ +LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections OBJS += $(BINARY).o @@ -75,7 +75,7 @@ flash: $(BINARY).flash @#printf " OBJDUMP $(*).list\n" $(Q)$(OBJDUMP) -S $(*).elf > $(*).list -%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/lpc13xx/libopencm3_lpc13xx.a +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_lpc13xx.a @#printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) $(LDFLAGS) -o $(*).elf $(OBJS) -lopencm3_lpc13xx diff --git a/examples/lpc17xx/Makefile.include b/examples/lpc17xx/Makefile.include index 8d6efe7..92df4b1 100644 --- a/examples/lpc17xx/Makefile.include +++ b/examples/lpc17xx/Makefile.include @@ -30,7 +30,7 @@ TOOLCHAIN_DIR = ../../../.. CFLAGS += -O0 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m3 -mthumb -MD LDSCRIPT ?= $(BINARY).ld -LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/lpc17xx \ +LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections OBJS += $(BINARY).o @@ -75,7 +75,7 @@ flash: $(BINARY).flash @#printf " OBJDUMP $(*).list\n" $(Q)$(OBJDUMP) -S $(*).elf > $(*).list -%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/lpc17xx/libopencm3_lpc17xx.a +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_lpc17xx.a @#printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) $(LDFLAGS) -o $(*).elf $(OBJS) -lopencm3_lpc17xx diff --git a/examples/lpc43xx/Makefile.include b/examples/lpc43xx/Makefile.include index 588ddee..074192a 100644 --- a/examples/lpc43xx/Makefile.include +++ b/examples/lpc43xx/Makefile.include @@ -34,7 +34,7 @@ CFLAGS += -O2 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m4 -mthumb -MD \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 LDSCRIPT ?= $(BINARY).ld -LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/lpc43xx \ +LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections -Xlinker -Map=$(BINARY).map OBJS += $(BINARY).o @@ -78,7 +78,7 @@ flash: $(BINARY).flash @#printf " OBJDUMP $(*).list\n" $(Q)$(OBJDUMP) -S $(*).elf > $(*).list -%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/lpc43xx/libopencm3_lpc43xx.a +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_lpc43xx.a @#printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) $(LDFLAGS) -o $(*).elf $(OBJS) -lopencm3_lpc43xx diff --git a/examples/stm32/f1/Makefile.include b/examples/stm32/f1/Makefile.include index b63f3f0..31c6dcc 100644 --- a/examples/stm32/f1/Makefile.include +++ b/examples/stm32/f1/Makefile.include @@ -33,7 +33,7 @@ CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common $(ARCH_FLAGS) -MD -DSTM32F1 LDSCRIPT ?= $(BINARY).ld LDFLAGS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \ - -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/f1 \ + -L$(TOOLCHAIN_DIR)/lib \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ $(ARCH_FLAGS) -mfix-cortex-m3-ldrd OBJS += $(BINARY).o @@ -81,7 +81,7 @@ flash: $(BINARY).flash @#printf " OBJDUMP $(*).list\n" $(Q)$(OBJDUMP) -S $(*).elf > $(*).list -%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/stm32/f1/libopencm3_stm32f1.a +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32f1.a @#printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32f1 $(LDFLAGS) diff --git a/lib/Makefile.include b/lib/Makefile.include new file mode 100644 index 0000000..1f071e0 --- /dev/null +++ b/lib/Makefile.include @@ -0,0 +1,48 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2012 Piotr Esden-Tempski +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +endif + +all: $(SRCLIBDIR)/$(LIBNAME).a + +$(SRCLIBDIR)/$(LIBNAME).a: $(SRCLIBDIR)/$(LIBNAME).ld $(OBJS) + @printf " AR $(shell basename $(@))\n" + $(Q)$(AR) $(ARFLAGS) $(SRCLIBDIR)/$(shell basename $(@)) $(OBJS) + +$(SRCLIBDIR)/$(LIBNAME).ld: $(LIBNAME).ld + @printf " CP $(LIBNAME).ld\n" + $(Q)cp $^ $@ + +%.o: %.c + @printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + @printf " CLEAN lib/stm32/f1\n" + $(Q)rm -f *.o *.d + $(Q)rm -f $(SRCLIBDIR)/$(LIBNAME).a + $(Q)rm -f $(SRCLIBDIR)/$(LIBNAME).ld + +.PHONY: clean + +-include $(OBJS:.o=.d) diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile index 7ebc365..bdad3a4 100644 --- a/lib/lm3s/Makefile +++ b/lib/lm3s/Makefile @@ -32,26 +32,4 @@ OBJS = gpio.o vector.o # VPATH += ../usb -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/lpc13xx\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) +include ../Makefile.include diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile index e4f2096..158a5bf 100644 --- a/lib/lpc13xx/Makefile +++ b/lib/lpc13xx/Makefile @@ -32,27 +32,4 @@ OBJS = gpio.o # VPATH += ../usb -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/lpc13xx\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) - +include ../Makefile.include diff --git a/lib/lpc17xx/Makefile b/lib/lpc17xx/Makefile index c29f690..f688716 100644 --- a/lib/lpc17xx/Makefile +++ b/lib/lpc17xx/Makefile @@ -32,27 +32,4 @@ OBJS = gpio.o vector.o # VPATH += ../usb -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/lpc17xx\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) - +include ../Makefile.include diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 91169d4..67e74d7 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -35,27 +35,4 @@ OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o # VPATH += ../usb -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/lpc43xx\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) - +include ../Makefile.include diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 0059ba1..3b4252b 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -35,27 +35,5 @@ OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ VPATH += ../../usb:../ -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/stm32/f1\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) +include ../../Makefile.include diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index e0f8d95..bd6f275 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -33,27 +33,4 @@ OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \ VPATH += ../../usb:../ -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/stm32/f2\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) - +include ../../Makefile.include diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index f8b4dd2..5760d29 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -34,27 +34,4 @@ OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \ VPATH += ../../usb:../ -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/stm32/f4\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) - +include ../../Makefile.include -- cgit v1.2.3 From 2a35377980a05b6eb7ed47e9979b0ff3849d749f Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Mon, 3 Sep 2012 19:41:36 +0200 Subject: Clean up and make linker scripts more uniform This includes: - fix some comments indent, - add entry point, - align exported symbols, - remove unneeded "." assignments. --- lib/lm3s/libopencm3_lm3s.ld | 14 +++++++++----- lib/lpc13xx/libopencm3_lpc13xx.ld | 14 +++++++++----- lib/lpc17xx/libopencm3_lpc17xx.ld | 12 ++++++------ lib/lpc43xx/libopencm3_lpc43xx.ld | 6 ++---- lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld | 5 ++--- lib/stm32/f1/libopencm3_stm32f1.ld | 12 ++++-------- lib/stm32/f2/libopencm3_stm32f2.ld | 12 ++++-------- lib/stm32/f4/libopencm3_stm32f4.ld | 3 +-- 8 files changed, 37 insertions(+), 41 deletions(-) (limited to 'lib/lpc43xx') diff --git a/lib/lm3s/libopencm3_lm3s.ld b/lib/lm3s/libopencm3_lm3s.ld index c1453fe..00ede3d 100644 --- a/lib/lm3s/libopencm3_lm3s.ld +++ b/lib/lm3s/libopencm3_lm3s.ld @@ -24,31 +24,34 @@ /* Enforce emmition of the vector table. */ EXTERN (vector_table) +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ + . = ALIGN(4); *(.rodata*) /* Read-only data */ + . = ALIGN(4); _etext = .; } >rom - . = ORIGIN(ram); - .data : { _data = .; *(.data*) /* Read-write initialized data */ + . = ALIGN(4); _edata = .; } >ram AT >rom .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) + . = ALIGN(4); _ebss = .; - } >ram AT >rom + } >ram /* * The .eh_frame section appears to be used for C++ exception handling. @@ -62,6 +65,7 @@ SECTIONS */ /DISCARD/ : { *(.ARM.exidx) } + . = ALIGN(4); end = .; } diff --git a/lib/lpc13xx/libopencm3_lpc13xx.ld b/lib/lpc13xx/libopencm3_lpc13xx.ld index 5f1630f..a1892cd 100644 --- a/lib/lpc13xx/libopencm3_lpc13xx.ld +++ b/lib/lpc13xx/libopencm3_lpc13xx.ld @@ -24,31 +24,34 @@ /* Enforce emmition of the vector table. */ EXTERN (vector_table) +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ + . = ALIGN(4); *(.rodata*) /* Read-only data */ + . = ALIGN(4); _etext = .; } >rom - . = ORIGIN(ram); - .data : { _data = .; *(.data*) /* Read-write initialized data */ + . = ALIGN(4); _edata = .; } >ram AT >rom .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) + . = ALIGN(4); _ebss = .; - } >ram AT >rom + } >ram /* * The .eh_frame section appears to be used for C++ exception handling. @@ -62,6 +65,7 @@ SECTIONS */ /DISCARD/ : { *(.ARM.exidx) } + . = ALIGN(4); end = .; } diff --git a/lib/lpc17xx/libopencm3_lpc17xx.ld b/lib/lpc17xx/libopencm3_lpc17xx.ld index 30a2c0f..a1892cd 100644 --- a/lib/lpc17xx/libopencm3_lpc17xx.ld +++ b/lib/lpc17xx/libopencm3_lpc17xx.ld @@ -1,4 +1,3 @@ - /* * This file is part of the libopencm3 project. * @@ -31,28 +30,28 @@ ENTRY(reset_handler) /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ + . = ALIGN(4); *(.rodata*) /* Read-only data */ + . = ALIGN(4); _etext = .; } >rom - . = ORIGIN(ram); - .data : { _data = .; *(.data*) /* Read-write initialized data */ + . = ALIGN(4); _edata = .; } >ram AT >rom .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) + . = ALIGN(4); _ebss = .; - } >ram AT >rom + } >ram /* * The .eh_frame section appears to be used for C++ exception handling. @@ -66,6 +65,7 @@ SECTIONS */ /DISCARD/ : { *(.ARM.exidx) } + . = ALIGN(4); end = .; } diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld index 47b403b..2fedf09 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx.ld @@ -32,8 +32,6 @@ ENTRY(reset_handler) /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { . = ALIGN(0x400); _text_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ @@ -51,12 +49,11 @@ SECTIONS } > rom __exidx_end = .; + . = ALIGN(4); _etext = .; _etext_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ _etext_rom = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ - . = ORIGIN(ram); - .data : { _data = .; *(.data*) /* Read-write initialized data */ @@ -88,6 +85,7 @@ SECTIONS */ /DISCARD/ : { *(.ARM.exidx) } + . = ALIGN(4); end = .; /* Leave room above stack for IAP to run. */ diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld index 0270ea8..e39f662 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld @@ -32,8 +32,6 @@ ENTRY(reset_handler) /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { . = ALIGN(0x400); _text_ram = (. - ORIGIN(rom)) + ORIGIN(ram); /* Start of Code in RAM */ @@ -52,6 +50,7 @@ SECTIONS } > rom __exidx_end = .; + . = ALIGN(4); _etext = .; _etext_ram = (. - ORIGIN(rom)) + ORIGIN(ram); _etext_rom = (. - ORIGIN(rom)) + ORIGIN(rom_flash); @@ -64,7 +63,6 @@ SECTIONS } >ram_data AT >rom .bss : { - . = _edata; *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); @@ -89,6 +87,7 @@ SECTIONS */ /DISCARD/ : { *(.ARM.exidx) } + . = ALIGN(4); end = .; /* Leave room above stack for IAP to run. */ diff --git a/lib/stm32/f1/libopencm3_stm32f1.ld b/lib/stm32/f1/libopencm3_stm32f1.ld index a64a1f7..f4f8e3b 100644 --- a/lib/stm32/f1/libopencm3_stm32f1.ld +++ b/lib/stm32/f1/libopencm3_stm32f1.ld @@ -30,8 +30,6 @@ ENTRY(reset_handler) /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ @@ -42,9 +40,9 @@ SECTIONS } >rom /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - */ + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ .ARM.extab : { *(.ARM.extab*) } >rom @@ -54,8 +52,6 @@ SECTIONS __exidx_end = .; } >rom - . = ORIGIN(ram); - .data : AT (__exidx_end) { _data = .; *(.data*) /* Read-write initialized data */ @@ -68,7 +64,7 @@ SECTIONS *(COMMON) . = ALIGN(4); _ebss = .; - } >ram AT >rom + } >ram /* * The .eh_frame section appears to be used for C++ exception handling. diff --git a/lib/stm32/f2/libopencm3_stm32f2.ld b/lib/stm32/f2/libopencm3_stm32f2.ld index a64a1f7..f4f8e3b 100644 --- a/lib/stm32/f2/libopencm3_stm32f2.ld +++ b/lib/stm32/f2/libopencm3_stm32f2.ld @@ -30,8 +30,6 @@ ENTRY(reset_handler) /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ @@ -42,9 +40,9 @@ SECTIONS } >rom /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - */ + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ .ARM.extab : { *(.ARM.extab*) } >rom @@ -54,8 +52,6 @@ SECTIONS __exidx_end = .; } >rom - . = ORIGIN(ram); - .data : AT (__exidx_end) { _data = .; *(.data*) /* Read-write initialized data */ @@ -68,7 +64,7 @@ SECTIONS *(COMMON) . = ALIGN(4); _ebss = .; - } >ram AT >rom + } >ram /* * The .eh_frame section appears to be used for C++ exception handling. diff --git a/lib/stm32/f4/libopencm3_stm32f4.ld b/lib/stm32/f4/libopencm3_stm32f4.ld index 0624b96..cf7e9ec 100644 --- a/lib/stm32/f4/libopencm3_stm32f4.ld +++ b/lib/stm32/f4/libopencm3_stm32f4.ld @@ -30,8 +30,6 @@ ENTRY(reset_handler) /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ @@ -48,6 +46,7 @@ SECTIONS __exidx_end = .; + . = ALIGN(4); _etext = .; .data : { -- cgit v1.2.3 From 74cd991e7e8972cf22933743c847b5ce2b165798 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Mon, 3 Sep 2012 19:49:47 +0200 Subject: Use a specific symbol for data source address in flash That way, data source address does not depend on any other unrelated change in linker script. This also fixes cases when .data input section is aligned on 8 bytes. The new version does not provide any address for the output section so that it is aligned to the strictest input section. The _data_loadaddr symbol will always take this alignment into account. --- lib/lm3s/libopencm3_lm3s.ld | 1 + lib/lm3s/vector.c | 5 +++-- lib/lpc13xx/libopencm3_lpc13xx.ld | 1 + lib/lpc17xx/libopencm3_lpc17xx.ld | 1 + lib/lpc17xx/vector.c | 7 ++++--- lib/lpc43xx/libopencm3_lpc43xx.ld | 1 + lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld | 1 + lib/lpc43xx/vector.c | 7 ++++--- lib/stm32/f1/libopencm3_stm32f1.ld | 5 +++-- lib/stm32/f1/vector.c | 6 +++--- lib/stm32/f2/libopencm3_stm32f2.ld | 5 +++-- lib/stm32/f2/vector.c | 4 ++-- lib/stm32/f4/libopencm3_stm32f4.ld | 1 + lib/stm32/f4/vector.c | 4 ++-- 14 files changed, 30 insertions(+), 19 deletions(-) (limited to 'lib/lpc43xx') diff --git a/lib/lm3s/libopencm3_lm3s.ld b/lib/lm3s/libopencm3_lm3s.ld index 00ede3d..d6de32b 100644 --- a/lib/lm3s/libopencm3_lm3s.ld +++ b/lib/lm3s/libopencm3_lm3s.ld @@ -45,6 +45,7 @@ SECTIONS . = ALIGN(4); _edata = .; } >ram AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c index 5968d76..3a1c4d1 100644 --- a/lib/lm3s/vector.c +++ b/lib/lm3s/vector.c @@ -20,7 +20,7 @@ #define WEAK __attribute__ ((weak)) /* Symbols exported by the linker script(s): */ -extern unsigned _etext, _data, _edata, _ebss, _stack; +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; void main(void); void reset_handler(void); @@ -61,9 +61,10 @@ void (*const vector_table[]) (void) = { void reset_handler(void) { volatile unsigned *src, *dest; + __asm__("MSR msp, %0" : : "r"(&_stack)); - for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; while (dest < &_ebss) diff --git a/lib/lpc13xx/libopencm3_lpc13xx.ld b/lib/lpc13xx/libopencm3_lpc13xx.ld index a1892cd..3d683de 100644 --- a/lib/lpc13xx/libopencm3_lpc13xx.ld +++ b/lib/lpc13xx/libopencm3_lpc13xx.ld @@ -45,6 +45,7 @@ SECTIONS . = ALIGN(4); _edata = .; } >ram AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ diff --git a/lib/lpc17xx/libopencm3_lpc17xx.ld b/lib/lpc17xx/libopencm3_lpc17xx.ld index a1892cd..3d683de 100644 --- a/lib/lpc17xx/libopencm3_lpc17xx.ld +++ b/lib/lpc17xx/libopencm3_lpc17xx.ld @@ -45,6 +45,7 @@ SECTIONS . = ALIGN(4); _edata = .; } >ram AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ diff --git a/lib/lpc17xx/vector.c b/lib/lpc17xx/vector.c index 016db7a..518f562 100644 --- a/lib/lpc17xx/vector.c +++ b/lib/lpc17xx/vector.c @@ -19,8 +19,8 @@ #define WEAK __attribute__ ((weak)) -/* Symbols exported by the linker script(s). */ -extern unsigned _etext, _data, _edata, _ebss, _stack; +/* Symbols exported by the linker script(s): */ +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; void main(void); void reset_handler(void); @@ -60,9 +60,10 @@ void (*const vector_table[]) (void) = { void reset_handler(void) { volatile unsigned *src, *dest; + __asm__("MSR msp, %0" : : "r"(&_stack)); - for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; while (dest < &_ebss) diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld index 2fedf09..b7f1d14 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx.ld @@ -60,6 +60,7 @@ SECTIONS . = ALIGN(4); _edata = .; } >ram AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld index e39f662..4037ddc 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld @@ -61,6 +61,7 @@ SECTIONS . = ALIGN(4); _edata = .; } >ram_data AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index daef5a9..23008bc 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -20,8 +20,8 @@ #define WEAK __attribute__ ((weak)) -/* Symbols exported by the linker script(s). */ -extern unsigned _etext, _data, _edata, _ebss, _stack; +/* Symbols exported by the linker script(s): */ +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; extern unsigned _etext_ram, _text_ram, _etext_rom; void main(void); @@ -165,6 +165,7 @@ void (*const vector_table[]) (void) = { void reset_handler(void) { volatile unsigned *src, *dest; + __asm__("MSR msp, %0" : : "r"(&_stack)); /* Copy the code from ROM to Real RAM (if enabled) */ @@ -185,7 +186,7 @@ void reset_handler(void) /* Continue Execution in RAM */ } - for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; while (dest < &_ebss) diff --git a/lib/stm32/f1/libopencm3_stm32f1.ld b/lib/stm32/f1/libopencm3_stm32f1.ld index f4f8e3b..c4a1bce 100644 --- a/lib/stm32/f1/libopencm3_stm32f1.ld +++ b/lib/stm32/f1/libopencm3_stm32f1.ld @@ -52,12 +52,13 @@ SECTIONS __exidx_end = .; } >rom - .data : AT (__exidx_end) { + .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; - } >ram + } >ram AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c index 119ce30..f496ae4 100644 --- a/lib/stm32/f1/vector.c +++ b/lib/stm32/f1/vector.c @@ -19,8 +19,8 @@ #define WEAK __attribute__ ((weak)) -/* Symbols exported by the linker script(s). */ -extern unsigned __exidx_end, _data, _edata, _ebss, _stack; +/* Symbols exported by the linker script(s): */ +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; void main(void); void reset_handler(void); @@ -197,7 +197,7 @@ void reset_handler(void) __asm__("MSR msp, %0" : : "r"(&_stack)); - for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++) + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; while (dest < &_ebss) diff --git a/lib/stm32/f2/libopencm3_stm32f2.ld b/lib/stm32/f2/libopencm3_stm32f2.ld index f4f8e3b..c4a1bce 100644 --- a/lib/stm32/f2/libopencm3_stm32f2.ld +++ b/lib/stm32/f2/libopencm3_stm32f2.ld @@ -52,12 +52,13 @@ SECTIONS __exidx_end = .; } >rom - .data : AT (__exidx_end) { + .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; - } >ram + } >ram AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c index 64d2426..3429bfb 100644 --- a/lib/stm32/f2/vector.c +++ b/lib/stm32/f2/vector.c @@ -21,7 +21,7 @@ #define WEAK __attribute__ ((weak)) /* Symbols exported by the linker script(s): */ -extern unsigned __exidx_end, _data, _edata, _ebss, _stack; +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; void main(void); void reset_handler(void); @@ -224,7 +224,7 @@ void reset_handler(void) __asm__("MSR msp, %0" : : "r"(&_stack)); - for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++) + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; while (dest < &_ebss) diff --git a/lib/stm32/f4/libopencm3_stm32f4.ld b/lib/stm32/f4/libopencm3_stm32f4.ld index cf7e9ec..25b0ace 100644 --- a/lib/stm32/f4/libopencm3_stm32f4.ld +++ b/lib/stm32/f4/libopencm3_stm32f4.ld @@ -55,6 +55,7 @@ SECTIONS . = ALIGN(4); _edata = .; } >ram AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c index 1c901da..3429bfb 100644 --- a/lib/stm32/f4/vector.c +++ b/lib/stm32/f4/vector.c @@ -21,7 +21,7 @@ #define WEAK __attribute__ ((weak)) /* Symbols exported by the linker script(s): */ -extern unsigned _etext, _data, _edata, _ebss, _stack; +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; void main(void); void reset_handler(void); @@ -224,7 +224,7 @@ void reset_handler(void) __asm__("MSR msp, %0" : : "r"(&_stack)); - for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; while (dest < &_ebss) -- cgit v1.2.3 From 82ef2936a673f0c6cba86e02d80104f56e1de5a2 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Mon, 3 Sep 2012 19:51:40 +0200 Subject: Support exceptions on all targets --- lib/lm3s/libopencm3_lm3s.ld | 23 ++++++++++++++++------- lib/lpc13xx/libopencm3_lpc13xx.ld | 23 ++++++++++++++++------- lib/lpc17xx/libopencm3_lpc17xx.ld | 23 ++++++++++++++++------- lib/lpc43xx/libopencm3_lpc43xx.ld | 25 ++++++++++--------------- lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld | 26 ++++++++++---------------- lib/stm32/f1/libopencm3_stm32f1.ld | 4 +++- lib/stm32/f2/libopencm3_stm32f2.ld | 4 +++- lib/stm32/f4/libopencm3_stm32f4.ld | 26 ++++++++++++++++---------- 8 files changed, 90 insertions(+), 64 deletions(-) (limited to 'lib/lpc43xx') diff --git a/lib/lm3s/libopencm3_lm3s.ld b/lib/lm3s/libopencm3_lm3s.ld index d6de32b..ceb391a 100644 --- a/lib/lm3s/libopencm3_lm3s.ld +++ b/lib/lm3s/libopencm3_lm3s.ld @@ -36,9 +36,24 @@ SECTIONS . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); - _etext = .; } >rom + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >rom + + . = ALIGN(4); + _etext = .; + .data : { _data = .; *(.data*) /* Read-write initialized data */ @@ -60,12 +75,6 @@ SECTIONS */ /DISCARD/ : { *(.eh_frame) } - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - discard it for now. - */ - /DISCARD/ : { *(.ARM.exidx) } - . = ALIGN(4); end = .; } diff --git a/lib/lpc13xx/libopencm3_lpc13xx.ld b/lib/lpc13xx/libopencm3_lpc13xx.ld index 3d683de..4e0f1df 100644 --- a/lib/lpc13xx/libopencm3_lpc13xx.ld +++ b/lib/lpc13xx/libopencm3_lpc13xx.ld @@ -36,9 +36,24 @@ SECTIONS . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); - _etext = .; } >rom + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >rom + + . = ALIGN(4); + _etext = .; + .data : { _data = .; *(.data*) /* Read-write initialized data */ @@ -60,12 +75,6 @@ SECTIONS */ /DISCARD/ : { *(.eh_frame) } - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - discard it for now. - */ - /DISCARD/ : { *(.ARM.exidx) } - . = ALIGN(4); end = .; } diff --git a/lib/lpc17xx/libopencm3_lpc17xx.ld b/lib/lpc17xx/libopencm3_lpc17xx.ld index 3d683de..4e0f1df 100644 --- a/lib/lpc17xx/libopencm3_lpc17xx.ld +++ b/lib/lpc17xx/libopencm3_lpc17xx.ld @@ -36,9 +36,24 @@ SECTIONS . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); - _etext = .; } >rom + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >rom + + . = ALIGN(4); + _etext = .; + .data : { _data = .; *(.data*) /* Read-write initialized data */ @@ -60,12 +75,6 @@ SECTIONS */ /DISCARD/ : { *(.eh_frame) } - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - discard it for now. - */ - /DISCARD/ : { *(.ARM.exidx) } - . = ALIGN(4); end = .; } diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld index b7f1d14..9402a54 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx.ld @@ -42,12 +42,18 @@ SECTIONS . = ALIGN(4); } >rom - /* exception index - required due to libgcc.a issuing /0 exceptions */ - __exidx_start = .; + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom .ARM.exidx : { + __exidx_start = .; *(.ARM.exidx*) - } > rom - __exidx_end = .; + __exidx_end = .; + } >rom . = ALIGN(4); _etext = .; @@ -69,23 +75,12 @@ SECTIONS _ebss = .; } >ram - /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ - .ARM.extab : { - *(.ARM.extab*) - } >ram - /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - discard it for now. - */ - /DISCARD/ : { *(.ARM.exidx) } - . = ALIGN(4); end = .; diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld index 4037ddc..06f7708 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld @@ -43,12 +43,18 @@ SECTIONS . = ALIGN(4); } >rom - /* exception index - required due to libgcc.a issuing /0 exceptions */ - __exidx_start = .; + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom .ARM.exidx : { + __exidx_start = .; *(.ARM.exidx*) - } > rom - __exidx_end = .; + __exidx_end = .; + } >rom . = ALIGN(4); _etext = .; @@ -70,24 +76,12 @@ SECTIONS _ebss = .; } >ram_data - /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ - .ARM.extab : { - . = _ebss; - *(.ARM.extab*) - } >ram_data - /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - discard it for now. - */ - /DISCARD/ : { *(.ARM.exidx) } - . = ALIGN(4); end = .; diff --git a/lib/stm32/f1/libopencm3_stm32f1.ld b/lib/stm32/f1/libopencm3_stm32f1.ld index c4a1bce..9d165f6 100644 --- a/lib/stm32/f1/libopencm3_stm32f1.ld +++ b/lib/stm32/f1/libopencm3_stm32f1.ld @@ -36,7 +36,6 @@ SECTIONS . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); - _etext = .; } >rom /* @@ -52,6 +51,9 @@ SECTIONS __exidx_end = .; } >rom + . = ALIGN(4); + _etext = .; + .data : { _data = .; *(.data*) /* Read-write initialized data */ diff --git a/lib/stm32/f2/libopencm3_stm32f2.ld b/lib/stm32/f2/libopencm3_stm32f2.ld index c4a1bce..9d165f6 100644 --- a/lib/stm32/f2/libopencm3_stm32f2.ld +++ b/lib/stm32/f2/libopencm3_stm32f2.ld @@ -36,7 +36,6 @@ SECTIONS . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); - _etext = .; } >rom /* @@ -52,6 +51,9 @@ SECTIONS __exidx_end = .; } >rom + . = ALIGN(4); + _etext = .; + .data : { _data = .; *(.data*) /* Read-write initialized data */ diff --git a/lib/stm32/f4/libopencm3_stm32f4.ld b/lib/stm32/f4/libopencm3_stm32f4.ld index 25b0ace..9d165f6 100644 --- a/lib/stm32/f4/libopencm3_stm32f4.ld +++ b/lib/stm32/f4/libopencm3_stm32f4.ld @@ -38,13 +38,18 @@ SECTIONS . = ALIGN(4); } >rom - /* exception index - required due to libgcc.a issuing /0 exceptions */ - __exidx_start = .; + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom .ARM.exidx : { - *(.ARM.exidx*) - } > rom - __exidx_end = .; - + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >rom . = ALIGN(4); _etext = .; @@ -64,10 +69,11 @@ SECTIONS _ebss = .; } >ram - /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ - .ARM.extab : { - *(.ARM.extab*) - } >ram + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; -- cgit v1.2.3