From a69d83d312396ee604426dce5341a54316c7c9b5 Mon Sep 17 00:00:00 2001 From: chrysn Date: Wed, 3 Oct 2012 18:15:20 +0200 Subject: unified vector table initialization the cortex generic interrupts get moved to lib/cm3/vector.c, the platorms' individual irq names, initialization and handler prototypes go to platoform specific irq.h files. as the vector.c file heavily depends on platoform specific headers, it can't be built once-and-for-all in lib/cm3/, so there are inclusion stubs in the various architecture dirs; this might be better solved with Makefile / include path handling. one particular file is lib/lpc43xx/vector.c; that platform's initialization code contains an additional section to copy everything from flash to ram (which probably performs better there). that code still resides in the inclusion stub, and gets mashed in using defines. would need a cleaner implementation together with the Makefile solution. this commit contains some files of the upcoming efm32 branch, from which it was cherry-picked. the .bin files produced from before and after this commit only differ in lpc43xx, where the startup sequence was subtly modified. --- include/libopencm3/cm3/vector.h | 65 ++++++ include/libopencm3/efm32/tinygecko/irq.h | 130 +++++++++++ include/libopencm3/lm3s/irq.h | 33 +++ include/libopencm3/lpc17xx/irq.h | 33 +++ include/libopencm3/lpc43xx/irq.h | 234 ++++++++++++++++++++ include/libopencm3/stm32/f1/irq.h | 306 ++++++++++++++++++++++++++ include/libopencm3/stm32/f2/irq.h | 359 +++++++++++++++++++++++++++++++ include/libopencm3/stm32/f4/irq.h | 359 +++++++++++++++++++++++++++++++ 8 files changed, 1519 insertions(+) create mode 100644 include/libopencm3/cm3/vector.h create mode 100644 include/libopencm3/efm32/tinygecko/irq.h create mode 100644 include/libopencm3/lm3s/irq.h create mode 100644 include/libopencm3/lpc17xx/irq.h create mode 100644 include/libopencm3/lpc43xx/irq.h create mode 100644 include/libopencm3/stm32/f1/irq.h create mode 100644 include/libopencm3/stm32/f2/irq.h create mode 100644 include/libopencm3/stm32/f4/irq.h (limited to 'include') diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h new file mode 100644 index 0000000..198992b --- /dev/null +++ b/include/libopencm3/cm3/vector.h @@ -0,0 +1,65 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions for handling vector tables. + * + * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2 + * (from the EFM32 documentation at + * http://www.energymicro.com/downloads/datasheets), and was seen analogously + * in other ARM implementations' libopencm3 files. + * + * The structure of the vector table is implemented independently of the system + * vector table starting at memory position 0x0, as it can be relocated to + * other memory locations too. + * + * The exact size of a vector interrupt table depends on the number of + * interrupts IRQ_COUNT, which is defined per family. + */ + +#ifndef LIBOPENCM3_VECTOR_H +#define LIBOPENCM3_VECTOR_H + +#include + +// #include "irq.h" /* we'll nede some definitions */ + +/** Type of an interrupt function. Only used to avoid hard-to-read function + * pointers in the efm32_vector_table_t struct. */ +typedef void (*vector_table_entry_t)(void); + +typedef struct { + unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ + vector_table_entry_t reset; + vector_table_entry_t nmi; + vector_table_entry_t hard_fault; + vector_table_entry_t memory_manage_fault; + vector_table_entry_t bus_fault; + vector_table_entry_t usage_fault; + vector_table_entry_t reserved_x001c[4]; + vector_table_entry_t sv_call; + vector_table_entry_t debug_monitor; + vector_table_entry_t reserved_x0034; + vector_table_entry_t pend_sv; + vector_table_entry_t systick; + vector_table_entry_t irq[IRQ_COUNT]; +} vector_table_t; + +#endif diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h new file mode 100644 index 0000000..f5263ae --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq.h @@ -0,0 +1,130 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions of interrupt names on EFM32 Tiny Gecko systems + * + * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. + */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H + +#define IRQ_DMA 0 +#define IRQ_GPIO_EVEN 1 +#define IRQ_TIMER0 2 +#define IRQ_USART0_RX 3 +#define IRQ_USART0_TX 4 +#define IRQ_ACMP01 5 +#define IRQ_ADC0 6 +#define IRQ_DAC0 7 +#define IRQ_I2C0 8 +#define IRQ_GPIO_ODD 9 +#define IRQ_TIMER1 10 +#define IRQ_USART1_RX 11 +#define IRQ_USART1_TX 12 +#define IRQ_LESENSE 13 +#define IRQ_LEUART0 14 +#define IRQ_LETIMER0 15 +#define IRQ_PCNT0 16 +#define IRQ_RTC 17 +#define IRQ_CMU 18 +#define IRQ_VCMP 19 +#define IRQ_LCD 20 +#define IRQ_MSC 21 +#define IRQ_AES 22 +#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ + +#define WEAK __attribute__ ((weak)) + +void WEAK dma_isr(void); +void WEAK gpio_even_isr(void); +void WEAK timer0_isr(void); +void WEAK usart0_rx_isr(void); +void WEAK usart0_tx_isr(void); +void WEAK acmp01_isr(void); +void WEAK adc0_isr(void); +void WEAK dac0_isr(void); +void WEAK i2c0_isr(void); +void WEAK gpio_odd_isr(void); +void WEAK timer1_isr(void); +void WEAK usart1_rx_isr(void); +void WEAK usart1_tx_isr(void); +void WEAK lesense_isr(void); +void WEAK leuart0_isr(void); +void WEAK letimer0_isr(void); +void WEAK pcnt0_isr(void); +void WEAK rtc_isr(void); +void WEAK cmu_isr(void); +void WEAK vcmp_isr(void); +void WEAK lcd_isr(void); +void WEAK msc_isr(void); +void WEAK aes_isr(void); + +#pragma weak dma_isr = blocking_handler +#pragma weak gpio_even_isr = blocking_handler +#pragma weak timer0_isr = blocking_handler +#pragma weak usart0_rx_isr = blocking_handler +#pragma weak usart0_tx_isr = blocking_handler +#pragma weak acmp01_isr = blocking_handler +#pragma weak adc0_isr = blocking_handler +#pragma weak dac0_isr = blocking_handler +#pragma weak i2c0_isr = blocking_handler +#pragma weak gpio_odd_isr = blocking_handler +#pragma weak timer1_isr = blocking_handler +#pragma weak usart1_rx_isr = blocking_handler +#pragma weak usart1_tx_isr = blocking_handler +#pragma weak lesense_isr = blocking_handler +#pragma weak leuart0_isr = blocking_handler +#pragma weak letimer0_isr = blocking_handler +#pragma weak pcnt0_isr = blocking_handler +#pragma weak rtc_isr = blocking_handler +#pragma weak cmu_isr = blocking_handler +#pragma weak vcmp_isr = blocking_handler +#pragma weak lcd_isr = blocking_handler +#pragma weak msc_isr = blocking_handler +#pragma weak aes_isr = blocking_handler + +#define IRQ_HANDLERS \ + [IRQ_DMA] = dma_isr, \ + [IRQ_GPIO_EVEN] = gpio_even_isr, \ + [IRQ_TIMER0] = timer0_isr, \ + [IRQ_USART0_RX] = usart0_rx_isr, \ + [IRQ_USART0_TX] = usart0_tx_isr, \ + [IRQ_ACMP01] = acmp01_isr, \ + [IRQ_ADC0] = adc0_isr, \ + [IRQ_DAC0] = dac0_isr, \ + [IRQ_I2C0] = i2c0_isr, \ + [IRQ_GPIO_ODD] = gpio_odd_isr, \ + [IRQ_TIMER1] = timer1_isr, \ + [IRQ_USART1_RX] = usart1_rx_isr, \ + [IRQ_USART1_TX] = usart1_tx_isr, \ + [IRQ_LESENSE] = lesense_isr, \ + [IRQ_LEUART0] = leuart0_isr, \ + [IRQ_LETIMER0] = letimer0_isr, \ + [IRQ_PCNT0] = pcnt0_isr, \ + [IRQ_RTC] = rtc_isr, \ + [IRQ_CMU] = cmu_isr, \ + [IRQ_VCMP] = vcmp_isr, \ + [IRQ_LCD] = lcd_isr, \ + [IRQ_MSC] = msc_isr, \ + [IRQ_AES] = aes_isr, + +#endif diff --git a/include/libopencm3/lm3s/irq.h b/include/libopencm3/lm3s/irq.h new file mode 100644 index 0000000..948c563 --- /dev/null +++ b/include/libopencm3/lm3s/irq.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LM3S_IRQ_H +#define LIBOPENCM3_LM3S_IRQ_H + +/* TODO: Interrupt definitions */ +#define IRQ_COUNT 0 + +/* TODO: Interrupt handler prototypes */ + +/* TODO: Interrupt handler weak aliases */ + +#define IRQ_HANDLERS + +#endif diff --git a/include/libopencm3/lpc17xx/irq.h b/include/libopencm3/lpc17xx/irq.h new file mode 100644 index 0000000..9c31267 --- /dev/null +++ b/include/libopencm3/lpc17xx/irq.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LPC17xx_IRQ_H +#define LIBOPENCM3_LPC17xx_IRQ_H + +/* TODO: Interrupt definitions */ +#define IRQ_COUNT 0 + +/* TODO: Interrupt handler prototypes */ + +/* TODO: Interrupt handler weak aliases */ + +#define IRQ_HANDLERS + +#endif diff --git a/include/libopencm3/lpc43xx/irq.h b/include/libopencm3/lpc43xx/irq.h new file mode 100644 index 0000000..a83a8d7 --- /dev/null +++ b/include/libopencm3/lpc43xx/irq.h @@ -0,0 +1,234 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LPC43XX_IRQ_H +#define LIBOPENCM3_LPC43XX_IRQ_H + +#define IRQ_DAC 0 +#define IRQ_M0CORE 1 +#define IRQ_DMA 2 +/* reserved: 3 */ +/* reserved: 4 */ +#define IRQ_ETHERNET 5 +#define IRQ_SDIO 6 +#define IRQ_LCD 7 +#define IRQ_USB0 8 +#define IRQ_USB1 9 +#define IRQ_SCT 10 +#define IRQ_RITIMER 11 +#define IRQ_TIMER0 12 +#define IRQ_TIMER1 13 +#define IRQ_TIMER2 14 +#define IRQ_TIMER3 15 +#define IRQ_MCPWM 16 +#define IRQ_ADC0 17 +#define IRQ_I2C0 18 +#define IRQ_I2C1 19 +#define IRQ_SPI 20 +#define IRQ_ADC1 21 +#define IRQ_SSP0 22 +#define IRQ_SSP1 23 +#define IRQ_USART0 24 +#define IRQ_UART1 25 +#define IRQ_USART2 26 +#define IRQ_USART3 27 +#define IRQ_I2S0 28 +#define IRQ_I2S1 29 +#define IRQ_SPIFI 30 +#define IRQ_SGPIO 31 +#define IRQ_PIN_INT0 32 +#define IRQ_PIN_INT1 33 +#define IRQ_PIN_INT2 34 +#define IRQ_PIN_INT3 35 +#define IRQ_PIN_INT4 36 +#define IRQ_PIN_INT5 37 +#define IRQ_PIN_INT6 38 +#define IRQ_PIN_INT7 39 +#define IRQ_GINT0 40 +#define IRQ_GINT1 41 +#define IRQ_EVENTROUTER 42 +#define IRQ_C_CAN1 43 +/* reserved: 44 */ +/* reserved: 45 */ +#define IRQ_ATIMER 46 +#define IRQ_RTC 47 +/* reserved: 48 */ +#define IRQ_WWDT 49 +/* reserved: 50 */ +#define IRQ_C_CAN0 51 +#define IRQ_QEI 52 + +#define IRQ_COUNT 53 + +#define WEAK __attribute__ ((weak)) + +void WEAK dac_irqhandler(void); +void WEAK m0core_irqhandler(void); +void WEAK dma_irqhandler(void); +void WEAK ethernet_irqhandler(void); +void WEAK sdio_irqhandler(void); +void WEAK lcd_irqhandler(void); +void WEAK usb0_irqhandler(void); +void WEAK usb1_irqhandler(void); +void WEAK sct_irqhandler(void); +void WEAK ritimer_irqhandler(void); +void WEAK timer0_irqhandler(void); +void WEAK timer1_irqhandler(void); +void WEAK timer2_irqhandler(void); +void WEAK timer3_irqhandler(void); +void WEAK mcpwm_irqhandler(void); +void WEAK adc0_irqhandler(void); +void WEAK i2c0_irqhandler(void); +void WEAK i2c1_irqhandler(void); +void WEAK spi_irqhandler(void); +void WEAK adc1_irqhandler(void); +void WEAK ssp0_irqhandler(void); +void WEAK ssp1_irqhandler(void); +void WEAK usart0_irqhandler(void); +void WEAK uart1_irqhandler(void); +void WEAK usart2_irqhandler(void); +void WEAK usart3_irqhandler(void); +void WEAK i2s0_irqhandler(void); +void WEAK i2s1_irqhandler(void); +void WEAK spifi_irqhandler(void); +void WEAK sgpio_irqhandler(void); +void WEAK pin_int0_irqhandler(void); +void WEAK pin_int1_irqhandler(void); +void WEAK pin_int2_irqhandler(void); +void WEAK pin_int3_irqhandler(void); +void WEAK pin_int4_irqhandler(void); +void WEAK pin_int5_irqhandler(void); +void WEAK pin_int6_irqhandler(void); +void WEAK pin_int7_irqhandler(void); +void WEAK gint0_irqhandler(void); +void WEAK gint1_irqhandler(void); +void WEAK eventrouter_irqhandler(void); +void WEAK c_can1_irqhandler(void); +void WEAK atimer_irqhandler(void); +void WEAK rtc_irqhandler(void); +void WEAK wwdt_irqhandler(void); +void WEAK c_can0_irqhandler(void); +void WEAK qei_irqhandler(void); + +#pragma weak dac_irqhandler = null_handler +#pragma weak m0core_irqhandler = null_handler +#pragma weak dma_irqhandler = null_handler +#pragma weak ethernet_irqhandler = null_handler +#pragma weak sdio_irqhandler = null_handler +#pragma weak lcd_irqhandler = null_handler +#pragma weak usb0_irqhandler = null_handler +#pragma weak usb1_irqhandler = null_handler +#pragma weak sct_irqhandler = null_handler +#pragma weak ritimer_irqhandler = null_handler +#pragma weak timer0_irqhandler = null_handler +#pragma weak timer1_irqhandler = null_handler +#pragma weak timer2_irqhandler = null_handler +#pragma weak timer3_irqhandler = null_handler +#pragma weak mcpwm_irqhandler = null_handler +#pragma weak adc0_irqhandler = null_handler +#pragma weak i2c0_irqhandler = null_handler +#pragma weak i2c1_irqhandler = null_handler +#pragma weak spi_irqhandler = null_handler +#pragma weak adc1_irqhandler = null_handler +#pragma weak ssp0_irqhandler = null_handler +#pragma weak ssp1_irqhandler = null_handler +#pragma weak usart0_irqhandler = null_handler +#pragma weak uart1_irqhandler = null_handler +#pragma weak usart2_irqhandler = null_handler +#pragma weak usart3_irqhandler = null_handler +#pragma weak i2s0_irqhandler = null_handler +#pragma weak i2s1_irqhandler = null_handler +#pragma weak spifi_irqhandler = null_handler +#pragma weak sgpio_irqhandler = null_handler +#pragma weak pin_int0_irqhandler = null_handler +#pragma weak pin_int1_irqhandler = null_handler +#pragma weak pin_int2_irqhandler = null_handler +#pragma weak pin_int3_irqhandler = null_handler +#pragma weak pin_int4_irqhandler = null_handler +#pragma weak pin_int5_irqhandler = null_handler +#pragma weak pin_int6_irqhandler = null_handler +#pragma weak pin_int7_irqhandler = null_handler +#pragma weak gint0_irqhandler = null_handler +#pragma weak gint1_irqhandler = null_handler +#pragma weak eventrouter_irqhandler = null_handler +#pragma weak c_can1_irqhandler = null_handler +#pragma weak atimer_irqhandler = null_handler +#pragma weak rtc_irqhandler = null_handler +#pragma weak wwdt_irqhandler = null_handler +#pragma weak c_can0_irqhandler = null_handler +#pragma weak qei_irqhandler = null_handler + +#define IRQ_HANDLERS \ + dac_irqhandler, \ + m0core_irqhandler, \ + dma_irqhandler, \ + 0, /* reserved */ \ + 0, /* reserved */ \ + ethernet_irqhandler, \ + sdio_irqhandler, \ + lcd_irqhandler, \ + usb0_irqhandler, \ + usb1_irqhandler, \ + sct_irqhandler, \ + ritimer_irqhandler, \ + timer0_irqhandler, \ + timer1_irqhandler, \ + timer2_irqhandler, \ + timer3_irqhandler, \ + mcpwm_irqhandler, \ + adc0_irqhandler, \ + i2c0_irqhandler, \ + i2c1_irqhandler, \ + spi_irqhandler, \ + adc1_irqhandler, \ + ssp0_irqhandler, \ + ssp1_irqhandler, \ + usart0_irqhandler, \ + uart1_irqhandler, \ + usart2_irqhandler, \ + usart3_irqhandler, \ + i2s0_irqhandler, \ + i2s1_irqhandler, \ + spifi_irqhandler, \ + sgpio_irqhandler, \ + pin_int0_irqhandler, \ + pin_int1_irqhandler, \ + pin_int2_irqhandler, \ + pin_int3_irqhandler, \ + pin_int4_irqhandler, \ + pin_int5_irqhandler, \ + pin_int6_irqhandler, \ + pin_int7_irqhandler, \ + gint0_irqhandler, \ + gint1_irqhandler, \ + eventrouter_irqhandler, \ + c_can1_irqhandler, \ + 0, /* reserved */ \ + 0, /* reserved */ \ + atimer_irqhandler, \ + rtc_irqhandler, \ + 0, /* reserved */ \ + wwdt_irqhandler, \ + 0, /* reserved */ \ + c_can0_irqhandler, \ + qei_irqhandler, + +#endif diff --git a/include/libopencm3/stm32/f1/irq.h b/include/libopencm3/stm32/f1/irq.h new file mode 100644 index 0000000..cfa07f1 --- /dev/null +++ b/include/libopencm3/stm32/f1/irq.h @@ -0,0 +1,306 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F1_IRQ_H +#define LIBOPENCM3_STM32_F1_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMPER 2 +#define IRQ_RTC 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_CHANNEL1 11 +#define IRQ_DMA1_CHANNEL2 12 +#define IRQ_DMA1_CHANNEL3 13 +#define IRQ_DMA1_CHANNEL4 14 +#define IRQ_DMA1_CHANNEL5 15 +#define IRQ_DMA1_CHANNEL6 16 +#define IRQ_DMA1_CHANNEL7 17 +#define IRQ_ADC1_2 18 +#define IRQ_USB_HP_CAN_TX 19 +#define IRQ_USB_LP_CAN_RX0 20 +#define IRQ_CAN_RX1 21 +#define IRQ_CAN_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK 24 +#define IRQ_TIM1_UP 25 +#define IRQ_TIM1_TRG_COM 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_WAKEUP 42 +#define IRQ_TIM8_BRK 43 +#define IRQ_TIM8_UP 44 +#define IRQ_TIM8_TRG_COM 45 +#define IRQ_TIM8_CC 46 +#define IRQ_ADC3 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_CHANNEL1 56 +#define IRQ_DMA2_CHANNEL2 57 +#define IRQ_DMA2_CHANNEL3 58 +#define IRQ_DMA2_CHANNEL4_5 59 +#define IRQ_DMA2_CHANNEL5 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 + +/* FIXME: number from list in lib/stm32/f1/vector.c, might miss irqs */ +#define IRQ_COUNT 68 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamper_isr(void); +void WEAK rtc_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_channel1_isr(void); +void WEAK dma1_channel2_isr(void); +void WEAK dma1_channel3_isr(void); +void WEAK dma1_channel4_isr(void); +void WEAK dma1_channel5_isr(void); +void WEAK dma1_channel6_isr(void); +void WEAK dma1_channel7_isr(void); +void WEAK adc1_2_isr(void); +void WEAK usb_hp_can_tx_isr(void); +void WEAK usb_lp_can_rx0_isr(void); +void WEAK can_rx1_isr(void); +void WEAK can_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_isr(void); +void WEAK tim1_up_isr(void); +void WEAK tim1_trg_com_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_wakeup_isr(void); +void WEAK tim8_brk_isr(void); +void WEAK tim8_up_isr(void); +void WEAK tim8_trg_com_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK adc3_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_channel1_isr(void); +void WEAK dma2_channel2_isr(void); +void WEAK dma2_channel3_isr(void); +void WEAK dma2_channel4_5_isr(void); +void WEAK dma2_channel5_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamper_isr = null_handler +#pragma weak rtc_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_channel1_isr = null_handler +#pragma weak dma1_channel2_isr = null_handler +#pragma weak dma1_channel3_isr = null_handler +#pragma weak dma1_channel4_isr = null_handler +#pragma weak dma1_channel5_isr = null_handler +#pragma weak dma1_channel6_isr = null_handler +#pragma weak dma1_channel7_isr = null_handler +#pragma weak adc1_2_isr = null_handler +#pragma weak usb_hp_can_tx_isr = null_handler +#pragma weak usb_lp_can_rx0_isr = null_handler +#pragma weak can_rx1_isr = null_handler +#pragma weak can_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_isr = null_handler +#pragma weak tim1_up_isr = null_handler +#pragma weak tim1_trg_com_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_wakeup_isr = null_handler +#pragma weak tim8_brk_isr = null_handler +#pragma weak tim8_up_isr = null_handler +#pragma weak tim8_trg_com_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak adc3_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_channel1_isr = null_handler +#pragma weak dma2_channel2_isr = null_handler +#pragma weak dma2_channel3_isr = null_handler +#pragma weak dma2_channel4_5_isr = null_handler +#pragma weak dma2_channel5_isr +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamper_isr, \ + rtc_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_channel1_isr, \ + dma1_channel2_isr, \ + dma1_channel3_isr, \ + dma1_channel4_isr, \ + dma1_channel5_isr, \ + dma1_channel6_isr, \ + dma1_channel7_isr, \ + adc1_2_isr, \ + usb_hp_can_tx_isr, \ + usb_lp_can_rx0_isr, \ + can_rx1_isr, \ + can_sce_isr, \ + exti9_5_isr, \ + tim1_brk_isr, \ + tim1_up_isr, \ + tim1_trg_com_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_wakeup_isr, \ + tim8_brk_isr, \ + tim8_up_isr, \ + tim8_trg_com_isr, \ + tim8_cc_isr, \ + adc3_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_isr, \ + tim7_isr, \ + dma2_channel1_isr, \ + dma2_channel2_isr, \ + dma2_channel3_isr, \ + dma2_channel4_5_isr, \ + dma2_channel5_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + +#endif diff --git a/include/libopencm3/stm32/f2/irq.h b/include/libopencm3/stm32/f2/irq.h new file mode 100644 index 0000000..7aec142 --- /dev/null +++ b/include/libopencm3/stm32/f2/irq.h @@ -0,0 +1,359 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F2_IRQ_H +#define LIBOPENCM3_STM32_F2_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMP_STAMP 2 +#define IRQ_RTC_WKUP 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_STREAM0 11 +#define IRQ_DMA1_STREAM1 12 +#define IRQ_DMA1_STREAM2 13 +#define IRQ_DMA1_STREAM3 14 +#define IRQ_DMA1_STREAM4 15 +#define IRQ_DMA1_STREAM5 16 +#define IRQ_DMA1_STREAM6 17 +#define IRQ_ADC 18 +#define IRQ_CAN1_TX 19 +#define IRQ_CAN1_RX0 20 +#define IRQ_CAN1_RX1 21 +#define IRQ_CAN1_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK_TIM9 24 +#define IRQ_TIM1_UP_TIM10 25 +#define IRQ_TIM1_TRG_COM_TIM11 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_FS_WKUP 42 +#define IRQ_TIM8_BRK_TIM12 43 +#define IRQ_TIM8_UP_TIM13 44 +#define IRQ_TIM8_TRG_COM_TIM14 45 +#define IRQ_TIM8_CC 46 +#define IRQ_DMA1_STREAM7 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6_DAC 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_STREAM0 56 +#define IRQ_DMA2_STREAM1 57 +#define IRQ_DMA2_STREAM2 58 +#define IRQ_DMA2_STREAM3 59 +#define IRQ_DMA2_STREAM4 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 +#define IRQ_DMA2_STREAM5 68 +#define IRQ_DMA2_STREAM6 69 +#define IRQ_DMA2_STREAM7 70 +#define IRQ_USART6 71 +#define IRQ_I2C3_EV 72 +#define IRQ_I2C3_ER 73 +#define IRQ_OTG_HS_EP1_OUT 74 +#define IRQ_OTG_HS_EP1_IN 75 +#define IRQ_OTG_HS_WKUP 76 +#define IRQ_OTG_HS 77 +#define IRQ_DCMI 78 +#define IRQ_CRYP 79 +#define IRQ_HASH_RNG 80 + +/* FIXME: number from list in lib/stm32/f2/vector.c, might miss irqs */ +#define IRQ_COUNT 81 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamp_stamp_isr, \ + rtc_wkup_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_stream0_isr, \ + dma1_stream1_isr, \ + dma1_stream2_isr, \ + dma1_stream3_isr, \ + dma1_stream4_isr, \ + dma1_stream5_isr, \ + dma1_stream6_isr, \ + adc_isr, \ + can1_tx_isr, \ + can1_rx0_isr, \ + can1_rx1_isr, \ + can1_sce_isr, \ + exti9_5_isr, \ + tim1_brk_tim9_isr, \ + tim1_up_tim10_isr, \ + tim1_trg_com_tim11_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_fs_wkup_isr, \ + tim8_brk_tim12_isr, \ + tim8_up_tim13_isr, \ + tim8_trg_com_tim14_isr, \ + tim8_cc_isr, \ + dma1_stream7_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_dac_isr, \ + tim7_isr, \ + dma2_stream0_isr, \ + dma2_stream1_isr, \ + dma2_stream2_isr, \ + dma2_stream3_isr, \ + dma2_stream4_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + dma2_stream5_isr, \ + dma2_stream6_isr, \ + dma2_stream7_isr, \ + usart6_isr, \ + i2c3_ev_isr, \ + i2c3_er_isr, \ + otg_hs_ep1_out_isr, \ + otg_hs_ep1_in_isr, \ + otg_hs_wkup_isr, \ + otg_hs_isr, \ + dcmi_isr, \ + cryp_isr, \ + hash_rng_isr, + +#endif diff --git a/include/libopencm3/stm32/f4/irq.h b/include/libopencm3/stm32/f4/irq.h new file mode 100644 index 0000000..4f4f5e5 --- /dev/null +++ b/include/libopencm3/stm32/f4/irq.h @@ -0,0 +1,359 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F4_IRQ_H +#define LIBOPENCM3_STM32_F4_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMP_STAMP 2 +#define IRQ_RTC_WKUP 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_STREAM0 11 +#define IRQ_DMA1_STREAM1 12 +#define IRQ_DMA1_STREAM2 13 +#define IRQ_DMA1_STREAM3 14 +#define IRQ_DMA1_STREAM4 15 +#define IRQ_DMA1_STREAM5 16 +#define IRQ_DMA1_STREAM6 17 +#define IRQ_ADC 18 +#define IRQ_CAN1_TX 19 +#define IRQ_CAN1_RX0 20 +#define IRQ_CAN1_RX1 21 +#define IRQ_CAN1_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK_TIM9 24 +#define IRQ_TIM1_UP_TIM10 25 +#define IRQ_TIM1_TRG_COM_TIM11 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_FS_WKUP 42 +#define IRQ_TIM8_BRK_TIM12 43 +#define IRQ_TIM8_UP_TIM13 44 +#define IRQ_TIM8_TRG_COM_TIM14 45 +#define IRQ_TIM8_CC 46 +#define IRQ_DMA1_STREAM7 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6_DAC 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_STREAM0 56 +#define IRQ_DMA2_STREAM1 57 +#define IRQ_DMA2_STREAM2 58 +#define IRQ_DMA2_STREAM3 59 +#define IRQ_DMA2_STREAM4 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 +#define IRQ_DMA2_STREAM5 68 +#define IRQ_DMA2_STREAM6 69 +#define IRQ_DMA2_STREAM7 70 +#define IRQ_USART6 71 +#define IRQ_I2C3_EV 72 +#define IRQ_I2C3_ER 73 +#define IRQ_OTG_HS_EP1_OUT 74 +#define IRQ_OTG_HS_EP1_IN 75 +#define IRQ_OTG_HS_WKUP 76 +#define IRQ_OTG_HS 77 +#define IRQ_DCMI 78 +#define IRQ_CRYP 79 +#define IRQ_HASH_RNG 80 + +/* FIXME: number from list in lib/stm32/f4/vector.c, might miss irqs */ +#define IRQ_COUNT 81 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamp_stamp_isr, \ + rtc_wkup_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_stream0_isr, \ + dma1_stream1_isr, \ + dma1_stream2_isr, \ + dma1_stream3_isr, \ + dma1_stream4_isr, \ + dma1_stream5_isr, \ + dma1_stream6_isr, \ + adc_isr, \ + can1_tx_isr, \ + can1_rx0_isr, \ + can1_rx1_isr, \ + can1_sce_isr, \ + exti9_5_isr, \ + tim1_brk_tim9_isr, \ + tim1_up_tim10_isr, \ + tim1_trg_com_tim11_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_fs_wkup_isr, \ + tim8_brk_tim12_isr, \ + tim8_up_tim13_isr, \ + tim8_trg_com_tim14_isr, \ + tim8_cc_isr, \ + dma1_stream7_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_dac_isr, \ + tim7_isr, \ + dma2_stream0_isr, \ + dma2_stream1_isr, \ + dma2_stream2_isr, \ + dma2_stream3_isr, \ + dma2_stream4_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + dma2_stream5_isr, \ + dma2_stream6_isr, \ + dma2_stream7_isr, \ + usart6_isr, \ + i2c3_ev_isr, \ + i2c3_er_isr, \ + otg_hs_ep1_out_isr, \ + otg_hs_ep1_in_isr, \ + otg_hs_wkup_isr, \ + otg_hs_isr, \ + dcmi_isr, \ + cryp_isr, \ + hash_rng_isr, + +#endif -- cgit v1.2.3 From 837de3ff9771ea03b5b54dda8ba7f77d404bdcdf Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 10:27:51 +0200 Subject: nvic.h factored out (incomplete) --- include/libopencm3/cm3/nvic.h | 123 +++++++++++++++++++++++++++++++++++++ include/libopencm3/lpc43xx/nvic.h | 85 -------------------------- include/libopencm3/stm32/nvic.h | 124 -------------------------------------- 3 files changed, 123 insertions(+), 209 deletions(-) create mode 100644 include/libopencm3/cm3/nvic.h (limited to 'include') diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h new file mode 100644 index 0000000..3a3aa2f --- /dev/null +++ b/include/libopencm3/cm3/nvic.h @@ -0,0 +1,123 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_nvic_defines NVIC Defines + +@brief libopencm3 Cortex Nested Vectored Interrupt Controller + +@ingroup CM3_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/**@{*/ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 and M4 System Interrupts */ +/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts +@ingroup CM3_nvic_defines + +IRQ numbers -3 and -6 to -9 are reserved +@{*/ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 +/**@}*/ + +/* Note: User interrupts are family specific and are defined in a family + * specific header file in the corresponding subfolder. + */ + +/* --- NVIC functions ------------------------------------------------------ */ + +BEGIN_DECLS + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u16 irqn); + +END_DECLS + +#endif diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index cdbf070..597e21a 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -1,70 +1,3 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_NVIC_H -#define LPC43XX_NVIC_H - -#include -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M4 System Interrupts */ @@ -131,21 +64,3 @@ /* LPC43xx M0 specific user interrupts */ //TODO - -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h index 694fab8..b8c22a2 100644 --- a/include/libopencm3/stm32/nvic.h +++ b/include/libopencm3/stm32/nvic.h @@ -1,108 +1,3 @@ -/** @defgroup STM32F_nvic_defines NVIC Defines - -@brief libopencm3 STM32F Nested Vectored Interrupt Controller - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -/** @defgroup nvic_sysint Cortex M3 System Interrupts -@ingroup STM32F_nvic_defines - -IRQ numbers -3 and -6 to -9 are reserved -@{*/ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 -/**@}*/ - - -/* Note: User interrupts are family specific and are defined in a family - * specific header file in the corresponding subfolder. - */ - #if defined(STM32F1) # include #elif defined(STM32F2) @@ -114,22 +9,3 @@ IRQ numbers -3 and -6 to -9 are reserved #endif -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u16 irqn); - -END_DECLS - -#endif -/**@}*/ - -- cgit v1.2.3 From a7f5f9f576977f97988b739fd98ff7f164edf156 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 12:26:41 +0200 Subject: merge irq and nvic code using a script --- include/libopencm3/efm32/tinygecko/Makefile | 2 + include/libopencm3/efm32/tinygecko/irq.h | 130 -------------------------- include/libopencm3/efm32/tinygecko/irq.yaml | 28 ++++++ include/libopencm3/efm32/tinygecko/irq2nvic_h | 92 ++++++++++++++++++ 4 files changed, 122 insertions(+), 130 deletions(-) create mode 100644 include/libopencm3/efm32/tinygecko/Makefile delete mode 100644 include/libopencm3/efm32/tinygecko/irq.h create mode 100644 include/libopencm3/efm32/tinygecko/irq.yaml create mode 100755 include/libopencm3/efm32/tinygecko/irq2nvic_h (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/Makefile b/include/libopencm3/efm32/tinygecko/Makefile new file mode 100644 index 0000000..4ac5347 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/Makefile @@ -0,0 +1,2 @@ +nvic.h: irq.yaml + ./irq2nvic_h diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h deleted file mode 100644 index f5263ae..0000000 --- a/include/libopencm3/efm32/tinygecko/irq.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Definitions of interrupt names on EFM32 Tiny Gecko systems - * - * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H -#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H - -#define IRQ_DMA 0 -#define IRQ_GPIO_EVEN 1 -#define IRQ_TIMER0 2 -#define IRQ_USART0_RX 3 -#define IRQ_USART0_TX 4 -#define IRQ_ACMP01 5 -#define IRQ_ADC0 6 -#define IRQ_DAC0 7 -#define IRQ_I2C0 8 -#define IRQ_GPIO_ODD 9 -#define IRQ_TIMER1 10 -#define IRQ_USART1_RX 11 -#define IRQ_USART1_TX 12 -#define IRQ_LESENSE 13 -#define IRQ_LEUART0 14 -#define IRQ_LETIMER0 15 -#define IRQ_PCNT0 16 -#define IRQ_RTC 17 -#define IRQ_CMU 18 -#define IRQ_VCMP 19 -#define IRQ_LCD 20 -#define IRQ_MSC 21 -#define IRQ_AES 22 -#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ - -#define WEAK __attribute__ ((weak)) - -void WEAK dma_isr(void); -void WEAK gpio_even_isr(void); -void WEAK timer0_isr(void); -void WEAK usart0_rx_isr(void); -void WEAK usart0_tx_isr(void); -void WEAK acmp01_isr(void); -void WEAK adc0_isr(void); -void WEAK dac0_isr(void); -void WEAK i2c0_isr(void); -void WEAK gpio_odd_isr(void); -void WEAK timer1_isr(void); -void WEAK usart1_rx_isr(void); -void WEAK usart1_tx_isr(void); -void WEAK lesense_isr(void); -void WEAK leuart0_isr(void); -void WEAK letimer0_isr(void); -void WEAK pcnt0_isr(void); -void WEAK rtc_isr(void); -void WEAK cmu_isr(void); -void WEAK vcmp_isr(void); -void WEAK lcd_isr(void); -void WEAK msc_isr(void); -void WEAK aes_isr(void); - -#pragma weak dma_isr = blocking_handler -#pragma weak gpio_even_isr = blocking_handler -#pragma weak timer0_isr = blocking_handler -#pragma weak usart0_rx_isr = blocking_handler -#pragma weak usart0_tx_isr = blocking_handler -#pragma weak acmp01_isr = blocking_handler -#pragma weak adc0_isr = blocking_handler -#pragma weak dac0_isr = blocking_handler -#pragma weak i2c0_isr = blocking_handler -#pragma weak gpio_odd_isr = blocking_handler -#pragma weak timer1_isr = blocking_handler -#pragma weak usart1_rx_isr = blocking_handler -#pragma weak usart1_tx_isr = blocking_handler -#pragma weak lesense_isr = blocking_handler -#pragma weak leuart0_isr = blocking_handler -#pragma weak letimer0_isr = blocking_handler -#pragma weak pcnt0_isr = blocking_handler -#pragma weak rtc_isr = blocking_handler -#pragma weak cmu_isr = blocking_handler -#pragma weak vcmp_isr = blocking_handler -#pragma weak lcd_isr = blocking_handler -#pragma weak msc_isr = blocking_handler -#pragma weak aes_isr = blocking_handler - -#define IRQ_HANDLERS \ - [IRQ_DMA] = dma_isr, \ - [IRQ_GPIO_EVEN] = gpio_even_isr, \ - [IRQ_TIMER0] = timer0_isr, \ - [IRQ_USART0_RX] = usart0_rx_isr, \ - [IRQ_USART0_TX] = usart0_tx_isr, \ - [IRQ_ACMP01] = acmp01_isr, \ - [IRQ_ADC0] = adc0_isr, \ - [IRQ_DAC0] = dac0_isr, \ - [IRQ_I2C0] = i2c0_isr, \ - [IRQ_GPIO_ODD] = gpio_odd_isr, \ - [IRQ_TIMER1] = timer1_isr, \ - [IRQ_USART1_RX] = usart1_rx_isr, \ - [IRQ_USART1_TX] = usart1_tx_isr, \ - [IRQ_LESENSE] = lesense_isr, \ - [IRQ_LEUART0] = leuart0_isr, \ - [IRQ_LETIMER0] = letimer0_isr, \ - [IRQ_PCNT0] = pcnt0_isr, \ - [IRQ_RTC] = rtc_isr, \ - [IRQ_CMU] = cmu_isr, \ - [IRQ_VCMP] = vcmp_isr, \ - [IRQ_LCD] = lcd_isr, \ - [IRQ_MSC] = msc_isr, \ - [IRQ_AES] = aes_isr, - -#endif diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/tinygecko/irq.yaml new file mode 100644 index 0000000..16fa69c --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq.yaml @@ -0,0 +1,28 @@ +includeguard: LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +partname_humanreadable: EFM32 Tiny Gecko series +partname_doxygen: EFM32TG +# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. +irqs: + - dma + - gpio_even + - timer0 + - usart0_rx + - usart0_tx + - acmp01 + - adc0 + - dac0 + - i2c0 + - gpio_odd + - timer1 + - usart1_rx + - usart1_tx + - lesense + - leuart0 + - letimer0 + - pcnt0 + - rtc + - cmu + - vcmp + - lcd + - msc + - aes diff --git a/include/libopencm3/efm32/tinygecko/irq2nvic_h b/include/libopencm3/efm32/tinygecko/irq2nvic_h new file mode 100755 index 0000000..a7df16e --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq2nvic_h @@ -0,0 +1,92 @@ +#!/usr/bin/env python + +# This file is part of the libopencm3 project. +# +# Copyright (C) 2012 chrysn +# +# This library is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this library. If not, see . + +import sys +import yaml + +template = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + */ + +#ifndef {includeguard} +#define {includeguard} + +/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} + @ingroup CM3_nvic_defines + + @{{*/ + +{irqdefinitions} + +#define NVIC_IRQ_COUNT {irqcount} + +/**@}}*/ + +#define WEAK __attribute__ ((weak)) + +/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} + @ingroup CM3_nvic_isrprototypes + + @{{*/ + +{isrprototypes} + +/**@}}*/ + +/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} + @ingroup CM3_nvic_isrpragmas + + @{{*/ + +{isrpragmas} + +/**@}}*/ + +/* Initialization template for the interrupt vector table. This definition is + * used by the startup code generator (vector.c) to set the initial values for + * the interrupt handling routines to the chip family specific _isr weak + * symbols. */ + +#define IRQ_HANDLERS \\ + {vectortableinitialization} + +#endif /* {includeguard} */ +''' + +def convert(infile, outfile): + data = yaml.load(infile) + + irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) + irqnames = [v for (k,v) in irq2name] + + data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) + data['irqcount'] = len(irq2name) # FIXME: what if it's a sparse dictionary? + data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) + data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) + data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) + + outfile.write(template.format(**data)) + +def main(): + convert(open('irq.yaml'), open('nvic.h', 'w')) + +if __name__ == "__main__": + main() -- cgit v1.2.3 From f705d1cd6ec77f6610046c3d9a009c263b526f25 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 12:46:30 +0200 Subject: dispatch for chip specific nvic --- include/libopencm3/cm3/nvic.h | 2 ++ include/libopencm3/cm3/vector.h | 5 ++--- include/libopencm3/dispatch/nvic.h | 16 ++++++++++++++++ include/libopencm3/stm32/nvic.h | 11 ----------- 4 files changed, 20 insertions(+), 14 deletions(-) create mode 100644 include/libopencm3/dispatch/nvic.h delete mode 100644 include/libopencm3/stm32/nvic.h (limited to 'include') diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h index 3a3aa2f..3f83285 100644 --- a/include/libopencm3/cm3/nvic.h +++ b/include/libopencm3/cm3/nvic.h @@ -104,6 +104,8 @@ IRQ numbers -3 and -6 to -9 are reserved * specific header file in the corresponding subfolder. */ +#include + /* --- NVIC functions ------------------------------------------------------ */ BEGIN_DECLS diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h index 198992b..f78e9d8 100644 --- a/include/libopencm3/cm3/vector.h +++ b/include/libopencm3/cm3/vector.h @@ -38,8 +38,7 @@ #define LIBOPENCM3_VECTOR_H #include - -// #include "irq.h" /* we'll nede some definitions */ +#include /** Type of an interrupt function. Only used to avoid hard-to-read function * pointers in the efm32_vector_table_t struct. */ @@ -59,7 +58,7 @@ typedef struct { vector_table_entry_t reserved_x0034; vector_table_entry_t pend_sv; vector_table_entry_t systick; - vector_table_entry_t irq[IRQ_COUNT]; + vector_table_entry_t irq[NVIC_IRQ_COUNT]; } vector_table_t; #endif diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h new file mode 100644 index 0000000..322ec29 --- /dev/null +++ b/include/libopencm3/dispatch/nvic.h @@ -0,0 +1,16 @@ +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include + +#elif defined(TINYGECKO) +# include + +#elif defined(LPC43XX) +# include + +#else +# error "no chipset defined." +#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h deleted file mode 100644 index b8c22a2..0000000 --- a/include/libopencm3/stm32/nvic.h +++ /dev/null @@ -1,11 +0,0 @@ -#if defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#else -# error "stm32 family not defined." -#endif - - -- cgit v1.2.3 From a8a6eb39e9dfa25a9934298c6321b912337c0621 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:19:55 +0200 Subject: add irq cound to existing nvic.h files --- include/libopencm3/lpc43xx/nvic.h | 2 ++ include/libopencm3/stm32/f1/nvic_f1.h | 2 ++ include/libopencm3/stm32/f2/nvic_f2.h | 2 ++ include/libopencm3/stm32/f4/nvic_f4.h | 2 ++ 4 files changed, 8 insertions(+) (limited to 'include') diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index 597e21a..0fc5cc6 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -62,5 +62,7 @@ #define NVIC_M4_C_CAN0_IRQ 51 #define NVIC_M4_QEI_IRQ 52 +#define NVIC_IRQ_COUNT 53 + /* LPC43xx M0 specific user interrupts */ //TODO diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h index 5223bb6..1544e4f 100644 --- a/include/libopencm3/stm32/f1/nvic_f1.h +++ b/include/libopencm3/stm32/f1/nvic_f1.h @@ -109,6 +109,8 @@ LGPL License Terms @ref lgpl_license #define NVIC_CAN2_RX1_IRQ 65 #define NVIC_CAN2_SCE_IRQ 66 #define NVIC_OTG_FS_IRQ 67 + +#define NVIC_IRQ_COUNT 68 /**@}*/ #endif diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h index 2bf2997..65a990d 100644 --- a/include/libopencm3/stm32/f2/nvic_f2.h +++ b/include/libopencm3/stm32/f2/nvic_f2.h @@ -109,4 +109,6 @@ #define NVIC_CRYP_IRQ 79 #define NVIC_HASH_RNG_IRQ 80 +#define NVIC_IRQ_COUNT 81 + #endif diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h index 91b6c25..013e3b5 100644 --- a/include/libopencm3/stm32/f4/nvic_f4.h +++ b/include/libopencm3/stm32/f4/nvic_f4.h @@ -109,4 +109,6 @@ #define NVIC_CRYP_IRQ 79 #define NVIC_HASH_RNG_IRQ 80 +#define NVIC_IRQ_COUNT 81 + #endif -- cgit v1.2.3 From 1684ffe18d4f8e54ebcec204b965bd1052ad7885 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:27:33 +0200 Subject: fallback for unknown chips --- include/libopencm3/dispatch/nvic.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 322ec29..a405b5d 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -12,5 +12,9 @@ # include #else -# error "no chipset defined." +# warning"no chipset defined; user interrupts are disabled" + +#define NVIC_IRQ_COUNT 0 +#define IRQ_HANDLERS + #endif -- cgit v1.2.3 From 5ceb377a378203c80580fbe5160000fca998b635 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 16:52:48 +0200 Subject: switch all interrupt lists to yaml format --- include/libopencm3/dispatch/nvic.h | 6 +- include/libopencm3/efm32/tinygecko/irq.yaml | 2 +- include/libopencm3/efm32/tinygecko/irq2nvic_h | 92 ----- include/libopencm3/lm3s/irq.h | 505 -------------------------- include/libopencm3/lm3s/irq.yaml | 120 ++++++ include/libopencm3/lpc17xx/irq.h | 33 -- include/libopencm3/lpc43xx/irq.h | 234 ------------ include/libopencm3/lpc43xx/irq.yaml | 55 +++ include/libopencm3/lpc43xx/nvic.h | 68 ---- include/libopencm3/stm32/f1/irq.h | 306 ---------------- include/libopencm3/stm32/f1/irq.yaml | 72 ++++ include/libopencm3/stm32/f1/nvic_f1.h | 116 ------ include/libopencm3/stm32/f2/irq.h | 359 ------------------ include/libopencm3/stm32/f2/irq.yaml | 85 +++++ include/libopencm3/stm32/f2/nvic_f2.h | 114 ------ include/libopencm3/stm32/f4/irq.h | 359 ------------------ include/libopencm3/stm32/f4/irq.yaml | 85 +++++ include/libopencm3/stm32/f4/nvic_f4.h | 114 ------ scripts/irq2nvic_h | 105 ++++++ 19 files changed, 526 insertions(+), 2304 deletions(-) delete mode 100755 include/libopencm3/efm32/tinygecko/irq2nvic_h delete mode 100644 include/libopencm3/lm3s/irq.h create mode 100644 include/libopencm3/lm3s/irq.yaml delete mode 100644 include/libopencm3/lpc17xx/irq.h delete mode 100644 include/libopencm3/lpc43xx/irq.h create mode 100644 include/libopencm3/lpc43xx/irq.yaml delete mode 100644 include/libopencm3/lpc43xx/nvic.h delete mode 100644 include/libopencm3/stm32/f1/irq.h create mode 100644 include/libopencm3/stm32/f1/irq.yaml delete mode 100644 include/libopencm3/stm32/f1/nvic_f1.h delete mode 100644 include/libopencm3/stm32/f2/irq.h create mode 100644 include/libopencm3/stm32/f2/irq.yaml delete mode 100644 include/libopencm3/stm32/f2/nvic_f2.h delete mode 100644 include/libopencm3/stm32/f4/irq.h create mode 100644 include/libopencm3/stm32/f4/irq.yaml delete mode 100644 include/libopencm3/stm32/f4/nvic_f4.h create mode 100755 scripts/irq2nvic_h (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index a405b5d..67ba544 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -1,9 +1,9 @@ #if defined(STM32F1) -# include +# include #elif defined(STM32F2) -# include +# include #elif defined(STM32F4) -# include +# include #elif defined(TINYGECKO) # include diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/tinygecko/irq.yaml index 16fa69c..da954f6 100644 --- a/include/libopencm3/efm32/tinygecko/irq.yaml +++ b/include/libopencm3/efm32/tinygecko/irq.yaml @@ -1,4 +1,4 @@ -includeguard: LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +includeguard: LIBOPENCM3_EFM32_TINYGECKO_NVIC_H partname_humanreadable: EFM32 Tiny Gecko series partname_doxygen: EFM32TG # The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. diff --git a/include/libopencm3/efm32/tinygecko/irq2nvic_h b/include/libopencm3/efm32/tinygecko/irq2nvic_h deleted file mode 100755 index a7df16e..0000000 --- a/include/libopencm3/efm32/tinygecko/irq2nvic_h +++ /dev/null @@ -1,92 +0,0 @@ -#!/usr/bin/env python - -# This file is part of the libopencm3 project. -# -# Copyright (C) 2012 chrysn -# -# This library is free software: you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this library. If not, see . - -import sys -import yaml - -template = '''\ -/* This file is part of the libopencm3 project. - * - * It was generated by the irq2nvic_h script. - */ - -#ifndef {includeguard} -#define {includeguard} - -/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} - @ingroup CM3_nvic_defines - - @{{*/ - -{irqdefinitions} - -#define NVIC_IRQ_COUNT {irqcount} - -/**@}}*/ - -#define WEAK __attribute__ ((weak)) - -/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} - @ingroup CM3_nvic_isrprototypes - - @{{*/ - -{isrprototypes} - -/**@}}*/ - -/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} - @ingroup CM3_nvic_isrpragmas - - @{{*/ - -{isrpragmas} - -/**@}}*/ - -/* Initialization template for the interrupt vector table. This definition is - * used by the startup code generator (vector.c) to set the initial values for - * the interrupt handling routines to the chip family specific _isr weak - * symbols. */ - -#define IRQ_HANDLERS \\ - {vectortableinitialization} - -#endif /* {includeguard} */ -''' - -def convert(infile, outfile): - data = yaml.load(infile) - - irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) - irqnames = [v for (k,v) in irq2name] - - data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) - data['irqcount'] = len(irq2name) # FIXME: what if it's a sparse dictionary? - data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) - data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) - data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) - - outfile.write(template.format(**data)) - -def main(): - convert(open('irq.yaml'), open('nvic.h', 'w')) - -if __name__ == "__main__": - main() diff --git a/include/libopencm3/lm3s/irq.h b/include/libopencm3/lm3s/irq.h deleted file mode 100644 index 331ee51..0000000 --- a/include/libopencm3/lm3s/irq.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LM3S_IRQ_H -#define LIBOPENCM3_LM3S_IRQ_H - -#define IRQ_GPIOA 0 -#define IRQ_GPIOB 1 -#define IRQ_GPIOC 2 -#define IRQ_GPIOD 3 -#define IRQ_GPIOE 4 -#define IRQ_UART0 5 -#define IRQ_UART1 6 -#define IRQ_SSI0 7 -#define IRQ_I2C0 8 -#define IRQ_PWM0_FAULT 9 -#define IRQ_PWM0_0 10 -#define IRQ_PWM0_1 11 -#define IRQ_PWM0_2 12 -#define IRQ_QEI0 13 -#define IRQ_ADC0SS0 14 -#define IRQ_ADC0SS1 15 -#define IRQ_ADC0SS2 16 -#define IRQ_ADC0SS3 17 -#define IRQ_WATCHDOG 18 -#define IRQ_TIMER0A 19 -#define IRQ_TIMER0B 20 -#define IRQ_TIMER1A 21 -#define IRQ_TIMER1B 22 -#define IRQ_TIMER2A 23 -#define IRQ_TIMER2B 24 -#define IRQ_COMP0 25 -#define IRQ_COMP1 26 -#define IRQ_COMP2 27 -#define IRQ_SYSCTL 28 -#define IRQ_FLASH 29 -#define IRQ_GPIOF 30 -#define IRQ_GPIOG 31 -#define IRQ_GPIOH 32 -#define IRQ_UART2 33 -#define IRQ_SSI1 34 -#define IRQ_TIMER3A 35 -#define IRQ_TIMER3B 36 -#define IRQ_I2C1 37 -#define IRQ_QEI1 38 -#define IRQ_CAN0 39 -#define IRQ_CAN1 40 -#define IRQ_CAN2 41 -#define IRQ_ETH 42 -#define IRQ_HIBERNATE 43 -#define IRQ_USB0 44 -#define IRQ_PWM0_3 45 -#define IRQ_UDMA 46 -#define IRQ_UDMAERR 47 -#define IRQ_ADC1SS0 48 -#define IRQ_ADC1SS1 49 -#define IRQ_ADC1SS2 50 -#define IRQ_ADC1SS3 51 -#define IRQ_I2S0 52 -#define IRQ_EPI0 53 -#define IRQ_GPIOJ 54 -#define IRQ_GPIOK 55 -#define IRQ_GPIOL 56 -#define IRQ_SSI2 57 -#define IRQ_SSI3 58 -#define IRQ_UART3 59 -#define IRQ_UART4 60 -#define IRQ_UART5 61 -#define IRQ_UART6 62 -#define IRQ_UART7 63 -/* undefined: slot 64 */ -/* undefined: slot 65 */ -/* undefined: slot 66 */ -/* undefined: slot 67 */ -#define IRQ_I2C2 68 -#define IRQ_I2C3 69 -#define IRQ_TIMER4A 70 -#define IRQ_TIMER4B 71 -/* undefined: slot 72 */ -/* undefined: slot 73 */ -/* undefined: slot 74 */ -/* undefined: slot 75 */ -/* undefined: slot 76 */ -/* undefined: slot 77 */ -/* undefined: slot 78 */ -/* undefined: slot 79 */ -/* undefined: slot 80 */ -/* undefined: slot 81 */ -/* undefined: slot 82 */ -/* undefined: slot 83 */ -/* undefined: slot 84 */ -/* undefined: slot 85 */ -/* undefined: slot 86 */ -/* undefined: slot 87 */ -/* undefined: slot 88 */ -/* undefined: slot 89 */ -/* undefined: slot 90 */ -/* undefined: slot 91 */ -#define IRQ_TIMER5A 92 -#define IRQ_TIMER5B 93 -#define IRQ_WTIMER0A 94 -#define IRQ_WTIMER0B 95 -#define IRQ_WTIMER1A 96 -#define IRQ_WTIMER1B 97 -#define IRQ_WTIMER2A 98 -#define IRQ_WTIMER2B 99 -#define IRQ_WTIMER3A 100 -#define IRQ_WTIMER3B 101 -#define IRQ_WTIMER4A 102 -#define IRQ_WTIMER4B 103 -#define IRQ_WTIMER5A 104 -#define IRQ_WTIMER5B 105 -#define IRQ_SYSEXC 106 -#define IRQ_PECI0 107 -#define IRQ_LPC0 108 -#define IRQ_I2C4 109 -#define IRQ_I2C5 110 -#define IRQ_GPIOM 111 -#define IRQ_GPION 112 -/* undefined: slot 113 */ -#define IRQ_FAN0 114 -/* undefined: slot 115 */ -#define IRQ_GPIOP0 116 -#define IRQ_GPIOP1 117 -#define IRQ_GPIOP2 118 -#define IRQ_GPIOP3 119 -#define IRQ_GPIOP4 120 -#define IRQ_GPIOP5 121 -#define IRQ_GPIOP6 122 -#define IRQ_GPIOP7 123 -#define IRQ_GPIOQ0 124 -#define IRQ_GPIOQ1 125 -#define IRQ_GPIOQ2 126 -#define IRQ_GPIOQ3 127 -#define IRQ_GPIOQ4 128 -#define IRQ_GPIOQ5 129 -#define IRQ_GPIOQ6 130 -#define IRQ_GPIOQ7 131 -/* undefined: slot 132 */ -/* undefined: slot 133 */ -#define IRQ_PWM1_0 134 -#define IRQ_PWM1_1 135 -#define IRQ_PWM1_2 136 -#define IRQ_PWM1_3 137 -#define IRQ_PWM1_FAULT 138 - -#define IRQ_COUNT 139 - -#define WEAK __attribute__ ((weak)) - -void WEAK gpioa_isr(void); -void WEAK gpiob_isr(void); -void WEAK gpioc_isr(void); -void WEAK gpiod_isr(void); -void WEAK gpioe_isr(void); -void WEAK uart0_isr(void); -void WEAK uart1_isr(void); -void WEAK ssi0_isr(void); -void WEAK i2c0_isr(void); -void WEAK pwm0_fault_isr(void); -void WEAK pwm0_0_isr(void); -void WEAK pwm0_1_isr(void); -void WEAK pwm0_2_isr(void); -void WEAK qei0_isr(void); -void WEAK adc0ss0_isr(void); -void WEAK adc0ss1_isr(void); -void WEAK adc0ss2_isr(void); -void WEAK adc0ss3_isr(void); -void WEAK watchdog_isr(void); -void WEAK timer0a_isr(void); -void WEAK timer0b_isr(void); -void WEAK timer1a_isr(void); -void WEAK timer1b_isr(void); -void WEAK timer2a_isr(void); -void WEAK timer2b_isr(void); -void WEAK comp0_isr(void); -void WEAK comp1_isr(void); -void WEAK comp2_isr(void); -void WEAK sysctl_isr(void); -void WEAK flash_isr(void); -void WEAK gpiof_isr(void); -void WEAK gpiog_isr(void); -void WEAK gpioh_isr(void); -void WEAK uart2_isr(void); -void WEAK ssi1_isr(void); -void WEAK timer3a_isr(void); -void WEAK timer3b_isr(void); -void WEAK i2c1_isr(void); -void WEAK qei1_isr(void); -void WEAK can0_isr(void); -void WEAK can1_isr(void); -void WEAK can2_isr(void); -void WEAK eth_isr(void); -void WEAK hibernate_isr(void); -void WEAK usb0_isr(void); -void WEAK pwm0_3_isr(void); -void WEAK udma_isr(void); -void WEAK udmaerr_isr(void); -void WEAK adc1ss0_isr(void); -void WEAK adc1ss1_isr(void); -void WEAK adc1ss2_isr(void); -void WEAK adc1ss3_isr(void); -void WEAK i2s0_isr(void); -void WEAK epi0_isr(void); -void WEAK gpioj_isr(void); -void WEAK gpiok_isr(void); -void WEAK gpiol_isr(void); -void WEAK ssi2_isr(void); -void WEAK ssi3_isr(void); -void WEAK uart3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK uart6_isr(void); -void WEAK uart7_isr(void); -void WEAK i2c2_isr(void); -void WEAK i2c3_isr(void); -void WEAK timer4a_isr(void); -void WEAK timer4b_isr(void); -void WEAK timer5a_isr(void); -void WEAK timer5b_isr(void); -void WEAK wtimer0a_isr(void); -void WEAK wtimer0b_isr(void); -void WEAK wtimer1a_isr(void); -void WEAK wtimer1b_isr(void); -void WEAK wtimer2a_isr(void); -void WEAK wtimer2b_isr(void); -void WEAK wtimer3a_isr(void); -void WEAK wtimer3b_isr(void); -void WEAK wtimer4a_isr(void); -void WEAK wtimer4b_isr(void); -void WEAK wtimer5a_isr(void); -void WEAK wtimer5b_isr(void); -void WEAK sysexc_isr(void); -void WEAK peci0_isr(void); -void WEAK lpc0_isr(void); -void WEAK i2c4_isr(void); -void WEAK i2c5_isr(void); -void WEAK gpiom_isr(void); -void WEAK gpion_isr(void); -void WEAK fan0_isr(void); -void WEAK gpiop0_isr(void); -void WEAK gpiop1_isr(void); -void WEAK gpiop2_isr(void); -void WEAK gpiop3_isr(void); -void WEAK gpiop4_isr(void); -void WEAK gpiop5_isr(void); -void WEAK gpiop6_isr(void); -void WEAK gpiop7_isr(void); -void WEAK gpioq0_isr(void); -void WEAK gpioq1_isr(void); -void WEAK gpioq2_isr(void); -void WEAK gpioq3_isr(void); -void WEAK gpioq4_isr(void); -void WEAK gpioq5_isr(void); -void WEAK gpioq6_isr(void); -void WEAK gpioq7_isr(void); -void WEAK pwm1_0_isr(void); -void WEAK pwm1_1_isr(void); -void WEAK pwm1_2_isr(void); -void WEAK pwm1_3_isr(void); -void WEAK pwm1_fault_isr(void); - -#pragma weak gpioa_isr = blocking_handler -#pragma weak gpiob_isr = blocking_handler -#pragma weak gpioc_isr = blocking_handler -#pragma weak gpiod_isr = blocking_handler -#pragma weak gpioe_isr = blocking_handler -#pragma weak uart0_isr = blocking_handler -#pragma weak uart1_isr = blocking_handler -#pragma weak ssi0_isr = blocking_handler -#pragma weak i2c0_isr = blocking_handler -#pragma weak pwm0_fault_isr = blocking_handler -#pragma weak pwm0_0_isr = blocking_handler -#pragma weak pwm0_1_isr = blocking_handler -#pragma weak pwm0_2_isr = blocking_handler -#pragma weak qei0_isr = blocking_handler -#pragma weak adc0ss0_isr = blocking_handler -#pragma weak adc0ss1_isr = blocking_handler -#pragma weak adc0ss2_isr = blocking_handler -#pragma weak adc0ss3_isr = blocking_handler -#pragma weak watchdog_isr = blocking_handler -#pragma weak timer0a_isr = blocking_handler -#pragma weak timer0b_isr = blocking_handler -#pragma weak timer1a_isr = blocking_handler -#pragma weak timer1b_isr = blocking_handler -#pragma weak timer2a_isr = blocking_handler -#pragma weak timer2b_isr = blocking_handler -#pragma weak comp0_isr = blocking_handler -#pragma weak comp1_isr = blocking_handler -#pragma weak comp2_isr = blocking_handler -#pragma weak sysctl_isr = blocking_handler -#pragma weak flash_isr = blocking_handler -#pragma weak gpiof_isr = blocking_handler -#pragma weak gpiog_isr = blocking_handler -#pragma weak gpioh_isr = blocking_handler -#pragma weak uart2_isr = blocking_handler -#pragma weak ssi1_isr = blocking_handler -#pragma weak timer3a_isr = blocking_handler -#pragma weak timer3b_isr = blocking_handler -#pragma weak i2c1_isr = blocking_handler -#pragma weak qei1_isr = blocking_handler -#pragma weak can0_isr = blocking_handler -#pragma weak can1_isr = blocking_handler -#pragma weak can2_isr = blocking_handler -#pragma weak eth_isr = blocking_handler -#pragma weak hibernate_isr = blocking_handler -#pragma weak usb0_isr = blocking_handler -#pragma weak pwm0_3_isr = blocking_handler -#pragma weak udma_isr = blocking_handler -#pragma weak udmaerr_isr = blocking_handler -#pragma weak adc1ss0_isr = blocking_handler -#pragma weak adc1ss1_isr = blocking_handler -#pragma weak adc1ss2_isr = blocking_handler -#pragma weak adc1ss3_isr = blocking_handler -#pragma weak i2s0_isr = blocking_handler -#pragma weak epi0_isr = blocking_handler -#pragma weak gpioj_isr = blocking_handler -#pragma weak gpiok_isr = blocking_handler -#pragma weak gpiol_isr = blocking_handler -#pragma weak ssi2_isr = blocking_handler -#pragma weak ssi3_isr = blocking_handler -#pragma weak uart3_isr = blocking_handler -#pragma weak uart4_isr = blocking_handler -#pragma weak uart5_isr = blocking_handler -#pragma weak uart6_isr = blocking_handler -#pragma weak uart7_isr = blocking_handler -#pragma weak i2c2_isr = blocking_handler -#pragma weak i2c3_isr = blocking_handler -#pragma weak timer4a_isr = blocking_handler -#pragma weak timer4b_isr = blocking_handler -#pragma weak timer5a_isr = blocking_handler -#pragma weak timer5b_isr = blocking_handler -#pragma weak wtimer0a_isr = blocking_handler -#pragma weak wtimer0b_isr = blocking_handler -#pragma weak wtimer1a_isr = blocking_handler -#pragma weak wtimer1b_isr = blocking_handler -#pragma weak wtimer2a_isr = blocking_handler -#pragma weak wtimer2b_isr = blocking_handler -#pragma weak wtimer3a_isr = blocking_handler -#pragma weak wtimer3b_isr = blocking_handler -#pragma weak wtimer4a_isr = blocking_handler -#pragma weak wtimer4b_isr = blocking_handler -#pragma weak wtimer5a_isr = blocking_handler -#pragma weak wtimer5b_isr = blocking_handler -#pragma weak sysexc_isr = blocking_handler -#pragma weak peci0_isr = blocking_handler -#pragma weak lpc0_isr = blocking_handler -#pragma weak i2c4_isr = blocking_handler -#pragma weak i2c5_isr = blocking_handler -#pragma weak gpiom_isr = blocking_handler -#pragma weak gpion_isr = blocking_handler -#pragma weak fan0_isr = blocking_handler -#pragma weak gpiop0_isr = blocking_handler -#pragma weak gpiop1_isr = blocking_handler -#pragma weak gpiop2_isr = blocking_handler -#pragma weak gpiop3_isr = blocking_handler -#pragma weak gpiop4_isr = blocking_handler -#pragma weak gpiop5_isr = blocking_handler -#pragma weak gpiop6_isr = blocking_handler -#pragma weak gpiop7_isr = blocking_handler -#pragma weak gpioq0_isr = blocking_handler -#pragma weak gpioq1_isr = blocking_handler -#pragma weak gpioq2_isr = blocking_handler -#pragma weak gpioq3_isr = blocking_handler -#pragma weak gpioq4_isr = blocking_handler -#pragma weak gpioq5_isr = blocking_handler -#pragma weak gpioq6_isr = blocking_handler -#pragma weak gpioq7_isr = blocking_handler -#pragma weak pwm1_0_isr = blocking_handler -#pragma weak pwm1_1_isr = blocking_handler -#pragma weak pwm1_2_isr = blocking_handler -#pragma weak pwm1_3_isr = blocking_handler -#pragma weak pwm1_fault_isr = blocking_handler - -#define IRQ_HANDLERS \ - [IRQ_GPIOA] = gpioa_isr, \ - [IRQ_GPIOB] = gpiob_isr, \ - [IRQ_GPIOC] = gpioc_isr, \ - [IRQ_GPIOD] = gpiod_isr, \ - [IRQ_GPIOE] = gpioe_isr, \ - [IRQ_UART0] = uart0_isr, \ - [IRQ_UART1] = uart1_isr, \ - [IRQ_SSI0] = ssi0_isr, \ - [IRQ_I2C0] = i2c0_isr, \ - [IRQ_PWM0_FAULT] = pwm0_fault_isr, \ - [IRQ_PWM0_0] = pwm0_0_isr, \ - [IRQ_PWM0_1] = pwm0_1_isr, \ - [IRQ_PWM0_2] = pwm0_2_isr, \ - [IRQ_QEI0] = qei0_isr, \ - [IRQ_ADC0SS0] = adc0ss0_isr, \ - [IRQ_ADC0SS1] = adc0ss1_isr, \ - [IRQ_ADC0SS2] = adc0ss2_isr, \ - [IRQ_ADC0SS3] = adc0ss3_isr, \ - [IRQ_WATCHDOG] = watchdog_isr, \ - [IRQ_TIMER0A] = timer0a_isr, \ - [IRQ_TIMER0B] = timer0b_isr, \ - [IRQ_TIMER1A] = timer1a_isr, \ - [IRQ_TIMER1B] = timer1b_isr, \ - [IRQ_TIMER2A] = timer2a_isr, \ - [IRQ_TIMER2B] = timer2b_isr, \ - [IRQ_COMP0] = comp0_isr, \ - [IRQ_COMP1] = comp1_isr, \ - [IRQ_COMP2] = comp2_isr, \ - [IRQ_SYSCTL] = sysctl_isr, \ - [IRQ_FLASH] = flash_isr, \ - [IRQ_GPIOF] = gpiof_isr, \ - [IRQ_GPIOG] = gpiog_isr, \ - [IRQ_GPIOH] = gpioh_isr, \ - [IRQ_UART2] = uart2_isr, \ - [IRQ_SSI1] = ssi1_isr, \ - [IRQ_TIMER3A] = timer3a_isr, \ - [IRQ_TIMER3B] = timer3b_isr, \ - [IRQ_I2C1] = i2c1_isr, \ - [IRQ_QEI1] = qei1_isr, \ - [IRQ_CAN0] = can0_isr, \ - [IRQ_CAN1] = can1_isr, \ - [IRQ_CAN2] = can2_isr, \ - [IRQ_ETH] = eth_isr, \ - [IRQ_HIBERNATE] = hibernate_isr, \ - [IRQ_USB0] = usb0_isr, \ - [IRQ_PWM0_3] = pwm0_3_isr, \ - [IRQ_UDMA] = udma_isr, \ - [IRQ_UDMAERR] = udmaerr_isr, \ - [IRQ_ADC1SS0] = adc1ss0_isr, \ - [IRQ_ADC1SS1] = adc1ss1_isr, \ - [IRQ_ADC1SS2] = adc1ss2_isr, \ - [IRQ_ADC1SS3] = adc1ss3_isr, \ - [IRQ_I2S0] = i2s0_isr, \ - [IRQ_EPI0] = epi0_isr, \ - [IRQ_GPIOJ] = gpioj_isr, \ - [IRQ_GPIOK] = gpiok_isr, \ - [IRQ_GPIOL] = gpiol_isr, \ - [IRQ_SSI2] = ssi2_isr, \ - [IRQ_SSI3] = ssi3_isr, \ - [IRQ_UART3] = uart3_isr, \ - [IRQ_UART4] = uart4_isr, \ - [IRQ_UART5] = uart5_isr, \ - [IRQ_UART6] = uart6_isr, \ - [IRQ_UART7] = uart7_isr, \ - [IRQ_I2C2] = i2c2_isr, \ - [IRQ_I2C3] = i2c3_isr, \ - [IRQ_TIMER4A] = timer4a_isr, \ - [IRQ_TIMER4B] = timer4b_isr, \ - [IRQ_TIMER5A] = timer5a_isr, \ - [IRQ_TIMER5B] = timer5b_isr, \ - [IRQ_WTIMER0A] = wtimer0a_isr, \ - [IRQ_WTIMER0B] = wtimer0b_isr, \ - [IRQ_WTIMER1A] = wtimer1a_isr, \ - [IRQ_WTIMER1B] = wtimer1b_isr, \ - [IRQ_WTIMER2A] = wtimer2a_isr, \ - [IRQ_WTIMER2B] = wtimer2b_isr, \ - [IRQ_WTIMER3A] = wtimer3a_isr, \ - [IRQ_WTIMER3B] = wtimer3b_isr, \ - [IRQ_WTIMER4A] = wtimer4a_isr, \ - [IRQ_WTIMER4B] = wtimer4b_isr, \ - [IRQ_WTIMER5A] = wtimer5a_isr, \ - [IRQ_WTIMER5B] = wtimer5b_isr, \ - [IRQ_SYSEXC] = sysexc_isr, \ - [IRQ_PECI0] = peci0_isr, \ - [IRQ_LPC0] = lpc0_isr, \ - [IRQ_I2C4] = i2c4_isr, \ - [IRQ_I2C5] = i2c5_isr, \ - [IRQ_GPIOM] = gpiom_isr, \ - [IRQ_GPION] = gpion_isr, \ - [IRQ_FAN0] = fan0_isr, \ - [IRQ_GPIOP0] = gpiop0_isr, \ - [IRQ_GPIOP1] = gpiop1_isr, \ - [IRQ_GPIOP2] = gpiop2_isr, \ - [IRQ_GPIOP3] = gpiop3_isr, \ - [IRQ_GPIOP4] = gpiop4_isr, \ - [IRQ_GPIOP5] = gpiop5_isr, \ - [IRQ_GPIOP6] = gpiop6_isr, \ - [IRQ_GPIOP7] = gpiop7_isr, \ - [IRQ_GPIOQ0] = gpioq0_isr, \ - [IRQ_GPIOQ1] = gpioq1_isr, \ - [IRQ_GPIOQ2] = gpioq2_isr, \ - [IRQ_GPIOQ3] = gpioq3_isr, \ - [IRQ_GPIOQ4] = gpioq4_isr, \ - [IRQ_GPIOQ5] = gpioq5_isr, \ - [IRQ_GPIOQ6] = gpioq6_isr, \ - [IRQ_GPIOQ7] = gpioq7_isr, \ - [IRQ_PWM1_0] = pwm1_0_isr, \ - [IRQ_PWM1_1] = pwm1_1_isr, \ - [IRQ_PWM1_2] = pwm1_2_isr, \ - [IRQ_PWM1_3] = pwm1_3_isr, \ - [IRQ_PWM1_FAULT] = pwm1_fault_isr, - -#endif diff --git a/include/libopencm3/lm3s/irq.yaml b/include/libopencm3/lm3s/irq.yaml new file mode 100644 index 0000000..7d5ff3a --- /dev/null +++ b/include/libopencm3/lm3s/irq.yaml @@ -0,0 +1,120 @@ +includeguard: LIBOPENCM3_LM3S_NVIC_H +partname_humanreadable: LM3S series +partname_doxygen: LM3S +irqs: + 0: GPIOA + 1: GPIOB + 2: GPIOC + 3: GPIOD + 4: GPIOE + 5: UART0 + 6: UART1 + 7: SSI0 + 8: I2C0 + 9: PWM0_FAULT + 10: PWM0_0 + 11: PWM0_1 + 12: PWM0_2 + 13: QEI0 + 14: ADC0SS0 + 15: ADC0SS1 + 16: ADC0SS2 + 17: ADC0SS3 + 18: WATCHDOG + 19: TIMER0A + 20: TIMER0B + 21: TIMER1A + 22: TIMER1B + 23: TIMER2A + 24: TIMER2B + 25: COMP0 + 26: COMP1 + 27: COMP2 + 28: SYSCTL + 29: FLASH + 30: GPIOF + 31: GPIOG + 32: GPIOH + 33: UART2 + 34: SSI1 + 35: TIMER3A + 36: TIMER3B + 37: I2C1 + 38: QEI1 + 39: CAN0 + 40: CAN1 + 41: CAN2 + 42: ETH + 43: HIBERNATE + 44: USB0 + 45: PWM0_3 + 46: UDMA + 47: UDMAERR + 48: ADC1SS0 + 49: ADC1SS1 + 50: ADC1SS2 + 51: ADC1SS3 + 52: I2S0 + 53: EPI0 + 54: GPIOJ + 55: GPIOK + 56: GPIOL + 57: SSI2 + 58: SSI3 + 59: UART3 + 60: UART4 + 61: UART5 + 62: UART6 + 63: UART7 +# undefined: slot 64 - 67 + 68: I2C2 + 69: I2C3 + 70: TIMER4A + 71: TIMER4B +# undefined: slot 72 - 91 + 92: TIMER5A + 93: TIMER5B + 94: WTIMER0A + 95: WTIMER0B + 96: WTIMER1A + 97: WTIMER1B + 98: WTIMER2A + 99: WTIMER2B + 100: WTIMER3A + 101: WTIMER3B + 102: WTIMER4A + 103: WTIMER4B + 104: WTIMER5A + 105: WTIMER5B + 106: SYSEXC + 107: PECI0 + 108: LPC0 + 109: I2C4 + 110: I2C5 + 111: GPIOM + 112: GPION +# undefined: slot 113 + 114: FAN0 +# undefined: slot 115 + 116: GPIOP0 + 117: GPIOP1 + 118: GPIOP2 + 119: GPIOP3 + 120: GPIOP4 + 121: GPIOP5 + 122: GPIOP6 + 123: GPIOP7 + 124: GPIOQ0 + 125: GPIOQ1 + 126: GPIOQ2 + 127: GPIOQ3 + 128: GPIOQ4 + 129: GPIOQ5 + 130: GPIOQ6 + 131: GPIOQ7 +# undefined: slot 132 - 133 + 134: PWM1_0 + 135: PWM1_1 + 136: PWM1_2 + 137: PWM1_3 + 138: PWM1_FAULT diff --git a/include/libopencm3/lpc17xx/irq.h b/include/libopencm3/lpc17xx/irq.h deleted file mode 100644 index 9c31267..0000000 --- a/include/libopencm3/lpc17xx/irq.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPC17xx_IRQ_H -#define LIBOPENCM3_LPC17xx_IRQ_H - -/* TODO: Interrupt definitions */ -#define IRQ_COUNT 0 - -/* TODO: Interrupt handler prototypes */ - -/* TODO: Interrupt handler weak aliases */ - -#define IRQ_HANDLERS - -#endif diff --git a/include/libopencm3/lpc43xx/irq.h b/include/libopencm3/lpc43xx/irq.h deleted file mode 100644 index a83a8d7..0000000 --- a/include/libopencm3/lpc43xx/irq.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPC43XX_IRQ_H -#define LIBOPENCM3_LPC43XX_IRQ_H - -#define IRQ_DAC 0 -#define IRQ_M0CORE 1 -#define IRQ_DMA 2 -/* reserved: 3 */ -/* reserved: 4 */ -#define IRQ_ETHERNET 5 -#define IRQ_SDIO 6 -#define IRQ_LCD 7 -#define IRQ_USB0 8 -#define IRQ_USB1 9 -#define IRQ_SCT 10 -#define IRQ_RITIMER 11 -#define IRQ_TIMER0 12 -#define IRQ_TIMER1 13 -#define IRQ_TIMER2 14 -#define IRQ_TIMER3 15 -#define IRQ_MCPWM 16 -#define IRQ_ADC0 17 -#define IRQ_I2C0 18 -#define IRQ_I2C1 19 -#define IRQ_SPI 20 -#define IRQ_ADC1 21 -#define IRQ_SSP0 22 -#define IRQ_SSP1 23 -#define IRQ_USART0 24 -#define IRQ_UART1 25 -#define IRQ_USART2 26 -#define IRQ_USART3 27 -#define IRQ_I2S0 28 -#define IRQ_I2S1 29 -#define IRQ_SPIFI 30 -#define IRQ_SGPIO 31 -#define IRQ_PIN_INT0 32 -#define IRQ_PIN_INT1 33 -#define IRQ_PIN_INT2 34 -#define IRQ_PIN_INT3 35 -#define IRQ_PIN_INT4 36 -#define IRQ_PIN_INT5 37 -#define IRQ_PIN_INT6 38 -#define IRQ_PIN_INT7 39 -#define IRQ_GINT0 40 -#define IRQ_GINT1 41 -#define IRQ_EVENTROUTER 42 -#define IRQ_C_CAN1 43 -/* reserved: 44 */ -/* reserved: 45 */ -#define IRQ_ATIMER 46 -#define IRQ_RTC 47 -/* reserved: 48 */ -#define IRQ_WWDT 49 -/* reserved: 50 */ -#define IRQ_C_CAN0 51 -#define IRQ_QEI 52 - -#define IRQ_COUNT 53 - -#define WEAK __attribute__ ((weak)) - -void WEAK dac_irqhandler(void); -void WEAK m0core_irqhandler(void); -void WEAK dma_irqhandler(void); -void WEAK ethernet_irqhandler(void); -void WEAK sdio_irqhandler(void); -void WEAK lcd_irqhandler(void); -void WEAK usb0_irqhandler(void); -void WEAK usb1_irqhandler(void); -void WEAK sct_irqhandler(void); -void WEAK ritimer_irqhandler(void); -void WEAK timer0_irqhandler(void); -void WEAK timer1_irqhandler(void); -void WEAK timer2_irqhandler(void); -void WEAK timer3_irqhandler(void); -void WEAK mcpwm_irqhandler(void); -void WEAK adc0_irqhandler(void); -void WEAK i2c0_irqhandler(void); -void WEAK i2c1_irqhandler(void); -void WEAK spi_irqhandler(void); -void WEAK adc1_irqhandler(void); -void WEAK ssp0_irqhandler(void); -void WEAK ssp1_irqhandler(void); -void WEAK usart0_irqhandler(void); -void WEAK uart1_irqhandler(void); -void WEAK usart2_irqhandler(void); -void WEAK usart3_irqhandler(void); -void WEAK i2s0_irqhandler(void); -void WEAK i2s1_irqhandler(void); -void WEAK spifi_irqhandler(void); -void WEAK sgpio_irqhandler(void); -void WEAK pin_int0_irqhandler(void); -void WEAK pin_int1_irqhandler(void); -void WEAK pin_int2_irqhandler(void); -void WEAK pin_int3_irqhandler(void); -void WEAK pin_int4_irqhandler(void); -void WEAK pin_int5_irqhandler(void); -void WEAK pin_int6_irqhandler(void); -void WEAK pin_int7_irqhandler(void); -void WEAK gint0_irqhandler(void); -void WEAK gint1_irqhandler(void); -void WEAK eventrouter_irqhandler(void); -void WEAK c_can1_irqhandler(void); -void WEAK atimer_irqhandler(void); -void WEAK rtc_irqhandler(void); -void WEAK wwdt_irqhandler(void); -void WEAK c_can0_irqhandler(void); -void WEAK qei_irqhandler(void); - -#pragma weak dac_irqhandler = null_handler -#pragma weak m0core_irqhandler = null_handler -#pragma weak dma_irqhandler = null_handler -#pragma weak ethernet_irqhandler = null_handler -#pragma weak sdio_irqhandler = null_handler -#pragma weak lcd_irqhandler = null_handler -#pragma weak usb0_irqhandler = null_handler -#pragma weak usb1_irqhandler = null_handler -#pragma weak sct_irqhandler = null_handler -#pragma weak ritimer_irqhandler = null_handler -#pragma weak timer0_irqhandler = null_handler -#pragma weak timer1_irqhandler = null_handler -#pragma weak timer2_irqhandler = null_handler -#pragma weak timer3_irqhandler = null_handler -#pragma weak mcpwm_irqhandler = null_handler -#pragma weak adc0_irqhandler = null_handler -#pragma weak i2c0_irqhandler = null_handler -#pragma weak i2c1_irqhandler = null_handler -#pragma weak spi_irqhandler = null_handler -#pragma weak adc1_irqhandler = null_handler -#pragma weak ssp0_irqhandler = null_handler -#pragma weak ssp1_irqhandler = null_handler -#pragma weak usart0_irqhandler = null_handler -#pragma weak uart1_irqhandler = null_handler -#pragma weak usart2_irqhandler = null_handler -#pragma weak usart3_irqhandler = null_handler -#pragma weak i2s0_irqhandler = null_handler -#pragma weak i2s1_irqhandler = null_handler -#pragma weak spifi_irqhandler = null_handler -#pragma weak sgpio_irqhandler = null_handler -#pragma weak pin_int0_irqhandler = null_handler -#pragma weak pin_int1_irqhandler = null_handler -#pragma weak pin_int2_irqhandler = null_handler -#pragma weak pin_int3_irqhandler = null_handler -#pragma weak pin_int4_irqhandler = null_handler -#pragma weak pin_int5_irqhandler = null_handler -#pragma weak pin_int6_irqhandler = null_handler -#pragma weak pin_int7_irqhandler = null_handler -#pragma weak gint0_irqhandler = null_handler -#pragma weak gint1_irqhandler = null_handler -#pragma weak eventrouter_irqhandler = null_handler -#pragma weak c_can1_irqhandler = null_handler -#pragma weak atimer_irqhandler = null_handler -#pragma weak rtc_irqhandler = null_handler -#pragma weak wwdt_irqhandler = null_handler -#pragma weak c_can0_irqhandler = null_handler -#pragma weak qei_irqhandler = null_handler - -#define IRQ_HANDLERS \ - dac_irqhandler, \ - m0core_irqhandler, \ - dma_irqhandler, \ - 0, /* reserved */ \ - 0, /* reserved */ \ - ethernet_irqhandler, \ - sdio_irqhandler, \ - lcd_irqhandler, \ - usb0_irqhandler, \ - usb1_irqhandler, \ - sct_irqhandler, \ - ritimer_irqhandler, \ - timer0_irqhandler, \ - timer1_irqhandler, \ - timer2_irqhandler, \ - timer3_irqhandler, \ - mcpwm_irqhandler, \ - adc0_irqhandler, \ - i2c0_irqhandler, \ - i2c1_irqhandler, \ - spi_irqhandler, \ - adc1_irqhandler, \ - ssp0_irqhandler, \ - ssp1_irqhandler, \ - usart0_irqhandler, \ - uart1_irqhandler, \ - usart2_irqhandler, \ - usart3_irqhandler, \ - i2s0_irqhandler, \ - i2s1_irqhandler, \ - spifi_irqhandler, \ - sgpio_irqhandler, \ - pin_int0_irqhandler, \ - pin_int1_irqhandler, \ - pin_int2_irqhandler, \ - pin_int3_irqhandler, \ - pin_int4_irqhandler, \ - pin_int5_irqhandler, \ - pin_int6_irqhandler, \ - pin_int7_irqhandler, \ - gint0_irqhandler, \ - gint1_irqhandler, \ - eventrouter_irqhandler, \ - c_can1_irqhandler, \ - 0, /* reserved */ \ - 0, /* reserved */ \ - atimer_irqhandler, \ - rtc_irqhandler, \ - 0, /* reserved */ \ - wwdt_irqhandler, \ - 0, /* reserved */ \ - c_can0_irqhandler, \ - qei_irqhandler, - -#endif diff --git a/include/libopencm3/lpc43xx/irq.yaml b/include/libopencm3/lpc43xx/irq.yaml new file mode 100644 index 0000000..bc9536b --- /dev/null +++ b/include/libopencm3/lpc43xx/irq.yaml @@ -0,0 +1,55 @@ +includeguard: LIBOPENCM3_LPC43xx_NVIC_H +partname_humanreadable: LPC 43xx series +partname_doxygen: LPC43xx +irqs: + 0: dac + 1: m0core + 2: dma +# reserved: 3, 4 + 5: ethernet + 6: sdio + 7: lcd + 8: usb0 + 9: usb1 + 10: sct + 11: ritimer + 12: timer0 + 13: timer1 + 14: timer2 + 15: timer3 + 16: mcpwm + 17: adc0 + 18: i2c0 + 19: i2c1 + 20: spi + 21: adc1 + 22: ssp0 + 23: ssp1 + 24: usart0 + 25: uart1 + 26: usart2 + 27: usart3 + 28: i2s0 + 29: i2s1 + 30: spifi + 31: sgpio + 32: pin_int0 + 33: pin_int1 + 34: pin_int2 + 35: pin_int3 + 36: pin_int4 + 37: pin_int5 + 38: pin_int6 + 39: pin_int7 + 40: gint0 + 41: gint1 + 42: eventrouter + 43: c_can1 +# reserved: 44, 45 + 46: atimer + 47: rtc +# reserved: 48 + 49: wwdt +# reserved: 50 + 51: c_can0 + 52: qei diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h deleted file mode 100644 index 0fc5cc6..0000000 --- a/include/libopencm3/lpc43xx/nvic.h +++ /dev/null @@ -1,68 +0,0 @@ -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M4 System Interrupts */ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 - -/* LPC43xx M4 specific user interrupts */ -#define NVIC_M4_DAC_IRQ 0 -#define NVIC_M4_M0CORE_IRQ 1 -#define NVIC_M4_DMA_IRQ 2 -#define NVIC_M4_ETHERNET_IRQ 5 -#define NVIC_M4_SDIO_IRQ 6 -#define NVIC_M4_LCD_IRQ 7 -#define NVIC_M4_USB0_IRQ 8 -#define NVIC_M4_USB1_IRQ 9 -#define NVIC_M4_SCT_IRQ 10 -#define NVIC_M4_RITIMER_IRQ 11 -#define NVIC_M4_TIMER0_IRQ 12 -#define NVIC_M4_TIMER1_IRQ 13 -#define NVIC_M4_TIMER2_IRQ 14 -#define NVIC_M4_TIMER3_IRQ 15 -#define NVIC_M4_MCPWM_IRQ 16 -#define NVIC_M4_ADC0_IRQ 17 -#define NVIC_M4_I2C0_IRQ 18 -#define NVIC_M4_I2C1_IRQ 19 -#define NVIC_M4_SPI_IRQ 20 -#define NVIC_M4_ADC1_IRQ 21 -#define NVIC_M4_SSP0_IRQ 22 -#define NVIC_M4_SSP1_IRQ 23 -#define NVIC_M4_USART0_IRQ 24 -#define NVIC_M4_UART1_IRQ 25 -#define NVIC_M4_USART2_IRQ 26 -#define NVIC_M4_USART3_IRQ 27 -#define NVIC_M4_I2S0_IRQ 28 -#define NVIC_M4_I2S1_IRQ 29 -#define NVIC_M4_SPIFI_IRQ 30 -#define NVIC_M4_SGPIO_IRQ 31 -#define NVIC_M4_PIN_INT0_IRQ 32 -#define NVIC_M4_PIN_INT1_IRQ 33 -#define NVIC_M4_PIN_INT2_IRQ 34 -#define NVIC_M4_PIN_INT3_IRQ 35 -#define NVIC_M4_PIN_INT4_IRQ 36 -#define NVIC_M4_PIN_INT5_IRQ 37 -#define NVIC_M4_PIN_INT6_IRQ 38 -#define NVIC_M4_PIN_INT7_IRQ 39 -#define NVIC_M4_GINT0_IRQ 40 -#define NVIC_M4_GINT1_IRQ 41 -#define NVIC_M4_EVENTROUTER_IRQ 42 -#define NVIC_M4_C_CAN1_IRQ 43 -#define NVIC_M4_ATIMER_IRQ 46 -#define NVIC_M4_RTC_IRQ 47 -#define NVIC_M4_WWDT_IRQ 49 -#define NVIC_M4_C_CAN0_IRQ 51 -#define NVIC_M4_QEI_IRQ 52 - -#define NVIC_IRQ_COUNT 53 - -/* LPC43xx M0 specific user interrupts */ -//TODO diff --git a/include/libopencm3/stm32/f1/irq.h b/include/libopencm3/stm32/f1/irq.h deleted file mode 100644 index cfa07f1..0000000 --- a/include/libopencm3/stm32/f1/irq.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F1_IRQ_H -#define LIBOPENCM3_STM32_F1_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMPER 2 -#define IRQ_RTC 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_CHANNEL1 11 -#define IRQ_DMA1_CHANNEL2 12 -#define IRQ_DMA1_CHANNEL3 13 -#define IRQ_DMA1_CHANNEL4 14 -#define IRQ_DMA1_CHANNEL5 15 -#define IRQ_DMA1_CHANNEL6 16 -#define IRQ_DMA1_CHANNEL7 17 -#define IRQ_ADC1_2 18 -#define IRQ_USB_HP_CAN_TX 19 -#define IRQ_USB_LP_CAN_RX0 20 -#define IRQ_CAN_RX1 21 -#define IRQ_CAN_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK 24 -#define IRQ_TIM1_UP 25 -#define IRQ_TIM1_TRG_COM 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_WAKEUP 42 -#define IRQ_TIM8_BRK 43 -#define IRQ_TIM8_UP 44 -#define IRQ_TIM8_TRG_COM 45 -#define IRQ_TIM8_CC 46 -#define IRQ_ADC3 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_CHANNEL1 56 -#define IRQ_DMA2_CHANNEL2 57 -#define IRQ_DMA2_CHANNEL3 58 -#define IRQ_DMA2_CHANNEL4_5 59 -#define IRQ_DMA2_CHANNEL5 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 - -/* FIXME: number from list in lib/stm32/f1/vector.c, might miss irqs */ -#define IRQ_COUNT 68 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamper_isr(void); -void WEAK rtc_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_channel1_isr(void); -void WEAK dma1_channel2_isr(void); -void WEAK dma1_channel3_isr(void); -void WEAK dma1_channel4_isr(void); -void WEAK dma1_channel5_isr(void); -void WEAK dma1_channel6_isr(void); -void WEAK dma1_channel7_isr(void); -void WEAK adc1_2_isr(void); -void WEAK usb_hp_can_tx_isr(void); -void WEAK usb_lp_can_rx0_isr(void); -void WEAK can_rx1_isr(void); -void WEAK can_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_isr(void); -void WEAK tim1_up_isr(void); -void WEAK tim1_trg_com_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_wakeup_isr(void); -void WEAK tim8_brk_isr(void); -void WEAK tim8_up_isr(void); -void WEAK tim8_trg_com_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK adc3_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_channel1_isr(void); -void WEAK dma2_channel2_isr(void); -void WEAK dma2_channel3_isr(void); -void WEAK dma2_channel4_5_isr(void); -void WEAK dma2_channel5_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamper_isr = null_handler -#pragma weak rtc_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_channel1_isr = null_handler -#pragma weak dma1_channel2_isr = null_handler -#pragma weak dma1_channel3_isr = null_handler -#pragma weak dma1_channel4_isr = null_handler -#pragma weak dma1_channel5_isr = null_handler -#pragma weak dma1_channel6_isr = null_handler -#pragma weak dma1_channel7_isr = null_handler -#pragma weak adc1_2_isr = null_handler -#pragma weak usb_hp_can_tx_isr = null_handler -#pragma weak usb_lp_can_rx0_isr = null_handler -#pragma weak can_rx1_isr = null_handler -#pragma weak can_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_isr = null_handler -#pragma weak tim1_up_isr = null_handler -#pragma weak tim1_trg_com_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_wakeup_isr = null_handler -#pragma weak tim8_brk_isr = null_handler -#pragma weak tim8_up_isr = null_handler -#pragma weak tim8_trg_com_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak adc3_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_channel1_isr = null_handler -#pragma weak dma2_channel2_isr = null_handler -#pragma weak dma2_channel3_isr = null_handler -#pragma weak dma2_channel4_5_isr = null_handler -#pragma weak dma2_channel5_isr -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamper_isr, \ - rtc_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_channel1_isr, \ - dma1_channel2_isr, \ - dma1_channel3_isr, \ - dma1_channel4_isr, \ - dma1_channel5_isr, \ - dma1_channel6_isr, \ - dma1_channel7_isr, \ - adc1_2_isr, \ - usb_hp_can_tx_isr, \ - usb_lp_can_rx0_isr, \ - can_rx1_isr, \ - can_sce_isr, \ - exti9_5_isr, \ - tim1_brk_isr, \ - tim1_up_isr, \ - tim1_trg_com_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_wakeup_isr, \ - tim8_brk_isr, \ - tim8_up_isr, \ - tim8_trg_com_isr, \ - tim8_cc_isr, \ - adc3_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_isr, \ - tim7_isr, \ - dma2_channel1_isr, \ - dma2_channel2_isr, \ - dma2_channel3_isr, \ - dma2_channel4_5_isr, \ - dma2_channel5_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - -#endif diff --git a/include/libopencm3/stm32/f1/irq.yaml b/include/libopencm3/stm32/f1/irq.yaml new file mode 100644 index 0000000..14cbcc0 --- /dev/null +++ b/include/libopencm3/stm32/f1/irq.yaml @@ -0,0 +1,72 @@ +includeguard: LIBOPENCM3_STM32_F1_NVIC_H +partname_humanreadable: STM32 F1 series +partname_doxygen: STM32F1 +irqs: + - wwdg + - pvd + - tamper + - rtc + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_channel1 + - dma1_channel2 + - dma1_channel3 + - dma1_channel4 + - dma1_channel5 + - dma1_channel6 + - dma1_channel7 + - adc1_2 + - usb_hp_can_tx + - usb_lp_can_rx0 + - can_rx1 + - can_sce + - exti9_5 + - tim1_brk + - tim1_up + - tim1_trg_com + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_wakeup + - tim8_brk + - tim8_up + - tim8_trg_com + - tim8_cc + - adc3 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6 + - tim7 + - dma2_channel1 + - dma2_channel2 + - dma2_channel3 + - dma2_channel4_5 + - dma2_channel5 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h deleted file mode 100644 index 1544e4f..0000000 --- a/include/libopencm3/stm32/f1/nvic_f1.h +++ /dev/null @@ -1,116 +0,0 @@ -/** @brief Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F1_H -#define LIBOPENCM3_NVIC_F1_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F1 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts -@ingroup STM32F_nvic_defines - -@{*/ -#define NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMPER_IRQ 2 -#define NVIC_RTC_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_CHANNEL1_IRQ 11 -#define NVIC_DMA1_CHANNEL2_IRQ 12 -#define NVIC_DMA1_CHANNEL3_IRQ 13 -#define NVIC_DMA1_CHANNEL4_IRQ 14 -#define NVIC_DMA1_CHANNEL5_IRQ 15 -#define NVIC_DMA1_CHANNEL6_IRQ 16 -#define NVIC_DMA1_CHANNEL7_IRQ 17 -#define NVIC_ADC1_2_IRQ 18 -#define NVIC_USB_HP_CAN_TX_IRQ 19 -#define NVIC_USB_LP_CAN_RX0_IRQ 20 -#define NVIC_CAN_RX1_IRQ 21 -#define NVIC_CAN_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_IRQ 24 -#define NVIC_TIM1_UP_IRQ 25 -#define NVIC_TIM1_TRG_COM_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_WAKEUP_IRQ 42 -#define NVIC_TIM8_BRK_IRQ 43 -#define NVIC_TIM8_UP_IRQ 44 -#define NVIC_TIM8_TRG_COM_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_ADC3_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_CHANNEL1_IRQ 56 -#define NVIC_DMA2_CHANNEL2_IRQ 57 -#define NVIC_DMA2_CHANNEL3_IRQ 58 -#define NVIC_DMA2_CHANNEL4_5_IRQ 59 -#define NVIC_DMA2_CHANNEL5_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 - -#define NVIC_IRQ_COUNT 68 -/**@}*/ - -#endif diff --git a/include/libopencm3/stm32/f2/irq.h b/include/libopencm3/stm32/f2/irq.h deleted file mode 100644 index 7aec142..0000000 --- a/include/libopencm3/stm32/f2/irq.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F2_IRQ_H -#define LIBOPENCM3_STM32_F2_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMP_STAMP 2 -#define IRQ_RTC_WKUP 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_STREAM0 11 -#define IRQ_DMA1_STREAM1 12 -#define IRQ_DMA1_STREAM2 13 -#define IRQ_DMA1_STREAM3 14 -#define IRQ_DMA1_STREAM4 15 -#define IRQ_DMA1_STREAM5 16 -#define IRQ_DMA1_STREAM6 17 -#define IRQ_ADC 18 -#define IRQ_CAN1_TX 19 -#define IRQ_CAN1_RX0 20 -#define IRQ_CAN1_RX1 21 -#define IRQ_CAN1_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK_TIM9 24 -#define IRQ_TIM1_UP_TIM10 25 -#define IRQ_TIM1_TRG_COM_TIM11 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_FS_WKUP 42 -#define IRQ_TIM8_BRK_TIM12 43 -#define IRQ_TIM8_UP_TIM13 44 -#define IRQ_TIM8_TRG_COM_TIM14 45 -#define IRQ_TIM8_CC 46 -#define IRQ_DMA1_STREAM7 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6_DAC 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_STREAM0 56 -#define IRQ_DMA2_STREAM1 57 -#define IRQ_DMA2_STREAM2 58 -#define IRQ_DMA2_STREAM3 59 -#define IRQ_DMA2_STREAM4 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 -#define IRQ_DMA2_STREAM5 68 -#define IRQ_DMA2_STREAM6 69 -#define IRQ_DMA2_STREAM7 70 -#define IRQ_USART6 71 -#define IRQ_I2C3_EV 72 -#define IRQ_I2C3_ER 73 -#define IRQ_OTG_HS_EP1_OUT 74 -#define IRQ_OTG_HS_EP1_IN 75 -#define IRQ_OTG_HS_WKUP 76 -#define IRQ_OTG_HS 77 -#define IRQ_DCMI 78 -#define IRQ_CRYP 79 -#define IRQ_HASH_RNG 80 - -/* FIXME: number from list in lib/stm32/f2/vector.c, might miss irqs */ -#define IRQ_COUNT 81 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_stream0_isr, \ - dma1_stream1_isr, \ - dma1_stream2_isr, \ - dma1_stream3_isr, \ - dma1_stream4_isr, \ - dma1_stream5_isr, \ - dma1_stream6_isr, \ - adc_isr, \ - can1_tx_isr, \ - can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim9_isr, \ - tim1_up_tim10_isr, \ - tim1_trg_com_tim11_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_fs_wkup_isr, \ - tim8_brk_tim12_isr, \ - tim8_up_tim13_isr, \ - tim8_trg_com_tim14_isr, \ - tim8_cc_isr, \ - dma1_stream7_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_stream0_isr, \ - dma2_stream1_isr, \ - dma2_stream2_isr, \ - dma2_stream3_isr, \ - dma2_stream4_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - dma2_stream5_isr, \ - dma2_stream6_isr, \ - dma2_stream7_isr, \ - usart6_isr, \ - i2c3_ev_isr, \ - i2c3_er_isr, \ - otg_hs_ep1_out_isr, \ - otg_hs_ep1_in_isr, \ - otg_hs_wkup_isr, \ - otg_hs_isr, \ - dcmi_isr, \ - cryp_isr, \ - hash_rng_isr, - -#endif diff --git a/include/libopencm3/stm32/f2/irq.yaml b/include/libopencm3/stm32/f2/irq.yaml new file mode 100644 index 0000000..c3600b3 --- /dev/null +++ b/include/libopencm3/stm32/f2/irq.yaml @@ -0,0 +1,85 @@ +includeguard: LIBOPENCM3_STM32_F2_NVIC_H +partname_humanreadable: STM32 F2 series +partname_doxygen: STM32F2 +irqs: + - nvic_wwdg + - pvd + - tamp_stamp + - rtc_wkup + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_stream0 + - dma1_stream1 + - dma1_stream2 + - dma1_stream3 + - dma1_stream4 + - dma1_stream5 + - dma1_stream6 + - adc + - can1_tx + - can1_rx0 + - can1_rx1 + - can1_sce + - exti9_5 + - tim1_brk_tim9 + - tim1_up_tim10 + - tim1_trg_com_tim11 + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_fs_wkup + - tim8_brk_tim12 + - tim8_up_tim13 + - tim8_trg_com_tim14 + - tim8_cc + - dma1_stream7 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6_dac + - tim7 + - dma2_stream0 + - dma2_stream1 + - dma2_stream2 + - dma2_stream3 + - dma2_stream4 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs + - dma2_stream5 + - dma2_stream6 + - dma2_stream7 + - usart6 + - i2c3_ev + - i2c3_er + - otg_hs_ep1_out + - otg_hs_ep1_in + - otg_hs_wkup + - otg_hs + - dcmi + - cryp + - hash_rng diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h deleted file mode 100644 index 65a990d..0000000 --- a/include/libopencm3/stm32/f2/nvic_f2.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F2_H -#define LIBOPENCM3_NVIC_F2_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F2 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -#define NVIC_NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMP_STAMP_IRQ 2 -#define NVIC_RTC_WKUP_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_STREAM0_IRQ 11 -#define NVIC_DMA1_STREAM1_IRQ 12 -#define NVIC_DMA1_STREAM2_IRQ 13 -#define NVIC_DMA1_STREAM3_IRQ 14 -#define NVIC_DMA1_STREAM4_IRQ 15 -#define NVIC_DMA1_STREAM5_IRQ 16 -#define NVIC_DMA1_STREAM6_IRQ 17 -#define NVIC_ADC_IRQ 18 -#define NVIC_CAN1_TX_IRQ 19 -#define NVIC_CAN1_RX0_IRQ 20 -#define NVIC_CAN1_RX1_IRQ 21 -#define NVIC_CAN1_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_TIM9_IRQ 24 -#define NVIC_TIM1_UP_TIM10_IRQ 25 -#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_FS_WKUP_IRQ 42 -#define NVIC_TIM8_BRK_TIM12_IRQ 43 -#define NVIC_TIM8_UP_TIM13_IRQ 44 -#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_DMA1_STREAM7_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_DAC_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_STREAM0_IRQ 56 -#define NVIC_DMA2_STREAM1_IRQ 57 -#define NVIC_DMA2_STREAM2_IRQ 58 -#define NVIC_DMA2_STREAM3_IRQ 59 -#define NVIC_DMA2_STREAM4_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 -#define NVIC_DMA2_STREAM5_IRQ 68 -#define NVIC_DMA2_STREAM6_IRQ 69 -#define NVIC_DMA2_STREAM7_IRQ 70 -#define NVIC_USART6_IRQ 71 -#define NVIC_I2C3_EV_IRQ 72 -#define NVIC_I2C3_ER_IRQ 73 -#define NVIC_OTG_HS_EP1_OUT_IRQ 74 -#define NVIC_OTG_HS_EP1_IN_IRQ 75 -#define NVIC_OTG_HS_WKUP_IRQ 76 -#define NVIC_OTG_HS_IRQ 77 -#define NVIC_DCMI_IRQ 78 -#define NVIC_CRYP_IRQ 79 -#define NVIC_HASH_RNG_IRQ 80 - -#define NVIC_IRQ_COUNT 81 - -#endif diff --git a/include/libopencm3/stm32/f4/irq.h b/include/libopencm3/stm32/f4/irq.h deleted file mode 100644 index 4f4f5e5..0000000 --- a/include/libopencm3/stm32/f4/irq.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F4_IRQ_H -#define LIBOPENCM3_STM32_F4_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMP_STAMP 2 -#define IRQ_RTC_WKUP 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_STREAM0 11 -#define IRQ_DMA1_STREAM1 12 -#define IRQ_DMA1_STREAM2 13 -#define IRQ_DMA1_STREAM3 14 -#define IRQ_DMA1_STREAM4 15 -#define IRQ_DMA1_STREAM5 16 -#define IRQ_DMA1_STREAM6 17 -#define IRQ_ADC 18 -#define IRQ_CAN1_TX 19 -#define IRQ_CAN1_RX0 20 -#define IRQ_CAN1_RX1 21 -#define IRQ_CAN1_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK_TIM9 24 -#define IRQ_TIM1_UP_TIM10 25 -#define IRQ_TIM1_TRG_COM_TIM11 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_FS_WKUP 42 -#define IRQ_TIM8_BRK_TIM12 43 -#define IRQ_TIM8_UP_TIM13 44 -#define IRQ_TIM8_TRG_COM_TIM14 45 -#define IRQ_TIM8_CC 46 -#define IRQ_DMA1_STREAM7 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6_DAC 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_STREAM0 56 -#define IRQ_DMA2_STREAM1 57 -#define IRQ_DMA2_STREAM2 58 -#define IRQ_DMA2_STREAM3 59 -#define IRQ_DMA2_STREAM4 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 -#define IRQ_DMA2_STREAM5 68 -#define IRQ_DMA2_STREAM6 69 -#define IRQ_DMA2_STREAM7 70 -#define IRQ_USART6 71 -#define IRQ_I2C3_EV 72 -#define IRQ_I2C3_ER 73 -#define IRQ_OTG_HS_EP1_OUT 74 -#define IRQ_OTG_HS_EP1_IN 75 -#define IRQ_OTG_HS_WKUP 76 -#define IRQ_OTG_HS 77 -#define IRQ_DCMI 78 -#define IRQ_CRYP 79 -#define IRQ_HASH_RNG 80 - -/* FIXME: number from list in lib/stm32/f4/vector.c, might miss irqs */ -#define IRQ_COUNT 81 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_stream0_isr, \ - dma1_stream1_isr, \ - dma1_stream2_isr, \ - dma1_stream3_isr, \ - dma1_stream4_isr, \ - dma1_stream5_isr, \ - dma1_stream6_isr, \ - adc_isr, \ - can1_tx_isr, \ - can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim9_isr, \ - tim1_up_tim10_isr, \ - tim1_trg_com_tim11_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_fs_wkup_isr, \ - tim8_brk_tim12_isr, \ - tim8_up_tim13_isr, \ - tim8_trg_com_tim14_isr, \ - tim8_cc_isr, \ - dma1_stream7_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_stream0_isr, \ - dma2_stream1_isr, \ - dma2_stream2_isr, \ - dma2_stream3_isr, \ - dma2_stream4_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - dma2_stream5_isr, \ - dma2_stream6_isr, \ - dma2_stream7_isr, \ - usart6_isr, \ - i2c3_ev_isr, \ - i2c3_er_isr, \ - otg_hs_ep1_out_isr, \ - otg_hs_ep1_in_isr, \ - otg_hs_wkup_isr, \ - otg_hs_isr, \ - dcmi_isr, \ - cryp_isr, \ - hash_rng_isr, - -#endif diff --git a/include/libopencm3/stm32/f4/irq.yaml b/include/libopencm3/stm32/f4/irq.yaml new file mode 100644 index 0000000..2d4bae9 --- /dev/null +++ b/include/libopencm3/stm32/f4/irq.yaml @@ -0,0 +1,85 @@ +includeguard: LIBOPENCM3_STM32_F4_NVIC_H +partname_humanreadable: STM32 F4 series +partname_doxygen: STM32F4 +irqs: + - nvic_wwdg + - pvd + - tamp_stamp + - rtc_wkup + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_stream0 + - dma1_stream1 + - dma1_stream2 + - dma1_stream3 + - dma1_stream4 + - dma1_stream5 + - dma1_stream6 + - adc + - can1_tx + - can1_rx0 + - can1_rx1 + - can1_sce + - exti9_5 + - tim1_brk_tim9 + - tim1_up_tim10 + - tim1_trg_com_tim11 + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_fs_wkup + - tim8_brk_tim12 + - tim8_up_tim13 + - tim8_trg_com_tim14 + - tim8_cc + - dma1_stream7 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6_dac + - tim7 + - dma2_stream0 + - dma2_stream1 + - dma2_stream2 + - dma2_stream3 + - dma2_stream4 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs + - dma2_stream5 + - dma2_stream6 + - dma2_stream7 + - usart6 + - i2c3_ev + - i2c3_er + - otg_hs_ep1_out + - otg_hs_ep1_in + - otg_hs_wkup + - otg_hs + - dcmi + - cryp + - hash_rng diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h deleted file mode 100644 index 013e3b5..0000000 --- a/include/libopencm3/stm32/f4/nvic_f4.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F4_H -#define LIBOPENCM3_NVIC_F4_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F4 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -#define NVIC_NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMP_STAMP_IRQ 2 -#define NVIC_RTC_WKUP_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_STREAM0_IRQ 11 -#define NVIC_DMA1_STREAM1_IRQ 12 -#define NVIC_DMA1_STREAM2_IRQ 13 -#define NVIC_DMA1_STREAM3_IRQ 14 -#define NVIC_DMA1_STREAM4_IRQ 15 -#define NVIC_DMA1_STREAM5_IRQ 16 -#define NVIC_DMA1_STREAM6_IRQ 17 -#define NVIC_ADC_IRQ 18 -#define NVIC_CAN1_TX_IRQ 19 -#define NVIC_CAN1_RX0_IRQ 20 -#define NVIC_CAN1_RX1_IRQ 21 -#define NVIC_CAN1_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_TIM9_IRQ 24 -#define NVIC_TIM1_UP_TIM10_IRQ 25 -#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_FS_WKUP_IRQ 42 -#define NVIC_TIM8_BRK_TIM12_IRQ 43 -#define NVIC_TIM8_UP_TIM13_IRQ 44 -#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_DMA1_STREAM7_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_DAC_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_STREAM0_IRQ 56 -#define NVIC_DMA2_STREAM1_IRQ 57 -#define NVIC_DMA2_STREAM2_IRQ 58 -#define NVIC_DMA2_STREAM3_IRQ 59 -#define NVIC_DMA2_STREAM4_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 -#define NVIC_DMA2_STREAM5_IRQ 68 -#define NVIC_DMA2_STREAM6_IRQ 69 -#define NVIC_DMA2_STREAM7_IRQ 70 -#define NVIC_USART6_IRQ 71 -#define NVIC_I2C3_EV_IRQ 72 -#define NVIC_I2C3_ER_IRQ 73 -#define NVIC_OTG_HS_EP1_OUT_IRQ 74 -#define NVIC_OTG_HS_EP1_IN_IRQ 75 -#define NVIC_OTG_HS_WKUP_IRQ 76 -#define NVIC_OTG_HS_IRQ 77 -#define NVIC_DCMI_IRQ 78 -#define NVIC_CRYP_IRQ 79 -#define NVIC_HASH_RNG_IRQ 80 - -#define NVIC_IRQ_COUNT 81 - -#endif diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h new file mode 100755 index 0000000..9346e9b --- /dev/null +++ b/scripts/irq2nvic_h @@ -0,0 +1,105 @@ +#!/usr/bin/env python + +# This file is part of the libopencm3 project. +# +# Copyright (C) 2012 chrysn +# +# This library is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this library. If not, see . + +"""Generate an nvic.h header from a small YAML file describing the interrupt +numbers. + +Code generation is chosen here because the resulting C code needs to be very +repetetive (definition of the IRQ numbers, function prototypes, weak fallback +definition and vector table definition), all being very repetitive. No portable +method to achive the same thing with C preprocessor is known to the author. +(Neither is any non-portable method, for that matter.)""" + +import sys +import yaml + +template = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + */ + +#ifndef {includeguard} +#define {includeguard} + +/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} + @ingroup CM3_nvic_defines + + @{{*/ + +{irqdefinitions} + +#define NVIC_IRQ_COUNT {irqcount} + +/**@}}*/ + +#define WEAK __attribute__ ((weak)) + +/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} + @ingroup CM3_nvic_isrprototypes + + @{{*/ + +{isrprototypes} + +/**@}}*/ + +/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} + @ingroup CM3_nvic_isrpragmas + + @{{*/ + +{isrpragmas} + +/**@}}*/ + +/* Initialization template for the interrupt vector table. This definition is + * used by the startup code generator (vector.c) to set the initial values for + * the interrupt handling routines to the chip family specific _isr weak + * symbols. */ + +#define IRQ_HANDLERS \\ + {vectortableinitialization} + +#endif /* {includeguard} */ +''' + +def convert(infile, outfile): + data = yaml.load(infile) + + irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) + irqnames = [v for (k,v) in irq2name] + + if isinstance(data['irqs'], list): + data['irqcount'] = len(irq2name) + else: + data['irqcount'] = max(data['irqs'].keys()) + 1 + + data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) + data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) + data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) + data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) + + outfile.write(template.format(**data)) + +def main(): + convert(open('irq.yaml'), open('nvic.h', 'w')) + +if __name__ == "__main__": + main() -- cgit v1.2.3 From ae832b4ee87f2cf94b29f790bc04d7b570109919 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 17:30:18 +0200 Subject: split irq.yaml output in nvic.h and vector_nvic.h the weak pragmas need to be used in the very compilation unit where their target is defined, requiring another dispatch --- include/libopencm3/dispatch/nvic.h | 1 - lib/cm3/vector.c | 2 ++ scripts/irq2nvic_h | 29 +++++++++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 67ba544..d8e7889 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -15,6 +15,5 @@ # warning"no chipset defined; user interrupts are disabled" #define NVIC_IRQ_COUNT 0 -#define IRQ_HANDLERS #endif diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index 7b660f9..e0c2972 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -22,6 +22,8 @@ /* load optional platform dependent initialization routines */ #include "../dispatch/vector.c" +/* load the weak symbols for IRQ_HANDLERS */ +#include #define WEAK __attribute__ ((weak)) diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index 9346e9b..fc5e571 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -29,7 +29,7 @@ method to achive the same thing with C preprocessor is known to the author. import sys import yaml -template = '''\ +template_nvic_h = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. @@ -38,6 +38,8 @@ template = '''\ #ifndef {includeguard} #define {includeguard} +#include + /** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} @ingroup CM3_nvic_defines @@ -60,6 +62,19 @@ template = '''\ /**@}}*/ +#endif /* {includeguard} */ +''' + +template_vector_nvic_h = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + * + * This part needs to get included in the compilation unit where + * blocking_handler gets defined due to the way #pragma works. + */ + + /** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} @ingroup CM3_nvic_isrpragmas @@ -76,11 +91,9 @@ template = '''\ #define IRQ_HANDLERS \\ {vectortableinitialization} - -#endif /* {includeguard} */ ''' -def convert(infile, outfile): +def convert(infile, outfile_nvic, outfile_vectornvic): data = yaml.load(infile) irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) @@ -96,10 +109,14 @@ def convert(infile, outfile): data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) - outfile.write(template.format(**data)) + outfile_nvic.write(template_nvic_h.format(**data)) + # FIXME: the vector_nvic.h file could just as well be a vector_nvic.c file + # in lib/, but that'd spread this mechanism over the whole library; just + # needs some thingking over + outfile_vectornvic.write(template_vector_nvic_h.format(**data)) def main(): - convert(open('irq.yaml'), open('nvic.h', 'w')) + convert(open('irq.yaml'), open('nvic.h', 'w'), open('vector_nvic.h', 'w')) if __name__ == "__main__": main() -- cgit v1.2.3 From c69916ffb6d515b1dd644830ba27daef4fc75b58 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 17:57:59 +0200 Subject: integrate irq2nvic_h script in buildprocess --- Makefile | 8 +++++++- include/libopencm3/efm32/tinygecko/Makefile | 2 -- lib/cm3/vector.c | 2 +- lib/dispatch/vector_nvic.c | 19 +++++++++++++++++++ scripts/irq2nvic_h | 14 ++++++++------ 5 files changed, 35 insertions(+), 10 deletions(-) delete mode 100644 include/libopencm3/efm32/tinygecko/Makefile create mode 100644 lib/dispatch/vector_nvic.c (limited to 'include') diff --git a/Makefile b/Makefile index 492b618..76c302d 100644 --- a/Makefile +++ b/Makefile @@ -39,7 +39,13 @@ all: build build: lib examples -lib: +generatedheaders: + @printf " UPDATING HEADERS\n" + $(Q)for yamlfile in `find -name 'irq.yaml'`; do \ + ./scripts/irq2nvic_h $$yamlfile ; \ + done + +lib: generatedheaders $(Q)for i in $(addprefix $@/,$(TARGETS)); do \ if [ -d $$i ]; then \ printf " BUILD $$i\n"; \ diff --git a/include/libopencm3/efm32/tinygecko/Makefile b/include/libopencm3/efm32/tinygecko/Makefile deleted file mode 100644 index 4ac5347..0000000 --- a/include/libopencm3/efm32/tinygecko/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -nvic.h: irq.yaml - ./irq2nvic_h diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index e0c2972..a6d2e93 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -23,7 +23,7 @@ /* load optional platform dependent initialization routines */ #include "../dispatch/vector.c" /* load the weak symbols for IRQ_HANDLERS */ -#include +#include "../dispatch/vector_nvic.c" #define WEAK __attribute__ ((weak)) diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c new file mode 100644 index 0000000..fc5fdd2 --- /dev/null +++ b/lib/dispatch/vector_nvic.c @@ -0,0 +1,19 @@ +#if defined(STM32F1) +# include "../stm32/f1/vector_nvic.c" +#elif defined(STM32F2) +# include "../stm32/f2/vector_nvic.c" +#elif defined(STM32F4) +# include "../stm32/f4/vector_nvic.c" + +#elif defined(TINYGECKO) +# include "../efm32/tinygecko/vector_nvic.c" + +#elif defined(LPC43XX) +# include "../lpc43xx/vector_nvic.c" + +#else +# warning"no chipset defined; user interrupts are disabled" + +#define IRQ_HANDLERS + +#endif diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index fc5e571..92d63b8 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -65,7 +65,7 @@ template_nvic_h = '''\ #endif /* {includeguard} */ ''' -template_vector_nvic_h = '''\ +template_vector_nvic_c = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. @@ -110,13 +110,15 @@ def convert(infile, outfile_nvic, outfile_vectornvic): data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) outfile_nvic.write(template_nvic_h.format(**data)) - # FIXME: the vector_nvic.h file could just as well be a vector_nvic.c file - # in lib/, but that'd spread this mechanism over the whole library; just - # needs some thingking over - outfile_vectornvic.write(template_vector_nvic_h.format(**data)) + outfile_vectornvic.write(template_vector_nvic_c.format(**data)) def main(): - convert(open('irq.yaml'), open('nvic.h', 'w'), open('vector_nvic.h', 'w')) + infile = sys.argv[1] + if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.yaml'): + raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml") + nvic_h = infile.replace('irq.yaml', 'nvic.h') + vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c') + convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w')) if __name__ == "__main__": main() -- cgit v1.2.3 From e20f1c0d8fb6c75c434b93834a9d67262198d908 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 21:42:12 +0200 Subject: unify scb (system control block) these register definitions are common to all cortex mcus. some of the registers might not be implemented everywhere (especially the floating point registers), but defining them does no harm. this modification does not result in any changes in the example binaries. --- examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c | 2 +- examples/stm32/f1/other/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/other/usb_hid/usbhid.c | 2 +- examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/stm32-h103/usb_hid/usbhid.c | 2 +- examples/stm32/f1/stm32-h103/usb_iap/usbiap.c | 2 +- include/libopencm3/cm3/scb.h | 376 ++++++++++++++++++++++++++ include/libopencm3/stm32/f1/scb.h | 307 --------------------- include/libopencm3/stm32/f2/scb.h | 307 --------------------- include/libopencm3/stm32/f4/scb.h | 376 -------------------------- lib/cm3/scb.c | 35 +++ lib/stm32/f1/scb.c | 35 --- lib/stm32/f2/scb.c | 35 --- lib/stm32/f4/scb.c | 35 --- lib/stm32/f4/vector_chipset.c | 2 +- 16 files changed, 419 insertions(+), 1103 deletions(-) create mode 100644 include/libopencm3/cm3/scb.h delete mode 100644 include/libopencm3/stm32/f1/scb.h delete mode 100644 include/libopencm3/stm32/f2/scb.h delete mode 100644 include/libopencm3/stm32/f4/scb.h create mode 100644 lib/cm3/scb.c delete mode 100644 lib/stm32/f1/scb.c delete mode 100644 lib/stm32/f2/scb.c delete mode 100644 lib/stm32/f4/scb.c (limited to 'include') diff --git a/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c b/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c index 4ffc0a1..d8fcde4 100644 --- a/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c index 8d83896..a0a4d12 100644 --- a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c +++ b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c @@ -32,7 +32,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/other/usb_dfu/usbdfu.c b/examples/stm32/f1/other/usb_dfu/usbdfu.c index 0211a47..84e1b36 100644 --- a/examples/stm32/f1/other/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/other/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/other/usb_hid/usbhid.c b/examples/stm32/f1/other/usb_hid/usbhid.c index dd3c57a..6329f0e 100644 --- a/examples/stm32/f1/other/usb_hid/usbhid.c +++ b/examples/stm32/f1/other/usb_hid/usbhid.c @@ -28,7 +28,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c b/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c index 49f265b..9c0bab9 100644 --- a/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c index 9ed40d1..d0c2aff 100644 --- a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c +++ b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c @@ -28,7 +28,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c b/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c index c5cc8ba..9091f36 100644 --- a/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c +++ b/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/libopencm3/cm3/scb.h b/include/libopencm3/cm3/scb.h new file mode 100644 index 0000000..8e9c757 --- /dev/null +++ b/include/libopencm3/cm3/scb.h @@ -0,0 +1,376 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SCB_H +#define LIBOPENCM3_SCB_H + +#include +#include + +/* --- SCB: Registers ------------------------------------------------------ */ + +/* CPUID: CPUID base register */ +#define SCB_CPUID MMIO32(SCB_BASE + 0x00) + +/* ICSR: Interrupt Control State Register */ +#define SCB_ICSR MMIO32(SCB_BASE + 0x04) + +/* VTOR: Vector Table Offset Register */ +#define SCB_VTOR MMIO32(SCB_BASE + 0x08) + +/* AIRCR: Application Interrupt and Reset Control Register */ +#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) + +/* SCR: System Control Register */ +#define SCB_SCR MMIO32(SCB_BASE + 0x10) + +/* CCR: Configuration Control Register */ +#define SCB_CCR MMIO32(SCB_BASE + 0x14) + +/* SHP: System Handler Priority Registers */ +/* Note: 12 8bit registers */ +#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) +#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) +#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) +#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) + +/* SHCSR: System Handler Control and State Register */ +#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) + +/* CFSR: Configurable Fault Status Registers */ +#define SCB_CFSR MMIO32(SCB_BASE + 0x28) + +/* HFSR: Hard Fault Status Register */ +#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) + +/* DFSR: Debug Fault Status Register */ +#define SCB_DFSR MMIO32(SCB_BASE + 0x30) + +/* MMFAR: Memory Manage Fault Address Register */ +#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) + +/* BFAR: Bus Fault Address Register */ +#define SCB_BFAR MMIO32(SCB_BASE + 0x38) + +/* AFSR: Auxiliary Fault Status Register */ +#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) + +/* ID_PFR0: Processor Feature Register 0 */ +#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) + +/* ID_PFR1: Processor Feature Register 1 */ +#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) + +/* ID_DFR0: Debug Features Register 0 */ +#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) + +/* ID_AFR0: Auxiliary Features Register 0 */ +#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) + +/* ID_MMFR0: Memory Model Feature Register 0 */ +#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) + +/* ID_MMFR1: Memory Model Feature Register 1 */ +#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) + +/* ID_MMFR2: Memory Model Feature Register 2 */ +#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) + +/* ID_MMFR3: Memory Model Feature Register 3 */ +#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) + +/* ID_ISAR0: Instruction Set Attributes Register 0 */ +#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) + +/* ID_ISAR1: Instruction Set Attributes Register 1 */ +#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) + +/* ID_ISAR2: Instruction Set Attributes Register 2 */ +#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) + +/* ID_ISAR3: Instruction Set Attributes Register 3 */ +#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) + +/* ID_ISAR4: Instruction Set Attributes Register 4 */ +#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) + +/* CPACR: Coprocessor Access Control Register */ +#define SCB_CPACR MMIO32(SCB_BASE + 0x88) + +/* FPCCR: Floating-Point Context Control Register */ +#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) + +/* FPCAR: Floating-Point Context Address Register */ +#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) + +/* FPDSCR: Floating-Point Default Status Control Register */ +#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) + +/* MVFR0: Media and Floating-Point Feature Register 0 */ +#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) + +/* MVFR1: Media and Floating-Point Feature Register 1 */ +#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) + +/* --- SCB values ---------------------------------------------------------- */ + +/* --- SCB_CPUID values ---------------------------------------------------- */ + +/* Implementer[31:24]: Implementer code */ +#define SCP_CPUID_IMPLEMENTER_LSB 24 +/* Variant[23:20]: Variant number */ +#define SCP_CPUID_VARIANT_LSB 20 +/* Constant[19:16]: Reads as 0xF */ +#define SCP_CPUID_CONSTANT_LSB 16 +/* PartNo[15:4]: Part number of the processor */ +#define SCP_CPUID_PARTNO_LSB 4 +/* Revision[3:0]: Revision number */ +#define SCP_CPUID_REVISION_LSB 0 + +/* --- SCB_ICSR values ----------------------------------------------------- */ + +/* NMIPENDSET: NMI set-pending bit */ +#define SCB_ICSR_NMIPENDSET (1 << 31) +/* Bits [30:29]: reserved - must be kept cleared */ +/* PENDSVSET: PendSV set-pending bit */ +#define SCB_ICSR_PENDSVSET (1 << 28) +/* PENDSVCLR: PendSV clear-pending bit */ +#define SCB_ICSR_PENDSVCLR (1 << 27) +/* PENDSTSET: SysTick exception set-pending bit */ +#define SCB_ICSR_PENDSTSET (1 << 26) +/* PENDSTCLR: SysTick exception clear-pending bit */ +#define SCB_ICSR_PENDSTCLR (1 << 25) +/* Bit 24: reserved - must be kept cleared */ +/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ +/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ +#define SCB_ICSR_ISRPENDING (1 << 22) +/* VECTPENDING[21:12] Pending vector */ +#define SCB_ICSR_VECTPENDING_LSB 12 +/* RETOBASE: Return to base level */ +#define SCB_ICSR_RETOBASE (1 << 11) +/* Bits [10:9]: reserved - must be kept cleared */ +/* VECTACTIVE[8:0] Active vector */ +#define SCB_ICSR_VECTACTIVE_LSB 0 + +/* --- SCB_VTOR values ----------------------------------------------------- */ + +/* Bits [31:30]: reserved - must be kept cleared */ +/* TBLOFF[29:9]: Vector table base offset field */ +#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ + +/* --- SCB_AIRCR values ---------------------------------------------------- */ + +/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ +#define SCB_AIRCR_VECTKEYSTAT_LSB 16 +#define SCB_AIRCR_VECTKEY 0x05FA0000 +/* ENDIANESS Data endianness bit */ +#define SCB_AIRCR_ENDIANESS (1 << 15) +/* Bits [14:11]: reserved - must be kept cleared */ +/* PRIGROUP[10:8]: Interrupt priority grouping field */ +#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) +#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) +#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) +#define SCB_AIRCR_PRIGROUP_SHIFT 8 +/* Bits [7:3]: reserved - must be kept cleared */ +/* SYSRESETREQ System reset request */ +#define SCB_AIRCR_SYSRESETREQ (1 << 2) +/* VECTCLRACTIVE */ +#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) +/* VECTRESET */ +#define SCB_AIRCR_VECTRESET (1 << 0) + +/* --- SCB_SCR values ------------------------------------------------------ */ + +/* Bits [31:5]: reserved - must be kept cleared */ +/* SEVEONPEND Send Event on Pending bit */ +#define SCB_SCR_SEVEONPEND (1 << 4) +/* Bit 3: reserved - must be kept cleared */ +/* SLEEPDEEP */ +#define SCB_SCR_SLEEPDEEP (1 << 2) +/* SLEEPONEXIT */ +#define SCB_SCR_SLEEPONEXIT (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_CCR values ------------------------------------------------------ */ + +/* Bits [31:10]: reserved - must be kept cleared */ +/* STKALIGN */ +#define SCB_CCR_STKALIGN (1 << 9) +/* BFHFNMIGN */ +#define SCB_CCR_BFHFNMIGN (1 << 8) +/* Bits [7:5]: reserved - must be kept cleared */ +/* DIV_0_TRP */ +#define SCB_CCR_DIV_0_TRP (1 << 4) +/* UNALIGN_TRP */ +#define SCB_CCR_UNALIGN_TRP (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* USERSETMPEND */ +#define SCB_CCR_USERSETMPEND (1 << 1) +/* NONBASETHRDENA */ +#define SCB_CCR_NONBASETHRDENA (1 << 0) + +/* --- SCB_SHPR1 values ---------------------------------------------------- */ + +/* Bits [31:24]: reserved - must be kept cleared */ +/* PRI_6[23:16]: Priority of system handler 6, usage fault */ +#define SCB_SHPR1_PRI_6_LSB 16 +/* PRI_5[15:8]: Priority of system handler 5, bus fault */ +#define SCB_SHPR1_PRI_5_LSB 8 +/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ +#define SCB_SHPR1_PRI_4_LSB 0 + +/* --- SCB_SHPR2 values ---------------------------------------------------- */ + +/* PRI_11[31:24]: Priority of system handler 11, SVCall */ +#define SCB_SHPR2_PRI_11_LSB 24 +/* Bits [23:0]: reserved - must be kept cleared */ + +/* --- SCB_SHPR3 values ---------------------------------------------------- */ + +/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ +#define SCB_SHPR3_PRI_15_LSB 24 +/* PRI_14[23:16]: Priority of system handler 14, PendSV */ +#define SCB_SHPR3_PRI_14_LSB 16 +/* Bits [15:0]: reserved - must be kept cleared */ + +/* --- SCB_SHCSR values ---------------------------------------------------- */ + +/* Bits [31:19]: reserved - must be kept cleared */ +/* USGFAULTENA: Usage fault enable */ +#define SCB_SHCSR_USGFAULTENA (1 << 18) +/* BUSFAULTENA: Bus fault enable */ +#define SCB_SHCSR_BUSFAULTENA (1 << 17) +/* MEMFAULTENA: Memory management fault enable */ +#define SCB_SHCSR_MEMFAULTENA (1 << 16) +/* SVCALLPENDED: SVC call pending */ +#define SCB_SHCSR_SVCALLPENDED (1 << 15) +/* BUSFAULTPENDED: Bus fault exception pending */ +#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) +/* MEMFAULTPENDED: Memory management fault exception pending */ +#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) +/* USGFAULTPENDED: Usage fault exception pending */ +#define SCB_SHCSR_USGFAULTPENDED (1 << 12) +/* SYSTICKACT: SysTick exception active */ +#define SCB_SHCSR_SYSTICKACT (1 << 11) +/* PENDSVACT: PendSV exception active */ +#define SCB_SHCSR_PENDSVACT (1 << 10) +/* Bit 9: reserved - must be kept cleared */ +/* MONITORACT: Debug monitor active */ +#define SCB_SHCSR_MONITORACT (1 << 8) +/* SVCALLACT: SVC call active */ +#define SCB_SHCSR_SVCALLACT (1 << 7) +/* Bits [6:4]: reserved - must be kept cleared */ +/* USGFAULTACT: Usage fault exception active */ +#define SCB_SHCSR_USGFAULTACT (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* BUSFAULTACT: Bus fault exception active */ +#define SCB_SHCSR_BUSFAULTACT (1 << 1) +/* MEMFAULTACT: Memory management fault exception active */ +#define SCB_SHCSR_MEMFAULTACT (1 << 0) + +/* --- SCB_CFSR values ----------------------------------------------------- */ + +/* Bits [31:26]: reserved - must be kept cleared */ +/* DIVBYZERO: Divide by zero usage fault */ +#define SCB_CFSR_DIVBYZERO (1 << 25) +/* UNALIGNED: Unaligned access usage fault */ +#define SCB_CFSR_UNALIGNED (1 << 24) +/* Bits [23:20]: reserved - must be kept cleared */ +/* NOCP: No coprocessor usage fault */ +#define SCB_CFSR_NOCP (1 << 19) +/* INVPC: Invalid PC load usage fault */ +#define SCB_CFSR_INVPC (1 << 18) +/* INVSTATE: Invalid state usage fault */ +#define SCB_CFSR_INVSTATE (1 << 17) +/* UNDEFINSTR: Undefined instruction usage fault */ +#define SCB_CFSR_UNDEFINSTR (1 << 16) +/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ +#define SCB_CFSR_BFARVALID (1 << 15) +/* Bits [14:13]: reserved - must be kept cleared */ +/* STKERR: Bus fault on stacking for exception entry */ +#define SCB_CFSR_STKERR (1 << 12) +/* UNSTKERR: Bus fault on unstacking for a return from exception */ +#define SCB_CFSR_UNSTKERR (1 << 11) +/* IMPRECISERR: Imprecise data bus error */ +#define SCB_CFSR_IMPRECISERR (1 << 10) +/* PRECISERR: Precise data bus error */ +#define SCB_CFSR_PRECISERR (1 << 9) +/* IBUSERR: Instruction bus error */ +#define SCB_CFSR_IBUSERR (1 << 8) +/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ +#define SCB_CFSR_MMARVALID (1 << 7) +/* Bits [6:5]: reserved - must be kept cleared */ +/* MSTKERR: Memory manager fault on stacking for exception entry */ +#define SCB_CFSR_MSTKERR (1 << 4) +/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ +#define SCB_CFSR_MUNSTKERR (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* DACCVIOL: Data access violation flag */ +#define SCB_CFSR_DACCVIOL (1 << 1) +/* IACCVIOL: Instruction access violation flag */ +#define SCB_CFSR_IACCVIOL (1 << 0) + +/* --- SCB_HFSR values ----------------------------------------------------- */ + +/* DEBUG_VT: reserved for debug use */ +#define SCB_HFSR_DEBUG_VT (1 << 31) +/* FORCED: Forced hard fault */ +#define SCB_HFSR_FORCED (1 << 30) +/* Bits [29:2]: reserved - must be kept cleared */ +/* VECTTBL: Vector table hard fault */ +#define SCB_HFSR_VECTTBL (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_MMFAR values ---------------------------------------------------- */ + +/* MMFAR [31:0]: Memory management fault address */ + +/* --- SCB_BFAR values ----------------------------------------------------- */ + +/* BFAR [31:0]: Bus fault address */ + +/* --- SCB_CPACR values ---------------------------------------------------- */ + +/* CPACR CPn: Access privileges values */ +#define SCB_CPACR_NONE 0 /* Access denied */ +#define SCB_CPACR_PRIV 1 /* Privileged access only */ +#define SCB_CPACR_FULL 3 /* Full access */ + +/* CPACR [20:21]: Access privileges for coprocessor 10 */ +#define SCB_CPACR_CP10 (1 << 20) +/* CPACR [22:23]: Access privileges for coprocessor 11 */ +#define SCB_CPACR_CP11 (1 << 22) + +/* --- SCB functions ------------------------------------------------------- */ + +BEGIN_DECLS + +void scb_reset_core(void); +void scb_reset_system(void); +void scb_set_priority_grouping(u32 prigroup); + +/* TODO: */ + +END_DECLS + +#endif diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h deleted file mode 100644 index 181aa7a..0000000 --- a/include/libopencm3/stm32/f1/scb.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h deleted file mode 100644 index 181aa7a..0000000 --- a/include/libopencm3/stm32/f2/scb.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h deleted file mode 100644 index 7187ca9..0000000 --- a/include/libopencm3/stm32/f4/scb.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* ID_PFR0: Processor Feature Register 0 */ -#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) - -/* ID_PFR1: Processor Feature Register 1 */ -#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) - -/* ID_DFR0: Debug Features Register 0 */ -#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) - -/* ID_AFR0: Auxiliary Features Register 0 */ -#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) - -/* ID_MMFR0: Memory Model Feature Register 0 */ -#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) - -/* ID_MMFR1: Memory Model Feature Register 1 */ -#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) - -/* ID_MMFR2: Memory Model Feature Register 2 */ -#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) - -/* ID_MMFR3: Memory Model Feature Register 3 */ -#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) - -/* ID_ISAR0: Instruction Set Attributes Register 0 */ -#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) - -/* ID_ISAR1: Instruction Set Attributes Register 1 */ -#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) - -/* ID_ISAR2: Instruction Set Attributes Register 2 */ -#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) - -/* ID_ISAR3: Instruction Set Attributes Register 3 */ -#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) - -/* ID_ISAR4: Instruction Set Attributes Register 4 */ -#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) - -/* CPACR: Coprocessor Access Control Register */ -#define SCB_CPACR MMIO32(SCB_BASE + 0x88) - -/* FPCCR: Floating-Point Context Control Register */ -#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) - -/* FPCAR: Floating-Point Context Address Register */ -#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) - -/* FPDSCR: Floating-Point Default Status Control Register */ -#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) - -/* MVFR0: Media and Floating-Point Feature Register 0 */ -#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) - -/* MVFR1: Media and Floating-Point Feature Register 1 */ -#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB_CPACR values ---------------------------------------------------- */ - -/* CPACR CPn: Access privileges values */ -#define SCB_CPACR_NONE 0 /* Access denied */ -#define SCB_CPACR_PRIV 1 /* Privileged access only */ -#define SCB_CPACR_FULL 3 /* Full access */ - -/* CPACR [20:21]: Access privileges for coprocessor 10 */ -#define SCB_CPACR_CP10 (1 << 20) -/* CPACR [22:23]: Access privileges for coprocessor 11 */ -#define SCB_CPACR_CP11 (1 << 22) - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c new file mode 100644 index 0000000..904bd7c --- /dev/null +++ b/lib/cm3/scb.c @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void scb_reset_core(void) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; +} + +void scb_reset_system(void) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; +} + +void scb_set_priority_grouping(u32 prigroup) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; +} diff --git a/lib/stm32/f1/scb.c b/lib/stm32/f1/scb.c deleted file mode 100644 index e59134e..0000000 --- a/lib/stm32/f1/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f2/scb.c b/lib/stm32/f2/scb.c deleted file mode 100644 index abb7b44..0000000 --- a/lib/stm32/f2/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f4/scb.c b/lib/stm32/f4/scb.c deleted file mode 100644 index cbf4d53..0000000 --- a/lib/stm32/f4/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f4/vector_chipset.c b/lib/stm32/f4/vector_chipset.c index 5304299..145be05 100644 --- a/lib/stm32/f4/vector_chipset.c +++ b/lib/stm32/f4/vector_chipset.c @@ -18,7 +18,7 @@ * along with this library. If not, see . */ -#include +#include static void pre_main(void) { -- cgit v1.2.3 From bc5146b710c8be3dfa4a8601bd3ca29408ae6397 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 22:26:46 +0200 Subject: unified systick handling the only change this results in in the example binaries is in the hackrf-jellybean/systick example, where the the check in systick_set_clocksource for overflowing from the stm32 area gets used. --- .../lpc43xx/hackrf-jellybean/systick/systickdemo.c | 2 +- examples/stm32/f1/lisa-m-1/can/can.c | 2 +- examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c | 2 +- .../lisa-m-2/usart_irq_printf/usart_irq_printf.c | 2 +- examples/stm32/f1/obldc/can/can.c | 2 +- examples/stm32/f1/obldc/systick/systick.c | 2 +- examples/stm32/f1/other/systick/systick.c | 2 +- examples/stm32/f1/other/usb_hid/usbhid.c | 2 +- .../stm32-h103/usart_irq_printf/usart_irq_printf.c | 2 +- examples/stm32/f1/stm32-h103/usb_hid/usbhid.c | 2 +- include/libopencm3/cm3/systick.h | 113 ++++++++++++++++ include/libopencm3/lpc43xx/systick.h | 88 ------------ include/libopencm3/stm32/systick.h | 111 --------------- lib/cm3/systick.c | 149 +++++++++++++++++++++ lib/lpc43xx/systick.c | 69 ---------- lib/stm32/systick.c | 139 ------------------- 16 files changed, 272 insertions(+), 417 deletions(-) create mode 100644 include/libopencm3/cm3/systick.h delete mode 100644 include/libopencm3/lpc43xx/systick.h delete mode 100644 include/libopencm3/stm32/systick.h create mode 100644 lib/cm3/systick.c delete mode 100644 lib/lpc43xx/systick.c delete mode 100644 lib/stm32/systick.c (limited to 'include') diff --git a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c index 61792d1..d38b0bc 100644 --- a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include "../jellybean_conf.h" diff --git a/examples/stm32/f1/lisa-m-1/can/can.c b/examples/stm32/f1/lisa-m-1/can/can.c index 92ebd85..41432b6 100644 --- a/examples/stm32/f1/lisa-m-1/can/can.c +++ b/examples/stm32/f1/lisa-m-1/can/can.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include struct can_tx_msg { diff --git a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c index a0a4d12..f5f0146 100644 --- a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c +++ b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c b/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c index e4e0127..dd2e221 100644 --- a/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/obldc/can/can.c b/examples/stm32/f1/obldc/can/can.c index a29d8d7..281ab1d 100644 --- a/examples/stm32/f1/obldc/can/can.c +++ b/examples/stm32/f1/obldc/can/can.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include struct can_tx_msg { diff --git a/examples/stm32/f1/obldc/systick/systick.c b/examples/stm32/f1/obldc/systick/systick.c index 7abdd54..1426793 100644 --- a/examples/stm32/f1/obldc/systick/systick.c +++ b/examples/stm32/f1/obldc/systick/systick.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include u32 temp32; diff --git a/examples/stm32/f1/other/systick/systick.c b/examples/stm32/f1/other/systick/systick.c index 9aa2e94..c04704d 100644 --- a/examples/stm32/f1/other/systick/systick.c +++ b/examples/stm32/f1/other/systick/systick.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include u32 temp32; diff --git a/examples/stm32/f1/other/usb_hid/usbhid.c b/examples/stm32/f1/other/usb_hid/usbhid.c index 6329f0e..a61d9ea 100644 --- a/examples/stm32/f1/other/usb_hid/usbhid.c +++ b/examples/stm32/f1/other/usb_hid/usbhid.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c b/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c index 5effb28..b052dc3 100644 --- a/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c index d0c2aff..1c27c2f 100644 --- a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c +++ b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/libopencm3/cm3/systick.h b/include/libopencm3/cm3/systick.h new file mode 100644 index 0000000..5e7715b --- /dev/null +++ b/include/libopencm3/cm3/systick.h @@ -0,0 +1,113 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_systick_defines SysTick Defines + +@brief libopencm3 Defined Constants and Types for the Cortex SysTick + +@ingroup CM3_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 19 August 2012 + +LGPL License Terms @ref lgpl_license + */ + +/**@{*/ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +#define STK_CTRL_CLKSOURCE_LSB 2 +/** @defgroup systick_clksource Clock source selection +@ingroup CM3_systick_defines + +@{*/ +#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 +#define STK_CTRL_CLKSOURCE_AHB 1 +/**@}*/ + +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +u32 systick_get_calib(void); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h deleted file mode 100644 index 2ae52c2..0000000 --- a/include/libopencm3/lpc43xx/systick.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ -/* See also libopencm3\cm3\scs.h for details on SysTicks registers */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -u32 systick_get_calib(void); - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h deleted file mode 100644 index e42c4e6..0000000 --- a/include/libopencm3/stm32/systick.h +++ /dev/null @@ -1,111 +0,0 @@ -/** @defgroup STM32F_systick_defines SysTick Defines - -@brief libopencm3 Defined Constants and Types for the STM32F SysTick - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 19 August 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -#define STK_CTRL_CLKSOURCE_LSB 2 -/** @defgroup systick_clksource Clock source selection -@ingroup STM32F_systick_defines - -@{*/ -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 -/**@}*/ - -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -END_DECLS - -#endif -/**@}*/ - diff --git a/lib/cm3/systick.c b/lib/cm3/systick.c new file mode 100644 index 0000000..325ffff --- /dev/null +++ b/lib/cm3/systick.c @@ -0,0 +1,149 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_systick_file SysTick + +@ingroup CM3_files + +@brief libopencm3 Cortex System Tick Timer + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 19 August 2012 + +This library supports the System Tick timer in ARM Cortex Microcontrollers. + +The System Tick timer is part of the ARM Cortex core. It is a 24 bit +down counter that can be configured with an automatical reload value. + +LGPL License Terms @ref lgpl_license + */ + +/**@{*/ +#include + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Set the Automatic Reload Value. + +The counter is set to the reload value when the counter starts and after it +reaches zero. + +@param[in] value u32. 24 bit reload value. +*/ + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Read the Automatic Reload Value. + +@returns 24 bit reload value as u32. +*/ + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Set the SysTick Clock Source. + +The clock source can be either the AHB clock or the same clock divided by 8. + +@param[in] clocksource u8. Clock source from @ref systick_clksource. +*/ + +void systick_set_clocksource(u8 clocksource) +{ + if (clocksource < 2) + STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Enable SysTick Interrupt. + +*/ + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Disable SysTick Interrupt. + +*/ + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Enable SysTick Counter. + +*/ + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Disable SysTick Counter. + +*/ + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Read the Counter Flag. + +The count flag is set when the timer count becomes zero, and is cleared when the +flag is read. + +@returns Boolean if flag set. +*/ + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Get Calibration Value + +@returns Current calibration value +*/ +u32 systick_get_calib(void) +{ + return (STK_CALIB&0x00FFFFFF); +} +/**@}*/ + diff --git a/lib/lpc43xx/systick.c b/lib/lpc43xx/systick.c deleted file mode 100644 index 82345a9..0000000 --- a/lib/lpc43xx/systick.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -void systick_set_clocksource(u8 clocksource) -{ - STK_CTRL |= clocksource; -} - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} - -u32 systick_get_calib(void) -{ - return (STK_CALIB&0x00FFFFFF); -} diff --git a/lib/stm32/systick.c b/lib/stm32/systick.c deleted file mode 100644 index 36077cc..0000000 --- a/lib/stm32/systick.c +++ /dev/null @@ -1,139 +0,0 @@ -/** @defgroup STM32F_systick_file SysTick - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxx System Tick Timer - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 19 August 2012 - -This library supports the System Tick timer in the -STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. - -The System Tick timer is part of the ARM Cortex core. It is a 24 bit -down counter that can be configured with an automatical reload value. - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#include - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Set the Automatic Reload Value. - -The counter is set to the reload value when the counter starts and after it -reaches zero. - -@param[in] value u32. 24 bit reload value. -*/ - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Read the Automatic Reload Value. - -@returns 24 bit reload value as u32. -*/ - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Set the SysTick Clock Source. - -The clock source can be either the AHB clock or the same clock divided by 8. - -@param[in] clocksource u8. Clock source from @ref systick_clksource. -*/ - -void systick_set_clocksource(u8 clocksource) -{ - if (clocksource < 2) - STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Enable SysTick Interrupt. - -*/ - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Disable SysTick Interrupt. - -*/ - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Enable SysTick Counter. - -*/ - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Disable SysTick Counter. - -*/ - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Read the Counter Flag. - -The count flag is set when the timer count becomes zero, and is cleared when the -flag is read. - -@returns Boolean if flag set. -*/ - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} -/**@}*/ - -- cgit v1.2.3 From 14a5fc78cf5e50364d6268aaeb1871966ee89b32 Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 19 Oct 2012 19:07:30 +0200 Subject: completing dispatch the LM3S irq list was previously unused as it was missing in the dispatch files; now it got added. (before HEAD^, it wouldn't have made any difference because the discriminating constant wasn't defined anyway) also, this enhances the warning messages --- include/libopencm3/dispatch/nvic.h | 5 ++++- lib/dispatch/vector_nvic.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index d8e7889..441fd28 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -11,8 +11,11 @@ #elif defined(LPC43XX) # include +#elif defined(LM3S) +# include + #else -# warning"no chipset defined; user interrupts are disabled" +# warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0" #define NVIC_IRQ_COUNT 0 diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index fc5fdd2..d5e4a60 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -11,8 +11,11 @@ #elif defined(LPC43XX) # include "../lpc43xx/vector_nvic.c" +#elif defined(LM3S) +# include "../lm3s/vector_nvic.c" + #else -# warning"no chipset defined; user interrupts are disabled" +# warning"no interrupts defined for chipset; not allocating space in the vector table" #define IRQ_HANDLERS -- cgit v1.2.3 From 0a1cf977eb2003dd55cee8f5f840f3a2f6e9c0ce Mon Sep 17 00:00:00 2001 From: Silvio Gissi Date: Fri, 19 Oct 2012 23:09:45 +0200 Subject: Added irq.yaml to lpc_13xx and lpc_17xx families --- include/libopencm3/dispatch/nvic.h | 4 +++ include/libopencm3/lpc13xx/irq.yaml | 62 +++++++++++++++++++++++++++++++++++++ include/libopencm3/lpc17xx/irq.yaml | 39 +++++++++++++++++++++++ lib/dispatch/vector_nvic.c | 4 +++ 4 files changed, 109 insertions(+) create mode 100644 include/libopencm3/lpc13xx/irq.yaml create mode 100644 include/libopencm3/lpc17xx/irq.yaml (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 441fd28..ff08269 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -8,6 +8,10 @@ #elif defined(TINYGECKO) # include +#elif defined(LPC13XX) +# include +#elif defined(LPC17XX) +# include #elif defined(LPC43XX) # include diff --git a/include/libopencm3/lpc13xx/irq.yaml b/include/libopencm3/lpc13xx/irq.yaml new file mode 100644 index 0000000..5a372db --- /dev/null +++ b/include/libopencm3/lpc13xx/irq.yaml @@ -0,0 +1,62 @@ +includeguard: LIBOPENCM3_LPC13xx_NVIC_H +partname_humanreadable: LPC 13xx series +partname_doxygen: LPC13xx +irqs: + 0: pio0_0 + 1: pio0_1 + 2: pio0_2 + 3: pio0_3 + 4: pio0_4 + 5: pio0_5 + 6: pio0_6 + 7: pio0_7 + 8: pio0_8 + 9: pio0_9 + 10: pio0_10 + 11: pio0_11 + 12: pio1_0 + 13: pio1_1 + 14: pio1_2 + 15: pio1_3 + 16: pio1_4 + 17: pio1_5 + 18: pio1_6 + 19: pio1_7 + 20: pio1_8 + 21: pio1_9 + 22: pio1_10 + 23: pio1_11 + 24: pio2_0 + 25: pio2_1 + 26: pio2_2 + 27: pio2_3 + 28: pio2_4 + 29: pio2_5 + 30: pio2_6 + 31: pio2_7 + 32: pio2_8 + 33: pio2_9 + 34: pio2_10 + 35: pio2_11 + 36: pio3_0 + 37: pio3_1 + 38: pio3_2 + 39: pio3_3 + 40: i2c0 + 41: ct16b0 + 42: ct16b1 + 43: ct32b0 + 44: ct32b1 + 45: ssp0 + 46: uart + 47: usb + 48: usb_fiq + 49: adc + 50: wdt + 51: bod +# 52: reserved + 53: pio3 + 54: pio2 + 55: pio1 + 56: pio0 + 56: ssp1 diff --git a/include/libopencm3/lpc17xx/irq.yaml b/include/libopencm3/lpc17xx/irq.yaml new file mode 100644 index 0000000..faa140f --- /dev/null +++ b/include/libopencm3/lpc17xx/irq.yaml @@ -0,0 +1,39 @@ +includeguard: LIBOPENCM3_LPC17xx_NVIC_H +partname_humanreadable: LPC 17xx series +partname_doxygen: LPC17xx +irqs: + 0: wdt + 1: timer0 + 2: timer1 + 3: timer2 + 4: timer3 + 5: uart0 + 6: uart1 + 7: uart2 + 8: uart3 + 9: pwm + 10: i2c0 + 11: i2c1 + 12: i2c2 + 13: spi + 14: ssp0 + 15: ssp1 + 16: pll0 + 17: rtc + 18: eint0 + 19: eint1 + 20: eint2 + 21: eint3 + 22: adc + 23: bod + 24: usb + 25: can + 26: gpdma + 27: i2s + 28: ethernet + 29: rit + 30: motor_pwm + 31: qei + 32: pll1 + 33: usb_act + 34: can_act diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index d5e4a60..1f4753d 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -8,6 +8,10 @@ #elif defined(TINYGECKO) # include "../efm32/tinygecko/vector_nvic.c" +#elif defined(LPC13XX) +# include "../lpc13xx/vector_nvic.c" +#elif defined(LPC17XX) +# include "../lpc17xx/vector_nvic.c" #elif defined(LPC43XX) # include "../lpc43xx/vector_nvic.c" -- cgit v1.2.3