From 2180a02e2f79b8ee77780ea11be188c0faaa8866 Mon Sep 17 00:00:00 2001 From: chrysn Date: Sat, 25 Feb 2012 18:57:11 +0100 Subject: first attempt at porting libopencm3 to energymicro unless sources are explicitly given, the linker scripts and make files were copied over from the stm32/f1 port. --- .../libopencm3/efm32/tinygecko/devicerevision.h | 26 +++++++++++++++++ include/libopencm3/efm32/tinygecko/vector.h | 11 +++++++ include/libopencm3/efm32/vector.h | 34 ++++++++++++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 include/libopencm3/efm32/tinygecko/devicerevision.h create mode 100644 include/libopencm3/efm32/tinygecko/vector.h create mode 100644 include/libopencm3/efm32/vector.h (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/devicerevision.h b/include/libopencm3/efm32/tinygecko/devicerevision.h new file mode 100644 index 0000000..83e0e0d --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/devicerevision.h @@ -0,0 +1,26 @@ +/* this implements d0034_efm32tg_reference_manual.pdf's 7.3.4 "Device Revision" + * section */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_DEVICEREVISION_H +#define LIBOPENCM3_EFM32_TINYGECKO_DEVICEREVISION_H + +#include + +#define DEVICEREVISION_PID2 MMIO32(0xE00FFFE8) +#define DEVICEREVISION_PID3 MMIO32(0xE00FFFEC) + +/* devicerevision_revision_get has a comment that would make these definitions + * obsolete; i'm not sure how far it is reasonable to parameterize everythin + * g*/ +#define DEVICEREVISION_REVISION_LENGTH 4 +#define DEVICEREVISION_REVISION_SHIFT 4 +#define DEVICEREVISION_REVISION_MASK (~(~0< + +typedef void (*efm32_vector_table_entry_t)(void); + +typedef struct { + unsigned int *initial_sp_value; + efm32_vector_table_entry_t reset; + efm32_vector_table_entry_t nmi; + efm32_vector_table_entry_t hard_fault; + efm32_vector_table_entry_t memory_manage_fault; + efm32_vector_table_entry_t bus_fault; + efm32_vector_table_entry_t usage_fault; + efm32_vector_table_entry_t reserved_x001c[4]; + efm32_vector_table_entry_t sv_call; + efm32_vector_table_entry_t reserved_debug; + efm32_vector_table_entry_t reserved_x0034; + efm32_vector_table_entry_t pend_sv; + efm32_vector_table_entry_t systick; + efm32_vector_table_entry_t irq[EFM32_VECTOR_NIRQ]; +} efm32_vector_table_t; + +#endif -- cgit v1.2.3 From 08918902ab8df5211516bc5771cb02b966cf19af Mon Sep 17 00:00:00 2001 From: chrysn Date: Sat, 25 Feb 2012 22:42:15 +0100 Subject: made blinking a led on efm32 possible this includes all register definitions for the gpu and mcu modules, but not all their bit definitions --- .../efm32-tg-stk3300/miniblink/miniblink.c | 69 +++------- include/libopencm3/efm32/tinygecko/cmu.h | 66 +++++++++ include/libopencm3/efm32/tinygecko/gpio.h | 152 +++++++++++++++++++++ 3 files changed, 239 insertions(+), 48 deletions(-) create mode 100644 include/libopencm3/efm32/tinygecko/cmu.h create mode 100644 include/libopencm3/efm32/tinygecko/gpio.h (limited to 'include') diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c index e19ba8f..3053626 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c @@ -18,55 +18,28 @@ * along with this program. If not, see . */ -//#include -// -//void gpio_setup(void) -//{ -// /* Enable GPIOC clock. */ -// /* Manually: */ -// // RCC_APB2ENR |= RCC_APB2ENR_IOPCEN; -// /* Using API functions: */ -// rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); -// -// /* Set GPIO8 (in GPIO port C) to 'output push-pull'. */ -// /* Manually: */ -// // GPIOC_CRH = (GPIO_CNF_OUTPUT_PUSHPULL << (((8 - 8) * 4) + 2)); -// // GPIOC_CRH |= (GPIO_MODE_OUTPUT_2_MHZ << ((8 - 8) * 4)); -// /* Using API functions: */ -// gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, -// GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); -//} +#include +#include int main(void) { -// int i; -// -// gpio_setup(); -// -// /* Blink the LED (PC8) on the board. */ -// while (1) { -// /* Manually: */ -// // GPIOC_BSRR = GPIO8; /* LED off */ -// // for (i = 0; i < 800000; i++) /* Wait a bit. */ -// // __asm__("nop"); -// // GPIOC_BRR = GPIO8; /* LED on */ -// // for (i = 0; i < 800000; i++) /* Wait a bit. */ -// // __asm__("nop"); -// -// /* Using API functions gpio_set()/gpio_clear(): */ -// // gpio_set(GPIOC, GPIO8); /* LED off */ -// // for (i = 0; i < 800000; i++) /* Wait a bit. */ -// // __asm__("nop"); -// // gpio_clear(GPIOC, GPIO8); /* LED on */ -// // for (i = 0; i < 800000; i++) /* Wait a bit. */ -// // __asm__("nop"); -// -// /* Using API function gpio_toggle(): */ -// gpio_toggle(GPIOC, GPIO8); /* LED on/off */ -// for (i = 0; i < 800000; i++) /* Wait a bit. */ -// __asm__("nop"); -// } -// -// return 0; - for(;;); + // FIXME: As of now, this doesn't work without x being volatile; an issue with linking? + volatile int x; + + // Before GPIO works, according to d0034_efm32tg_reference_manual.pdf + // note in section 28.3.7, we'll have to enable GPIO in CMU_HFPERCLKEN0 + + CMU_HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; + + // The User LED is connected to PD7 to the plus side of the LED + // according to t0011_efm32_tiny_gecko_stk_user_manual.pdf figures 16.2 + // and 16.3 (called UIF_LED0) + + GPIO_PD_MODEL = GPIO_MODE_PUSHPULL<<(7*4); + GPIO_PD_DOUTSET = 1<<7; + + while(1) { + for(x = 0; x < 200000; ++x); + GPIO_PD_DOUTTGL = 1<<7; + }; } diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h new file mode 100644 index 0000000..38217ed --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -0,0 +1,66 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* this interface correspons to the description in + * d0034_efm32tg_reference_manual.pdf section 11. */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_CMU_H +#define LIBOPENCM3_EFM32_TINYGECKO_CMU_H + +#include + +#define CMU_BASE 0x400C8000 /* according to d0034_efm32tg_reference_manual.pdf figure 5.2 */ + +/* this is d0034_efm32tg_reference_manual.pdf section 11.4 */ + +#define CMU_CTRL MMIO32(CMU_BASE + 0x000) +#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) +#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) +#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00C) +#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) +#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) +#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) +#define CMU_CALCNT MMIO32(CMU_BASE + 0x01C) +#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) +#define CMU_CMD MMIO32(CMU_BASE + 0x024) +#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) +#define CMU_STATUS MMIO32(CMU_BASE + 0x02C) +#define CMU_IF MMIO32(CMU_BASE + 0x030) +#define CMU_IFS MMIO32(CMU_BASE + 0x034) +#define CMU_IFC MMIO32(CMU_BASE + 0x038) +#define CMU_IEN MMIO32(CMU_BASE + 0x03C) +#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) +#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) +#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) +#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) +#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) +#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) +#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) +#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) +#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) +#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07C) +#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) +#define CMU_LOCK MMIO32(CMU_BASE + 0x084) + +/* this is incomplete because i'm impatient and want a working result + * quickly */ + +#define CMU_HFPERCLKEN0_GPIO (1<<6) + +#endif diff --git a/include/libopencm3/efm32/tinygecko/gpio.h b/include/libopencm3/efm32/tinygecko/gpio.h new file mode 100644 index 0000000..3417eee --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/gpio.h @@ -0,0 +1,152 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* this interface corresponds to the description in + * d0034_efm32tg_reference_manual.pdf section 28. the interface tries to be + * close to stm32/f1's gpio interface. */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_GPIO_H +#define LIBOPENCM3_EFM32_TINYGECKO_GPIO_H + +#include + +#define GPIO_BASE 0x40006000 /* according to d0034_efm32tg_reference_manual.pdf figure 5.2 */ + +/* this is rather straight forward d0034_efm32tg_reference_manual.pdf section 28.4 */ +#define GPIO_Px_CTRL_OFFSET 0x000 +#define GPIO_Px_MODEL_OFFSET 0x004 +#define GPIO_Px_MODEH_OFFSET 0x008 +#define GPIO_Px_DOUT_OFFSET 0x00C +#define GPIO_Px_DOUTSET_OFFSET 0x010 +#define GPIO_Px_DOUTCLR_OFFSET 0x014 +#define GPIO_Px_DOUTTGL_OFFSET 0x018 +#define GPIO_Px_DIN_OFFSET 0x01C +#define GPIO_Px_PINLOCKN_OFFSET 0x020 + +#define GPIO_PA (GPIO_BASE + 0x000) +#define GPIO_PA_CTRL MMIO32(GPIO_PA + GPIO_Px_CTRL_OFFSET) +#define GPIO_PA_MODEL MMIO32(GPIO_PA + GPIO_Px_MODEL_OFFSET) +#define GPIO_PA_MODEH MMIO32(GPIO_PA + GPIO_Px_MODEH_OFFSET) +#define GPIO_PA_DOUT MMIO32(GPIO_PA + GPIO_Px_DOUT_OFFSET) +#define GPIO_PA_DOUTSET MMIO32(GPIO_PA + GPIO_Px_DOUTSET_OFFSET) +#define GPIO_PA_DOUTCLR MMIO32(GPIO_PA + GPIO_Px_DOUTCLR_OFFSET) +#define GPIO_PA_DOUTTGL MMIO32(GPIO_PA + GPIO_Px_DOUTTGL_OFFSET) +#define GPIO_PA_DIN MMIO32(GPIO_PA + GPIO_Px_DIN_OFFSET) +#define GPIO_PA_PINLOCKN MMIO32(GPIO_PA + GPIO_Px_PINLOCKN_OFFSET) + +#define GPIO_PB (GPIO_BASE + 0x024) +#define GPIO_PB_CTRL MMIO32(GPIO_PB + GPIO_Px_CTRL_OFFSET) +#define GPIO_PB_MODEL MMIO32(GPIO_PB + GPIO_Px_MODEL_OFFSET) +#define GPIO_PB_MODEH MMIO32(GPIO_PB + GPIO_Px_MODEH_OFFSET) +#define GPIO_PB_DOUT MMIO32(GPIO_PB + GPIO_Px_DOUT_OFFSET) +#define GPIO_PB_DOUTSET MMIO32(GPIO_PB + GPIO_Px_DOUTSET_OFFSET) +#define GPIO_PB_DOUTCLR MMIO32(GPIO_PB + GPIO_Px_DOUTCLR_OFFSET) +#define GPIO_PB_DOUTTGL MMIO32(GPIO_PB + GPIO_Px_DOUTTGL_OFFSET) +#define GPIO_PB_DIN MMIO32(GPIO_PB + GPIO_Px_DIN_OFFSET) +#define GPIO_PB_PINLOCKN MMIO32(GPIO_PB + GPIO_Px_PINLOCKN_OFFSET) + +#define GPIO_PC (GPIO_BASE + 0x048) +#define GPIO_PC_CTRL MMIO32(GPIO_PC + GPIO_Px_CTRL_OFFSET) +#define GPIO_PC_MODEL MMIO32(GPIO_PC + GPIO_Px_MODEL_OFFSET) +#define GPIO_PC_MODEH MMIO32(GPIO_PC + GPIO_Px_MODEH_OFFSET) +#define GPIO_PC_DOUT MMIO32(GPIO_PC + GPIO_Px_DOUT_OFFSET) +#define GPIO_PC_DOUTSET MMIO32(GPIO_PC + GPIO_Px_DOUTSET_OFFSET) +#define GPIO_PC_DOUTCLR MMIO32(GPIO_PC + GPIO_Px_DOUTCLR_OFFSET) +#define GPIO_PC_DOUTTGL MMIO32(GPIO_PC + GPIO_Px_DOUTTGL_OFFSET) +#define GPIO_PC_DIN MMIO32(GPIO_PC + GPIO_Px_DIN_OFFSET) +#define GPIO_PC_PINLOCKN MMIO32(GPIO_PC + GPIO_Px_PINLOCKN_OFFSET) + +#define GPIO_PD (GPIO_BASE + 0x06C) +#define GPIO_PD_CTRL MMIO32(GPIO_PD + GPIO_Px_CTRL_OFFSET) +#define GPIO_PD_MODEL MMIO32(GPIO_PD + GPIO_Px_MODEL_OFFSET) +#define GPIO_PD_MODEH MMIO32(GPIO_PD + GPIO_Px_MODEH_OFFSET) +#define GPIO_PD_DOUT MMIO32(GPIO_PD + GPIO_Px_DOUT_OFFSET) +#define GPIO_PD_DOUTSET MMIO32(GPIO_PD + GPIO_Px_DOUTSET_OFFSET) +#define GPIO_PD_DOUTCLR MMIO32(GPIO_PD + GPIO_Px_DOUTCLR_OFFSET) +#define GPIO_PD_DOUTTGL MMIO32(GPIO_PD + GPIO_Px_DOUTTGL_OFFSET) +#define GPIO_PD_DIN MMIO32(GPIO_PD + GPIO_Px_DIN_OFFSET) +#define GPIO_PD_PINLOCKN MMIO32(GPIO_PD + GPIO_Px_PINLOCKN_OFFSET) + +#define GPIO_PE (GPIO_BASE + 0x090) +#define GPIO_PE_CTRL MMIO32(GPIO_PE + GPIO_Px_CTRL_OFFSET) +#define GPIO_PE_MODEL MMIO32(GPIO_PE + GPIO_Px_MODEL_OFFSET) +#define GPIO_PE_MODEH MMIO32(GPIO_PE + GPIO_Px_MODEH_OFFSET) +#define GPIO_PE_DOUT MMIO32(GPIO_PE + GPIO_Px_DOUT_OFFSET) +#define GPIO_PE_DOUTSET MMIO32(GPIO_PE + GPIO_Px_DOUTSET_OFFSET) +#define GPIO_PE_DOUTCLR MMIO32(GPIO_PE + GPIO_Px_DOUTCLR_OFFSET) +#define GPIO_PE_DOUTTGL MMIO32(GPIO_PE + GPIO_Px_DOUTTGL_OFFSET) +#define GPIO_PE_DIN MMIO32(GPIO_PE + GPIO_Px_DIN_OFFSET) +#define GPIO_PE_PINLOCKN MMIO32(GPIO_PE + GPIO_Px_PINLOCKN_OFFSET) + +#define GPIO_PF (GPIO_BASE + 0x0B4) +#define GPIO_PF_CTRL MMIO32(GPIO_PF + GPIO_Px_CTRL_OFFSET) +#define GPIO_PF_MODEL MMIO32(GPIO_PF + GPIO_Px_MODEL_OFFSET) +#define GPIO_PF_MODEH MMIO32(GPIO_PF + GPIO_Px_MODEH_OFFSET) +#define GPIO_PF_DOUT MMIO32(GPIO_PF + GPIO_Px_DOUT_OFFSET) +#define GPIO_PF_DOUTSET MMIO32(GPIO_PF + GPIO_Px_DOUTSET_OFFSET) +#define GPIO_PF_DOUTCLR MMIO32(GPIO_PF + GPIO_Px_DOUTCLR_OFFSET) +#define GPIO_PF_DOUTTGL MMIO32(GPIO_PF + GPIO_Px_DOUTTGL_OFFSET) +#define GPIO_PF_DIN MMIO32(GPIO_PF + GPIO_Px_DIN_OFFSET) +#define GPIO_PF_PINLOCKN MMIO32(GPIO_PF + GPIO_Px_PINLOCKN_OFFSET) + +#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) +#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) +#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) +#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) +#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) +#define GPIO_IF MMIO32(GPIO_BASE + 0x114) +#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) +#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) +#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) +#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) +#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) +#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) +#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) +#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) +#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) +#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) + +/* these are the modes defined for the MODEx fields in the MODEL/MODEH + * registers, named as in d0034_efm32tg_reference_manual.pdf's sections + * 28.5.2/28.5.3. for explanations of what they really do, rather see section + * 28.3.1. */ + +#define GPIO_MODE_DISABLED 0 +#define GPIO_MODE_INPUT 1 +#define GPIO_MODE_INPUTPULL 2 +#define GPIO_MODE_INPUTPULLFILTER 3 +#define GPIO_MODE_PUSHPULL 4 +#define GPIO_MODE_PUSHPULLDRIVE 5 +#define GPIO_MODE_WIREDOR 6 +#define GPIO_MODE_WIREDORPULLDOWN 7 +#define GPIO_MODE_WIREDAND 8 +#define GPIO_MODE_WIREDANDFILTER 9 +#define GPIO_MODE_WIREDANDPULLUP 10 +#define GPIO_MODE_WIREDANDPULLUPFILTER 11 +#define GPIO_MODE_WIREDANDDRIVE 12 +#define GPIO_MODE_WIREDANDDRIVEFILTER 13 +#define GPIO_MODE_WIREDANDDRIVEPULLUP 14 +#define GPIO_MODE_WIREDANDDRIVEPULLUPFILTER 15 + +//void gpio_set(u32 gpioport, u16 gpios); +//void gpio_clear(u32 gpioport, u16 gpios); +//void gpio_toggle(u32 gpioport, u16 gpios); +//u16 gpio_get(u32 gpioport, u16 gpios); + +#endif -- cgit v1.2.3 From 2275ed7b0c355920927be6709a87a0482a749eb2 Mon Sep 17 00:00:00 2001 From: chrysn Date: Sun, 26 Feb 2012 03:40:18 +0100 Subject: overhauled documentation includes minor refactoring in example code and modification of how the generic and the tinygecko specific vector.h go together (bringing it in line with stm32/f1's memorymap.h) --- Makefile | 2 +- examples/efm32/tinygecko/Makefile.include | 2 +- .../efm32-tg-stk3300/miniblink/miniblink.c | 35 ++++++++++++--- include/libopencm3/efm32/tinygecko/cmu.h | 30 ++++++++++--- .../libopencm3/efm32/tinygecko/devicerevision.h | 4 ++ include/libopencm3/efm32/tinygecko/gpio.h | 52 ++++++++++++++++++---- include/libopencm3/efm32/tinygecko/vector.h | 14 +++--- include/libopencm3/efm32/vector.h | 24 ++++++---- lib/efm32/tinygecko/Makefile | 3 +- lib/efm32/tinygecko/vector.c | 2 +- 10 files changed, 131 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index 4e41096..07825ec 100644 --- a/Makefile +++ b/Makefile @@ -25,7 +25,7 @@ LIBDIR = $(DESTDIR)/$(PREFIX)/lib SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL = install -TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lm3s +TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lm3s efm32/tinygecko # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) diff --git a/examples/efm32/tinygecko/Makefile.include b/examples/efm32/tinygecko/Makefile.include index 1ee8d49..76691ce 100644 --- a/examples/efm32/tinygecko/Makefile.include +++ b/examples/efm32/tinygecko/Makefile.include @@ -30,7 +30,7 @@ GDB = $(PREFIX)-gdb #TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) TOOLCHAIN_DIR = ../../../../.. CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ - -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F1 + -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD LDSCRIPT ?= ${TOOLCHAIN_DIR}/lib/efm32/tinygecko/$(MCU).ld LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib/efm32/tinygecko \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c index 3053626..0941add 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c @@ -21,11 +21,37 @@ #include #include +void led_setup(void); +void led_toggle(void); + +/** @file + * Minimal example for making the User LED of the EFM32-TG-STK330 eval board blink. + */ + +/** + * Toggle the User LED in an infinite loop, with time between the toggling + * determined by a busy loop stupidly counting up. + */ + int main(void) { // FIXME: As of now, this doesn't work without x being volatile; an issue with linking? volatile int x; + led_setup(); + + while(1) { + for(x = 0; x < 200000; ++x); + led_toggle(); + }; +} + +/** + * Enable GPIO, and set up port D7 as an output pin. + */ + +void led_setup(void) +{ // Before GPIO works, according to d0034_efm32tg_reference_manual.pdf // note in section 28.3.7, we'll have to enable GPIO in CMU_HFPERCLKEN0 @@ -36,10 +62,9 @@ int main(void) // and 16.3 (called UIF_LED0) GPIO_PD_MODEL = GPIO_MODE_PUSHPULL<<(7*4); - GPIO_PD_DOUTSET = 1<<7; +} - while(1) { - for(x = 0; x < 200000; ++x); - GPIO_PD_DOUTTGL = 1<<7; - }; +void led_toggle(void) +{ + GPIO_PD_DOUTTGL = 1<<7; } diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index 38217ed..e690ebd 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -17,17 +17,29 @@ * along with this program. If not, see . */ -/* this interface correspons to the description in - * d0034_efm32tg_reference_manual.pdf section 11. */ +/** @file + * + * Definitions for the CMU (Clock Management Unit). + * + * This corresponds to the description in d0034_efm32tg_reference_manual.pdf + * section 11. + * + * @see CMU_registers + */ +/* FIXME: i'd prefer not to @see CMU_registers but have some direct link placed + * automatically from a file to its groups */ #ifndef LIBOPENCM3_EFM32_TINYGECKO_CMU_H #define LIBOPENCM3_EFM32_TINYGECKO_CMU_H #include -#define CMU_BASE 0x400C8000 /* according to d0034_efm32tg_reference_manual.pdf figure 5.2 */ +#define CMU_BASE 0x400C8000 /**< Register base address for the CMU according to d0034_efm32tg_reference_manual.pdf figure 5.2. */ -/* this is d0034_efm32tg_reference_manual.pdf section 11.4 */ +/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4. + * + * @defgroup CMU_registers CMU registers + * @{ */ #define CMU_CTRL MMIO32(CMU_BASE + 0x000) #define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) @@ -58,8 +70,14 @@ #define CMU_ROUTE MMIO32(CMU_BASE + 0x080) #define CMU_LOCK MMIO32(CMU_BASE + 0x084) -/* this is incomplete because i'm impatient and want a working result - * quickly */ +/** @} */ + +/** + * This section is incomplete because i'm impatient and want a working result + * quickly + * + * @todo Include all bits and bit groups from the manual. + */ #define CMU_HFPERCLKEN0_GPIO (1<<6) diff --git a/include/libopencm3/efm32/tinygecko/devicerevision.h b/include/libopencm3/efm32/tinygecko/devicerevision.h index 83e0e0d..c7c64aa 100644 --- a/include/libopencm3/efm32/tinygecko/devicerevision.h +++ b/include/libopencm3/efm32/tinygecko/devicerevision.h @@ -1,3 +1,7 @@ +/* FIXME: proper documentation, see where this fits, if we need this at all + * etc. this was just a first attempt at implementing something easy with + * MMIO32. */ + /* this implements d0034_efm32tg_reference_manual.pdf's 7.3.4 "Device Revision" * section */ diff --git a/include/libopencm3/efm32/tinygecko/gpio.h b/include/libopencm3/efm32/tinygecko/gpio.h index 3417eee..710651c 100644 --- a/include/libopencm3/efm32/tinygecko/gpio.h +++ b/include/libopencm3/efm32/tinygecko/gpio.h @@ -17,18 +17,36 @@ * along with this program. If not, see . */ -/* this interface corresponds to the description in - * d0034_efm32tg_reference_manual.pdf section 28. the interface tries to be - * close to stm32/f1's gpio interface. */ +/** @file + * + * Definitions for the GPIO subsystem (General Purpose Input Output). + * + * This corresponds to the description in d0034_efm32tg_reference_manual.pdf + * section 28. + * + * @see GPIO_registers + * @see GPIO_MODE_values + */ +/* FIXME: i'd prefer not to @see CMU_registers but have some direct link placed + * automatically from a file to its groups */ #ifndef LIBOPENCM3_EFM32_TINYGECKO_GPIO_H #define LIBOPENCM3_EFM32_TINYGECKO_GPIO_H #include -#define GPIO_BASE 0x40006000 /* according to d0034_efm32tg_reference_manual.pdf figure 5.2 */ +#define GPIO_BASE 0x40006000 /**< Register base address for the GPIO according to d0034_efm32tg_reference_manual.pdf figure 5.2. */ -/* this is rather straight forward d0034_efm32tg_reference_manual.pdf section 28.4 */ +/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 28.4 + * + * The bulk of the registers defined here (like GPIO_PA_CTRL) will not be used + * inside the convenience functions, but are provided for direct access. + * + * @todo This section could profit from bit-banding. + * + * @defgroup GPIO_registers GPIO registers + * @{ + */ #define GPIO_Px_CTRL_OFFSET 0x000 #define GPIO_Px_MODEL_OFFSET 0x004 #define GPIO_Px_MODEH_OFFSET 0x008 @@ -122,10 +140,24 @@ #define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) #define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) -/* these are the modes defined for the MODEx fields in the MODEL/MODEH - * registers, named as in d0034_efm32tg_reference_manual.pdf's sections - * 28.5.2/28.5.3. for explanations of what they really do, rather see section - * 28.3.1. */ +/** @} */ + +/** These are the modes defined for the MODEx fields in the MODEL/MODEH + * registers. + * + * For example, to set the mode for the 3rd pin of port A to pushpull, set + * `GPIO_PA_MODEL = GPIO_MODE_PUSHPULL << (3*4);`. + * + * @todo Update the example as soon as there are convenience functions to do + * this properly. + * + * They are named as in d0034_efm32tg_reference_manual.pdf's sections + * 28.5.2/28.5.3. For explanations of what they really do, rather see section + * 28.3.1. + * + * @defgroup GPIO_MODE_values GPIO MODE values + * @{ + */ #define GPIO_MODE_DISABLED 0 #define GPIO_MODE_INPUT 1 @@ -144,6 +176,8 @@ #define GPIO_MODE_WIREDANDDRIVEPULLUP 14 #define GPIO_MODE_WIREDANDDRIVEPULLUPFILTER 15 +/** @} */ + //void gpio_set(u32 gpioport, u16 gpios); //void gpio_clear(u32 gpioport, u16 gpios); //void gpio_toggle(u32 gpioport, u16 gpios); diff --git a/include/libopencm3/efm32/tinygecko/vector.h b/include/libopencm3/efm32/tinygecko/vector.h index c609da3..1f2eeb7 100644 --- a/include/libopencm3/efm32/tinygecko/vector.h +++ b/include/libopencm3/efm32/tinygecko/vector.h @@ -1,11 +1,15 @@ -/* this implements d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line. */ - +/** @file + * + * Definitions for vector tables on Tiny Gecko systems. + * + * @see include/libopencm3/efm32/vector.h + * + * @todo The definitions of the individual IRQs will go here too. + * */ #ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H #define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H -#define EFM32_VECTOR_NIRQ 23 - -#include "../vector.h" +#define EFM32_VECTOR_NIRQ 23 /**< See d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line */ #endif diff --git a/include/libopencm3/efm32/vector.h b/include/libopencm3/efm32/vector.h index 96ca301..8a385ec 100644 --- a/include/libopencm3/efm32/vector.h +++ b/include/libopencm3/efm32/vector.h @@ -1,21 +1,29 @@ -/* this implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2. +/** @file * - * the structure of the vector table is implemented independently of the vector - * table, as it can be relocated to other memory locations too. + * Definitions for handling vector tables. * - * don't include this file directly; rather, include the family's vector.h - * file, which defines the number of interrupts (EFM_VECTOR_NIRQ) from table - * 1.1 */ + * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2. + * + * The structure of the vector table is implemented independently of the system + * vector table starting at memory position 0x0, as it can be relocated to + * other memory locations too. + */ #ifndef LIBOPENCM3_EFM32_VECTOR_H #define LIBOPENCM3_EFM32_VECTOR_H #include -typedef void (*efm32_vector_table_entry_t)(void); +#ifdef TINYGECKO +# include +#else +# error "efm32 family not defined." +#endif + +typedef void (*efm32_vector_table_entry_t)(void); /**< Type of an interrupt function. Only used to avoid hard-to-read function pointers in the efm32_vector_table_t struct. */ typedef struct { - unsigned int *initial_sp_value; + unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ efm32_vector_table_entry_t reset; efm32_vector_table_entry_t nmi; efm32_vector_table_entry_t hard_fault; diff --git a/lib/efm32/tinygecko/Makefile b/lib/efm32/tinygecko/Makefile index b785d4d..afe1e93 100644 --- a/lib/efm32/tinygecko/Makefile +++ b/lib/efm32/tinygecko/Makefile @@ -19,6 +19,7 @@ ## LIBNAME = libopencm3_efm32tinygecko +FAMILY = TINYGECKO PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf @@ -26,7 +27,7 @@ CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD -DSTM32F1 + -ffunction-sections -fdata-sections -MD -D$(FAMILY) # ARFLAGS = rcsv ARFLAGS = rcs OBJS = vector.o devicerevision.o diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c index 0a7c09f..624785e 100644 --- a/lib/efm32/tinygecko/vector.c +++ b/lib/efm32/tinygecko/vector.c @@ -18,7 +18,7 @@ * along with this program. If not, see . */ -#include +#include #define WEAK __attribute__ ((weak)) -- cgit v1.2.3 From be62115f007cba85db361b4235ec23da446d7803 Mon Sep 17 00:00:00 2001 From: chrysn Date: Mon, 27 Feb 2012 12:01:41 +0100 Subject: efm32: created memory map from all base addresses --- include/libopencm3/efm32/memorymap.h | 29 ++++++++++ include/libopencm3/efm32/tinygecko/cmu.h | 3 +- include/libopencm3/efm32/tinygecko/gpio.h | 3 +- include/libopencm3/efm32/tinygecko/memorymap.h | 76 ++++++++++++++++++++++++++ 4 files changed, 107 insertions(+), 4 deletions(-) create mode 100644 include/libopencm3/efm32/memorymap.h create mode 100644 include/libopencm3/efm32/tinygecko/memorymap.h (limited to 'include') diff --git a/include/libopencm3/efm32/memorymap.h b/include/libopencm3/efm32/memorymap.h new file mode 100644 index 0000000..35bfdd3 --- /dev/null +++ b/include/libopencm3/efm32/memorymap.h @@ -0,0 +1,29 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H +#define LIBOPENCM3_EFM32_MEMORYMAP_H + +#ifdef TINYGECKO +# include +#else +# error "efm32 family not defined." +#endif + +#endif diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index e690ebd..b003289 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -33,8 +33,7 @@ #define LIBOPENCM3_EFM32_TINYGECKO_CMU_H #include - -#define CMU_BASE 0x400C8000 /**< Register base address for the CMU according to d0034_efm32tg_reference_manual.pdf figure 5.2. */ +#include /** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4. * diff --git a/include/libopencm3/efm32/tinygecko/gpio.h b/include/libopencm3/efm32/tinygecko/gpio.h index 710651c..7551a41 100644 --- a/include/libopencm3/efm32/tinygecko/gpio.h +++ b/include/libopencm3/efm32/tinygecko/gpio.h @@ -34,8 +34,7 @@ #define LIBOPENCM3_EFM32_TINYGECKO_GPIO_H #include - -#define GPIO_BASE 0x40006000 /**< Register base address for the GPIO according to d0034_efm32tg_reference_manual.pdf figure 5.2. */ +#include /** These definitions reflect d0034_efm32tg_reference_manual.pdf section 28.4 * diff --git a/include/libopencm3/efm32/tinygecko/memorymap.h b/include/libopencm3/efm32/tinygecko/memorymap.h new file mode 100644 index 0000000..672c013 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/memorymap.h @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/** @file + * + * Layout of the system address space of Tiny Gecko devices. + * + * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2. + */ + +/* The common cortex-m3 definitions were verified from + * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be + * missing there. The details (everything based on SCS_BASE) was verified from + * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but + * there are discrepancies. */ +#include + +#define CODE_BASE 0x00000000 + +#define SRAM_BASE 0x20000000 +#define SRAM_BASE_BITBAND 0x22000000 + +#define PERIPH_BASE 0x40000000 +#define PERIPH_BASE_BITBAND 0x42000000 + +/* Details of the "Code" section */ + +#define FLASH_BASE (CODE_BASE + 0x00000000) +#define USERDATA_BASE (CODE_BASE + 0x0fe00000) +#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000) +#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000) +#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000) + +/* Tiny Gecko peripherial definitions */ + +#define VCMP_BASE (PERIPH_BASE + 0x00000000) +#define ACMP0_BASE (PERIPH_BASE + 0x00001000) +#define ACMP1_BASE (PERIPH_BASE + 0x00001400) +#define ADC_BASE (PERIPH_BASE + 0x00002000) +#define DAC0_BASE (PERIPH_BASE + 0x00004000) +#define GPIO_BASE (PERIPH_BASE + 0x00006000) +#define I2C0_BASE (PERIPH_BASE + 0x0000a000) +#define USART0_BASE (PERIPH_BASE + 0x0000c000) +#define USART1_BASE (PERIPH_BASE + 0x0000c400) +#define TIMER0_BASE (PERIPH_BASE + 0x00010000) +#define TIMER1_BASE (PERIPH_BASE + 0x00010400) +#define RTC_BASE (PERIPH_BASE + 0x00080000) +#define LETIMER0_BASE (PERIPH_BASE + 0x00082000) +#define LEUART0_BASE (PERIPH_BASE + 0x00084000) +#define PCNT0_BASE (PERIPH_BASE + 0x00086000) +#define WDOG_BASE (PERIPH_BASE + 0x00088000) +#define LCD_BASE (PERIPH_BASE + 0x0008a000) +#define LESENSE_BASE (PERIPH_BASE + 0x0008c000) +#define MSC_BASE (PERIPH_BASE + 0x000c0000) +#define DMA_BASE (PERIPH_BASE + 0x000c2000) +#define EMU_BASE (PERIPH_BASE + 0x000c6000) +#define CMU_BASE (PERIPH_BASE + 0x000c8000) +#define RMU_BASE (PERIPH_BASE + 0x000ca000) +#define PRS_BASE (PERIPH_BASE + 0x000cc000) +#define AES_BASE (PERIPH_BASE + 0x000e0000) -- cgit v1.2.3 From f6025af859b4a2b27a01aaf314c66b531f3dbc21 Mon Sep 17 00:00:00 2001 From: chrysn Date: Mon, 27 Feb 2012 13:21:40 +0100 Subject: efm32 tinygecko: defined interrupts there seems not to be anything family specific about the interrupt vectors of m3 based efm32 systems, thus renaming vector.h to irq.h --- include/libopencm3/efm32/tinygecko/irq.h | 36 +++++++++++++++++++++++++++++ include/libopencm3/efm32/tinygecko/vector.h | 15 ------------ include/libopencm3/efm32/vector.h | 11 ++++++--- 3 files changed, 44 insertions(+), 18 deletions(-) create mode 100644 include/libopencm3/efm32/tinygecko/irq.h delete mode 100644 include/libopencm3/efm32/tinygecko/vector.h (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h new file mode 100644 index 0000000..ee0c631 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq.h @@ -0,0 +1,36 @@ +/** @file + * + * Definitions of interrupt names on EFM32 Tiny Gecko systems + * + * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. + */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H + +#define IRQ_DMA 0 +#define IRQ_GPIO_EVEN 1 +#define IRQ_TIMER0 2 +#define IRQ_USART0_RX 3 +#define IRQ_USART0_TX 4 +#define IRQ_ACMP01 5 +#define IRQ_ADC0 6 +#define IRQ_DAC0 7 +#define IRQ_I2C0 8 +#define IRQ_GPIO_ODD 9 +#define IRQ_TIMER1 10 +#define IRQ_USART1_RX 11 +#define IRQ_USART1_TX 12 +#define IRQ_LESENSE 13 +#define IRQ_LEUART0 14 +#define IRQ_LETIMER0 15 +#define IRQ_PCNT0 16 +#define IRQ_RTC 17 +#define IRQ_CMU 18 +#define IRQ_VCMP 19 +#define IRQ_LCD 20 +#define IRQ_MSC 21 +#define IRQ_AES 22 +#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ + +#endif diff --git a/include/libopencm3/efm32/tinygecko/vector.h b/include/libopencm3/efm32/tinygecko/vector.h deleted file mode 100644 index 1f2eeb7..0000000 --- a/include/libopencm3/efm32/tinygecko/vector.h +++ /dev/null @@ -1,15 +0,0 @@ -/** @file - * - * Definitions for vector tables on Tiny Gecko systems. - * - * @see include/libopencm3/efm32/vector.h - * - * @todo The definitions of the individual IRQs will go here too. - * */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H -#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H - -#define EFM32_VECTOR_NIRQ 23 /**< See d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line */ - -#endif diff --git a/include/libopencm3/efm32/vector.h b/include/libopencm3/efm32/vector.h index 8a385ec..ae6b9ba 100644 --- a/include/libopencm3/efm32/vector.h +++ b/include/libopencm3/efm32/vector.h @@ -7,6 +7,9 @@ * The structure of the vector table is implemented independently of the system * vector table starting at memory position 0x0, as it can be relocated to * other memory locations too. + * + * The exact size of a vector interrupt table depends on the number of + * interrupts IRQ_COUNT, which is defined per family. */ #ifndef LIBOPENCM3_EFM32_VECTOR_H @@ -15,12 +18,14 @@ #include #ifdef TINYGECKO -# include +# include #else # error "efm32 family not defined." #endif -typedef void (*efm32_vector_table_entry_t)(void); /**< Type of an interrupt function. Only used to avoid hard-to-read function pointers in the efm32_vector_table_t struct. */ +/** Type of an interrupt function. Only used to avoid hard-to-read function + * pointers in the efm32_vector_table_t struct. */ +typedef void (*efm32_vector_table_entry_t)(void); typedef struct { unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ @@ -36,7 +41,7 @@ typedef struct { efm32_vector_table_entry_t reserved_x0034; efm32_vector_table_entry_t pend_sv; efm32_vector_table_entry_t systick; - efm32_vector_table_entry_t irq[EFM32_VECTOR_NIRQ]; + efm32_vector_table_entry_t irq[IRQ_COUNT]; } efm32_vector_table_t; #endif -- cgit v1.2.3 From f4376371ec34b34021aa266a95a2a7bdc87b2683 Mon Sep 17 00:00:00 2001 From: chrysn Date: Mon, 27 Feb 2012 13:24:19 +0100 Subject: efm32: minor documentation enhancements --- include/libopencm3/efm32/memorymap.h | 8 ++++++++ include/libopencm3/efm32/tinygecko/memorymap.h | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/libopencm3/efm32/memorymap.h b/include/libopencm3/efm32/memorymap.h index 35bfdd3..481883c 100644 --- a/include/libopencm3/efm32/memorymap.h +++ b/include/libopencm3/efm32/memorymap.h @@ -17,6 +17,14 @@ * along with this program. If not, see . */ +/** @file + * + * Dispatcher for the base address definitions, depending on the particular + * Gecko family. + * + * @see tinygecko/memorymap.h + */ + #ifndef LIBOPENCM3_EFM32_MEMORYMAP_H #define LIBOPENCM3_EFM32_MEMORYMAP_H diff --git a/include/libopencm3/efm32/tinygecko/memorymap.h b/include/libopencm3/efm32/tinygecko/memorymap.h index 672c013..87395b5 100644 --- a/include/libopencm3/efm32/tinygecko/memorymap.h +++ b/include/libopencm3/efm32/tinygecko/memorymap.h @@ -54,7 +54,7 @@ #define ACMP1_BASE (PERIPH_BASE + 0x00001400) #define ADC_BASE (PERIPH_BASE + 0x00002000) #define DAC0_BASE (PERIPH_BASE + 0x00004000) -#define GPIO_BASE (PERIPH_BASE + 0x00006000) +#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */ #define I2C0_BASE (PERIPH_BASE + 0x0000a000) #define USART0_BASE (PERIPH_BASE + 0x0000c000) #define USART1_BASE (PERIPH_BASE + 0x0000c400) @@ -70,7 +70,7 @@ #define MSC_BASE (PERIPH_BASE + 0x000c0000) #define DMA_BASE (PERIPH_BASE + 0x000c2000) #define EMU_BASE (PERIPH_BASE + 0x000c6000) -#define CMU_BASE (PERIPH_BASE + 0x000c8000) +#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */ #define RMU_BASE (PERIPH_BASE + 0x000ca000) #define PRS_BASE (PERIPH_BASE + 0x000cc000) #define AES_BASE (PERIPH_BASE + 0x000e0000) -- cgit v1.2.3 From a747e887bd819ad20bca83e8f43c9e81798a59f6 Mon Sep 17 00:00:00 2001 From: chrysn Date: Wed, 29 Feb 2012 02:32:14 +0100 Subject: efm32 tinygecko gpio: implemented all the bit values along with the actual implementation comes a first attempt to better structure the doxygen groups. putting all the groups in a bigger one makes it easier to reference them from the file itself, and makes the structure clearer on the module page. --- include/libopencm3/efm32/tinygecko/gpio.h | 199 ++++++++++++++++++++++++++++-- 1 file changed, 191 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/gpio.h b/include/libopencm3/efm32/tinygecko/gpio.h index 7551a41..ea4eafd 100644 --- a/include/libopencm3/efm32/tinygecko/gpio.h +++ b/include/libopencm3/efm32/tinygecko/gpio.h @@ -24,11 +24,8 @@ * This corresponds to the description in d0034_efm32tg_reference_manual.pdf * section 28. * - * @see GPIO_registers - * @see GPIO_MODE_values + * @see EFM32TG_GPIO */ -/* FIXME: i'd prefer not to @see CMU_registers but have some direct link placed - * automatically from a file to its groups */ #ifndef LIBOPENCM3_EFM32_TINYGECKO_GPIO_H #define LIBOPENCM3_EFM32_TINYGECKO_GPIO_H @@ -36,6 +33,12 @@ #include #include +/** Register definitions and register value definitions for the GPIO subsystem + * + * @defgroup EFM32TG_GPIO EFM32 Tiny Gecko GPIO registers and values + * @{ + */ + /** These definitions reflect d0034_efm32tg_reference_manual.pdf section 28.4 * * The bulk of the registers defined here (like GPIO_PA_CTRL) will not be used @@ -43,7 +46,7 @@ * * @todo This section could profit from bit-banding. * - * @defgroup GPIO_registers GPIO registers + * @defgroup EFM32TG_GPIO_registers EFM32 Tiny Gecko GPIO registers * @{ */ #define GPIO_Px_CTRL_OFFSET 0x000 @@ -141,8 +144,29 @@ /** @} */ -/** These are the modes defined for the MODEx fields in the MODEL/MODEH - * registers. +/** Bit states for the GPIO_Px_CTRL register + * + * They are named as in d0034_efm32tg_reference_manual.pdf's section + * 28.5.1. + * + * @defgroup EFM32TG_GPIO_Px_CTRL_bits EFM32 Tiny Gecko GPIO Px CTRL bits + * @{ + */ + +#define GPIO_CTRL_DRIVEMODE_STANDARD 0 /**< 6mA drive current */ +#define GPIO_CTRL_DRIVEMODE_LOWEST 1 /**< 0.5mA drive current */ +#define GPIO_CTRL_DRIVEMODE_HIGH 2 /**< 20mA drive current */ +#define GPIO_CTRL_DRIVEMODE_LOW 3 /**< 2mA drive current */ + +/** @} */ + +/** These are the modes defined for the MODEx fields in the GPIO_Px_MODEL and + * GPIO_Px_MODEH registers. + * + * These bit state definitions are not localized, meaning that they have to be + * bitshifted by multiples of 4 to configure other pins than 0; configurations + * for pins 0 to 7 go to GPIO_Px_MODEL (shifted by 4*pin), configurations for + * pins 8 to 15 go to GPIO_Px_MODEH (shifted by 4*(pin-8)). * * For example, to set the mode for the 3rd pin of port A to pushpull, set * `GPIO_PA_MODEL = GPIO_MODE_PUSHPULL << (3*4);`. @@ -154,7 +178,7 @@ * 28.5.2/28.5.3. For explanations of what they really do, rather see section * 28.3.1. * - * @defgroup GPIO_MODE_values GPIO MODE values + * @defgroup EFM32TG_GPIO_MODE_values EFM32 Tiny Gecko GPIO MODE values * @{ */ @@ -177,6 +201,165 @@ /** @} */ +/** These are the modes defined for the EXTIPSELx fields in the GPIO_EXTIPSELL + * and GPIO_EXTIPSELH registers. + * + * These bit state definitions are not localized, meaning that they have to be + * bitshifted by multiples of 4 to configure other pins than 0; configurations + * for pins 0 to 7 go to GPIO_EXTIPSELL (shifted by 4*pin), configurations for + * pins 8 to 15 go to GPIO_EXTIPSELH (shifted by 4*(pin-8)). + * + * They are named as in d0034_efm32tg_reference_manual.pdf's sections + * 28.5.10/28.5.11. For explanations of what they do, rather see section + * 28.3.5. + * + * @defgroup EFM32TG_GPIO_EXTIP_values EFM32 Tiny Gecko GPIO EXTIPSEL values + * @{ + */ + +#define GPIO_EXTIPSEL_PORTA 0 /**< Port A pin x selected for external interrupt x */ +#define GPIO_EXTIPSEL_PORTB 1 /**< Port B pin x selected for external interrupt x */ +#define GPIO_EXTIPSEL_PORTC 2 /**< Port C pin x selected for external interrupt x */ +#define GPIO_EXTIPSEL_PORTD 3 /**< Port D pin x selected for external interrupt x */ +#define GPIO_EXTIPSEL_PORTE 4 /**< Port E pin x selected for external interrupt x */ +#define GPIO_EXTIPSEL_PORTF 5 /**< Port F pin x selected for external interrupt x */ + +/** @} */ + +/** Bit states for the GPIO_ROUTE register + * + * See d0034_efm32tg_reference_manual.pdf section 28.5.18 for definitions, and + * 28.3.4.1 for explanations. + * + * @defgroup EFM32TG_GPIO_ROUTE_bits EFM32 Tiny Gecko GPIO ROUTE bits + * @{ + */ + +#define GPIO_ROUTE_SWLOCATION_MASK (0x03<<8) +#define GPIO_ROUTE_SWLOCATION_LOC0 (0<<8) /**< Route SW pins to location 0 (see chip data sheet for exact pins */ +#define GPIO_ROUTE_SWLOCATION_LOC1 (1<<8) /**< Route SW pins to location 1 (see chip data sheet for exact pins */ +#define GPIO_ROUTE_SWLOCATION_LOC2 (2<<8) /**< Route SW pins to location 2 (see chip data sheet for exact pins */ +#define GPIO_ROUTE_SWLOCATION_LOC3 (3<<8) /**< Route SW pins to location 3 (see chip data sheet for exact pins */ + +#define GPIO_ROUTE_SWOPEN (1<<2) /**< Serial Wire Viewer Output pin enabled */ +#define GPIO_ROUTE_SWDIOPEN (1<<1) /**< Serial Wire Data pin enabled */ +#define GPIO_ROUTE_SWCLKPEN (1<<0) /**< Serial Wire Clock pin enabled */ + +/** @} */ + +/** Bit states for the GPIO_INSENSE register + * + * See d0034_efm32tg_reference_manual.pdf section 28.5.19 for definitions, and + * 28.3.7 for details. + * + * @defgroup EFM32TG_GPIO_INSENSE_bits EFM32 Tiny Gecko GPIO INSENSE bits + * @{ + */ + +#define GPIO_INSENSE_PRS (1<<1) /**< Input sensing for PRS enabled */ +#define GPIO_INSENSE_INT (1<<0) /**< Input sensing for interrupts enabled */ + +/** @} */ + +/** Values for the GPIO_LOCK register + * + * See d0034_efm32tg_reference_manual.pdf section 28.5.20 for definitions, and + * 28.3.1.1 for explanations. + * + * @defgroup EFM32TG_GPIO_LOCK_values EFM32 Tiny Gecko GPIO LOCK bits + * @{ + */ + +#define GPIO_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */ +#define GPIO_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */ +#define GPIO_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock down GPIO */ +#define GPIO_LOCK_SET_UNLOCKED 0xa543 /**< Write this to the LOCK register to unlock the GPIO */ + +/** @} */ + +/** Bit states for the GPIO_CTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 28.5.21 for definitions, and + * 28.3.4 for explanations. + * + * @defgroup EFM32TG_GPIO_CTRL_bits EFM32 Tiny Gecko GPIO CTRL bits + * @{ + */ + +#define GPIO_CTRL_EM4RET (1<<0) /**< Retention of states in EM4 */ + +/** @} */ + +/** Bit states for the GPIO_CMD register + * + * See d0034_efm32tg_reference_manual.pdf section 28.5.22 for definitions and + * figure 28.5 in case you wonder if that register is mentioned anywhere else + * at all. + * + * @defgroup EFM32TG_GPIO_CMD_bits EFM32 Tiny Gecko GPIO CMD bits + * @{ + */ + +#define GPIO_CMD_EM4WUCLR (1<<0) /**< Write this flag to clear EM4 wakeup requests */ + +/** @} */ + +/** Bit states for the GPIO_EM4WUEN register + * + * See d0034_efm32tg_reference_manual.pdf section 28.5.23 for definitions, and + * 28.3.2 for explanations. + * + * @defgroup EFM32TG_GPIO_EM4WUEN_bits EFM32 Tiny Gecko GPIO EM4WUEN bits + * @{ + */ + +#define GPIO_EM4WUEN_A0 0x01 /**< Wake up from EM4 on A0 activity */ +#define GPIO_EM4WUEN_A6 0x02 /**< Wake up from EM4 on A6 activity */ +#define GPIO_EM4WUEN_C9 0x04 /**< Wake up from EM4 on C9 activity */ +#define GPIO_EM4WUEN_F1 0x08 /**< Wake up from EM4 on F1 activity */ +#define GPIO_EM4WUEN_F3 0x10 /**< Wake up from EM4 on F3 activity */ +#define GPIO_EM4WUEN_E13 0x20 /**< Wake up from EM4 on E13 activity */ + +/** @} */ + +/** Bit states for the GPIO_EM4WUPOL register + * + * See d0034_efm32tg_reference_manual.pdf section 28.5.24 for definitions, and + * 28.3.2 for explanations. + * + * @defgroup EFM32TG_GPIO_EM4WUPOL_bits EFM32 Tiny Gecko GPIO EM4WUPOL bits + * @{ + */ + +#define GPIO_EM4WUPOL_A0 0x01 /**< High wake up from EM4 on A0 */ +#define GPIO_EM4WUPOL_A6 0x02 /**< High wake up from EM4 on A6 */ +#define GPIO_EM4WUPOL_C9 0x04 /**< High wake up from EM4 on C9 */ +#define GPIO_EM4WUPOL_F1 0x08 /**< High wake up from EM4 on F1 */ +#define GPIO_EM4WUPOL_F3 0x10 /**< High wake up from EM4 on F3 */ +#define GPIO_EM4WUPOL_E13 0x20 /**< High wake up from EM4 on E13 */ + +/** @} */ + +/** Bit states for the GPIO_EM4WUCAUSE register + * + * See d0034_efm32tg_reference_manual.pdf section 28.5.25 for definitions, and + * 28.3.2 for explanations. + * + * @defgroup EFM32TG_GPIO_EM4WUCAUSE_bits EFM32 Tiny Gecko GPIO EM4WUCAUSE bits + * @{ + */ + +#define GPIO_EM4WUCAUSE_A0 0x01 /**< Woke up from EM4 on A0 */ +#define GPIO_EM4WUCAUSE_A6 0x02 /**< Woke up from EM4 on A6 */ +#define GPIO_EM4WUCAUSE_C9 0x04 /**< Woke up from EM4 on C9 */ +#define GPIO_EM4WUCAUSE_F1 0x08 /**< Woke up from EM4 on F1 */ +#define GPIO_EM4WUCAUSE_F3 0x10 /**< Woke up from EM4 on F3 */ +#define GPIO_EM4WUCAUSE_E13 0x20 /**< Woke up from EM4 on E13 */ + +/** @} */ + +/** @} */ + //void gpio_set(u32 gpioport, u16 gpios); //void gpio_clear(u32 gpioport, u16 gpios); //void gpio_toggle(u32 gpioport, u16 gpios); -- cgit v1.2.3 From 541fded753a27b8670c5b485ecec1794c02de187 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 1 Mar 2012 02:09:02 +0100 Subject: convenience functions for efm32 gpio also, the whole gpio header file is now a big doxygen group, structuring the convenience functions and the register/value definitions --- .../efm32-tg-stk3300/miniblink/miniblink.c | 6 +- include/libopencm3/efm32/tinygecko/gpio.h | 310 +++++++++++++++------ lib/efm32/tinygecko/Makefile | 2 +- lib/efm32/tinygecko/gpio.c | 23 ++ 4 files changed, 250 insertions(+), 91 deletions(-) create mode 100644 lib/efm32/tinygecko/gpio.c (limited to 'include') diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c index 1976080..e9907d3 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c @@ -60,10 +60,12 @@ void led_setup(void) // according to t0011_efm32_tiny_gecko_stk_user_manual.pdf figures 16.2 // and 16.3 (called UIF_LED0) - GPIO_PD_MODEL = GPIO_MODE_PUSHPULL<<(7*4); + gpio_set_mode(GPIO_PD, GPIO_MODE_PUSHPULL, GPIO7); + // GPIO_PD_MODEL = GPIO_MODE_PUSHPULL<<(7*4); } void led_toggle(void) { - GPIO_PD_DOUTTGL = 1<<7; + gpio_toggle(GPIO_PD, GPIO7); + // GPIO_PD_DOUTTGL = 1<<7; } diff --git a/include/libopencm3/efm32/tinygecko/gpio.h b/include/libopencm3/efm32/tinygecko/gpio.h index ea4eafd..3e782f3 100644 --- a/include/libopencm3/efm32/tinygecko/gpio.h +++ b/include/libopencm3/efm32/tinygecko/gpio.h @@ -18,13 +18,16 @@ */ /** @file - * - * Definitions for the GPIO subsystem (General Purpose Input Output). + * @see EFM32TG_GPIO + */ + +/** Definitions for the GPIO subsystem (General Purpose Input Output). * * This corresponds to the description in d0034_efm32tg_reference_manual.pdf * section 28. * - * @see EFM32TG_GPIO + * @defgroup EFM32TG_GPIO EFM32 Tiny Gecko GPIO + * @{ */ #ifndef LIBOPENCM3_EFM32_TINYGECKO_GPIO_H @@ -35,7 +38,7 @@ /** Register definitions and register value definitions for the GPIO subsystem * - * @defgroup EFM32TG_GPIO EFM32 Tiny Gecko GPIO registers and values + * @defgroup EFM32TG_GPIO_regsandvals EFM32 Tiny Gecko GPIO registers and values * @{ */ @@ -49,98 +52,129 @@ * @defgroup EFM32TG_GPIO_registers EFM32 Tiny Gecko GPIO registers * @{ */ -#define GPIO_Px_CTRL_OFFSET 0x000 -#define GPIO_Px_MODEL_OFFSET 0x004 -#define GPIO_Px_MODEH_OFFSET 0x008 -#define GPIO_Px_DOUT_OFFSET 0x00C -#define GPIO_Px_DOUTSET_OFFSET 0x010 -#define GPIO_Px_DOUTCLR_OFFSET 0x014 -#define GPIO_Px_DOUTTGL_OFFSET 0x018 -#define GPIO_Px_DIN_OFFSET 0x01C -#define GPIO_Px_PINLOCKN_OFFSET 0x020 +#define GPIO_Px_CTRL(port) MMIO32(port + 0x000) /**< @see EFM32TG_GPIO_Px_CTRL_bits */ +#define GPIO_Px_MODEL(port) MMIO32(port + 0x004) /**< @see EFM32TG_GPIO_MODE_values */ +#define GPIO_Px_MODEH(port) MMIO32(port + 0x008) /**< @see EFM32TG_GPIO_MODE_values */ +#define GPIO_Px_DOUT(port) MMIO32(port + 0x00C) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_Px_DOUTSET(port) MMIO32(port + 0x010) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_Px_DOUTCLR(port) MMIO32(port + 0x014) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_Px_DOUTTGL(port) MMIO32(port + 0x018) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_Px_DIN(port) MMIO32(port + 0x01C) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_Px_PINLOCKN(port) MMIO32(port + 0x020) /**< @see EFM32TG_GPIO_pinnumberbits */ #define GPIO_PA (GPIO_BASE + 0x000) -#define GPIO_PA_CTRL MMIO32(GPIO_PA + GPIO_Px_CTRL_OFFSET) -#define GPIO_PA_MODEL MMIO32(GPIO_PA + GPIO_Px_MODEL_OFFSET) -#define GPIO_PA_MODEH MMIO32(GPIO_PA + GPIO_Px_MODEH_OFFSET) -#define GPIO_PA_DOUT MMIO32(GPIO_PA + GPIO_Px_DOUT_OFFSET) -#define GPIO_PA_DOUTSET MMIO32(GPIO_PA + GPIO_Px_DOUTSET_OFFSET) -#define GPIO_PA_DOUTCLR MMIO32(GPIO_PA + GPIO_Px_DOUTCLR_OFFSET) -#define GPIO_PA_DOUTTGL MMIO32(GPIO_PA + GPIO_Px_DOUTTGL_OFFSET) -#define GPIO_PA_DIN MMIO32(GPIO_PA + GPIO_Px_DIN_OFFSET) -#define GPIO_PA_PINLOCKN MMIO32(GPIO_PA + GPIO_Px_PINLOCKN_OFFSET) +#define GPIO_PA_CTRL GPIO_Px_CTRL(GPIO_PA) +#define GPIO_PA_MODEL GPIO_Px_MODEL(GPIO_PA) +#define GPIO_PA_MODEH GPIO_Px_MODEH(GPIO_PA) +#define GPIO_PA_DOUT GPIO_Px_DOUT(GPIO_PA) +#define GPIO_PA_DOUTSET GPIO_Px_DOUTSET(GPIO_PA) +#define GPIO_PA_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PA) +#define GPIO_PA_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PA) +#define GPIO_PA_DIN GPIO_Px_DIN(GPIO_PA) +#define GPIO_PA_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PA) #define GPIO_PB (GPIO_BASE + 0x024) -#define GPIO_PB_CTRL MMIO32(GPIO_PB + GPIO_Px_CTRL_OFFSET) -#define GPIO_PB_MODEL MMIO32(GPIO_PB + GPIO_Px_MODEL_OFFSET) -#define GPIO_PB_MODEH MMIO32(GPIO_PB + GPIO_Px_MODEH_OFFSET) -#define GPIO_PB_DOUT MMIO32(GPIO_PB + GPIO_Px_DOUT_OFFSET) -#define GPIO_PB_DOUTSET MMIO32(GPIO_PB + GPIO_Px_DOUTSET_OFFSET) -#define GPIO_PB_DOUTCLR MMIO32(GPIO_PB + GPIO_Px_DOUTCLR_OFFSET) -#define GPIO_PB_DOUTTGL MMIO32(GPIO_PB + GPIO_Px_DOUTTGL_OFFSET) -#define GPIO_PB_DIN MMIO32(GPIO_PB + GPIO_Px_DIN_OFFSET) -#define GPIO_PB_PINLOCKN MMIO32(GPIO_PB + GPIO_Px_PINLOCKN_OFFSET) +#define GPIO_PB_CTRL GPIO_Px_CTRL(GPIO_PB) +#define GPIO_PB_MODEL GPIO_Px_MODEL(GPIO_PB) +#define GPIO_PB_MODEH GPIO_Px_MODEH(GPIO_PB) +#define GPIO_PB_DOUT GPIO_Px_DOUT(GPIO_PB) +#define GPIO_PB_DOUTSET GPIO_Px_DOUTSET(GPIO_PB) +#define GPIO_PB_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PB) +#define GPIO_PB_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PB) +#define GPIO_PB_DIN GPIO_Px_DIN(GPIO_PB) +#define GPIO_PB_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PB) #define GPIO_PC (GPIO_BASE + 0x048) -#define GPIO_PC_CTRL MMIO32(GPIO_PC + GPIO_Px_CTRL_OFFSET) -#define GPIO_PC_MODEL MMIO32(GPIO_PC + GPIO_Px_MODEL_OFFSET) -#define GPIO_PC_MODEH MMIO32(GPIO_PC + GPIO_Px_MODEH_OFFSET) -#define GPIO_PC_DOUT MMIO32(GPIO_PC + GPIO_Px_DOUT_OFFSET) -#define GPIO_PC_DOUTSET MMIO32(GPIO_PC + GPIO_Px_DOUTSET_OFFSET) -#define GPIO_PC_DOUTCLR MMIO32(GPIO_PC + GPIO_Px_DOUTCLR_OFFSET) -#define GPIO_PC_DOUTTGL MMIO32(GPIO_PC + GPIO_Px_DOUTTGL_OFFSET) -#define GPIO_PC_DIN MMIO32(GPIO_PC + GPIO_Px_DIN_OFFSET) -#define GPIO_PC_PINLOCKN MMIO32(GPIO_PC + GPIO_Px_PINLOCKN_OFFSET) +#define GPIO_PC_CTRL GPIO_Px_CTRL(GPIO_PC) +#define GPIO_PC_MODEL GPIO_Px_MODEL(GPIO_PC) +#define GPIO_PC_MODEH GPIO_Px_MODEH(GPIO_PC) +#define GPIO_PC_DOUT GPIO_Px_DOUT(GPIO_PC) +#define GPIO_PC_DOUTSET GPIO_Px_DOUTSET(GPIO_PC) +#define GPIO_PC_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PC) +#define GPIO_PC_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PC) +#define GPIO_PC_DIN GPIO_Px_DIN(GPIO_PC) +#define GPIO_PC_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PC) #define GPIO_PD (GPIO_BASE + 0x06C) -#define GPIO_PD_CTRL MMIO32(GPIO_PD + GPIO_Px_CTRL_OFFSET) -#define GPIO_PD_MODEL MMIO32(GPIO_PD + GPIO_Px_MODEL_OFFSET) -#define GPIO_PD_MODEH MMIO32(GPIO_PD + GPIO_Px_MODEH_OFFSET) -#define GPIO_PD_DOUT MMIO32(GPIO_PD + GPIO_Px_DOUT_OFFSET) -#define GPIO_PD_DOUTSET MMIO32(GPIO_PD + GPIO_Px_DOUTSET_OFFSET) -#define GPIO_PD_DOUTCLR MMIO32(GPIO_PD + GPIO_Px_DOUTCLR_OFFSET) -#define GPIO_PD_DOUTTGL MMIO32(GPIO_PD + GPIO_Px_DOUTTGL_OFFSET) -#define GPIO_PD_DIN MMIO32(GPIO_PD + GPIO_Px_DIN_OFFSET) -#define GPIO_PD_PINLOCKN MMIO32(GPIO_PD + GPIO_Px_PINLOCKN_OFFSET) +#define GPIO_PD_CTRL GPIO_Px_CTRL(GPIO_PD) +#define GPIO_PD_MODEL GPIO_Px_MODEL(GPIO_PD) +#define GPIO_PD_MODEH GPIO_Px_MODEH(GPIO_PD) +#define GPIO_PD_DOUT GPIO_Px_DOUT(GPIO_PD) +#define GPIO_PD_DOUTSET GPIO_Px_DOUTSET(GPIO_PD) +#define GPIO_PD_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PD) +#define GPIO_PD_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PD) +#define GPIO_PD_DIN GPIO_Px_DIN(GPIO_PD) +#define GPIO_PD_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PD) #define GPIO_PE (GPIO_BASE + 0x090) -#define GPIO_PE_CTRL MMIO32(GPIO_PE + GPIO_Px_CTRL_OFFSET) -#define GPIO_PE_MODEL MMIO32(GPIO_PE + GPIO_Px_MODEL_OFFSET) -#define GPIO_PE_MODEH MMIO32(GPIO_PE + GPIO_Px_MODEH_OFFSET) -#define GPIO_PE_DOUT MMIO32(GPIO_PE + GPIO_Px_DOUT_OFFSET) -#define GPIO_PE_DOUTSET MMIO32(GPIO_PE + GPIO_Px_DOUTSET_OFFSET) -#define GPIO_PE_DOUTCLR MMIO32(GPIO_PE + GPIO_Px_DOUTCLR_OFFSET) -#define GPIO_PE_DOUTTGL MMIO32(GPIO_PE + GPIO_Px_DOUTTGL_OFFSET) -#define GPIO_PE_DIN MMIO32(GPIO_PE + GPIO_Px_DIN_OFFSET) -#define GPIO_PE_PINLOCKN MMIO32(GPIO_PE + GPIO_Px_PINLOCKN_OFFSET) +#define GPIO_PE_CTRL GPIO_Px_CTRL(GPIO_PE) +#define GPIO_PE_MODEL GPIO_Px_MODEL(GPIO_PE) +#define GPIO_PE_MODEH GPIO_Px_MODEH(GPIO_PE) +#define GPIO_PE_DOUT GPIO_Px_DOUT(GPIO_PE) +#define GPIO_PE_DOUTSET GPIO_Px_DOUTSET(GPIO_PE) +#define GPIO_PE_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PE) +#define GPIO_PE_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PE) +#define GPIO_PE_DIN GPIO_Px_DIN(GPIO_PE) +#define GPIO_PE_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PE) #define GPIO_PF (GPIO_BASE + 0x0B4) -#define GPIO_PF_CTRL MMIO32(GPIO_PF + GPIO_Px_CTRL_OFFSET) -#define GPIO_PF_MODEL MMIO32(GPIO_PF + GPIO_Px_MODEL_OFFSET) -#define GPIO_PF_MODEH MMIO32(GPIO_PF + GPIO_Px_MODEH_OFFSET) -#define GPIO_PF_DOUT MMIO32(GPIO_PF + GPIO_Px_DOUT_OFFSET) -#define GPIO_PF_DOUTSET MMIO32(GPIO_PF + GPIO_Px_DOUTSET_OFFSET) -#define GPIO_PF_DOUTCLR MMIO32(GPIO_PF + GPIO_Px_DOUTCLR_OFFSET) -#define GPIO_PF_DOUTTGL MMIO32(GPIO_PF + GPIO_Px_DOUTTGL_OFFSET) -#define GPIO_PF_DIN MMIO32(GPIO_PF + GPIO_Px_DIN_OFFSET) -#define GPIO_PF_PINLOCKN MMIO32(GPIO_PF + GPIO_Px_PINLOCKN_OFFSET) - -#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) -#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) -#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) -#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) -#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) -#define GPIO_IF MMIO32(GPIO_BASE + 0x114) -#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) -#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) -#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) -#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) -#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) -#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) -#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) -#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) -#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) -#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) +#define GPIO_PF_CTRL GPIO_Px_CTRL(GPIO_PF) +#define GPIO_PF_MODEL GPIO_Px_MODEL(GPIO_PF) +#define GPIO_PF_MODEH GPIO_Px_MODEH(GPIO_PF) +#define GPIO_PF_DOUT GPIO_Px_DOUT(GPIO_PF) +#define GPIO_PF_DOUTSET GPIO_Px_DOUTSET(GPIO_PF) +#define GPIO_PF_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PF) +#define GPIO_PF_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PF) +#define GPIO_PF_DIN GPIO_Px_DIN(GPIO_PF) +#define GPIO_PF_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PF) + +#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) /**< @see EFM32TG_GPIO_EXTIP_values */ +#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) /**< @see EFM32TG_GPIO_EXTIP_values */ +#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_IF MMIO32(GPIO_BASE + 0x114) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) /**< @see EFM32TG_GPIO_pinnumberbits */ +#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) /**< @see EFM32TG_GPIO_ROUTE_bits */ +#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) /**< @see EFM32TG_GPIO_INSENSE_bits */ +#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) /**< @see EFM32TG_GPIO_LOCK_values */ +#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) /**< @see EFM32TG_GPIO_CTRL_bits */ +#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) /**< @see EFM32TG_GPIO_CMD_bits */ +#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) /**< @see EFM32TG_GPIO_EM4WUEN_bits */ +#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) /**< @see EFM32TG_GPIO_EM4WUPOL_bits */ +#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) /**< @see EFM32TG_GPIO_EM4WUCAUSE_bits */ + +/** @} */ + +/** Pin number bits + * + * Provided for convenience. They can be used on the GPIO_Px_DOUT, + * GPIO_Px_DOUTSET, GPIO_Px_DOUTCLR, GPIO_Px_DOUTTGL, GPIO_Px_DIN, + * GPIO_Px_PINLOCKN, GPIO_Px_EXTIRISE, GPIO_Px_EXTIFALL, GPIO_IEN, GPIO_IF, + * GPIO_IFS, and GPIO_IFC registers. + * + * @defgroup EFM32TG_GPIO_pinnumberbits EFM32 Tiny Gecko GPIO pin number bits + * @{ + */ + +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff /** @} */ @@ -198,6 +232,7 @@ #define GPIO_MODE_WIREDANDDRIVEFILTER 13 #define GPIO_MODE_WIREDANDDRIVEPULLUP 14 #define GPIO_MODE_WIREDANDDRIVEPULLUPFILTER 15 +#define GPIO_MODE_MASK 0x0f /** @} */ @@ -360,9 +395,108 @@ /** @} */ -//void gpio_set(u32 gpioport, u16 gpios); -//void gpio_clear(u32 gpioport, u16 gpios); -//void gpio_toggle(u32 gpioport, u16 gpios); -//u16 gpio_get(u32 gpioport, u16 gpios); +/** GPIO convenience functions + * + * These functions try to be close to the STM32 F1 utility functions where + * possible. + * + * The functions intentionally don't cover all the possible read- and write + * operations to the GPIO registers. For example, reading the configured output + * strength for a port is rarely required. + * + * Many convenience functions are static to allow inlining by the compiler. + * + * @todo Implement all the non-trivial but useful convenience functions. + * + * @defgroup EFM32TG_GPIO_convenience EFM32 Tiny Gecko GPIO convenience functions + * @{ + */ + +/** Set a whole GPIO port's out data to a particular value + * + * \param gpioport Address of a GPIO port to use (eg GPIO_PA) + * \param gpios Bit pattern the output of the port will be configured to (eg GPIO6|GPIO3 to switch pins 6 and 3 to high and all the others to low) + */ +static void gpio_port_write(u32 gpioport, u16 data) +{ + GPIO_Px_DOUT(gpioport) = data; +} +/** Set some bits in a GPIO port's out data + * + * \param gpioport Address of a GPIO port to use (eg GPIO_PA) + * \param gpios GPIO pin(s) to be set to 1 (eg GPIO6|GPIO3 to switch pins 6 and 3 to high and leave all the others in their previous state) + */ +static void gpio_set(u32 gpioport, u16 gpios) +{ + GPIO_Px_DOUTSET(gpioport) = gpios; +} +/** Clear some bits in a GPIO port's out data + * + * \param gpioport Address of a GPIO port to use (eg GPIO_PA) + * \param gpios GPIO pin(s) to be set to 0 (eg GPIO6|GPIO3 to switch pins 6 and 3 to low and leave all the others in their previous state) + */ +static void gpio_clear(u32 gpioport, u16 gpios) +{ + GPIO_Px_DOUTCLR(gpioport) = gpios; +} +/** Toggle some bits in a GPIO port's out data + * + * \param gpioport Address of a GPIO port to use (eg GPIO_PA) + * \param gpios GPIO pin(s) that will be toggled (eg GPIO6|GPIO3 to toggle the output directions of pins 6 and 3 and leave all the others in their previous state) + */ +static void gpio_toggle(u32 gpioport, u16 gpios) +{ + GPIO_Px_DOUTTGL(gpioport) = gpios; +} + +/** Read input bits from a GPIO's port in data + * + * \param gpioport Address of a GPIO port to use (eg GPIO_PA) + * \returns Current value of the in register of the given port + */ +static u16 gpio_port_read(u32 gpioport) +{ + return GPIO_Px_DIN(gpioport); +} +/** Read input bits from a GPIO's port in data + * + * \param gpioport Address of a GPIO port to use (eg GPIO_PA) + * \param gpios Bits that will be read (eg GPIO6|GPIO3 to read pins 6 and 3) + * \returns Bit pattern that contains 1 in all pin positions that currently read as high (eg GPIO6 if port A's 6th pin is currently high and the 3rd pin is low) + */ +static u16 gpio_get(u32 gpioport, u16 gpios) +{ + return gpio_port_read(gpioport) & gpios; +} + +/** Configure a particular pin configuration on one or more pins + * + * This function is not atomic. It has to be made sure that it is not + * interrupted by other code that modifies the port's configuration. + * + * @todo Find out if that is really the case (if &= and |= are atomic, the + * worst thing that happens when this function is interrupted with itself is + * that the ports stay disabled for the time being, which is to be expected + * anyway when changing a pin's mode. + * + * \param gpioport Address of a GPIO port to use (eg GPIO_PA) + * \param mode Pin configuration mode to set (eg GPIO_MODE_INPUT) + * \param gpios Pins to configure (eg GPIO6|GPIO3 to set the mode on pins 6 and 3) + */ +void gpio_set_mode(u32 gpioport, u8 mode, u16 gpios); + +/** Configure the alternate drive strength for a port + * + * \param gpioport Address of a GPIO port to use (eg GPIO_PA) + * \param strength Alternate drive strength to configure for the port (eg GPIO_CTRL_DRIVEMODE_HIGH) + */ +static void gpio_set_strength(u32 gpioport, u8 strength) +{ + GPIO_Px_CTRL(gpioport) = strength; +} + +/** @} */ + +/** @} */ #endif diff --git a/lib/efm32/tinygecko/Makefile b/lib/efm32/tinygecko/Makefile index afe1e93..a2bffc1 100644 --- a/lib/efm32/tinygecko/Makefile +++ b/lib/efm32/tinygecko/Makefile @@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -D$(FAMILY) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o devicerevision.o +OBJS = vector.o devicerevision.o gpio.o VPATH += ../ diff --git a/lib/efm32/tinygecko/gpio.c b/lib/efm32/tinygecko/gpio.c new file mode 100644 index 0000000..6e49f17 --- /dev/null +++ b/lib/efm32/tinygecko/gpio.c @@ -0,0 +1,23 @@ +#include + +void gpio_set_mode(u32 gpioport, u8 mode, u16 gpios) +{ + u8 i; + u32 modemaskl = 0, modesetl = 0, modemaskh = 0, modeseth = 0; + + for (i = 0; i < 8; ++i) + { + if (gpios & (1< + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#define ISER0 MMIO32(0xE000E100) +#define ICER0 MMIO32(0xE000E180) +#define ISPR0 MMIO32(0XE000E200) +#define ICPR0 MMIO32(0XE000E280) + +/** @file Simplest implementation of the lightswitch mechanism. */ + +int main(void) +{ + gpio_setup(); + + while(1) { + if (pb0_get()) + led_on(); + if (pb1_get()) + led_off(); + }; +} diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c new file mode 100644 index 0000000..0cd1204 --- /dev/null +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c @@ -0,0 +1,88 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/** @file Common definitions used by all lightswitch implementations */ + +#include +#include + +/** The User LED is connected to PD7 to the plus side of the LED according to + * t0011_efm32_tiny_gecko_stk_user_manual.pdf figures 16.2 and 16.3 (called + * UIF_LED0) + */ +#define LED_PORT GPIO_PD +#define LED_PIN GPIO7 + +#define BUTTON0_PORT GPIO_PD +#define BUTTON0_PORT_EXTIPSEL GPIO_EXTIPSEL_PORTD +#define BUTTON0_PIN_NUMBER 8 +#define BUTTON0_PIN GPIO8 +#define BUTTON1_PORT GPIO_PB +#define BUTTON1_PORT_EXTIPSEL GPIO_EXTIPSEL_PORTB +#define BUTTON1_PIN_NUMBER 11 +#define BUTTON1_PIN GPIO11 + +void gpio_setup(void); +void led_on(void); +void led_off(void); + +bool pb0_get(void); +bool pb1_get(void); + +/** + * Enable GPIO, and set up port D7 as an output pin and D8 and B11 as input. + */ + +void gpio_setup(void) +{ + // Before GPIO works, according to d0034_efm32tg_reference_manual.pdf + // note in section 28.3.7, we'll have to enable GPIO in CMU_HFPERCLKEN0 + + CMU_HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; + + gpio_set_mode(LED_PORT, GPIO_MODE_PUSHPULL, LED_PIN); + + // Button PB0 is connected to pin PD8 and pulled low when pushed, + // Botton PB1 to pin PB11 (sources as for LED). Pullups and debouncing + // are alreay in place in hardware, so no filtering or pullup is + // needed. + + gpio_set_mode(BUTTON0_PORT, GPIO_MODE_INPUT, BUTTON0_PIN); + gpio_set_mode(BUTTON1_PORT, GPIO_MODE_INPUT, BUTTON1_PIN); +} + +void led_on(void) +{ + gpio_set(LED_PORT, LED_PIN); +} + +void led_off(void) +{ + gpio_clear(LED_PORT, LED_PIN); +} + +bool pb0_get(void) +{ + return !gpio_get(GPIO_PD, GPIO8); +} + +bool pb1_get(void) +{ + return !gpio_get(GPIO_PB, GPIO11); +} diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c new file mode 100644 index 0000000..f19423b --- /dev/null +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c @@ -0,0 +1,71 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#define ISER0 MMIO32(0xE000E100) + +void interrupt_setup() +{ + // These are the ports the pin interrupts for 8 and 11 are to be + // configured to, and they should trigger on falling edge. + + GPIO_EXTIPSELH = (BUTTON0_PORT_EXTIPSEL << ((BUTTON0_PIN_NUMBER-8)*4)) | + (BUTTON1_PORT_EXTIPSEL << ((BUTTON1_PIN_NUMBER-8)*4)); + + GPIO_EXTIFALL = BUTTON0_PIN | BUTTON1_PIN; + + // Enable interrupts on the GPIO side + + GPIO_INSENSE = GPIO_INSENSE_INT; + GPIO_IEN = BUTTON0_PIN | BUTTON1_PIN; + + // Enable GPIO interrupts in NVIC + + ISER0 = (1<. */ -#include -#include - -void gpio_setup(void); -void led_on(void); -void led_off(void); -bool pb0_get(void); -bool pb1_get(void); - /** @file * Example for switching the User LED of the EFM32-TG-STK330 eval board on and * off using the buttons. */ -int main(void) -{ - gpio_setup(); - - while(1) { - if (pb0_get()) led_on(); - if (pb1_get()) led_off(); - }; -} - -/** - * Enable GPIO, and set up port D7 as an output pin. - */ - -void gpio_setup(void) -{ - // Before GPIO works, according to d0034_efm32tg_reference_manual.pdf - // note in section 28.3.7, we'll have to enable GPIO in CMU_HFPERCLKEN0 - - CMU_HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; - - // The User LED is connected to PD7 to the plus side of the LED - // according to t0011_efm32_tiny_gecko_stk_user_manual.pdf figures 16.2 - // and 16.3 (called UIF_LED0) - - gpio_set_mode(GPIO_PD, GPIO_MODE_PUSHPULL, GPIO7); - - // Button PB0 is connected to pin PD8 and pulled low when pushed, - // Botton PB1 to pin PB11 (sources as for LED). Pullups and debouncing - // are alreay in place in hardware, so no filtering or pullup is - // needed. - - gpio_set_mode(GPIO_PD, GPIO_MODE_INPUT, GPIO8); - gpio_set_mode(GPIO_PB, GPIO_MODE_INPUT, GPIO11); -} - -void led_on(void) -{ - gpio_set(GPIO_PD, GPIO7); -} - -void led_off(void) -{ - gpio_clear(GPIO_PD, GPIO7); -} - -bool pb0_get(void) -{ - return !gpio_get(GPIO_PD, GPIO8); -} +#include "lightswitch-common.c" -bool pb1_get(void) -{ - return !gpio_get(GPIO_PB, GPIO11); -} +/** Change this include to -busywait, -interrupt, or -prs (not implemented + * yet). The overall behavior will not change, but different implementations + * will be used. */ +#include "lightswitch-busywait.c" diff --git a/include/libopencm3/efm32/tinygecko/emu.h b/include/libopencm3/efm32/tinygecko/emu.h new file mode 100644 index 0000000..07327fd --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/emu.h @@ -0,0 +1,125 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/** @file + * @see EFM32TG_EMU + */ + +/** Definitions for the EMU subsystem (Energy Management Unit). + * + * This corresponds to the description in d0034_efm32tg_reference_manual.pdf + * section 10. + * + * @defgroup EFM32TG_EMU EFM32 Tiny Gecko EMU + * @{ + */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_EMU_H +#define LIBOPENCM3_EFM32_TINYGECKO_EMU_H + +#include +#include + +/** Register definitions and register value definitions for the EMU subsystem + * + * @defgroup EFM32TG_EMU_regsandvals EFM32 Tiny Gecko EMU registers and values + * @{ + */ + +/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 10.4 + * + * @defgroup EFM32TG_EMU_registers EFM32 Tiny Gecko EMU registers + * @{ + */ + +#define EMU_CTRL MMIO32(EMU_BASE + 0x000) /**< @see EFM32TG_EMU_CTRL_bits */ +#define EMU_LOCK MMIO32(EMU_BASE + 0x008) /**< @see EFM32TG_EMU_LOCK_values */ +#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) /**< @see EFM32TG_EMU_AUXCTRL_bits */ + +/** @} */ + +/** Bit states for the EMU_CTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 10.5.1 for definitions, and + * 10.3.2 for details (especially on why EM4CTRL_TWO and _THREE are defined). + * + * @defgroup EFM32TG_EMU_CTRL_bits EFM32 Tiny Gecko EMU CTRL bits + * @{ + */ + +#define EMU_CTRL_EM4CTRL_TWO (2<<2) +#define EMU_CTRL_EM4CTRL_THREE (3<<2) +#define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */ +#define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */ + +/** @} */ + +/** Values for the EMU_LOCK register + * + * See d0034_efm32tg_reference_manual.pdf section 10.5.2. There seems not to be + * another mention of it. + * + * @defgroup EFM32TG_EMU_LOCK_values EFM32 Tiny Gecko EMU LOCK values + * @{ + */ + +#define EMU_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */ +#define EMU_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */ +#define EMU_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock the EMU */ +#define EMU_LOCK_SET_UNLOCKED 0xade8 /**< Write this to the LOCK register to unlock the EMU */ + +/** @} */ + +/** Bit states for the EMU_AUXCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 10.5.3 for definition, and + * 9.5.3 for details. + * + * @defgroup EFM32TG_EMU_AUXCTRL_bits EFM32 Tiny Gecko EMU AUXCTRL bits + * @{ + */ + +#define EMU_AUXCTRL_HRCCLR (1<<0) + +/** @} */ + +/** @} */ + +/** EMU convenience functions + * + * These functions can be used to send the chip to low energy modes. + * + * @todo Implement other sleep modes than EM1. Implement WFI vs WFE waits. + * + * @defgroup EFM32TG_EMU_convenience EFM32 Tiny Gecko EMU convenience functions + * @{ + */ + +/** Put the system into EM1 low energy mode. */ +static void emu_sleep_em1(void) +{ + /* FIXME: set SLEEPDEEP to 0 */ + __asm__("wfi"); +} + +/** @} */ + +/** @} */ + +#endif -- cgit v1.2.3 From 4668adcf1fa7654434ad3becda8ab4245488d981 Mon Sep 17 00:00:00 2001 From: chrysn Date: Sat, 3 Mar 2012 00:21:21 +0100 Subject: follow the license change to lgpl3 in efm32 this follows the license change of the master branches in [43561de]. all files whose copyright is not my own are originally based on files whose license has been changed in master. the expression used for the conversion was: sed -i -e 's/This program is free software: you can redistribute/This library is free software: you can redistribute/g' -e 's/under the terms of the GNU General Public License as published/under the terms of the GNU Lesser General Public License as published/' -e 's/This program is distributed in the hope that/This library is distributed in the hope that/g' -e 's/You should have received a copy of the GNU General/You should have received a copy of the GNU Lesser General/' -e 's/along with this program. If not/along with this library. If not/' -e 's/GNU General Public License for more details/GNU Lesser General Public License for more details/' */**/efm32/**/*(.) [43561de] 43561de3297b88d68753cb4625d6dc48bfb43d71 --- examples/efm32/tinygecko/Makefile.include | 12 ++++++------ examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include | 12 ++++++------ .../efm32/tinygecko/efm32-tg-stk3300/lightswitch/Makefile | 12 ++++++------ .../efm32-tg-stk3300/lightswitch/lightswitch-busywait.c | 12 ++++++------ .../efm32-tg-stk3300/lightswitch/lightswitch-common.c | 12 ++++++------ .../efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c | 12 ++++++------ .../tinygecko/efm32-tg-stk3300/lightswitch/lightswitch.c | 12 ++++++------ examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile | 12 ++++++------ .../efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c | 12 ++++++------ include/libopencm3/efm32/memorymap.h | 12 ++++++------ include/libopencm3/efm32/tinygecko/cmu.h | 12 ++++++------ include/libopencm3/efm32/tinygecko/emu.h | 12 ++++++------ include/libopencm3/efm32/tinygecko/gpio.h | 12 ++++++------ include/libopencm3/efm32/tinygecko/memorymap.h | 12 ++++++------ lib/efm32/tinygecko/Makefile | 12 ++++++------ lib/efm32/tinygecko/tinygecko.ld | 12 ++++++------ lib/efm32/tinygecko/vector.c | 12 ++++++------ 17 files changed, 102 insertions(+), 102 deletions(-) (limited to 'include') diff --git a/examples/efm32/tinygecko/Makefile.include b/examples/efm32/tinygecko/Makefile.include index 2426e98..8c42816 100644 --- a/examples/efm32/tinygecko/Makefile.include +++ b/examples/efm32/tinygecko/Makefile.include @@ -5,18 +5,18 @@ ## Copyright (C) 2010 Piotr Esden-Tempski ## Copyright (C) 2012 chrysn ## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## -## This program is distributed in the hope that it will be useful, +## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. +## GNU Lesser General Public License for more details. ## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . ## PREFIX ?= arm-none-eabi diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include b/examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include index a2ad07a..c7d0f38 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include @@ -3,18 +3,18 @@ ## ## Copyright (C) 2012 chrysn ## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## -## This program is distributed in the hope that it will be useful, +## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. +## GNU Lesser General Public License for more details. ## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . ## MCU = EFM32TG840F32 diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/Makefile b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/Makefile index c6e785a..d3a1987 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/Makefile +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/Makefile @@ -3,18 +3,18 @@ ## ## Copyright (C) 2012 chrysn ## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## -## This program is distributed in the hope that it will be useful, +## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. +## GNU Lesser General Public License for more details. ## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . ## BINARY = lightswitch diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-busywait.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-busywait.c index 662d9df..d78d0e1 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-busywait.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-busywait.c @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ #include diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c index 0cd1204..dcc5984 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ /** @file Common definitions used by all lightswitch implementations */ diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c index f19423b..71a1008 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ #include diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch.c index b8675f8..72a5299 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch.c @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ /** @file diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile index a2e44dc..cf46fb8 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile @@ -4,18 +4,18 @@ ## Copyright (C) 2009 Uwe Hermann ## 2012 chrysn ## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## -## This program is distributed in the hope that it will be useful, +## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. +## GNU Lesser General Public License for more details. ## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . ## BINARY = miniblink diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c index e9907d3..72c3b2b 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c @@ -4,18 +4,18 @@ * Copyright (C) 2009 Uwe Hermann * 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ #include diff --git a/include/libopencm3/efm32/memorymap.h b/include/libopencm3/efm32/memorymap.h index 481883c..ff0e544 100644 --- a/include/libopencm3/efm32/memorymap.h +++ b/include/libopencm3/efm32/memorymap.h @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ /** @file diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index b003289..6351057 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ /** @file diff --git a/include/libopencm3/efm32/tinygecko/emu.h b/include/libopencm3/efm32/tinygecko/emu.h index 07327fd..307d1d6 100644 --- a/include/libopencm3/efm32/tinygecko/emu.h +++ b/include/libopencm3/efm32/tinygecko/emu.h @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ /** @file diff --git a/include/libopencm3/efm32/tinygecko/gpio.h b/include/libopencm3/efm32/tinygecko/gpio.h index 1f4ae69..f1e097b 100644 --- a/include/libopencm3/efm32/tinygecko/gpio.h +++ b/include/libopencm3/efm32/tinygecko/gpio.h @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ /** @file diff --git a/include/libopencm3/efm32/tinygecko/memorymap.h b/include/libopencm3/efm32/tinygecko/memorymap.h index 87395b5..abf37ce 100644 --- a/include/libopencm3/efm32/tinygecko/memorymap.h +++ b/include/libopencm3/efm32/tinygecko/memorymap.h @@ -3,18 +3,18 @@ * * Copyright (C) 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ /** @file diff --git a/lib/efm32/tinygecko/Makefile b/lib/efm32/tinygecko/Makefile index a2bffc1..b910509 100644 --- a/lib/efm32/tinygecko/Makefile +++ b/lib/efm32/tinygecko/Makefile @@ -4,18 +4,18 @@ ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 chrysn ## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## -## This program is distributed in the hope that it will be useful, +## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. +## GNU Lesser General Public License for more details. ## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . ## LIBNAME = libopencm3_efm32tinygecko diff --git a/lib/efm32/tinygecko/tinygecko.ld b/lib/efm32/tinygecko/tinygecko.ld index db3b81f..55d37c6 100644 --- a/lib/efm32/tinygecko/tinygecko.ld +++ b/lib/efm32/tinygecko/tinygecko.ld @@ -4,18 +4,18 @@ * Copyright (C) 2009 Uwe Hermann , * 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ /* Generic linker script for EFM32 targets using libopencm3. */ diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c index fb8fbd4..4c6563e 100644 --- a/lib/efm32/tinygecko/vector.c +++ b/lib/efm32/tinygecko/vector.c @@ -4,18 +4,18 @@ * Copyright (C) 2010 Piotr Esden-Tempski , * 2012 chrysn * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * GNU Lesser General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . */ #include -- cgit v1.2.3 From 78c93dc779b42f94f531f81757ad4a911bd3e953 Mon Sep 17 00:00:00 2001 From: chrysn Date: Sat, 3 Mar 2012 00:24:58 +0100 Subject: add missed license headers to efm32 files some files had nonstandard shared copyright lines, fixed them too --- .../tinygecko/efm32-tg-stk3300/miniblink/Makefile | 2 +- .../tinygecko/efm32-tg-stk3300/miniblink/miniblink.c | 2 +- include/libopencm3/efm32/tinygecko/devicerevision.h | 19 +++++++++++++++++++ include/libopencm3/efm32/tinygecko/irq.h | 19 +++++++++++++++++++ include/libopencm3/efm32/vector.h | 19 +++++++++++++++++++ lib/efm32/tinygecko/devicerevision.c | 19 +++++++++++++++++++ lib/efm32/tinygecko/gpio.c | 19 +++++++++++++++++++ lib/efm32/tinygecko/tinygecko.ld | 2 +- lib/efm32/tinygecko/vector.c | 2 +- 9 files changed, 99 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile index cf46fb8..760b99b 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile @@ -2,7 +2,7 @@ ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann -## 2012 chrysn +## Copyright (C) 2012 chrysn ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c index 72c3b2b..0269847 100644 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c @@ -2,7 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann - * 2012 chrysn + * Copyright (C) 2012 chrysn * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by diff --git a/include/libopencm3/efm32/tinygecko/devicerevision.h b/include/libopencm3/efm32/tinygecko/devicerevision.h index c7c64aa..45da408 100644 --- a/include/libopencm3/efm32/tinygecko/devicerevision.h +++ b/include/libopencm3/efm32/tinygecko/devicerevision.h @@ -1,3 +1,22 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + /* FIXME: proper documentation, see where this fits, if we need this at all * etc. this was just a first attempt at implementing something easy with * MMIO32. */ diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h index ee0c631..1b0a484 100644 --- a/include/libopencm3/efm32/tinygecko/irq.h +++ b/include/libopencm3/efm32/tinygecko/irq.h @@ -1,3 +1,22 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + /** @file * * Definitions of interrupt names on EFM32 Tiny Gecko systems diff --git a/include/libopencm3/efm32/vector.h b/include/libopencm3/efm32/vector.h index ae6b9ba..2ae55af 100644 --- a/include/libopencm3/efm32/vector.h +++ b/include/libopencm3/efm32/vector.h @@ -1,3 +1,22 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + /** @file * * Definitions for handling vector tables. diff --git a/lib/efm32/tinygecko/devicerevision.c b/lib/efm32/tinygecko/devicerevision.c index 216ab1b..0af3e90 100644 --- a/lib/efm32/tinygecko/devicerevision.c +++ b/lib/efm32/tinygecko/devicerevision.c @@ -1,3 +1,22 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + #include u8 devicerevision_revision_get(void) diff --git a/lib/efm32/tinygecko/gpio.c b/lib/efm32/tinygecko/gpio.c index 6e49f17..839d1b8 100644 --- a/lib/efm32/tinygecko/gpio.c +++ b/lib/efm32/tinygecko/gpio.c @@ -1,3 +1,22 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + #include void gpio_set_mode(u32 gpioport, u8 mode, u16 gpios) diff --git a/lib/efm32/tinygecko/tinygecko.ld b/lib/efm32/tinygecko/tinygecko.ld index 55d37c6..92f4282 100644 --- a/lib/efm32/tinygecko/tinygecko.ld +++ b/lib/efm32/tinygecko/tinygecko.ld @@ -2,7 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann , - * 2012 chrysn + * Copyright (C) 2012 chrysn * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c index 4c6563e..264426b 100644 --- a/lib/efm32/tinygecko/vector.c +++ b/lib/efm32/tinygecko/vector.c @@ -2,7 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski , - * 2012 chrysn + * Copyright (C) 2012 chrysn * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by -- cgit v1.2.3 From cdf36e6c8e4d1a6a06d646629c9a00b96cecc100 Mon Sep 17 00:00:00 2001 From: chrysn Date: Sat, 3 Mar 2012 20:19:03 +0100 Subject: efm32: some more cmu registers and doxygen update --- include/libopencm3/efm32/tinygecko/cmu.h | 38 +++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index 6351057..19accd5 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -18,16 +18,17 @@ */ /** @file - * - * Definitions for the CMU (Clock Management Unit). + * @see EFM32TG_CMU + */ + +/** Definitions for the CMU (Clock Management Unit). * * This corresponds to the description in d0034_efm32tg_reference_manual.pdf * section 11. * - * @see CMU_registers + * @defgroup EFM32TG_CMU EFM32 Tiny Geco CMU + * @{ */ -/* FIXME: i'd prefer not to @see CMU_registers but have some direct link placed - * automatically from a file to its groups */ #ifndef LIBOPENCM3_EFM32_TINYGECKO_CMU_H #define LIBOPENCM3_EFM32_TINYGECKO_CMU_H @@ -35,10 +36,17 @@ #include #include +/** Register definitions and register value definitions for the CMU subsystem + * + * @defgroup EFM32TG_CMU_regsandvals EFM32 Tiny Gecko CMU registers and values + * @{ + */ + /** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4. * - * @defgroup CMU_registers CMU registers - * @{ */ + * @defgroup EFM32TG_CMU_registers EFM32 Tiny Gecko CMU registers + * @{ + */ #define CMU_CTRL MMIO32(CMU_BASE + 0x000) #define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) @@ -71,6 +79,10 @@ /** @} */ +/** @} */ + +/** @} */ + /** * This section is incomplete because i'm impatient and want a working result * quickly @@ -78,6 +90,16 @@ * @todo Include all bits and bit groups from the manual. */ -#define CMU_HFPERCLKEN0_GPIO (1<<6) +#define CMU_HFPERCLKEN0_GPIO (1<<6) +#define CMU_LFCLKSEL_LFB_DISABLED (0<<2) +#define CMU_LFCLKSEL_LFB_LFRCO (1<<2) +#define CMU_LFCLKSEL_LFB_LFXO (2<<2) +#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2) +#define CMU_LFCLKSEL_LFB_MASK (0x03<<2) +#define CMU_LFCLKSEL_LFA_DISABLED 0 +#define CMU_LFCLKSEL_LFA_LFRCO 1 +#define CMU_LFCLKSEL_LFA_LFXO 2 +#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 3 +#define CMU_LFCLKSEL_LFA_MASK 0x03 #endif -- cgit v1.2.3 From d3fe8c18f8942bc91062a8c721155582a03123ad Mon Sep 17 00:00:00 2001 From: chrysn Date: Sun, 4 Mar 2012 04:23:58 +0100 Subject: experimental yaml based header file generation the header file genertion mechanism here is designed to: * use human readable source data that is better structured and less repetitive than the header files themselves * produce same quality header files than the manual process of writing them. some features were not yet enabled to show that the existing headers didn't change. (look at emu.h's differences. whitespace switched from tabs to spaces as they are easier to handle, use --color-words to see the few differences that stemmed from inconsistencies in the original file.) * be less tedious and thus error prone when doing large modifications (eg, i forgot to add _MASK to bitfields, would like to enable bitbanding acces, and to overhaul the naming in doxygen modules) --- .../efm32/tinygecko/cmu.convenienceheaders | 0 include/libopencm3/efm32/tinygecko/cmu.h | 562 +++++++++++++++++++-- include/libopencm3/efm32/tinygecko/cmu.yaml | 437 ++++++++++++++++ .../efm32/tinygecko/emu.convenienceheaders | 18 + include/libopencm3/efm32/tinygecko/emu.h | 30 +- include/libopencm3/efm32/tinygecko/emu.yaml | 50 ++ .../efm32/tinygecko/generate-license.yaml | 19 + include/libopencm3/efm32/tinygecko/generate.py | 112 ++++ include/libopencm3/efm32/tinygecko/generate.yaml | 2 + 9 files changed, 1159 insertions(+), 71 deletions(-) create mode 100644 include/libopencm3/efm32/tinygecko/cmu.convenienceheaders create mode 100644 include/libopencm3/efm32/tinygecko/cmu.yaml create mode 100644 include/libopencm3/efm32/tinygecko/emu.convenienceheaders create mode 100644 include/libopencm3/efm32/tinygecko/emu.yaml create mode 100644 include/libopencm3/efm32/tinygecko/generate-license.yaml create mode 100644 include/libopencm3/efm32/tinygecko/generate.py create mode 100644 include/libopencm3/efm32/tinygecko/generate.yaml (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders b/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders new file mode 100644 index 0000000..e69de29 diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index 19accd5..0914561 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -21,12 +21,12 @@ * @see EFM32TG_CMU */ -/** Definitions for the CMU (Clock Management Unit). +/** Definitions for the CMU subsystem (Clock Management Unit). * * This corresponds to the description in d0034_efm32tg_reference_manual.pdf * section 11. * - * @defgroup EFM32TG_CMU EFM32 Tiny Geco CMU + * @defgroup EFM32TG_CMU EFM32 Tiny Gecko CMU * @{ */ @@ -42,64 +42,514 @@ * @{ */ -/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4. +/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4 * * @defgroup EFM32TG_CMU_registers EFM32 Tiny Gecko CMU registers * @{ */ -#define CMU_CTRL MMIO32(CMU_BASE + 0x000) -#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) -#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) -#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00C) -#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) -#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) -#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) -#define CMU_CALCNT MMIO32(CMU_BASE + 0x01C) -#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) -#define CMU_CMD MMIO32(CMU_BASE + 0x024) -#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) -#define CMU_STATUS MMIO32(CMU_BASE + 0x02C) -#define CMU_IF MMIO32(CMU_BASE + 0x030) -#define CMU_IFS MMIO32(CMU_BASE + 0x034) -#define CMU_IFC MMIO32(CMU_BASE + 0x038) -#define CMU_IEN MMIO32(CMU_BASE + 0x03C) -#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) -#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) -#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) -#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) -#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) -#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) -#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) -#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) -#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) -#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07C) -#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) -#define CMU_LOCK MMIO32(CMU_BASE + 0x084) - -/** @} */ - -/** @} */ - -/** @} */ - -/** - * This section is incomplete because i'm impatient and want a working result - * quickly - * - * @todo Include all bits and bit groups from the manual. - */ - -#define CMU_HFPERCLKEN0_GPIO (1<<6) -#define CMU_LFCLKSEL_LFB_DISABLED (0<<2) -#define CMU_LFCLKSEL_LFB_LFRCO (1<<2) -#define CMU_LFCLKSEL_LFB_LFXO (2<<2) -#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2) -#define CMU_LFCLKSEL_LFB_MASK (0x03<<2) -#define CMU_LFCLKSEL_LFA_DISABLED 0 -#define CMU_LFCLKSEL_LFA_LFRCO 1 -#define CMU_LFCLKSEL_LFA_LFXO 2 -#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 3 -#define CMU_LFCLKSEL_LFA_MASK 0x03 +#define CMU_CTRL MMIO32(CMU_BASE + 0x000) /**< @see EFM32TG_CMU_CTRL_bits */ +#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) /**< @see EFM32TG_CMU_HFCORECLKDIV_values */ +#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) /**< @see EFM32TG_CMU_HFPERCLKDIV_bits */ +#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00c) /**< @see EFM32TG_CMU_HFRCOCTRL_bits */ +#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) /**< @see EFM32TG_CMU_LFRCOCTRL_bits */ +#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) /**< @see EFM32TG_CMU_AUXHFRCOCTRL_bits */ +#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) /**< @see EFM32TG_CMU_CALCTRL_bits */ +#define CMU_CALCNT MMIO32(CMU_BASE + 0x01c) /**< @see EFM32TG_CMU_CALCNT_bits */ +#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) /**< @see EFM32TG_CMU_OSCENCMD_bits */ +#define CMU_CMD MMIO32(CMU_BASE + 0x024) /**< @see EFM32TG_CMU_CMD_bits */ +#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) /**< @see EFM32TG_CMU_LFCLKSEL_bits */ +#define CMU_STATUS MMIO32(CMU_BASE + 0x02c) /**< @see EFM32TG_CMU_STATUS_bits */ +#define CMU_IF MMIO32(CMU_BASE + 0x030) /**< @see EFM32TG_CMU_IF_bits */ +#define CMU_IFS MMIO32(CMU_BASE + 0x034) /**< @see EFM32TG_CMU_IFS_bits */ +#define CMU_IFC MMIO32(CMU_BASE + 0x038) /**< @see EFM32TG_CMU_IFC_bits */ +#define CMU_IEN MMIO32(CMU_BASE + 0x03c) /**< @see EFM32TG_CMU_IEN_bits */ +#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) /**< @see EFM32TG_CMU_HFCORECLKEN0_bits */ +#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) /**< @see EFM32TG_CMU_HFPERCLKEN0_bits */ +#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) /**< @see EFM32TG_CMU_SYNCBUSY_bits */ +#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) /**< @see EFM32TG_CMU_FREEZE_bits */ +#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) /**< @see EFM32TG_CMU_LFACLKEN0_bits */ +#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) /**< @see EFM32TG_CMU_LFBCLKEN0_bits */ +#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) /**< @see EFM32TG_CMU_LFAPRESC0_bits */ +#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) /**< @see EFM32TG_CMU_LFBPRESC0_bits */ +#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) /**< @see EFM32TG_CMU_PCNTCTRL_bits */ +#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07c) /**< @see EFM32TG_CMU_LCDCTRL_bits */ +#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) /**< @see EFM32TG_CMU_ROUTE_bits */ +#define CMU_LOCK MMIO32(CMU_BASE + 0x084) /**< @see EFM32TG_CMU_LOCK_values */ + +/** @} */ + +/** Bit states for the CMU_CTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.1 for definitions. + * + * @defgroup EFM32TG_CMU_CTRL_bits EFM32 Tiny Gecko CMU CTRL bits + * @{ + */ + +#define CMU_CTRL_DBGCLK_AUXHFRCO (0<<28) +#define CMU_CTRL_DBGCLK_HFCLK (1<<28) +#define CMU_CTRL_CLKOUTSEL1_LFRCO (0<<23) +#define CMU_CTRL_CLKOUTSEL1_LFXO (1<<23) +#define CMU_CTRL_CLKOUTSEL1_HFCLK (2<<23) +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (3<<23) +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (4<<23) +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (5<<23) +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (6<<23) +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (7<<23) +#define CMU_CTRL_CLKOUTSEL0_LFRCO (0<<20) +#define CMU_CTRL_CLKOUTSEL0_LFXO (1<<20) +#define CMU_CTRL_CLKOUTSEL0_HFCLK (2<<20) +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (3<<20) +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (4<<20) +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (5<<20) +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (6<<20) +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (7<<20) +#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (0<<18) +#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (1<<18) +#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (2<<18) +#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (3<<18) +#define CMU_CTRL_LFXOBUFCUR (1<<17) +#define CMU_CTRL_LXFOBOOST_70PCENT (0<<13) +#define CMU_CTRL_LXFOBOOST_100PCENT (1<<13) +#define CMU_CTRL_LFXOMODE_XTAL (0<<11) +#define CMU_CTRL_LFXOMODE_BUFEXTCLK (1<<11) +#define CMU_CTRL_LFXOMODE_DIGEXTCLK (2<<11) +#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (0<<9) +#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (1<<9) +#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (2<<9) +#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (3<<9) +#define CMU_CTRL_HFXOGLITCHDETEN (1<<7) +/* No values defined for the field HFXOBUFCUR */ +#define CMU_CTRL_HFXOBOOST_50PCENT (0<<2) +#define CMU_CTRL_HFXOBOOST_70PCENT (1<<2) +#define CMU_CTRL_HFXOBOOST_80PCENT (2<<2) +#define CMU_CTRL_HFXOBOOST_100PCENT (3<<2) +#define CMU_CTRL_HFXOMODE_XTAL (0<<0) +#define CMU_CTRL_HFXOMODE_BUFEXTCLK (1<<0) +#define CMU_CTRL_HFXOMODE_DIGEXTCLK (2<<0) + +/** @} */ + +/** Values for the CMU_HFCORECLKDIV register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.2 for definitions. + * + * @defgroup EFM32TG_CMU_HFCORECLKDIV_values EFM32 Tiny Gecko CMU HFCORECLKDIV + * values + * @{ + */ + +#define CMU_HFCORECLKDIV_HFCLK 0 +#define CMU_HFCORECLKDIV_HFCLK2 1 +#define CMU_HFCORECLKDIV_HFCLK4 2 +#define CMU_HFCORECLKDIV_HFCLK8 3 +#define CMU_HFCORECLKDIV_HFCLK16 4 +#define CMU_HFCORECLKDIV_HFCLK32 5 +#define CMU_HFCORECLKDIV_HFCLK64 6 +#define CMU_HFCORECLKDIV_HFCLK128 7 +#define CMU_HFCORECLKDIV_HFCLK256 8 +#define CMU_HFCORECLKDIV_HFCLK512 9 + +/** @} */ + +/** Bit states for the CMU_HFPERCLKDIV register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.3 for definitions. + * + * @defgroup EFM32TG_CMU_HFPERCLKDIV_bits EFM32 Tiny Gecko CMU HFPERCLKDIV bits + * @{ + */ + +#define CMU_HFPERCLKDIV_HFPERCLKEN (1<<8) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (0<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (1<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (2<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (3<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (4<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (5<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (6<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (7<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (8<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (9<<0) + +/** @} */ + +/** Bit states for the CMU_HFRCOCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.4 for definitions. + * + * @defgroup EFM32TG_CMU_HFRCOCTRL_bits EFM32 Tiny Gecko CMU HFRCOCTRL bits + * @{ + */ + +/* No values defined for the field SUDELAY */ +#define CMU_HFRCOCTRL_BAND_1MHZ (0<<8) +#define CMU_HFRCOCTRL_BAND_7MHZ (1<<8) +#define CMU_HFRCOCTRL_BAND_11MHZ (2<<8) +#define CMU_HFRCOCTRL_BAND_14MHZ (3<<8) +#define CMU_HFRCOCTRL_BAND_21MHZ (4<<8) +#define CMU_HFRCOCTRL_BAND_28MHZ (5<<8) +/* No values defined for the field TUNING */ + +/** @} */ + +/** Bit states for the CMU_AUXHFRCOCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.6 for definitions. + * + * @defgroup EFM32TG_CMU_AUXHFRCOCTRL_bits EFM32 Tiny Gecko CMU AUXHFRCOCTRL + * bits + * @{ + */ + +#define CMU_AUXHFRCOCTRL_BAND_14MHZ (0<<8) +#define CMU_AUXHFRCOCTRL_BAND_11MHZ (1<<8) +#define CMU_AUXHFRCOCTRL_BAND_7MHZ (2<<8) +#define CMU_AUXHFRCOCTRL_BAND_1MHZ (3<<8) +#define CMU_AUXHFRCOCTRL_BAND_28MHZ (6<<8) +#define CMU_AUXHFRCOCTRL_BAND_21MHZ (7<<8) +/* No values defined for the field TUNING */ + +/** @} */ + +/** Bit states for the CMU_CALCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.6.7 for definitions. + * + * @defgroup EFM32TG_CMU_CALCTRL_bits EFM32 Tiny Gecko CMU CALCTRL bits + * @{ + */ + +#define CMU_CALCTRL_CONT (1<<6) +#define CMU_CALCTRL_DOWNSEL_HFCLK (0<<3) +#define CMU_CALCTRL_DOWNSEL_HFXO (1<<3) +#define CMU_CALCTRL_DOWNSEL_LFXO (2<<3) +#define CMU_CALCTRL_DOWNSEL_HFRCO (3<<3) +#define CMU_CALCTRL_DOWNSEL_LFRCO (4<<3) +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (5<<3) +#define CMU_CALCTRL_UPSEL_HFXO (0<<0) +#define CMU_CALCTRL_UPSEL_LFXO (1<<0) +#define CMU_CALCTRL_UPSEL_HFRCO (2<<0) +#define CMU_CALCTRL_UPSEL_LFRCO (3<<0) +#define CMU_CALCTRL_UPSEL_AUXHFRCO (4<<0) + +/** @} */ + +/** Bit states for the CMU_OSCENCMD register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.9 for definitions. + * + * @defgroup EFM32TG_CMU_OSCENCMD_bits EFM32 Tiny Gecko CMU OSCENCMD bits + * @{ + */ + +#define CMU_OSCENCMD_LFXODIS (1<<9) +#define CMU_OSCENCMD_LFXOEN (1<<8) +#define CMU_OSCENCMD_LFRCODIS (1<<7) +#define CMU_OSCENCMD_LFRCOEN (1<<6) +#define CMU_OSCENCMD_AUXHFRCODIS (1<<5) +#define CMU_OSCENCMD_AUXHFRCOEN (1<<4) +#define CMU_OSCENCMD_HFXODIS (1<<3) +#define CMU_OSCENCMD_HFXOEN (1<<2) +#define CMU_OSCENCMD_HFRCODIS (1<<1) +#define CMU_OSCENCMD_HFRCOEN (1<<0) + +/** @} */ + +/** Bit states for the CMU_CMD register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.10 for definitions. + * + * @defgroup EFM32TG_CMU_CMD_bits EFM32 Tiny Gecko CMU CMD bits + * @{ + */ + +#define CMU_CMD_CALSTOP (1<<4) +#define CMU_CMD_CALSTART (1<<3) +#define CMU_CMD_HFCLKSEL_HFRCO (1<<0) +#define CMU_CMD_HFCLKSEL_HFXO (2<<0) +#define CMU_CMD_HFCLKSEL_LFRCO (3<<0) +#define CMU_CMD_HFCLKSEL_LFXO (4<<0) + +/** @} */ + +/** Bit states for the CMU_LFCLKSEL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.11 for definitions. + * + * @defgroup EFM32TG_CMU_LFCLKSEL_bits EFM32 Tiny Gecko CMU LFCLKSEL bits + * @{ + */ + +#define CMU_LFCLKSEL_LFBE_DISABLED (0<<20) +#define CMU_LFCLKSEL_LFBE_ULFRCO (1<<20) +#define CMU_LFCLKSEL_LFAE_DISABLED (0<<16) +#define CMU_LFCLKSEL_LFAE_ULFRCO (1<<16) +#define CMU_LFCLKSEL_LFB_DISABLED (0<<2) +#define CMU_LFCLKSEL_LFB_LFRCO (1<<2) +#define CMU_LFCLKSEL_LFB_LFXO (2<<2) +#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2) +#define CMU_LFCLKSEL_LFA_DISABLED (0<<0) +#define CMU_LFCLKSEL_LFA_LFRCO (1<<0) +#define CMU_LFCLKSEL_LFA_LFXO (2<<0) +#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (3<<0) + +/** @} */ + +/** Bit states for the CMU_STATUS register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.12 for definitions. + * + * @defgroup EFM32TG_CMU_STATUS_bits EFM32 Tiny Gecko CMU STATUS bits + * @{ + */ + +#define CMU_STATUS_CALBSY (1<<14) +#define CMU_STATUS_LFXOSEL (1<<13) +#define CMU_STATUS_LFRCOSEL (1<<12) +#define CMU_STATUS_HFXOSEL (1<<11) +#define CMU_STATUS_HFRCOSEL (1<<10) +#define CMU_STATUS_LFXORDY (1<<9) +#define CMU_STATUS_LFXOENS (1<<8) +#define CMU_STATUS_LFRCORDY (1<<7) +#define CMU_STATUS_LFRCOENS (1<<6) +#define CMU_STATUS_AUXHFRCORDY (1<<5) +#define CMU_STATUS_AUXHFRCOENS (1<<4) +#define CMU_STATUS_HFXORDY (1<<3) +#define CMU_STATUS_HFXOENS (1<<2) +#define CMU_STATUS_HFRCORDY (1<<1) +#define CMU_STATUS_HFRCOENS (1<<0) + +/** @} */ + +/** Bit states for the CMU_HFCORECLKEN0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.17 for definitions. + * + * @defgroup EFM32TG_CMU_HFCORECLKEN0_bits EFM32 Tiny Gecko CMU HFCORECLKEN0 + * bits + * @{ + */ + +#define CMU_HFCORECLKEN0_LE (1<<2) +#define CMU_HFCORECLKEN0_DMA (1<<1) +#define CMU_HFCORECLKEN0_AES (1<<0) + +/** @} */ + +/** Bit states for the CMU_HFPERCLKEN0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.18 for definitions. + * + * @defgroup EFM32TG_CMU_HFPERCLKEN0_bits EFM32 Tiny Gecko CMU HFPERCLKEN0 bits + * @{ + */ + +#define CMU_HFPERCLKEN0_I2C0 (1<<11) +#define CMU_HFPERCLKEN0_DAC0 (1<<10) +#define CMU_HFPERCLKEN0_ADC0 (1<<9) +#define CMU_HFPERCLKEN0_PRS (1<<8) +#define CMU_HFPERCLKEN0_VCMP (1<<7) +#define CMU_HFPERCLKEN0_GPIO (1<<6) +#define CMU_HFPERCLKEN0_TIMER1 (1<<5) +#define CMU_HFPERCLKEN0_TIMER0 (1<<4) +#define CMU_HFPERCLKEN0_USART1 (1<<3) +#define CMU_HFPERCLKEN0_USART0 (1<<2) +#define CMU_HFPERCLKEN0_ACMP1 (1<<1) +#define CMU_HFPERCLKEN0_ACMP0 (1<<0) + +/** @} */ + +/** Bit states for the CMU_SYNCBUSY register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.19 for definitions. + * + * @defgroup EFM32TG_CMU_SYNCBUSY_bits EFM32 Tiny Gecko CMU SYNCBUSY bits + * @{ + */ + +#define CMU_SYNCBUSY_LFBPRESC0 (1<<6) +#define CMU_SYNCBUSY_LFBCLKEN0 (1<<4) +#define CMU_SYNCBUSY_LFAPRESC0 (1<<2) +#define CMU_SYNCBUSY_LFACLKEN0 (1<<0) + +/** @} */ + +/** Bit states for the CMU_FREEZE register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.20 for definitions. + * + * @defgroup EFM32TG_CMU_FREEZE_bits EFM32 Tiny Gecko CMU FREEZE bits + * @{ + */ + +#define CMU_FREEZE_REGFREEZE_UPDATE (0<<0) +#define CMU_FREEZE_REGFREEZE_FREEZE (1<<0) + +/** @} */ + +/** Bit states for the CMU_LFACLKEN0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.21 for definitions. + * + * @defgroup EFM32TG_CMU_LFACLKEN0_bits EFM32 Tiny Gecko CMU LFACLKEN0 bits + * @{ + */ + +#define CMU_LFACLKEN0_LCD (1<<3) +#define CMU_LFACLKEN0_LETIMER0 (1<<2) +#define CMU_LFACLKEN0_RTC (1<<1) +#define CMU_LFACLKEN0_LESENSE (1<<0) + +/** @} */ + +/** Bit states for the CMU_LFBCLKEN0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.22 for definitions. + * + * @defgroup EFM32TG_CMU_LFBCLKEN0_bits EFM32 Tiny Gecko CMU LFBCLKEN0 bits + * @{ + */ + +#define CMU_LFBCLKEN0_LEUART0 (1<<0) + +/** @} */ + +/** Bit states for the CMU_LFAPRESC0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.23 for definitions. + * + * @defgroup EFM32TG_CMU_LFAPRESC0_bits EFM32 Tiny Gecko CMU LFAPRESC0 bits + * @{ + */ + +#define CMU_LFAPRESC0_LCD_DIV16 (0<<12) +#define CMU_LFAPRESC0_LCD_DIV32 (1<<12) +#define CMU_LFAPRESC0_LCD_DIV64 (2<<12) +#define CMU_LFAPRESC0_LCD_DIV128 (3<<12) +#define CMU_LFAPRESC0_LETIMER0_DIV1 (0<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV2 (1<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV4 (2<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV8 (3<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV16 (4<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV32 (5<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV64 (6<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV128 (7<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV256 (8<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV512 (9<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (10<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (11<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (12<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (13<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (14<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (15<<8) +#define CMU_LFAPRESC0_RTC_DIV1 (0<<4) +#define CMU_LFAPRESC0_RTC_DIV2 (1<<4) +#define CMU_LFAPRESC0_RTC_DIV4 (2<<4) +#define CMU_LFAPRESC0_RTC_DIV8 (3<<4) +#define CMU_LFAPRESC0_RTC_DIV16 (4<<4) +#define CMU_LFAPRESC0_RTC_DIV32 (5<<4) +#define CMU_LFAPRESC0_RTC_DIV64 (6<<4) +#define CMU_LFAPRESC0_RTC_DIV128 (7<<4) +#define CMU_LFAPRESC0_RTC_DIV256 (8<<4) +#define CMU_LFAPRESC0_RTC_DIV512 (9<<4) +#define CMU_LFAPRESC0_RTC_DIV1024 (10<<4) +#define CMU_LFAPRESC0_RTC_DIV2048 (11<<4) +#define CMU_LFAPRESC0_RTC_DIV4096 (12<<4) +#define CMU_LFAPRESC0_RTC_DIV8192 (13<<4) +#define CMU_LFAPRESC0_RTC_DIV16384 (14<<4) +#define CMU_LFAPRESC0_RTC_DIV32768 (15<<4) +#define CMU_LFAPRESC0_LESENSE_DIV1 (0<<0) +#define CMU_LFAPRESC0_LESENSE_DIV2 (1<<0) +#define CMU_LFAPRESC0_LESENSE_DIV4 (2<<0) +#define CMU_LFAPRESC0_LESENSE_DIV8 (3<<0) + +/** @} */ + +/** Bit states for the CMU_LFBPRESC0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.24 for definitions. + * + * @defgroup EFM32TG_CMU_LFBPRESC0_bits EFM32 Tiny Gecko CMU LFBPRESC0 bits + * @{ + */ + +#define CMU_LFBPRESC0_LEUART0_DIV1 (0<<0) +#define CMU_LFBPRESC0_LEUART0_DIV2 (1<<0) +#define CMU_LFBPRESC0_LEUART0_DIV4 (2<<0) +#define CMU_LFBPRESC0_LEUART0_DIV8 (3<<0) + +/** @} */ + +/** Bit states for the CMU_PCNTCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.25 for definitions. + * + * @defgroup EFM32TG_CMU_PCNTCTRL_bits EFM32 Tiny Gecko CMU PCNTCTRL bits + * @{ + */ + +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (0<<1) +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (1<<1) +#define CMU_PCNTCTRL_PCNT0CLKEN (1<<0) + +/** @} */ + +/** Bit states for the CMU_LCDCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.26 for definitions. + * + * @defgroup EFM32TG_CMU_LCDCTRL_bits EFM32 Tiny Gecko CMU LCDCTRL bits + * @{ + */ + +#define CMU_LCDCTRL_VBFDIV_DIV1 (0<<4) +#define CMU_LCDCTRL_VBFDIV_DIV2 (1<<4) +#define CMU_LCDCTRL_VBFDIV_DIV4 (2<<4) +#define CMU_LCDCTRL_VBFDIV_DIV8 (3<<4) +#define CMU_LCDCTRL_VBFDIV_DIV16 (4<<4) +#define CMU_LCDCTRL_VBFDIV_DIV32 (5<<4) +#define CMU_LCDCTRL_VBFDIV_DIV64 (6<<4) +#define CMU_LCDCTRL_VBFDIV_DIV128 (7<<4) +#define CMU_LCDCTRL_VBOOSTEN (1<<3) +/* No values defined for the field FDIV */ + +/** @} */ + +/** Bit states for the CMU_ROUTE register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.27 for definitions. + * + * @defgroup EFM32TG_CMU_ROUTE_bits EFM32 Tiny Gecko CMU ROUTE bits + * @{ + */ + +#define CMU_ROUTE_LOCATION_LOC0 (0<<4) +#define CMU_ROUTE_LOCATION_LOC1 (1<<4) +#define CMU_ROUTE_CLKOUT1PEN (1<<1) +#define CMU_ROUTE_CLKOUT0PEN (1<<0) + +/** @} */ + +/** Values for the CMU_LOCK register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.28 for definitions. + * + * @defgroup EFM32TG_CMU_LOCK_values EFM32 Tiny Gecko CMU LOCK values + * @{ + */ + +#define CMU_LOCK_IS_UNLOCKED 0 +#define CMU_LOCK_IS_LOCKED 1 +#define CMU_LOCK_SET_LOCKED 0 +#define CMU_LOCK_SET_UNLOCKED 0x580E + +/** @} */ + +/** @} */ + + +/** @} */ #endif diff --git a/include/libopencm3/efm32/tinygecko/cmu.yaml b/include/libopencm3/efm32/tinygecko/cmu.yaml new file mode 100644 index 0000000..52906f7 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/cmu.yaml @@ -0,0 +1,437 @@ +copyright: "2012 chrysn " +license: lgpl-3+ +shortdocname: EFM32TG_CMU +longdocname: EFM32 Tiny Gecko CMU +shortname: CMU +longname: Clock Management Unit +baseref: d0034_efm32tg_reference_manual.pdf section 11 +registers_baserefext: ".4" +registers: + - name: CTRL + offset: 0x000 + definition_baserefext: ".5.1" + fields: + - name: DBGCLK + shift: 28 + values: + - {name: AUXHFRCO, value: 0} + - {name: HFCLK, value: 1} + - name: CLKOUTSEL1 + shift: 23 + length: 3 + values: &CLKOUTSEL1_values + - {name: LFRCO, value: 0} + - {name: LFXO, value: 1} + - {name: HFCLK, value: 2} + - {name: LFXOQ, value: 3} + - {name: HFXOQ, value: 4} + - {name: LFRCOQ, value: 5} + - {name: HFRCOQ, value: 6} + - {name: AUXHFRCOQ, value: 7} + - name: CLKOUTSEL0 + shift: 20 + length: 3 + values: *CLKOUTSEL1_values + - name: LFXOTIMEOUT + shift: 18 + length: 2 + values: + - {name: 8CYCLES, value: 0} + - {name: 1KCYCLES, value: 1} + - {name: 16KCYCLES, value: 2} + - {name: 32KCYCLES, value: 3} + - name: LFXOBUFCUR + shift: 17 + - name: LXFOBOOST + shift: 13 + values: + - {name: 70PCENT, value: 0} + - {name: 100PCENT, value: 1} + - name: LFXOMODE + shift: 11 + length: 2 + values: + - {name: XTAL, value: 0} + - {name: BUFEXTCLK, value: 1} + - {name: DIGEXTCLK, value: 2} + - name: HFXOTIMEOUT + shift: 9 + length: 2 + values: + - {name: 8CYCLES, value: 0} + - {name: 256CYCLES, value: 1} + - {name: 1KCYCLES, value: 2} + - {name: 16KCYCLES, value: 3} + - name: HFXOGLITCHDETEN + shift: 7 + - name: HFXOBUFCUR + shift: 5 + length: 2 + type: undocumented + - name: HFXOBOOST + shift: 2 + length: 2 + values: + - {name: 50PCENT, value: 0} + - {name: 70PCENT, value: 1} + - {name: 80PCENT, value: 2} + - {name: 100PCENT, value: 3} + - name: HFXOMODE + shift: 0 + length: 2 + values: + - {name: XTAL, value: 0} + - {name: BUFEXTCLK, value: 1} + - {name: DIGEXTCLK, value: 2} + - name: HFCORECLKDIV + offset: 0x004 + definition_baserefext: ".5.2" + values: &HFCORECLKDIV_values + - {value: 0, name: HFCLK} + - {value: 1, name: HFCLK2} + - {value: 2, name: HFCLK4} + - {value: 3, name: HFCLK8} + - {value: 4, name: HFCLK16} + - {value: 5, name: HFCLK32} + - {value: 6, name: HFCLK64} + - {value: 7, name: HFCLK128} + - {value: 8, name: HFCLK256} + - {value: 9, name: HFCLK512} + - name: HFPERCLKDIV + offset: 0x008 + definition_baserefext: ".5.3" + fields: + - name: HFPERCLKEN + shift: 8 + - name: HFPERCLKDIV + shift: 0 + length: 3 + # not using generically named values here due to different register structure + values: *HFCORECLKDIV_values + - name: HFRCOCTRL + offset: 0x00c + definition_baserefext: ".5.4" + fields: + - name: SUDELAY + shift: 12 + length: 5 + type: undocumented + - name: BAND + shift: 8 + length: 3 + values: + - {value: 0, name: 1MHZ} + - {value: 1, name: 7MHZ} + - {value: 2, name: 11MHZ} + - {value: 3, name: 14MHZ} + - {value: 4, name: 21MHZ} + - {value: 5, name: 28MHZ} + - name: TUNING + shift: 0 + length: 8 + type: uint + - name: LFRCOCTRL + offset: 0x010 + definition_baserefext: ".5.5" + length: 7 + - name: AUXHFRCOCTRL + offset: 0x014 + definition_baserefext: ".5.6" + fields: + - name: BAND + shift: 8 + length: 3 + values: + - {value: 0, name: 14MHZ} + - {value: 1, name: 11MHZ} + - {value: 2, name: 7MHZ} + - {value: 3, name: 1MHZ} + - {value: 6, name: 28MHZ} + - {value: 7, name: 21MHZ} + - name: TUNING + shift: 0 + length: 8 + type: uint + - name: CALCTRL + offset: 0x018 + definition_baserefext: ".6.7" + fields: + - name: CONT + shift: 6 + - name: DOWNSEL + shift: 3 + length: 3 + values: + - {value: 0, name: HFCLK} + - {value: 1, name: HFXO} + - {value: 2, name: LFXO} + - {value: 3, name: HFRCO} + - {value: 4, name: LFRCO} + - {value: 5, name: AUXHFRCO} + - name: UPSEL + shift: 0 + length: 3 + values: + - {value: 0, name: HFXO} + - {value: 1, name: LFXO} + - {value: 2, name: HFRCO} + - {value: 3, name: LFRCO} + - {value: 4, name: AUXHFRCO} + - name: CALCNT + offset: 0x01c + definition_baserefext: ".5.8" + length: 19 + - name: OSCENCMD + offset: 0x020 + definition_baserefext: ".5.9" + fields: + - {name: LFXODIS, shift: 9} + - {name: LFXOEN, shift: 8} + - {name: LFRCODIS, shift: 7} + - {name: LFRCOEN, shift: 6} + - {name: AUXHFRCODIS, shift: 5} + - {name: AUXHFRCOEN, shift: 4} + - {name: HFXODIS, shift: 3} + - {name: HFXOEN, shift: 2} + - {name: HFRCODIS, shift: 1} + - {name: HFRCOEN, shift: 0} + - name: CMD + offset: 0x024 + definition_baserefext: ".5.10" + fields: + - name: CALSTOP + shift: 4 + - name: CALSTART + shift: 3 + - name: HFCLKSEL + shift: 0 + length: 3 + values: + - {value: 1, name: HFRCO} + - {value: 2, name: HFXO} + - {value: 3, name: LFRCO} + - {value: 4, name: LFXO} + - name: LFCLKSEL + offset: 0x028 + definition_baserefext: ".5.11" + fields: + - name: LFBE + shift: 20 + values: &LFCLKSEL_LFBE + - {value: 0, name: DISABLED} + - {value: 1, name: ULFRCO} + - name: LFAE + shift: 16 + values: *LFCLKSEL_LFBE + - name: LFB + shift: 2 + length: 2 + values: &LFCLKSEL_LFB + - {value: 0, name: DISABLED} + - {value: 1, name: LFRCO} + - {value: 2, name: LFXO} + - {value: 3, name: HFCORECLKLEDIV2} + - name: LFA + shift: 0 + length: 2 + values: *LFCLKSEL_LFB + - name: STATUS + offset: 0x02c + definition_baserefext: ".5.12" + fields: + - {name: CALBSY, shift: 14} + - {name: LFXOSEL, shift: 13} + - {name: LFRCOSEL, shift: 12} + - {name: HFXOSEL, shift: 11} + - {name: HFRCOSEL, shift: 10} + - {name: LFXORDY, shift: 9} + - {name: LFXOENS, shift: 8} + - {name: LFRCORDY, shift: 7} + - {name: LFRCOENS, shift: 6} + - {name: AUXHFRCORDY, shift: 5} + - {name: AUXHFRCOENS, shift: 4} + - {name: HFXORDY, shift: 3} + - {name: HFXOENS, shift: 2} + - {name: HFRCORDY, shift: 1} + - {name: HFRCOENS, shift: 0} + - name: IF + offset: 0x030 + definition_baserefext: ".5.13" + #fields: I + - name: IFS + offset: 0x034 + definition_baserefext: ".5.14" + #fields: I + - name: IFC + offset: 0x038 + definition_baserefext: ".5.15" + #fields: I + - name: IEN + offset: 0x03c + definition_baserefext: ".5.16" + #fields: I + - name: HFCORECLKEN0 + offset: 0x040 + definition_baserefext: ".5.17" + fields: + - {name: LE, shift: 2} + - {name: DMA, shift: 1} + - {name: AES, shift: 0} + - name: HFPERCLKEN0 + offset: 0x044 + definition_baserefext: ".5.18" + fields: + - {name: I2C0, shift: 11} + - {name: DAC0, shift: 10} + - {name: ADC0, shift: 9} + - {name: PRS, shift: 8} + - {name: VCMP, shift: 7} + - {name: GPIO, shift: 6} + - {name: TIMER1, shift: 5} + - {name: TIMER0, shift: 4} + - {name: USART1, shift: 3} + - {name: USART0, shift: 2} + - {name: ACMP1, shift: 1} + - {name: ACMP0, shift: 0} + - name: SYNCBUSY + offset: 0x050 + definition_baserefext: ".5.19" + fields: + - {name: LFBPRESC0, shift: 6} + - {name: LFBCLKEN0, shift: 4} + - {name: LFAPRESC0, shift: 2} + - {name: LFACLKEN0, shift: 0} + - name: FREEZE + offset: 0x054 + definition_baserefext: ".5.20" + fields: + - name: REGFREEZE + shift: 0 + values: + - {value: 0, name: UPDATE} + - {value: 1, name: FREEZE} + - name: LFACLKEN0 + offset: 0x058 + definition_baserefext: ".5.21" + fields: + - {name: LCD, shift: 3} + - {name: LETIMER0, shift: 2} + - {name: RTC, shift: 1} + - {name: LESENSE, shift: 0} + - name: LFBCLKEN0 + offset: 0x060 + definition_baserefext: ".5.22" + fields: + - {name: LEUART0, shift: 0} + - name: LFAPRESC0 + offset: 0x068 + definition_baserefext: ".5.23" + fields: + - name: LCD + shift: 12 + length: 2 + values: + - {value: 0, name: DIV16} + - {value: 1, name: DIV32} + - {value: 2, name: DIV64} + - {value: 3, name: DIV128} + - name: LETIMER0 + shift: 8 + length: 4 + values: &LFAPRESC0_LETIMER0_values + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - {value: 4, name: DIV16} + - {value: 5, name: DIV32} + - {value: 6, name: DIV64} + - {value: 7, name: DIV128} + - {value: 8, name: DIV256} + - {value: 9, name: DIV512} + - {value: 10, name: DIV1024} + - {value: 11, name: DIV2048} + - {value: 12, name: DIV4096} + - {value: 13, name: DIV8192} + - {value: 14, name: DIV16384} + - {value: 15, name: DIV32768} + - name: RTC + shift: 4 + length: 4 + values: *LFAPRESC0_LETIMER0_values + - name: LESENSE + shift: 0 + length: 2 + values: + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - name: LFBPRESC0 + offset: 0x070 + definition_baserefext: ".5.24" + fields: + - name: LEUART0 + shift: 0 + length: 2 + values: + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - name: PCNTCTRL + offset: 0x078 + definition_baserefext: ".5.25" + fields: + - name: PCNT0CLKSEL + shift: 1 + values: + - {value: 0, name: LFACLK} + - {value: 1, name: PCNT0S0} + - name: PCNT0CLKEN + shift: 0 + - name: LCDCTRL + offset: 0x07c + definition_baserefext: ".5.26" + fields: + - name: VBFDIV + shift: 4 + length: 3 + values: + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - {value: 4, name: DIV16} + - {value: 5, name: DIV32} + - {value: 6, name: DIV64} + - {value: 7, name: DIV128} + - name: VBOOSTEN + shift: 3 + - name: FDIV + shift: 0 + length: 3 + type: uint + - name: ROUTE + offset: 0x080 + definition_baserefext: ".5.27" + fields: + - name: LOCATION + shift: 4 + length: 3 + values: + - {value: 0, name: LOC0} + - {value: 1, name: LOC1} + - name: CLKOUT1PEN + shift: 1 + - name: CLKOUT0PEN + shift: 0 + - name: LOCK + offset: 0x084 + definition_baserefext: ".5.28" + length: 16 + values: + - {name: IS_UNLOCKED, value: 0} + - {name: IS_LOCKED, value: 1} + - {name: SET_LOCKED, value: 0} + - {name: SET_UNLOCKED, value: "0x580E"} diff --git a/include/libopencm3/efm32/tinygecko/emu.convenienceheaders b/include/libopencm3/efm32/tinygecko/emu.convenienceheaders new file mode 100644 index 0000000..4be5b30 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/emu.convenienceheaders @@ -0,0 +1,18 @@ +/** EMU convenience functions + * + * These functions can be used to send the chip to low energy modes. + * + * @todo Implement other sleep modes than EM1. Implement WFI vs WFE waits. + * + * @defgroup EFM32TG_EMU_convenience EFM32 Tiny Gecko EMU convenience functions + * @{ + */ + +/** Put the system into EM1 low energy mode. */ +static void emu_sleep_em1(void) +{ + /* FIXME: set SLEEPDEEP to 0 */ + __asm__("wfi"); +} + +/** @} */ diff --git a/include/libopencm3/efm32/tinygecko/emu.h b/include/libopencm3/efm32/tinygecko/emu.h index 307d1d6..0a97679 100644 --- a/include/libopencm3/efm32/tinygecko/emu.h +++ b/include/libopencm3/efm32/tinygecko/emu.h @@ -48,9 +48,9 @@ * @{ */ -#define EMU_CTRL MMIO32(EMU_BASE + 0x000) /**< @see EFM32TG_EMU_CTRL_bits */ -#define EMU_LOCK MMIO32(EMU_BASE + 0x008) /**< @see EFM32TG_EMU_LOCK_values */ -#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) /**< @see EFM32TG_EMU_AUXCTRL_bits */ +#define EMU_CTRL MMIO32(EMU_BASE + 0x000) /**< @see EFM32TG_EMU_CTRL_bits */ +#define EMU_LOCK MMIO32(EMU_BASE + 0x008) /**< @see EFM32TG_EMU_LOCK_values */ +#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) /**< @see EFM32TG_EMU_AUXCTRL_bits */ /** @} */ @@ -63,39 +63,39 @@ * @{ */ -#define EMU_CTRL_EM4CTRL_TWO (2<<2) -#define EMU_CTRL_EM4CTRL_THREE (3<<2) -#define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */ -#define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */ +#define EMU_CTRL_EM4CTRL_TWO (2<<2) +#define EMU_CTRL_EM4CTRL_THREE (3<<2) +#define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */ +#define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */ /** @} */ /** Values for the EMU_LOCK register * - * See d0034_efm32tg_reference_manual.pdf section 10.5.2. There seems not to be - * another mention of it. + * See d0034_efm32tg_reference_manual.pdf section 10.5.2 for definitions. There + * seems not to be another mention of it. * * @defgroup EFM32TG_EMU_LOCK_values EFM32 Tiny Gecko EMU LOCK values * @{ */ -#define EMU_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */ -#define EMU_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */ -#define EMU_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock the EMU */ -#define EMU_LOCK_SET_UNLOCKED 0xade8 /**< Write this to the LOCK register to unlock the EMU */ +#define EMU_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */ +#define EMU_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */ +#define EMU_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock the EMU */ +#define EMU_LOCK_SET_UNLOCKED 0xade8 /**< Write this to the LOCK register to unlock the EMU */ /** @} */ /** Bit states for the EMU_AUXCTRL register * - * See d0034_efm32tg_reference_manual.pdf section 10.5.3 for definition, and + * See d0034_efm32tg_reference_manual.pdf section 10.5.3 for definitions, and * 9.5.3 for details. * * @defgroup EFM32TG_EMU_AUXCTRL_bits EFM32 Tiny Gecko EMU AUXCTRL bits * @{ */ -#define EMU_AUXCTRL_HRCCLR (1<<0) +#define EMU_AUXCTRL_HRCCLR (1<<0) /** @} */ diff --git a/include/libopencm3/efm32/tinygecko/emu.yaml b/include/libopencm3/efm32/tinygecko/emu.yaml new file mode 100644 index 0000000..376c76c --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/emu.yaml @@ -0,0 +1,50 @@ +copyright: "2012 chrysn " +license: lgpl-3+ +shortdocname: EFM32TG_EMU +longdocname: EFM32 Tiny Gecko EMU +shortname: EMU +longname: Energy Management Unit +baseref: d0034_efm32tg_reference_manual.pdf section 10 +registers_baserefext: ".4" +registers: + - name: CTRL + definition_baserefext: .5.1 + details: ", and 10.3.2 for details (especially on why EM4CTRL_TWO and _THREE are defined)." + offset: 0x000 + fields: + - name: EM4CTRL + shift: 2 + length: 2 + values: + - {name: TWO, value: 2} + - {name: THREE, value: 3} + - name: EM2BLOCK + shift: 1 + doc: When this bit is set, no mode lower than EM1 will be entered + - name: EMVREG + shift: 0 + doc: When this bit is set, the voltage regulator will stay on in modes lower than EM1 + - name: LOCK + definition_baserefext: .5.2 + details: ". There seems not to be another mention of it." + offset: 0x008 + values: + - name: IS_UNLOCKED + value: 0 + doc: When the LOCK register reads as this value, it is open + - name: IS_LOCKED + value: 1 + doc: When the LOCK register reads as this value, it is locked + - name: SET_LOCKED + value: 0 + doc: Write this to the LOCK register to lock the EMU + - name: SET_UNLOCKED + value: "0xade8" + doc: Write this to the LOCK register to unlock the EMU + - name: AUXCTRL + definition_baserefext: .5.3 + details: ", and 9.5.3 for details." + offset: 0x024 + fields: + - name: HRCCLR + shift: 0 diff --git a/include/libopencm3/efm32/tinygecko/generate-license.yaml b/include/libopencm3/efm32/tinygecko/generate-license.yaml new file mode 100644 index 0000000..baeef88 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/generate-license.yaml @@ -0,0 +1,19 @@ +"lgpl-3+": | + /* + * This file is part of the {projectname} project. + * + * Copyright (C) {copyright} + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ diff --git a/include/libopencm3/efm32/tinygecko/generate.py b/include/libopencm3/efm32/tinygecko/generate.py new file mode 100644 index 0000000..8bd8184 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/generate.py @@ -0,0 +1,112 @@ +#!/usr/bin/env python + +import yaml +import logging +import textwrap + +def commentblock(*textblocks, **formatargs): + ret = [] + ret.extend(textwrap.wrap(textblocks[0].format(**formatargs), 80, initial_indent="/** ", subsequent_indent=" * ")) + last_block_was_at = textblocks[0].startswith('@') + for b in textblocks[1:]: + if not (last_block_was_at and b.startswith('@')): + ret.append(" *") + # FIXME: some blocks don't like being wrapped, eg @defgroup + ret.extend(textwrap.wrap(b.format(**formatargs), 80, initial_indent=" * ", subsequent_indent=" * ")) + last_block_was_at = b.startswith('@') + return "\n".join(ret) + "\n */\n" + +def yaml2h(filenamebase): + headername = "%s.h"%filenamebase + yamlname = "%s.yaml"%filenamebase + conveniencename = "%s.convenienceheaders"%filenamebase + + logging.info("Generating %s from %s", headername, yamlname) + + data = yaml.load(open(yamlname)) + # some defaults + data.setdefault("projectname", "libopencm3") + data.setdefault("includeguard", "LIBOPENCM3_EFM32_TINYGECKO_%s_H"%data['shortname']) + + with open(headername, 'w') as outfile: + def wc(*args, **kwargs): # wrap "outfile" and "data" (as default) arguments -- i'm a lazy typer + final_kwargs = data.copy() + final_kwargs.update(kwargs) + outfile.write(commentblock(*args, **final_kwargs)) + def wc_close(): + outfile.write("/** @} */\n") + def nl(): outfile.write("\n") + def define(key, value, comment=None): + outfile.write("#define ") + outfile.write(key) + outfile.write(" "*max(24-len(key), 1)) + outfile.write(str(value)) + if comment is not None: + outfile.write(" /**< %s */"%comment) + nl() + + outfile.write(licensedata[data['license']].format(**data)) + nl() + wc("@file", "@see {shortdocname}") + nl() + wc("Definitions for the {shortname} subsystem ({longname}).", "This corresponds to the description in {baseref}.", "@defgroup {shortdocname} {longdocname}", "@{{") + nl() + outfile.write("#ifndef {includeguard}\n#define {includeguard}\n".format(**data)) + nl() + outfile.write("#include \n#include \n") + nl() + wc("Register definitions and register value definitions for the {shortname} subsystem", "@defgroup {shortdocname}_regsandvals {longdocname} registers and values", "@{{") + nl() + + regs = data['registers'] + wc("These definitions reflect {baseref}{registers_baserefext}", "@defgroup {shortdocname}_registers {longdocname} registers", "@{{") + nl() + for regdata in regs: + define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], regdata['name'], 'values' if 'values' in regdata else 'bits')) + nl() + wc_close() # close register definitions + nl() + for regdata in regs: + has_bits = "fields" in regdata + has_values = "values" in regdata + if not has_bits and not has_values: + continue + + wc("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values"), "See {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."), '@defgroup {shortdocname}_{name}_%s {longdocname} {name} %s'%(('bits' if has_bits else 'values',)*2), '@{{', **regdata) + nl() + + if has_bits: + for field in regdata['fields']: + #shiftdefine = "_%s_%s_%s_shift"%(shortname, regdata['name'], field['name']) + #define(shiftdefine, field['shift']) + if "values" in field: + for value in field.get("values"): + define("%s_%s_%s_%s"%(data['shortname'], regdata['name'], field['name'], value['name']), "(%s<<%s)"%(value['value'], field['shift']), value.get('doc', None)) + else: + if field.get('length', 1) == 1: + define("%s_%s_%s"%(data['shortname'], regdata['name'], field['name']), "(1<<%s)"%field['shift'], field.get('doc', None)) + else: + # FIXME: this should require the 'type' parameter to be set on this field + outfile.write("/* No values defined for the field %s */\n"%field['name']) + # FIXME: define mask + else: + for value in regdata['values']: + define("%s_%s_%s"%(data['shortname'], regdata['name'], value['name']), value['value'], value.get('doc', None)) + + nl() + wc_close() + nl() + wc_close() # close registers and values + nl() + + outfile.write(open(conveniencename).read()) + + nl() + wc_close() # close convenience + nl() + outfile.write("#endif\n") + +if __name__ == "__main__": + licensedata = yaml.load(open("generate-license.yaml")) + for basename in yaml.load(open('generate.yaml')): + yaml2h(basename) diff --git a/include/libopencm3/efm32/tinygecko/generate.yaml b/include/libopencm3/efm32/tinygecko/generate.yaml new file mode 100644 index 0000000..878d0ad --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/generate.yaml @@ -0,0 +1,2 @@ +- emu +- cmu -- cgit v1.2.3 From bc1bff477ba038fff46a4c4fd63856475faf0352 Mon Sep 17 00:00:00 2001 From: chrysn Date: Sun, 4 Mar 2012 14:39:40 +0100 Subject: efm32: shortened doxygen names and grouped them per chip family --- include/libopencm3/efm32/tinygecko/README.dox | 14 ++++++ include/libopencm3/efm32/tinygecko/cmu.h | 54 +++++++++++----------- include/libopencm3/efm32/tinygecko/cmu.yaml | 2 +- .../efm32/tinygecko/emu.convenienceheaders | 2 +- include/libopencm3/efm32/tinygecko/emu.h | 15 +++--- include/libopencm3/efm32/tinygecko/emu.yaml | 2 +- include/libopencm3/efm32/tinygecko/generate.py | 17 ++++--- include/libopencm3/efm32/tinygecko/gpio.h | 33 ++++++------- 8 files changed, 79 insertions(+), 60 deletions(-) create mode 100644 include/libopencm3/efm32/tinygecko/README.dox (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/README.dox b/include/libopencm3/efm32/tinygecko/README.dox new file mode 100644 index 0000000..04da755 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/README.dox @@ -0,0 +1,14 @@ +/** + +@brief EFM32 Tiny Gecko headers + +This directory contains all headers specific to the Tiny Gecko family of the +Energy Micro EFM32 series. + +The individual peripherials described here all include hints at where the +information was taken from, but usually it stems from +d0034_efm32tg_reference_manual.pdf. + +@defgroup EFM32TG EFM32 Tiny Gecko + +*/ diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index 0914561..5926cb0 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -26,7 +26,8 @@ * This corresponds to the description in d0034_efm32tg_reference_manual.pdf * section 11. * - * @defgroup EFM32TG_CMU EFM32 Tiny Gecko CMU + * @ingroup EFM32TG + * @defgroup EFM32TG_CMU CMU (Clock Management Unit) * @{ */ @@ -38,13 +39,13 @@ /** Register definitions and register value definitions for the CMU subsystem * - * @defgroup EFM32TG_CMU_regsandvals EFM32 Tiny Gecko CMU registers and values + * @defgroup EFM32TG_CMU_regsandvals CMU registers and values * @{ */ /** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4 * - * @defgroup EFM32TG_CMU_registers EFM32 Tiny Gecko CMU registers + * @defgroup EFM32TG_CMU_registers CMU registers * @{ */ @@ -83,7 +84,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.1 for definitions. * - * @defgroup EFM32TG_CMU_CTRL_bits EFM32 Tiny Gecko CMU CTRL bits + * @defgroup EFM32TG_CMU_CTRL_bits CMU CTRL bits * @{ */ @@ -135,8 +136,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.2 for definitions. * - * @defgroup EFM32TG_CMU_HFCORECLKDIV_values EFM32 Tiny Gecko CMU HFCORECLKDIV - * values + * @defgroup EFM32TG_CMU_HFCORECLKDIV_values CMU HFCORECLKDIV values * @{ */ @@ -157,7 +157,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.3 for definitions. * - * @defgroup EFM32TG_CMU_HFPERCLKDIV_bits EFM32 Tiny Gecko CMU HFPERCLKDIV bits + * @defgroup EFM32TG_CMU_HFPERCLKDIV_bits CMU HFPERCLKDIV bits * @{ */ @@ -179,7 +179,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.4 for definitions. * - * @defgroup EFM32TG_CMU_HFRCOCTRL_bits EFM32 Tiny Gecko CMU HFRCOCTRL bits + * @defgroup EFM32TG_CMU_HFRCOCTRL_bits CMU HFRCOCTRL bits * @{ */ @@ -198,8 +198,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.6 for definitions. * - * @defgroup EFM32TG_CMU_AUXHFRCOCTRL_bits EFM32 Tiny Gecko CMU AUXHFRCOCTRL - * bits + * @defgroup EFM32TG_CMU_AUXHFRCOCTRL_bits CMU AUXHFRCOCTRL bits * @{ */ @@ -217,7 +216,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.6.7 for definitions. * - * @defgroup EFM32TG_CMU_CALCTRL_bits EFM32 Tiny Gecko CMU CALCTRL bits + * @defgroup EFM32TG_CMU_CALCTRL_bits CMU CALCTRL bits * @{ */ @@ -240,7 +239,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.9 for definitions. * - * @defgroup EFM32TG_CMU_OSCENCMD_bits EFM32 Tiny Gecko CMU OSCENCMD bits + * @defgroup EFM32TG_CMU_OSCENCMD_bits CMU OSCENCMD bits * @{ */ @@ -261,7 +260,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.10 for definitions. * - * @defgroup EFM32TG_CMU_CMD_bits EFM32 Tiny Gecko CMU CMD bits + * @defgroup EFM32TG_CMU_CMD_bits CMU CMD bits * @{ */ @@ -278,7 +277,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.11 for definitions. * - * @defgroup EFM32TG_CMU_LFCLKSEL_bits EFM32 Tiny Gecko CMU LFCLKSEL bits + * @defgroup EFM32TG_CMU_LFCLKSEL_bits CMU LFCLKSEL bits * @{ */ @@ -301,7 +300,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.12 for definitions. * - * @defgroup EFM32TG_CMU_STATUS_bits EFM32 Tiny Gecko CMU STATUS bits + * @defgroup EFM32TG_CMU_STATUS_bits CMU STATUS bits * @{ */ @@ -327,8 +326,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.17 for definitions. * - * @defgroup EFM32TG_CMU_HFCORECLKEN0_bits EFM32 Tiny Gecko CMU HFCORECLKEN0 - * bits + * @defgroup EFM32TG_CMU_HFCORECLKEN0_bits CMU HFCORECLKEN0 bits * @{ */ @@ -342,7 +340,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.18 for definitions. * - * @defgroup EFM32TG_CMU_HFPERCLKEN0_bits EFM32 Tiny Gecko CMU HFPERCLKEN0 bits + * @defgroup EFM32TG_CMU_HFPERCLKEN0_bits CMU HFPERCLKEN0 bits * @{ */ @@ -365,7 +363,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.19 for definitions. * - * @defgroup EFM32TG_CMU_SYNCBUSY_bits EFM32 Tiny Gecko CMU SYNCBUSY bits + * @defgroup EFM32TG_CMU_SYNCBUSY_bits CMU SYNCBUSY bits * @{ */ @@ -380,7 +378,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.20 for definitions. * - * @defgroup EFM32TG_CMU_FREEZE_bits EFM32 Tiny Gecko CMU FREEZE bits + * @defgroup EFM32TG_CMU_FREEZE_bits CMU FREEZE bits * @{ */ @@ -393,7 +391,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.21 for definitions. * - * @defgroup EFM32TG_CMU_LFACLKEN0_bits EFM32 Tiny Gecko CMU LFACLKEN0 bits + * @defgroup EFM32TG_CMU_LFACLKEN0_bits CMU LFACLKEN0 bits * @{ */ @@ -408,7 +406,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.22 for definitions. * - * @defgroup EFM32TG_CMU_LFBCLKEN0_bits EFM32 Tiny Gecko CMU LFBCLKEN0 bits + * @defgroup EFM32TG_CMU_LFBCLKEN0_bits CMU LFBCLKEN0 bits * @{ */ @@ -420,7 +418,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.23 for definitions. * - * @defgroup EFM32TG_CMU_LFAPRESC0_bits EFM32 Tiny Gecko CMU LFAPRESC0 bits + * @defgroup EFM32TG_CMU_LFAPRESC0_bits CMU LFAPRESC0 bits * @{ */ @@ -471,7 +469,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.24 for definitions. * - * @defgroup EFM32TG_CMU_LFBPRESC0_bits EFM32 Tiny Gecko CMU LFBPRESC0 bits + * @defgroup EFM32TG_CMU_LFBPRESC0_bits CMU LFBPRESC0 bits * @{ */ @@ -486,7 +484,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.25 for definitions. * - * @defgroup EFM32TG_CMU_PCNTCTRL_bits EFM32 Tiny Gecko CMU PCNTCTRL bits + * @defgroup EFM32TG_CMU_PCNTCTRL_bits CMU PCNTCTRL bits * @{ */ @@ -500,7 +498,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.26 for definitions. * - * @defgroup EFM32TG_CMU_LCDCTRL_bits EFM32 Tiny Gecko CMU LCDCTRL bits + * @defgroup EFM32TG_CMU_LCDCTRL_bits CMU LCDCTRL bits * @{ */ @@ -521,7 +519,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.27 for definitions. * - * @defgroup EFM32TG_CMU_ROUTE_bits EFM32 Tiny Gecko CMU ROUTE bits + * @defgroup EFM32TG_CMU_ROUTE_bits CMU ROUTE bits * @{ */ @@ -536,7 +534,7 @@ * * See d0034_efm32tg_reference_manual.pdf section 11.5.28 for definitions. * - * @defgroup EFM32TG_CMU_LOCK_values EFM32 Tiny Gecko CMU LOCK values + * @defgroup EFM32TG_CMU_LOCK_values CMU LOCK values * @{ */ diff --git a/include/libopencm3/efm32/tinygecko/cmu.yaml b/include/libopencm3/efm32/tinygecko/cmu.yaml index 52906f7..0229de1 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.yaml +++ b/include/libopencm3/efm32/tinygecko/cmu.yaml @@ -1,7 +1,7 @@ copyright: "2012 chrysn " license: lgpl-3+ +ingroup: EFM32TG shortdocname: EFM32TG_CMU -longdocname: EFM32 Tiny Gecko CMU shortname: CMU longname: Clock Management Unit baseref: d0034_efm32tg_reference_manual.pdf section 11 diff --git a/include/libopencm3/efm32/tinygecko/emu.convenienceheaders b/include/libopencm3/efm32/tinygecko/emu.convenienceheaders index 4be5b30..7d5893d 100644 --- a/include/libopencm3/efm32/tinygecko/emu.convenienceheaders +++ b/include/libopencm3/efm32/tinygecko/emu.convenienceheaders @@ -4,7 +4,7 @@ * * @todo Implement other sleep modes than EM1. Implement WFI vs WFE waits. * - * @defgroup EFM32TG_EMU_convenience EFM32 Tiny Gecko EMU convenience functions + * @defgroup EFM32TG_EMU_convenience EMU convenience functions * @{ */ diff --git a/include/libopencm3/efm32/tinygecko/emu.h b/include/libopencm3/efm32/tinygecko/emu.h index 0a97679..31f4241 100644 --- a/include/libopencm3/efm32/tinygecko/emu.h +++ b/include/libopencm3/efm32/tinygecko/emu.h @@ -26,7 +26,8 @@ * This corresponds to the description in d0034_efm32tg_reference_manual.pdf * section 10. * - * @defgroup EFM32TG_EMU EFM32 Tiny Gecko EMU + * @ingroup EFM32TG + * @defgroup EFM32TG_EMU EMU (Energy Management Unit) * @{ */ @@ -38,13 +39,13 @@ /** Register definitions and register value definitions for the EMU subsystem * - * @defgroup EFM32TG_EMU_regsandvals EFM32 Tiny Gecko EMU registers and values + * @defgroup EFM32TG_EMU_regsandvals EMU registers and values * @{ */ /** These definitions reflect d0034_efm32tg_reference_manual.pdf section 10.4 * - * @defgroup EFM32TG_EMU_registers EFM32 Tiny Gecko EMU registers + * @defgroup EFM32TG_EMU_registers EMU registers * @{ */ @@ -59,7 +60,7 @@ * See d0034_efm32tg_reference_manual.pdf section 10.5.1 for definitions, and * 10.3.2 for details (especially on why EM4CTRL_TWO and _THREE are defined). * - * @defgroup EFM32TG_EMU_CTRL_bits EFM32 Tiny Gecko EMU CTRL bits + * @defgroup EFM32TG_EMU_CTRL_bits EMU CTRL bits * @{ */ @@ -75,7 +76,7 @@ * See d0034_efm32tg_reference_manual.pdf section 10.5.2 for definitions. There * seems not to be another mention of it. * - * @defgroup EFM32TG_EMU_LOCK_values EFM32 Tiny Gecko EMU LOCK values + * @defgroup EFM32TG_EMU_LOCK_values EMU LOCK values * @{ */ @@ -91,7 +92,7 @@ * See d0034_efm32tg_reference_manual.pdf section 10.5.3 for definitions, and * 9.5.3 for details. * - * @defgroup EFM32TG_EMU_AUXCTRL_bits EFM32 Tiny Gecko EMU AUXCTRL bits + * @defgroup EFM32TG_EMU_AUXCTRL_bits EMU AUXCTRL bits * @{ */ @@ -107,7 +108,7 @@ * * @todo Implement other sleep modes than EM1. Implement WFI vs WFE waits. * - * @defgroup EFM32TG_EMU_convenience EFM32 Tiny Gecko EMU convenience functions + * @defgroup EFM32TG_EMU_convenience EMU convenience functions * @{ */ diff --git a/include/libopencm3/efm32/tinygecko/emu.yaml b/include/libopencm3/efm32/tinygecko/emu.yaml index 376c76c..4e0b30e 100644 --- a/include/libopencm3/efm32/tinygecko/emu.yaml +++ b/include/libopencm3/efm32/tinygecko/emu.yaml @@ -1,7 +1,7 @@ copyright: "2012 chrysn " license: lgpl-3+ +ingroup: EFM32TG shortdocname: EFM32TG_EMU -longdocname: EFM32 Tiny Gecko EMU shortname: EMU longname: Energy Management Unit baseref: d0034_efm32tg_reference_manual.pdf section 10 diff --git a/include/libopencm3/efm32/tinygecko/generate.py b/include/libopencm3/efm32/tinygecko/generate.py index 8bd8184..96407b5 100644 --- a/include/libopencm3/efm32/tinygecko/generate.py +++ b/include/libopencm3/efm32/tinygecko/generate.py @@ -6,13 +6,18 @@ import textwrap def commentblock(*textblocks, **formatargs): ret = [] + nowrapcommands = set("@defgroup") ret.extend(textwrap.wrap(textblocks[0].format(**formatargs), 80, initial_indent="/** ", subsequent_indent=" * ")) last_block_was_at = textblocks[0].startswith('@') for b in textblocks[1:]: + formatted = b.format(**formatargs) + if not (last_block_was_at and b.startswith('@')): ret.append(" *") - # FIXME: some blocks don't like being wrapped, eg @defgroup - ret.extend(textwrap.wrap(b.format(**formatargs), 80, initial_indent=" * ", subsequent_indent=" * ")) + if any(b.startswith(c) for c in nowrapcommands): + ret.append(" * " + formatted) + else: + ret.extend(textwrap.wrap(formatted, 80, initial_indent=" * ", subsequent_indent=" * ")) last_block_was_at = b.startswith('@') return "\n".join(ret) + "\n */\n" @@ -49,17 +54,17 @@ def yaml2h(filenamebase): nl() wc("@file", "@see {shortdocname}") nl() - wc("Definitions for the {shortname} subsystem ({longname}).", "This corresponds to the description in {baseref}.", "@defgroup {shortdocname} {longdocname}", "@{{") + wc("Definitions for the {shortname} subsystem ({longname}).", "This corresponds to the description in {baseref}.", "@ingroup {ingroup}", "@defgroup {shortdocname} {shortname} ({longname})", "@{{") nl() outfile.write("#ifndef {includeguard}\n#define {includeguard}\n".format(**data)) nl() outfile.write("#include \n#include \n") nl() - wc("Register definitions and register value definitions for the {shortname} subsystem", "@defgroup {shortdocname}_regsandvals {longdocname} registers and values", "@{{") + wc("Register definitions and register value definitions for the {shortname} subsystem", "@defgroup {shortdocname}_regsandvals {shortname} registers and values", "@{{") nl() regs = data['registers'] - wc("These definitions reflect {baseref}{registers_baserefext}", "@defgroup {shortdocname}_registers {longdocname} registers", "@{{") + wc("These definitions reflect {baseref}{registers_baserefext}", "@defgroup {shortdocname}_registers {shortname} registers", "@{{") nl() for regdata in regs: define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], regdata['name'], 'values' if 'values' in regdata else 'bits')) @@ -72,7 +77,7 @@ def yaml2h(filenamebase): if not has_bits and not has_values: continue - wc("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values"), "See {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."), '@defgroup {shortdocname}_{name}_%s {longdocname} {name} %s'%(('bits' if has_bits else 'values',)*2), '@{{', **regdata) + wc("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values"), "See {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."), '@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values',)*2), '@{{', **regdata) nl() if has_bits: diff --git a/include/libopencm3/efm32/tinygecko/gpio.h b/include/libopencm3/efm32/tinygecko/gpio.h index f1e097b..2c65d0d 100644 --- a/include/libopencm3/efm32/tinygecko/gpio.h +++ b/include/libopencm3/efm32/tinygecko/gpio.h @@ -26,7 +26,8 @@ * This corresponds to the description in d0034_efm32tg_reference_manual.pdf * section 28. * - * @defgroup EFM32TG_GPIO EFM32 Tiny Gecko GPIO + * @ingroup EFM32TG + * @defgroup EFM32TG_GPIO GPIO (General Purpose Input Output) * @{ */ @@ -38,7 +39,7 @@ /** Register definitions and register value definitions for the GPIO subsystem * - * @defgroup EFM32TG_GPIO_regsandvals EFM32 Tiny Gecko GPIO registers and values + * @defgroup EFM32TG_GPIO_regsandvals GPIO registers and values * @{ */ @@ -49,7 +50,7 @@ * * @todo This section could profit from bit-banding. * - * @defgroup EFM32TG_GPIO_registers EFM32 Tiny Gecko GPIO registers + * @defgroup EFM32TG_GPIO_registers GPIO registers * @{ */ #define GPIO_Px_CTRL(port) MMIO32(port + 0x000) /**< @see EFM32TG_GPIO_Px_CTRL_bits */ @@ -154,7 +155,7 @@ * GPIO_Px_PINLOCKN, GPIO_Px_EXTIRISE, GPIO_Px_EXTIFALL, GPIO_IEN, GPIO_IF, * GPIO_IFS, and GPIO_IFC registers. * - * @defgroup EFM32TG_GPIO_pinnumberbits EFM32 Tiny Gecko GPIO pin number bits + * @defgroup EFM32TG_GPIO_pinnumberbits GPIO pin number bits * @{ */ @@ -183,7 +184,7 @@ * They are named as in d0034_efm32tg_reference_manual.pdf's section * 28.5.1. * - * @defgroup EFM32TG_GPIO_Px_CTRL_bits EFM32 Tiny Gecko GPIO Px CTRL bits + * @defgroup EFM32TG_GPIO_Px_CTRL_bits GPIO Px CTRL bits * @{ */ @@ -212,7 +213,7 @@ * 28.5.2/28.5.3. For explanations of what they really do, rather see section * 28.3.1. * - * @defgroup EFM32TG_GPIO_MODE_values EFM32 Tiny Gecko GPIO MODE values + * @defgroup EFM32TG_GPIO_MODE_values GPIO MODE values * @{ */ @@ -248,7 +249,7 @@ * 28.5.10/28.5.11. For explanations of what they do, rather see section * 28.3.5. * - * @defgroup EFM32TG_GPIO_EXTIP_values EFM32 Tiny Gecko GPIO EXTIPSEL values + * @defgroup EFM32TG_GPIO_EXTIP_values GPIO EXTIPSEL values * @{ */ @@ -266,7 +267,7 @@ * See d0034_efm32tg_reference_manual.pdf section 28.5.18 for definitions, and * 28.3.4.1 for explanations. * - * @defgroup EFM32TG_GPIO_ROUTE_bits EFM32 Tiny Gecko GPIO ROUTE bits + * @defgroup EFM32TG_GPIO_ROUTE_bits GPIO ROUTE bits * @{ */ @@ -287,7 +288,7 @@ * See d0034_efm32tg_reference_manual.pdf section 28.5.19 for definitions, and * 28.3.7 for details. * - * @defgroup EFM32TG_GPIO_INSENSE_bits EFM32 Tiny Gecko GPIO INSENSE bits + * @defgroup EFM32TG_GPIO_INSENSE_bits GPIO INSENSE bits * @{ */ @@ -301,7 +302,7 @@ * See d0034_efm32tg_reference_manual.pdf section 28.5.20 for definitions, and * 28.3.1.1 for explanations. * - * @defgroup EFM32TG_GPIO_LOCK_values EFM32 Tiny Gecko GPIO LOCK bits + * @defgroup EFM32TG_GPIO_LOCK_values GPIO LOCK bits * @{ */ @@ -317,7 +318,7 @@ * See d0034_efm32tg_reference_manual.pdf section 28.5.21 for definitions, and * 28.3.4 for explanations. * - * @defgroup EFM32TG_GPIO_CTRL_bits EFM32 Tiny Gecko GPIO CTRL bits + * @defgroup EFM32TG_GPIO_CTRL_bits GPIO CTRL bits * @{ */ @@ -331,7 +332,7 @@ * figure 28.5 in case you wonder if that register is mentioned anywhere else * at all. * - * @defgroup EFM32TG_GPIO_CMD_bits EFM32 Tiny Gecko GPIO CMD bits + * @defgroup EFM32TG_GPIO_CMD_bits GPIO CMD bits * @{ */ @@ -344,7 +345,7 @@ * See d0034_efm32tg_reference_manual.pdf section 28.5.23 for definitions, and * 28.3.2 for explanations. * - * @defgroup EFM32TG_GPIO_EM4WUEN_bits EFM32 Tiny Gecko GPIO EM4WUEN bits + * @defgroup EFM32TG_GPIO_EM4WUEN_bits GPIO EM4WUEN bits * @{ */ @@ -362,7 +363,7 @@ * See d0034_efm32tg_reference_manual.pdf section 28.5.24 for definitions, and * 28.3.2 for explanations. * - * @defgroup EFM32TG_GPIO_EM4WUPOL_bits EFM32 Tiny Gecko GPIO EM4WUPOL bits + * @defgroup EFM32TG_GPIO_EM4WUPOL_bits GPIO EM4WUPOL bits * @{ */ @@ -380,7 +381,7 @@ * See d0034_efm32tg_reference_manual.pdf section 28.5.25 for definitions, and * 28.3.2 for explanations. * - * @defgroup EFM32TG_GPIO_EM4WUCAUSE_bits EFM32 Tiny Gecko GPIO EM4WUCAUSE bits + * @defgroup EFM32TG_GPIO_EM4WUCAUSE_bits GPIO EM4WUCAUSE bits * @{ */ @@ -408,7 +409,7 @@ * * @todo Implement all the non-trivial but useful convenience functions. * - * @defgroup EFM32TG_GPIO_convenience EFM32 Tiny Gecko GPIO convenience functions + * @defgroup EFM32TG_GPIO_convenience GPIO convenience functions * @{ */ -- cgit v1.2.3 From 61b649370f87313a9ff2a10299538f4430ce24ce Mon Sep 17 00:00:00 2001 From: chrysn Date: Sun, 4 Mar 2012 16:57:43 +0100 Subject: efm32: generate _MASK constants constants are generated for all fields that either have named values or length > 1 --- include/libopencm3/efm32/tinygecko/cmu.h | 33 ++++++++++++++++++++++++++ include/libopencm3/efm32/tinygecko/emu.h | 1 + include/libopencm3/efm32/tinygecko/generate.py | 5 +++- 3 files changed, 38 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index 5926cb0..aafb261 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -90,6 +90,7 @@ #define CMU_CTRL_DBGCLK_AUXHFRCO (0<<28) #define CMU_CTRL_DBGCLK_HFCLK (1<<28) +#define CMU_CTRL_DBGCLK_MASK (0x1<<28) #define CMU_CTRL_CLKOUTSEL1_LFRCO (0<<23) #define CMU_CTRL_CLKOUTSEL1_LFXO (1<<23) #define CMU_CTRL_CLKOUTSEL1_HFCLK (2<<23) @@ -98,6 +99,7 @@ #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (5<<23) #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (6<<23) #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (7<<23) +#define CMU_CTRL_CLKOUTSEL1_MASK (0x7<<23) #define CMU_CTRL_CLKOUTSEL0_LFRCO (0<<20) #define CMU_CTRL_CLKOUTSEL0_LFXO (1<<20) #define CMU_CTRL_CLKOUTSEL0_HFCLK (2<<20) @@ -106,29 +108,37 @@ #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (5<<20) #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (6<<20) #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (7<<20) +#define CMU_CTRL_CLKOUTSEL0_MASK (0x7<<20) #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (0<<18) #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (1<<18) #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (2<<18) #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (3<<18) +#define CMU_CTRL_LFXOTIMEOUT_MASK (0x3<<18) #define CMU_CTRL_LFXOBUFCUR (1<<17) #define CMU_CTRL_LXFOBOOST_70PCENT (0<<13) #define CMU_CTRL_LXFOBOOST_100PCENT (1<<13) +#define CMU_CTRL_LXFOBOOST_MASK (0x1<<13) #define CMU_CTRL_LFXOMODE_XTAL (0<<11) #define CMU_CTRL_LFXOMODE_BUFEXTCLK (1<<11) #define CMU_CTRL_LFXOMODE_DIGEXTCLK (2<<11) +#define CMU_CTRL_LFXOMODE_MASK (0x3<<11) #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (0<<9) #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (1<<9) #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (2<<9) #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (3<<9) +#define CMU_CTRL_HFXOTIMEOUT_MASK (0x3<<9) #define CMU_CTRL_HFXOGLITCHDETEN (1<<7) /* No values defined for the field HFXOBUFCUR */ +#define CMU_CTRL_HFXOBUFCUR_MASK (0x3<<5) #define CMU_CTRL_HFXOBOOST_50PCENT (0<<2) #define CMU_CTRL_HFXOBOOST_70PCENT (1<<2) #define CMU_CTRL_HFXOBOOST_80PCENT (2<<2) #define CMU_CTRL_HFXOBOOST_100PCENT (3<<2) +#define CMU_CTRL_HFXOBOOST_MASK (0x3<<2) #define CMU_CTRL_HFXOMODE_XTAL (0<<0) #define CMU_CTRL_HFXOMODE_BUFEXTCLK (1<<0) #define CMU_CTRL_HFXOMODE_DIGEXTCLK (2<<0) +#define CMU_CTRL_HFXOMODE_MASK (0x3<<0) /** @} */ @@ -172,6 +182,7 @@ #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (7<<0) #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (8<<0) #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (9<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK (0x7<<0) /** @} */ @@ -184,13 +195,16 @@ */ /* No values defined for the field SUDELAY */ +#define CMU_HFRCOCTRL_SUDELAY_MASK (0x1f<<12) #define CMU_HFRCOCTRL_BAND_1MHZ (0<<8) #define CMU_HFRCOCTRL_BAND_7MHZ (1<<8) #define CMU_HFRCOCTRL_BAND_11MHZ (2<<8) #define CMU_HFRCOCTRL_BAND_14MHZ (3<<8) #define CMU_HFRCOCTRL_BAND_21MHZ (4<<8) #define CMU_HFRCOCTRL_BAND_28MHZ (5<<8) +#define CMU_HFRCOCTRL_BAND_MASK (0x7<<8) /* No values defined for the field TUNING */ +#define CMU_HFRCOCTRL_TUNING_MASK (0xff<<0) /** @} */ @@ -208,7 +222,9 @@ #define CMU_AUXHFRCOCTRL_BAND_1MHZ (3<<8) #define CMU_AUXHFRCOCTRL_BAND_28MHZ (6<<8) #define CMU_AUXHFRCOCTRL_BAND_21MHZ (7<<8) +#define CMU_AUXHFRCOCTRL_BAND_MASK (0x7<<8) /* No values defined for the field TUNING */ +#define CMU_AUXHFRCOCTRL_TUNING_MASK (0xff<<0) /** @} */ @@ -227,11 +243,13 @@ #define CMU_CALCTRL_DOWNSEL_HFRCO (3<<3) #define CMU_CALCTRL_DOWNSEL_LFRCO (4<<3) #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (5<<3) +#define CMU_CALCTRL_DOWNSEL_MASK (0x7<<3) #define CMU_CALCTRL_UPSEL_HFXO (0<<0) #define CMU_CALCTRL_UPSEL_LFXO (1<<0) #define CMU_CALCTRL_UPSEL_HFRCO (2<<0) #define CMU_CALCTRL_UPSEL_LFRCO (3<<0) #define CMU_CALCTRL_UPSEL_AUXHFRCO (4<<0) +#define CMU_CALCTRL_UPSEL_MASK (0x7<<0) /** @} */ @@ -270,6 +288,7 @@ #define CMU_CMD_HFCLKSEL_HFXO (2<<0) #define CMU_CMD_HFCLKSEL_LFRCO (3<<0) #define CMU_CMD_HFCLKSEL_LFXO (4<<0) +#define CMU_CMD_HFCLKSEL_MASK (0x7<<0) /** @} */ @@ -283,16 +302,20 @@ #define CMU_LFCLKSEL_LFBE_DISABLED (0<<20) #define CMU_LFCLKSEL_LFBE_ULFRCO (1<<20) +#define CMU_LFCLKSEL_LFBE_MASK (0x1<<20) #define CMU_LFCLKSEL_LFAE_DISABLED (0<<16) #define CMU_LFCLKSEL_LFAE_ULFRCO (1<<16) +#define CMU_LFCLKSEL_LFAE_MASK (0x1<<16) #define CMU_LFCLKSEL_LFB_DISABLED (0<<2) #define CMU_LFCLKSEL_LFB_LFRCO (1<<2) #define CMU_LFCLKSEL_LFB_LFXO (2<<2) #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2) +#define CMU_LFCLKSEL_LFB_MASK (0x3<<2) #define CMU_LFCLKSEL_LFA_DISABLED (0<<0) #define CMU_LFCLKSEL_LFA_LFRCO (1<<0) #define CMU_LFCLKSEL_LFA_LFXO (2<<0) #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (3<<0) +#define CMU_LFCLKSEL_LFA_MASK (0x3<<0) /** @} */ @@ -384,6 +407,7 @@ #define CMU_FREEZE_REGFREEZE_UPDATE (0<<0) #define CMU_FREEZE_REGFREEZE_FREEZE (1<<0) +#define CMU_FREEZE_REGFREEZE_MASK (0x1<<0) /** @} */ @@ -426,6 +450,7 @@ #define CMU_LFAPRESC0_LCD_DIV32 (1<<12) #define CMU_LFAPRESC0_LCD_DIV64 (2<<12) #define CMU_LFAPRESC0_LCD_DIV128 (3<<12) +#define CMU_LFAPRESC0_LCD_MASK (0x3<<12) #define CMU_LFAPRESC0_LETIMER0_DIV1 (0<<8) #define CMU_LFAPRESC0_LETIMER0_DIV2 (1<<8) #define CMU_LFAPRESC0_LETIMER0_DIV4 (2<<8) @@ -442,6 +467,7 @@ #define CMU_LFAPRESC0_LETIMER0_DIV8192 (13<<8) #define CMU_LFAPRESC0_LETIMER0_DIV16384 (14<<8) #define CMU_LFAPRESC0_LETIMER0_DIV32768 (15<<8) +#define CMU_LFAPRESC0_LETIMER0_MASK (0xf<<8) #define CMU_LFAPRESC0_RTC_DIV1 (0<<4) #define CMU_LFAPRESC0_RTC_DIV2 (1<<4) #define CMU_LFAPRESC0_RTC_DIV4 (2<<4) @@ -458,10 +484,12 @@ #define CMU_LFAPRESC0_RTC_DIV8192 (13<<4) #define CMU_LFAPRESC0_RTC_DIV16384 (14<<4) #define CMU_LFAPRESC0_RTC_DIV32768 (15<<4) +#define CMU_LFAPRESC0_RTC_MASK (0xf<<4) #define CMU_LFAPRESC0_LESENSE_DIV1 (0<<0) #define CMU_LFAPRESC0_LESENSE_DIV2 (1<<0) #define CMU_LFAPRESC0_LESENSE_DIV4 (2<<0) #define CMU_LFAPRESC0_LESENSE_DIV8 (3<<0) +#define CMU_LFAPRESC0_LESENSE_MASK (0x3<<0) /** @} */ @@ -477,6 +505,7 @@ #define CMU_LFBPRESC0_LEUART0_DIV2 (1<<0) #define CMU_LFBPRESC0_LEUART0_DIV4 (2<<0) #define CMU_LFBPRESC0_LEUART0_DIV8 (3<<0) +#define CMU_LFBPRESC0_LEUART0_MASK (0x3<<0) /** @} */ @@ -490,6 +519,7 @@ #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (0<<1) #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (1<<1) +#define CMU_PCNTCTRL_PCNT0CLKSEL_MASK (0x1<<1) #define CMU_PCNTCTRL_PCNT0CLKEN (1<<0) /** @} */ @@ -510,8 +540,10 @@ #define CMU_LCDCTRL_VBFDIV_DIV32 (5<<4) #define CMU_LCDCTRL_VBFDIV_DIV64 (6<<4) #define CMU_LCDCTRL_VBFDIV_DIV128 (7<<4) +#define CMU_LCDCTRL_VBFDIV_MASK (0x7<<4) #define CMU_LCDCTRL_VBOOSTEN (1<<3) /* No values defined for the field FDIV */ +#define CMU_LCDCTRL_FDIV_MASK (0x7<<0) /** @} */ @@ -525,6 +557,7 @@ #define CMU_ROUTE_LOCATION_LOC0 (0<<4) #define CMU_ROUTE_LOCATION_LOC1 (1<<4) +#define CMU_ROUTE_LOCATION_MASK (0x7<<4) #define CMU_ROUTE_CLKOUT1PEN (1<<1) #define CMU_ROUTE_CLKOUT0PEN (1<<0) diff --git a/include/libopencm3/efm32/tinygecko/emu.h b/include/libopencm3/efm32/tinygecko/emu.h index 31f4241..9a043cb 100644 --- a/include/libopencm3/efm32/tinygecko/emu.h +++ b/include/libopencm3/efm32/tinygecko/emu.h @@ -66,6 +66,7 @@ #define EMU_CTRL_EM4CTRL_TWO (2<<2) #define EMU_CTRL_EM4CTRL_THREE (3<<2) +#define EMU_CTRL_EM4CTRL_MASK (0x3<<2) #define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */ #define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */ diff --git a/include/libopencm3/efm32/tinygecko/generate.py b/include/libopencm3/efm32/tinygecko/generate.py index 96407b5..f96f38b 100644 --- a/include/libopencm3/efm32/tinygecko/generate.py +++ b/include/libopencm3/efm32/tinygecko/generate.py @@ -93,7 +93,10 @@ def yaml2h(filenamebase): else: # FIXME: this should require the 'type' parameter to be set on this field outfile.write("/* No values defined for the field %s */\n"%field['name']) - # FIXME: define mask + + if "values" in field or field.get("length", 1) != 1: + mask = "(%#x<<%s)"%(~(~0< + * + *
  • The CMU_IF register; see d0034_efm32tg_reference_manual.pdf section + * 11.5.13 for definitions.
  • + * + *
  • The CMU_IFS register; see d0034_efm32tg_reference_manual.pdf section + * 11.5.14 for definitions.
  • + * + *
  • The CMU_IFC register; see d0034_efm32tg_reference_manual.pdf section + * 11.5.15 for definitions.
  • + * + *
  • The CMU_IEN register; see d0034_efm32tg_reference_manual.pdf section + * 11.5.16 for definitions.
  • + * + * + * + * @defgroup EFM32TG_CMU_I_bits CMU I bits group + * @{ + */ + +#define CMU_I_CALOF (1<<6) +#define CMU_I_CALRDY (1<<5) +#define CMU_I_AUXHFRCORDY (1<<4) +#define CMU_I_LFXORDY (1<<3) +#define CMU_I_LFRCORDY (1<<2) +#define CMU_I_HFXORDY (1<<1) +#define CMU_I_HFRCORDY (1<<0) + +/** @} */ + /** @} */ /** CMU convenience functions diff --git a/include/libopencm3/efm32/tinygecko/cmu.yaml b/include/libopencm3/efm32/tinygecko/cmu.yaml index bba053c..6153c47 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.yaml +++ b/include/libopencm3/efm32/tinygecko/cmu.yaml @@ -6,6 +6,17 @@ shortname: CMU longname: Clock Management Unit baseref: d0034_efm32tg_reference_manual.pdf section 11 registers_baserefext: ".4" +templateregs: + - name: I + comment: Bits for the various CMU interrupt registers + fields: + - {name: CALOF, shift: 6} + - {name: CALRDY, shift: 5} + - {name: AUXHFRCORDY, shift: 4} + - {name: LFXORDY, shift: 3} + - {name: LFRCORDY, shift: 2} + - {name: HFXORDY, shift: 1} + - {name: HFRCORDY, shift: 0} registers: - name: CTRL offset: 0x000 @@ -265,19 +276,19 @@ registers: - name: IF offset: 0x030 definition_baserefext: ".5.13" - #fields: I + fields: I - name: IFS offset: 0x034 definition_baserefext: ".5.14" - #fields: I + fields: I - name: IFC offset: 0x038 definition_baserefext: ".5.15" - #fields: I + fields: I - name: IEN offset: 0x03c definition_baserefext: ".5.16" - #fields: I + fields: I - name: HFCORECLKEN0 offset: 0x040 definition_baserefext: ".5.17" diff --git a/include/libopencm3/efm32/tinygecko/generate.py b/include/libopencm3/efm32/tinygecko/generate.py index f96f38b..035b4d9 100644 --- a/include/libopencm3/efm32/tinygecko/generate.py +++ b/include/libopencm3/efm32/tinygecko/generate.py @@ -64,20 +64,62 @@ def yaml2h(filenamebase): nl() regs = data['registers'] + + for template in data.get('templateregs', []): + template['is_template'] = [] + regs.append(template) + + regs_dict = dict((x['name'], x) for x in regs) # for easier access. they've got to be a list in yaml to preserve order + wc("These definitions reflect {baseref}{registers_baserefext}", "@defgroup {shortdocname}_registers {shortname} registers", "@{{") nl() + for regdata in regs: - define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], regdata['name'], 'values' if 'values' in regdata else 'bits')) + if 'is_template' in regdata: + # this isn't a real register, just a template + continue + secondcomponent_name = regdata['name'] + if ('fields' in regdata and isinstance(regdata['fields'], str)) or ('values' in regdata and isinstance(regdata['values'], str)): + # uses a template + secondcomponent_name = regdata['fields'] if 'fields' in regdata else regdata['values'] + regs_dict[secondcomponent_name]['is_template'].append(regdata['name']) + + define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], secondcomponent_name, 'values' if 'values' in regdata else 'bits')) nl() wc_close() # close register definitions nl() + for regdata in regs: has_bits = "fields" in regdata has_values = "values" in regdata + is_template = "is_template" in regdata if not has_bits and not has_values: continue - wc("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values"), "See {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."), '@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values',)*2), '@{{', **regdata) + if (has_bits and isinstance(regdata['fields'], str)) or (has_values and isinstance(regdata['values'], str)): + # uses a template, doesn't need own section + continue + + commentlines = [] + if is_template: + commentlines.append("%s for the {shortname} \"{name}\" group of registers (%s)"%("Bit states" if has_bits else "Values", ", ".join(regdata['is_template']))) + assert len(regdata['is_template']) > 0, "What should I talk about when nobody uses this template?" + commentlines.append("These registers use this:") + commentlines.append("
      ") # FIXME: once we're using markdown 1.8, this can be changed to markdown + for user in regdata['is_template']: + userdata = regs_dict[user] + # FIXME: this is an ugly hack around this being in a single wc() line which doesn't take per-line contexts + mergeddata = data.copy() + mergeddata.update(userdata) + commentlines.append(("
    • The {shortname}_{name} register; see {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."+"
    • ")).format(**mergeddata)) + commentlines.append("
    ") + commentlines.append('@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values', 'bits group' if has_bits else 'values group'))) + else: + commentlines.append("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values")) + commentlines.append("See {baseref}{definition_baserefext} for definitions"+regdata.get("details", ".")) + commentlines.append('@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values',)*2)) + commentlines.append('@{{') + wc(*commentlines, **regdata) nl() if has_bits: -- cgit v1.2.3 From 692817059cb53fe854e7c4d8f3c0e3a8a6836eab Mon Sep 17 00:00:00 2001 From: chrysn Date: Sun, 4 Mar 2012 22:43:52 +0100 Subject: various enhancements for header generation * don't reference sections that don't exist (typically happens for registers that don't contain any fields and are interpreted numerically. * allow templates to use override_backref for surpressing the list of registers that use it * print doc for fields even when it uses values or only exports a mask * allow fields to define their own mask; those fields have to define their values explicitly too, and don't have to provide a shift * don't print a "No values defined for the field" lines, as there's always a mask in that case by now. --- include/libopencm3/efm32/tinygecko/cmu.h | 9 ++--- include/libopencm3/efm32/tinygecko/cmu.yaml | 2 ++ include/libopencm3/efm32/tinygecko/generate.py | 46 +++++++++++++++++--------- 3 files changed, 34 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index db0cbde..80c959f 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -53,10 +53,10 @@ #define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) /**< @see EFM32TG_CMU_HFCORECLKDIV_values */ #define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) /**< @see EFM32TG_CMU_HFPERCLKDIV_bits */ #define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00c) /**< @see EFM32TG_CMU_HFRCOCTRL_bits */ -#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) /**< @see EFM32TG_CMU_LFRCOCTRL_bits */ +#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) #define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) /**< @see EFM32TG_CMU_AUXHFRCOCTRL_bits */ #define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) /**< @see EFM32TG_CMU_CALCTRL_bits */ -#define CMU_CALCNT MMIO32(CMU_BASE + 0x01c) /**< @see EFM32TG_CMU_CALCNT_bits */ +#define CMU_CALCNT MMIO32(CMU_BASE + 0x01c) #define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) /**< @see EFM32TG_CMU_OSCENCMD_bits */ #define CMU_CMD MMIO32(CMU_BASE + 0x024) /**< @see EFM32TG_CMU_CMD_bits */ #define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) /**< @see EFM32TG_CMU_LFCLKSEL_bits */ @@ -128,7 +128,6 @@ #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (3<<9) #define CMU_CTRL_HFXOTIMEOUT_MASK (0x3<<9) #define CMU_CTRL_HFXOGLITCHDETEN (1<<7) -/* No values defined for the field HFXOBUFCUR */ #define CMU_CTRL_HFXOBUFCUR_MASK (0x3<<5) #define CMU_CTRL_HFXOBOOST_50PCENT (0<<2) #define CMU_CTRL_HFXOBOOST_70PCENT (1<<2) @@ -194,7 +193,6 @@ * @{ */ -/* No values defined for the field SUDELAY */ #define CMU_HFRCOCTRL_SUDELAY_MASK (0x1f<<12) #define CMU_HFRCOCTRL_BAND_1MHZ (0<<8) #define CMU_HFRCOCTRL_BAND_7MHZ (1<<8) @@ -203,7 +201,6 @@ #define CMU_HFRCOCTRL_BAND_21MHZ (4<<8) #define CMU_HFRCOCTRL_BAND_28MHZ (5<<8) #define CMU_HFRCOCTRL_BAND_MASK (0x7<<8) -/* No values defined for the field TUNING */ #define CMU_HFRCOCTRL_TUNING_MASK (0xff<<0) /** @} */ @@ -223,7 +220,6 @@ #define CMU_AUXHFRCOCTRL_BAND_28MHZ (6<<8) #define CMU_AUXHFRCOCTRL_BAND_21MHZ (7<<8) #define CMU_AUXHFRCOCTRL_BAND_MASK (0x7<<8) -/* No values defined for the field TUNING */ #define CMU_AUXHFRCOCTRL_TUNING_MASK (0xff<<0) /** @} */ @@ -542,7 +538,6 @@ #define CMU_LCDCTRL_VBFDIV_DIV128 (7<<4) #define CMU_LCDCTRL_VBFDIV_MASK (0x7<<4) #define CMU_LCDCTRL_VBOOSTEN (1<<3) -/* No values defined for the field FDIV */ #define CMU_LCDCTRL_FDIV_MASK (0x7<<0) /** @} */ diff --git a/include/libopencm3/efm32/tinygecko/cmu.yaml b/include/libopencm3/efm32/tinygecko/cmu.yaml index 6153c47..7b83b7f 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.yaml +++ b/include/libopencm3/efm32/tinygecko/cmu.yaml @@ -153,6 +153,7 @@ registers: offset: 0x010 definition_baserefext: ".5.5" length: 7 + type: uint - name: AUXHFRCOCTRL offset: 0x014 definition_baserefext: ".5.6" @@ -200,6 +201,7 @@ registers: offset: 0x01c definition_baserefext: ".5.8" length: 19 + type: uint - name: OSCENCMD offset: 0x020 definition_baserefext: ".5.9" diff --git a/include/libopencm3/efm32/tinygecko/generate.py b/include/libopencm3/efm32/tinygecko/generate.py index 035b4d9..7f426a4 100644 --- a/include/libopencm3/efm32/tinygecko/generate.py +++ b/include/libopencm3/efm32/tinygecko/generate.py @@ -75,16 +75,19 @@ def yaml2h(filenamebase): nl() for regdata in regs: - if 'is_template' in regdata: + has_bits = "fields" in regdata + has_values = "values" in regdata + is_template = "is_template" in regdata + if is_template: # this isn't a real register, just a template continue secondcomponent_name = regdata['name'] - if ('fields' in regdata and isinstance(regdata['fields'], str)) or ('values' in regdata and isinstance(regdata['values'], str)): + if (has_bits and isinstance(regdata['fields'], str)) or (has_values and isinstance(regdata['values'], str)): # uses a template - secondcomponent_name = regdata['fields'] if 'fields' in regdata else regdata['values'] + secondcomponent_name = regdata['fields'] if has_bits else regdata['values'] regs_dict[secondcomponent_name]['is_template'].append(regdata['name']) - define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], secondcomponent_name, 'values' if 'values' in regdata else 'bits')) + define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], secondcomponent_name, 'values' if 'values' in regdata else 'bits') if has_bits or has_values else None) nl() wc_close() # close register definitions nl() @@ -104,15 +107,18 @@ def yaml2h(filenamebase): if is_template: commentlines.append("%s for the {shortname} \"{name}\" group of registers (%s)"%("Bit states" if has_bits else "Values", ", ".join(regdata['is_template']))) assert len(regdata['is_template']) > 0, "What should I talk about when nobody uses this template?" - commentlines.append("These registers use this:") - commentlines.append("
      ") # FIXME: once we're using markdown 1.8, this can be changed to markdown - for user in regdata['is_template']: - userdata = regs_dict[user] - # FIXME: this is an ugly hack around this being in a single wc() line which doesn't take per-line contexts - mergeddata = data.copy() - mergeddata.update(userdata) - commentlines.append(("
    • The {shortname}_{name} register; see {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."+"
    • ")).format(**mergeddata)) - commentlines.append("
    ") + if 'override_backref' in regdata: + commentlines.append(regdata['override_backref']) + else: + commentlines.append("These registers use this:") + commentlines.append("
      ") # FIXME: once we're using markdown 1.8, this can be changed to markdown + for user in regdata['is_template']: + userdata = regs_dict[user] + # FIXME: this is an ugly hack around this being in a single wc() line which doesn't take per-line contexts + mergeddata = data.copy() + mergeddata.update(userdata) + commentlines.append(("
    • The {shortname}_{name} register; see {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."+"
    • ")).format(**mergeddata)) + commentlines.append("
    ") commentlines.append('@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values', 'bits group' if has_bits else 'values group'))) else: commentlines.append("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values")) @@ -126,18 +132,26 @@ def yaml2h(filenamebase): for field in regdata['fields']: #shiftdefine = "_%s_%s_%s_shift"%(shortname, regdata['name'], field['name']) #define(shiftdefine, field['shift']) + + # there is one condition under which field's doc would get shown; show it immediately otherwise + if 'doc' in field and not ("values" not in field and field.get("length", 1) == 1): + wc(field['doc']) + if "values" in field: for value in field.get("values"): - define("%s_%s_%s_%s"%(data['shortname'], regdata['name'], field['name'], value['name']), "(%s<<%s)"%(value['value'], field['shift']), value.get('doc', None)) + define("%s_%s_%s_%s"%(data['shortname'], regdata['name'], field['name'], value['name']), value['value'] if "mask" in field else "(%s<<%s)"%(value['value'], field['shift']), value.get('doc', None)) else: if field.get('length', 1) == 1: define("%s_%s_%s"%(data['shortname'], regdata['name'], field['name']), "(1<<%s)"%field['shift'], field.get('doc', None)) else: # FIXME: this should require the 'type' parameter to be set on this field - outfile.write("/* No values defined for the field %s */\n"%field['name']) + pass if "values" in field or field.get("length", 1) != 1: - mask = "(%#x<<%s)"%(~(~0< + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * @see EFM32TG_LCD + */ + +/** Definitions for the LCD subsystem (Liquid Crystal Display driver). + * + * This corresponds to the description in d0034_efm32tg_reference_manual.pdf + * section 29. + * + * @ingroup EFM32TG + * @defgroup EFM32TG_LCD LCD (Liquid Crystal Display driver) + * @{ + */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_LCD_H +#define LIBOPENCM3_EFM32_TINYGECKO_LCD_H + +#include +#include + +/** Register definitions and register value definitions for the LCD subsystem + * + * @defgroup EFM32TG_LCD_regsandvals LCD registers and values + * @{ + */ + +/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 29.4 + * + * @defgroup EFM32TG_LCD_registers LCD registers + * @{ + */ + +#define LCD_CTRL MMIO32(LCD_BASE + 0x000) /**< @see EFM32TG_LCD_CTRL_bits */ +#define LCD_DISPCTRL MMIO32(LCD_BASE + 0x004) /**< @see EFM32TG_LCD_DISPCTRL_bits */ +#define LCD_SEGEN MMIO32(LCD_BASE + 0x008) +#define LCD_BACTRL MMIO32(LCD_BASE + 0x00c) /**< @see EFM32TG_LCD_BACTRL_bits */ +#define LCD_STATUS MMIO32(LCD_BASE + 0x010) /**< @see EFM32TG_LCD_STATUS_bits */ +#define LCD_AREGA MMIO32(LCD_BASE + 0x014) +#define LCD_AREGB MMIO32(LCD_BASE + 0x018) +#define LCD_IF MMIO32(LCD_BASE + 0x01c) /**< @see EFM32TG_LCD_I_bits */ +#define LCD_IFS MMIO32(LCD_BASE + 0x020) /**< @see EFM32TG_LCD_I_bits */ +#define LCD_IFC MMIO32(LCD_BASE + 0x024) /**< @see EFM32TG_LCD_I_bits */ +#define LCD_IEN MMIO32(LCD_BASE + 0x028) /**< @see EFM32TG_LCD_I_bits */ +#define LCD_SEGD0L MMIO32(LCD_BASE + 0x040) /**< @see EFM32TG_LCD_SEG_bits */ +#define LCD_SEGD1L MMIO32(LCD_BASE + 0x044) /**< @see EFM32TG_LCD_SEG_bits */ +#define LCD_SEGD2L MMIO32(LCD_BASE + 0x048) /**< @see EFM32TG_LCD_SEG_bits */ +#define LCD_SEGD3L MMIO32(LCD_BASE + 0x04c) /**< @see EFM32TG_LCD_SEG_bits */ +#define LCD_FREEZE MMIO32(LCD_BASE + 0x060) /**< @see EFM32TG_LCD_FREEZE_bits */ +#define LCD_SYNGBUSY MMIO32(LCD_BASE + 0x064) /**< @see EFM32TG_LCD_SYNGBUSY_bits */ +#define LCD_SEGD4L MMIO32(LCD_BASE + 0x0cc) /**< @see EFM32TG_LCD_SEG_bits */ +#define LCD_SEGD5L MMIO32(LCD_BASE + 0x0d0) /**< @see EFM32TG_LCD_SEG_bits */ +#define LCD_SEGD6L MMIO32(LCD_BASE + 0x0d4) /**< @see EFM32TG_LCD_SEG_bits */ +#define LCD_SEGD7L MMIO32(LCD_BASE + 0x0d8) /**< @see EFM32TG_LCD_SEG_bits */ + +/** @} */ + +/** Bit states for the LCD_CTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 29.5.1 for definitions. + * + * @defgroup EFM32TG_LCD_CTRL_bits LCD CTRL bits + * @{ + */ + +#define LCD_CTRL_DSC (1<<23) +#define LCD_CTRL_UDCTRL_REGULAR (0<<1) +#define LCD_CTRL_UDCTRL_FCEVENT (1<<1) +#define LCD_CTRL_UDCTRL_FRAMESTART (2<<1) +#define LCD_CTRL_UDCTRL_MASK (0x3<<1) +#define LCD_CTRL_EN (1<<0) + +/** @} */ + +/** Bit states for the LCD_DISPCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 29.5.2 for definitions. + * + * @defgroup EFM32TG_LCD_DISPCTRL_bits LCD DISPCTRL bits + * @{ + */ + +#define LCD_DISPCTRL_VBLEV_LEVEL0 (0<<18) +#define LCD_DISPCTRL_VBLEV_LEVEL1 (1<<18) +#define LCD_DISPCTRL_VBLEV_LEVEL2 (2<<18) +#define LCD_DISPCTRL_VBLEV_LEVEL3 (3<<18) +#define LCD_DISPCTRL_VBLEV_LEVEL4 (4<<18) +#define LCD_DISPCTRL_VBLEV_LEVEL5 (5<<18) +#define LCD_DISPCTRL_VBLEV_LEVEL6 (6<<18) +#define LCD_DISPCTRL_VBLEV_LEVEL7 (7<<18) +#define LCD_DISPCTRL_VBLEV_MASK (0x7<<18) +#define LCD_DISPCTRL_VLCDSEL_VDD (0<<16) +#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (1<<16) +#define LCD_DISPCTRL_VLCDSEL_MASK (0x1<<16) +#define LCD_DISPCTRL_CONCONF_VLCD (0<<15) +#define LCD_DISPCTRL_CONCONF_GND (1<<15) +#define LCD_DISPCTRL_CONCONF_MASK (0x1<<15) +/** By this parameter, the voltage V_LCD_OUT is interpolated linearly from + * 0.5V_LCD to V_LCD. + */ +#define LCD_DISPCTRL_CONLEV_MASK (0x1f<<8) +#define LCD_DISPCTRL_WAVE_LOWPOWER (0<<4) +#define LCD_DISPCTRL_WAVE_NORMAL (1<<4) +#define LCD_DISPCTRL_WAVE_MASK (0x1<<4) +#define LCD_DISPCTRL_BIAS_STATIC (0<<2) +#define LCD_DISPCTRL_BIAS_ONEHALF (1<<2) +#define LCD_DISPCTRL_BIAS_ONETHIRD (2<<2) +#define LCD_DISPCTRL_BIAS_ONEFOURTH (3<<2) +#define LCD_DISPCTRL_BIAS_MASK (0x3<<2) +/** These definitions munge the MUX and the MUXE fields, as they are described + * in the documentation only together too. + */ +#define LCD_DISPCTRL_MUX_STATIC 0x00000000 +#define LCD_DISPCTRL_MUX_DUPLEX 0x00000001 +#define LCD_DISPCTRL_MUX_TRIPLEX 0x00000002 +#define LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003 +#define LCD_DISPCTRL_MUX_SEXTAPLEX 0x00400001 +#define LCD_DISPCTRL_MUX_OCTAPLEX 0x00400003 +#define LCD_DISPCTRL_MUX_MASK 0x00400003 + +/** @} */ + +/** Bit states for the LCD_BACTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 29.5.4 for definitions. + * + * @defgroup EFM32TG_LCD_BACTRL_bits LCD BACTRL bits + * @{ + */ + +#define LCD_BACTRL_FCTOP_MASK (0x3f<<18) +#define LCD_BACTRL_FCPRESC_DIV1 (0<<16) +#define LCD_BACTRL_FCPRESC_DIV2 (1<<16) +#define LCD_BACTRL_FCPRESC_DIV4 (2<<16) +#define LCD_BACTRL_FCPRESC_DIV8 (3<<16) +#define LCD_BACTRL_FCPRESC_MASK (0x3<<16) +#define LCD_BACTRL_FCEN (1<<8) +#define LCD_BACTRL_ALGOSEL_AND (0<<7) +#define LCD_BACTRL_ALGOSEL_OR (1<<7) +#define LCD_BACTRL_ALGOSEL_MASK (0x1<<7) +#define LCD_BACTRL_AREGBSC_NOSHIFT (0<<5) +#define LCD_BACTRL_AREGBSC_SHIFTLEFT (1<<5) +#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (2<<5) +#define LCD_BACTRL_AREGBSC_MASK (0x3<<5) +#define LCD_BACTRL_AREGASC_NOSHIFT (0<<3) +#define LCD_BACTRL_AREGASC_SHIFTLEFT (1<<3) +#define LCD_BACTRL_AREGASC_SHIFTRIGHT (2<<3) +#define LCD_BACTRL_AREGASC_MASK (0x3<<3) +#define LCD_BACTRL_AEN (1<<2) +#define LCD_BACTRL_BLANK (1<<1) +#define LCD_BACTRL_BLINKEN (1<<0) + +/** @} */ + +/** Bit states for the LCD_STATUS register + * + * See d0034_efm32tg_reference_manual.pdf section 29.5.5 for definitions. + * + * @defgroup EFM32TG_LCD_STATUS_bits LCD STATUS bits + * @{ + */ + +#define LCD_STATUS_BLINK (1<<8) +#define LCD_STATUS_ASTATE_MASK (0xf<<0) + +/** @} */ + +/** Bit states for the LCD_FREEZE register + * + * See d0034_efm32tg_reference_manual.pdf section 29.5.16 for definitions. + * + * @defgroup EFM32TG_LCD_FREEZE_bits LCD FREEZE bits + * @{ + */ + +#define LCD_FREEZE_REGFREEZE_UPDATE (0<<0) +#define LCD_FREEZE_REGFREEZE_FREEZE (1<<0) +#define LCD_FREEZE_REGFREEZE_MASK (0x1<<0) + +/** @} */ + +/** Bit states for the LCD_SYNGBUSY register + * + * See d0034_efm32tg_reference_manual.pdf section 29.5.17 for definitions. + * + * @defgroup EFM32TG_LCD_SYNGBUSY_bits LCD SYNGBUSY bits + * @{ + */ + +#define LCD_SYNGBUSY_SEGD7L (1<<19) +#define LCD_SYNGBUSY_SEGD6L (1<<18) +#define LCD_SYNGBUSY_SEGD5L (1<<17) +#define LCD_SYNGBUSY_SEGD4L (1<<16) +#define LCD_SYNGBUSY_SEGD3L (1<<7) +#define LCD_SYNGBUSY_SEGD2L (1<<6) +#define LCD_SYNGBUSY_SEGD1L (1<<5) +#define LCD_SYNGBUSY_SEGD0L (1<<4) +#define LCD_SYNGBUSY_AREGB (1<<3) +#define LCD_SYNGBUSY_AREGA (1<<2) +#define LCD_SYNGBUSY_BACTRL (1<<1) +#define LCD_SYNGBUSY_CTRL (1<<0) + +/** @} */ + +/** Bit states for the LCD "I" group of registers (IF, IFS, IFC, IEN) + * + * These registers use this: + * + *
      + * + *
    • The LCD_IF register; see d0034_efm32tg_reference_manual.pdf section + * 29.5.8 for definitions.
    • + * + *
    • The LCD_IFS register; see d0034_efm32tg_reference_manual.pdf section + * 29.5.9 for definitions.
    • + * + *
    • The LCD_IFC register; see d0034_efm32tg_reference_manual.pdf section + * 29.5.10 for definitions.
    • + * + *
    • The LCD_IEN register; see d0034_efm32tg_reference_manual.pdf section + * 29.5.11 for definitions.
    • + * + *
    + * + * @defgroup EFM32TG_LCD_I_bits LCD I bits group + * @{ + */ + +#define LCD_I_FC (1<<0) + +/** @} */ + +/** Bit states for the LCD "SEG" group of registers (SEGD0L, SEGD1L, SEGD2L, + * SEGD3L, SEGD4L, SEGD5L, SEGD6L, SEGD7L) + * + * These values are used by the SEGDxL registers, as defined in + * d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21. + * + * @defgroup EFM32TG_LCD_SEG_bits LCD SEG bits group + * @{ + */ + +#define LCD_SEG_23 (1<<23) +#define LCD_SEG_22 (1<<22) +#define LCD_SEG_21 (1<<21) +#define LCD_SEG_20 (1<<20) +#define LCD_SEG_19 (1<<19) +#define LCD_SEG_18 (1<<18) +#define LCD_SEG_17 (1<<17) +#define LCD_SEG_16 (1<<16) +#define LCD_SEG_15 (1<<15) +#define LCD_SEG_14 (1<<14) +#define LCD_SEG_13 (1<<13) +#define LCD_SEG_12 (1<<12) +#define LCD_SEG_11 (1<<11) +#define LCD_SEG_10 (1<<10) +#define LCD_SEG_9 (1<<9) +#define LCD_SEG_8 (1<<8) +#define LCD_SEG_7 (1<<7) +#define LCD_SEG_6 (1<<6) +#define LCD_SEG_5 (1<<5) +#define LCD_SEG_4 (1<<4) +#define LCD_SEG_3 (1<<3) +#define LCD_SEG_2 (1<<2) +#define LCD_SEG_1 (1<<1) +#define LCD_SEG_0 (1<<0) + +/** @} */ + +/** @} */ + + +/** @} */ + +#endif diff --git a/include/libopencm3/efm32/tinygecko/lcd.yaml b/include/libopencm3/efm32/tinygecko/lcd.yaml new file mode 100644 index 0000000..1b2b758 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/lcd.yaml @@ -0,0 +1,238 @@ +copyright: "2012 chrysn " +license: lgpl-3+ +ingroup: EFM32TG +shortdocname: EFM32TG_LCD +shortname: LCD +longname: Liquid Crystal Display driver +baseref: d0034_efm32tg_reference_manual.pdf section 29 +registers_baserefext: ".4" +templateregs: + - name: I + comment: Bits for the various LCD interrupt registers + fields: + - {name: FC, shift: 0} + - name: SEG + comment: Bits for the individual SEG pins + override_backref: These values are used by the SEGDxL registers, as defined in d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21. + fields: + - {name: 23, shift: 23} + - {name: 22, shift: 22} + - {name: 21, shift: 21} + - {name: 20, shift: 20} + - {name: 19, shift: 19} + - {name: 18, shift: 18} + - {name: 17, shift: 17} + - {name: 16, shift: 16} + - {name: 15, shift: 15} + - {name: 14, shift: 14} + - {name: 13, shift: 13} + - {name: 12, shift: 12} + - {name: 11, shift: 11} + - {name: 10, shift: 10} + - {name: 9, shift: 9} + - {name: 8, shift: 8} + - {name: 7, shift: 7} + - {name: 6, shift: 6} + - {name: 5, shift: 5} + - {name: 4, shift: 4} + - {name: 3, shift: 3} + - {name: 2, shift: 2} + - {name: 1, shift: 1} + - {name: 0, shift: 0} +registers: + - name: CTRL + offset: 0x000 + definition_baserefext: .5.1 + fields: + - name: DSC + shift: 23 + - name: UDCTRL + shift: 1 + length: 2 + values: + - {name: REGULAR, value: 0} + - {name: FCEVENT, value: 1} + - {name: FRAMESTART, value: 2} + - name: EN + shift: 0 + - name: DISPCTRL + offset: 0x004 + definition_baserefext: .5.2 + fields: + # MUXE left out and defined manually at the end + - name: VBLEV + shift: 18 + length: 3 + values: + - {name: LEVEL0, value: 0} + - {name: LEVEL1, value: 1} + - {name: LEVEL2, value: 2} + - {name: LEVEL3, value: 3} + - {name: LEVEL4, value: 4} + - {name: LEVEL5, value: 5} + - {name: LEVEL6, value: 6} + - {name: LEVEL7, value: 7} + - name: VLCDSEL + shift: 16 + values: + - {name: VDD, value: 0} + - {name: VEXTBOOST, value: 1} + - name: CONCONF + shift: 15 + values: + - {value: 0, name: VLCD} + - {value: 1, name: GND} + - name: CONLEV + shift: 8 + length: 5 + type: uint + doc: "By this parameter, the voltage V_LCD_OUT is interpolated linearly from 0.5V_LCD to V_LCD." + - name: WAVE + shift: 4 + values: + - {value: 0, name: LOWPOWER} + - {value: 1, name: NORMAL} + - name: BIAS + shift: 2 + length: 2 + values: + - {value: 0, name: STATIC} + - {value: 1, name: ONEHALF} + - {value: 2, name: ONETHIRD} + - {value: 3, name: ONEFOURTH} + - name: MUX + mask: "0x00400003" + values: + - {value: "0x00000000", name: STATIC} + - {value: "0x00000001", name: DUPLEX} + - {value: "0x00000002", name: TRIPLEX} + - {value: "0x00000003", name: QUADRUPLEX} + - {value: "0x00400001", name: SEXTAPLEX} + - {value: "0x00400003", name: OCTAPLEX} + doc: These definitions munge the MUX and the MUXE fields, as they are described in the documentation only together too. + - name: SEGEN + offset: 0x008 + definition_baserefext: .5.3 + # FIXME how do we reperesent this best? + - name: BACTRL + offset: 0x00c + definition_baserefext: .5.4 + fields: + - name: FCTOP + shift: 18 + length: 6 + type: uint + - name: FCPRESC + shift: 16 + length: 2 + values: + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - name: FCEN + shift: 8 + - name: ALGOSEL + shift: 7 + values: + - {value: 0, name: AND} + - {value: 1, name: OR} + - name: AREGBSC + shift: 5 + length: 2 + values: &BACTRL_AREGBSC + - {value: 0, name: NOSHIFT} + - {value: 1, name: SHIFTLEFT} + - {value: 2, name: SHIFTRIGHT} + - name: AREGASC + shift: 3 + length: 2 + values: *BACTRL_AREGBSC + - name: AEN + shift: 2 + - name: BLANK + shift: 1 + - name: BLINKEN + shift: 0 + - name: STATUS + offset: 0x010 + definition_baserefext: .5.5 + fields: + - name: BLINK + shift: 8 + - name: ASTATE + shift: 0 + length: 4 + type: uint + - name: AREGA + offset: 0x014 + # FIXME: how do we represent this in the header? + - name: AREGB + offset: 0x018 + # FIXME: how do we represent this in the header? + - name: IF + offset: 0x01c + definition_baserefext: .5.8 + fields: I + - name: IFS + offset: 0x020 + definition_baserefext: .5.9 + fields: I + - name: IFC + offset: 0x024 + definition_baserefext: .5.10 + fields: I + - name: IEN + offset: 0x028 + definition_baserefext: .5.11 + fields: I + - name: SEGD0L + offset: 0x040 + fields: SEG + - name: SEGD1L + offset: 0x044 + fields: SEG + - name: SEGD2L + offset: 0x048 + fields: SEG + - name: SEGD3L + offset: 0x04c + fields: SEG + - name: FREEZE + offset: 0x060 + definition_baserefext: .5.16 + fields: + - name: REGFREEZE + shift: 0 + values: + - {value: 0, name: UPDATE} + - {value: 1, name: FREEZE} + # FIXME: this seems to be a typical FREEZE register + - name: SYNGBUSY + offset: 0x064 + definition_baserefext: .5.17 + fields: + - {name: SEGD7L, shift: 19} + - {name: SEGD6L, shift: 18} + - {name: SEGD5L, shift: 17} + - {name: SEGD4L, shift: 16} + - {name: SEGD3L, shift: 7} + - {name: SEGD2L, shift: 6} + - {name: SEGD1L, shift: 5} + - {name: SEGD0L, shift: 4} + - {name: AREGB, shift: 3} + - {name: AREGA, shift: 2} + - {name: BACTRL, shift: 1} + - {name: CTRL, shift: 0} + - name: SEGD4L + offset: 0x0CC + fields: SEG + - name: SEGD5L + offset: 0x0D0 + fields: SEG + - name: SEGD6L + offset: 0x0D4 + fields: SEG + - name: SEGD7L + offset: 0x0D8 + fields: SEG -- cgit v1.2.3 From 0e62b15125c46b63913dd240d8cccefe510034d1 Mon Sep 17 00:00:00 2001 From: chrysn Date: Wed, 4 Apr 2012 19:59:45 +0200 Subject: added lcd example the way text is generated is currently rather awkward, looking for a better solution. --- .../tinygecko/efm32-tg-stk3300/lcd_demo/Makefile | 23 +++ .../tinygecko/efm32-tg-stk3300/lcd_demo/README | 8 + .../lcd_demo/generate_lcd_mapping.py | 76 ++++++++ .../tinygecko/efm32-tg-stk3300/lcd_demo/lcd_demo.c | 130 ++++++++++++++ .../efm32-tg-stk3300/lcd_demo/lcd_mapping.yaml | 192 +++++++++++++++++++++ include/libopencm3/efm32/tinygecko/lcd.h | 32 ++-- include/libopencm3/efm32/tinygecko/lcd.yaml | 5 +- 7 files changed, 450 insertions(+), 16 deletions(-) create mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/Makefile create mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/README create mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/generate_lcd_mapping.py create mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/lcd_demo.c create mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/lcd_mapping.yaml (limited to 'include') diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/Makefile b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/Makefile new file mode 100644 index 0000000..7ef06ad --- /dev/null +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2012 chrysn +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = lcd_demo + +include ../Makefile.include diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/README b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/README new file mode 100644 index 0000000..207ed10 --- /dev/null +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/README @@ -0,0 +1,8 @@ +========================================= +EFM32-TG-STK3300 Examples LCD Demo README +========================================= + +This is an example on how to use the LCD peripherial on Energy Micro Tiny Gecko +chips. + +It's intended for the EFM32-TG-STK3300 eval board. diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/generate_lcd_mapping.py b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/generate_lcd_mapping.py new file mode 100644 index 0000000..1b6405f --- /dev/null +++ b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/generate_lcd_mapping.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python + +import yaml + +class Font(dict): + def __init__(self, letterdict): + for (k, v) in letterdict.items(): + self[k] = set(v.split()) + +class Display(object): + def __init__(self, data): + self.mapping = {} + + for c, segs in enumerate(data['coms']): + for s, name in enumerate(segs): + self.mapping[name] = (c, s) + + def render_text(self, text, symbols, font): + cursor = 1 + segments = set() + for letter in text: + if letter == '.': + segments.add("a%s_dp"%(cursor-1)) + elif letter == ':': + segments.add("a%s_colon"%(cursor-1)) + elif letter in font: + for segment in font[letter]: + segments.add("a%s_%s"%(cursor, segment)) + cursor += 1 + + for s in symbols: + segments.add(s) + + coms = {} + for segment in segments: + com, seg = self.mapping[segment] + coms[com] = coms.get(com, 0) | (1< + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * Demo of the LCD display aboard the EFM32-TG-STK330 eval board. + */ + +#include +#include +#include +#include "../lightswitch/lightswitch-common.c" +void led_toggle(void) { gpio_toggle(GPIO_PD, GPIO7); } + +void delay(void) +{ + int x; + + /* Start up delay until we mess with clock stuff, so the debugger can catch up. */ + for(x = 0; x < 10000000; ++x) led_on(); +} + +void lcd_init(void) +{ + /* LCD is a LE module. We're constantly powered on for now, so using + * HFCORECLK/2 */ + CMU_HFCORECLKEN0 |= CMU_HFCORECLKEN0_LE; + CMU_LFCLKSEL = (CMU_LFCLKSEL & ~CMU_LFCLKSEL_LFA_MASK) | CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; + /* We need to get this down to reasonable 100Hz from 14MHz, 7MHz at + * LFACLK, 70kHz after LFA prescaler, 10kHz after FDIV. Octaplexing + * brings us down to about 500Hz. */ + CMU_LFAPRESC0 |= CMU_LFAPRESC0_LCD_DIV128; + CMU_LCDCTRL |= CMU_LCDCTRL_FDIV_MASK; /* factor 7+1 */ + + /* If we don't wait for the prescaler to become ready, the "Do it" step + * won't pass. */ + while (CMU_SYNCBUSY & CMU_SYNCBUSY_LFAPRESC0); + + CMU_LFACLKEN0 |= CMU_LFACLKEN0_LCD; + + while (CMU_SYNCBUSY & CMU_SYNCBUSY_LFACLKEN0); + + /* Voltage is around 3.3V anyway, we don't need voltage boosting, + * leaving it disabled. I don't fully understand the implications of + * biasing yet, but it seems like he more biased the better, and will + * just affect frame rate negatively. */ + LCD_DISPCTRL = (LCD_DISPCTRL & ~(LCD_DISPCTRL_BIAS_MASK | LCD_DISPCTRL_MUX_MASK)) | LCD_DISPCTRL_BIAS_ONEFOURTH | LCD_DISPCTRL_MUX_OCTAPLEX; + + /* Segments default to disabled, enable the 20 relevant ones */ + LCD_SEGEN = ~(~0<<5); + + /* Do it */ + LCD_CTRL |= LCD_CTRL_EN; + + while (LCD_SYNCBUSY & LCD_SYNCBUSY_CTRL) led_off(); + led_on(); +} + +void set_bank(u8 com, u32 data) +{ + switch(com) + { + case 0: LCD_SEGD0L = data; break; + case 1: LCD_SEGD1L = data; break; + case 2: LCD_SEGD2L = data; break; + case 3: LCD_SEGD3L = data; break; + case 4: LCD_SEGD4L = data; break; + case 5: LCD_SEGD5L = data; break; + case 6: LCD_SEGD6L = data; break; + case 7: LCD_SEGD7L = data; break; + } +} + +int main(void) +{ + u8 active_bit = 0; + u8 active_com = 0; + + gpio_setup(); + +// delay(); + + lcd_init(); + + /* "{FNORD}" with a gecko as generated by current generate_lcd_mapping.py */ +set_bank(0, 0x000a00); +set_bank(1, 0x0031cb); +set_bank(2, 0x004622); +set_bank(3, 0x0012a8); +set_bank(4, 0x00481a); +set_bank(5, 0x001140); +set_bank(6, 0x004642); +set_bank(7, 0x0051ac); + + while(1) + { + if (pb0_get()) + { + while(pb0_get()); + + set_bank(active_com, ~0); + active_bit = (active_bit + 1) % 21; /* one more to see where 0 is */ + set_bank(active_com, ~(1< - -/* needed by system_efm32.h:196, guessing */ -#define __INLINE inline - -/* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the - * libopencm3 ones, "volatile" is all that's missing. */ -#define __IO volatile -#define __O volatile -#define __I volatile - -/* -> style access for what is defined in libopencm3/stm32/f1/scb.h / - * cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */ - -/* from stm32/f1/scb.h */ -#define SCB_SCR_SLEEPDEEP_Msk (1 << 2) -/* structure as in, for example, - * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from - * libopencm3/stm32/f1/scb.h. incomplete. */ -typedef struct -{ - __IO uint32_t CPUID; - __IO uint32_t ICSR; - __IO uint32_t VTOR; - __IO uint32_t AIRCR; - __IO uint32_t SCR; - __IO uint32_t CCR; - __IO uint8_t SHPR[12]; /* FIXME: how is this properly indexed? */ - __IO uint32_t SHCSR; -} SCB_TypeDef; -#define SCB ((SCB_TypeDef *) SCB_BASE) -/* from libopencm3/cm3/memorymap.h */ -#define PPBI_BASE 0xE0000000 -#define SCS_BASE (PPBI_BASE + 0xE000) -#define SCB_BASE (SCS_BASE + 0x0D00) - -/* needed by efm32_emu.h, guessing and taking the implementation used in - * lightswitch-interrupt.c */ -#define __WFI() __asm__("wfi") - -/* needed by efm32_cmu.h, probably it's just what gcc provides anyway */ -#define __CLZ(div) __builtin_clz(div) - -/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 */ -#define __REV(x) __builtin_bswap32(x) - -/* stubs for efm32_cmu.c */ -uint32_t SystemCoreClockGet(void); -uint32_t SystemHFClockGet(void); - -uint32_t SystemLFRCOClockGet(void); -uint32_t SystemLFXOClockGet(void); - -/* stubs for efm32_dbg.h */ -typedef struct -{ - uint32_t DHCSR; -} CoreDebug_TypeDef; -#define CoreDebug ((CoreDebug_TypeDef *) 0) -#define CoreDebug_DHCSR_C_DEBUGEN_Msk 0 - -/* stubs for efm32_dma */ - -#define NVIC_ClearPendingIRQ(irq) 1 -#define NVIC_EnableIRQ(irq) 1 -#define NVIC_DisableIRQ(irq) 1 - -/* stubs for efm32_int */ - -#define __enable_irq() 1 -#define __disable_irq() 1 - -/* stubs for efm32_mpu */ - -#define SCB_SHCSR_MEMFAULTENA_Msk 0 - -typedef struct -{ - uint32_t CTRL; - uint32_t RNR; - uint32_t RBAR; - uint32_t RASR; -} MPU_TypeDef; -#define MPU ((MPU_TypeDef *) 0) -#define MPU_CTRL_ENABLE_Msk 0 -#define MPU_RASR_XN_Pos 0 -#define MPU_RASR_AP_Pos 0 -#define MPU_RASR_TEX_Pos 0 -#define MPU_RASR_S_Pos 0 -#define MPU_RASR_C_Pos 0 -#define MPU_RASR_B_Pos 0 -#define MPU_RASR_SRD_Pos 0 -#define MPU_RASR_SIZE_Pos 0 -#define MPU_RASR_ENA_Pos 0 - -#endif diff --git a/examples/efm32/tinygecko/olimex-em32-32g880f128-h/miniblink-efm32lib/core_cm3.h b/examples/efm32/tinygecko/olimex-em32-32g880f128-h/miniblink-efm32lib/core_cm3.h deleted file mode 120000 index b7a19ea..0000000 --- a/examples/efm32/tinygecko/olimex-em32-32g880f128-h/miniblink-efm32lib/core_cm3.h +++ /dev/null @@ -1 +0,0 @@ -../../efm32-tg-stk3300/miniblink-efm32lib/core_cm3.h \ No newline at end of file diff --git a/examples/efm32/tinygecko/olimex-em32-32g880f128-h/test-efm32lib/core_cm3.c b/examples/efm32/tinygecko/olimex-em32-32g880f128-h/test-efm32lib/core_cm3.c deleted file mode 100644 index 8b412ad..0000000 --- a/examples/efm32/tinygecko/olimex-em32-32g880f128-h/test-efm32lib/core_cm3.c +++ /dev/null @@ -1,8 +0,0 @@ -#include "core_cm3.h" - -/* stubs for efm32_cmu.c */ -uint32_t SystemCoreClockGet(void) {return 1;} -uint32_t SystemHFClockGet(void) {return 1;} - -uint32_t SystemLFRCOClockGet(void) {return 1;} -uint32_t SystemLFXOClockGet(void) {return 1;} diff --git a/examples/efm32/tinygecko/olimex-em32-32g880f128-h/test-efm32lib/core_cm3.h b/examples/efm32/tinygecko/olimex-em32-32g880f128-h/test-efm32lib/core_cm3.h deleted file mode 120000 index b7a19ea..0000000 --- a/examples/efm32/tinygecko/olimex-em32-32g880f128-h/test-efm32lib/core_cm3.h +++ /dev/null @@ -1 +0,0 @@ -../../efm32-tg-stk3300/miniblink-efm32lib/core_cm3.h \ No newline at end of file diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h new file mode 100644 index 0000000..999fc48 --- /dev/null +++ b/include/libopencmsis/core_cm3.h @@ -0,0 +1,100 @@ +#ifndef OPENCMSIS_CORECM3_H +#define OPENCMSIS_CORECM3_H + +/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant of the symbols efm32lib needs of CMSIS. */ +#include + +/* needed by system_efm32.h:196, guessing */ +#define __INLINE inline + +/* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the + * libopencm3 ones, "volatile" is all that's missing. */ +#define __IO volatile +#define __O volatile +#define __I volatile + +/* -> style access for what is defined in libopencm3/stm32/f1/scb.h / + * cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */ + +/* from stm32/f1/scb.h */ +#define SCB_SCR_SLEEPDEEP_Msk (1 << 2) +/* structure as in, for example, + * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from + * libopencm3/stm32/f1/scb.h. incomplete. */ +typedef struct +{ + __IO uint32_t CPUID; + __IO uint32_t ICSR; + __IO uint32_t VTOR; + __IO uint32_t AIRCR; + __IO uint32_t SCR; + __IO uint32_t CCR; + __IO uint8_t SHPR[12]; /* FIXME: how is this properly indexed? */ + __IO uint32_t SHCSR; +} SCB_TypeDef; +#define SCB ((SCB_TypeDef *) SCB_BASE) +/* from libopencm3/cm3/memorymap.h */ +#define PPBI_BASE 0xE0000000 +#define SCS_BASE (PPBI_BASE + 0xE000) +#define SCB_BASE (SCS_BASE + 0x0D00) + +/* needed by efm32_emu.h, guessing and taking the implementation used in + * lightswitch-interrupt.c */ +#define __WFI() __asm__("wfi") + +/* needed by efm32_cmu.h, probably it's just what gcc provides anyway */ +#define __CLZ(div) __builtin_clz(div) + +/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 */ +#define __REV(x) __builtin_bswap32(x) + +/* stubs for efm32_cmu.c */ +#define SystemCoreClockGet() 1 +#define SystemHFClockGet() 1 + +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemLFXOClockGet(void); + +/* stubs for efm32_dbg.h */ +typedef struct +{ + uint32_t DHCSR; +} CoreDebug_TypeDef; +#define CoreDebug ((CoreDebug_TypeDef *) 0) +#define CoreDebug_DHCSR_C_DEBUGEN_Msk 0 + +/* stubs for efm32_dma */ + +#define NVIC_ClearPendingIRQ(irq) 1 +#define NVIC_EnableIRQ(irq) 1 +#define NVIC_DisableIRQ(irq) 1 + +/* stubs for efm32_int */ + +#define __enable_irq() 1 +#define __disable_irq() 1 + +/* stubs for efm32_mpu */ + +#define SCB_SHCSR_MEMFAULTENA_Msk 0 + +typedef struct +{ + uint32_t CTRL; + uint32_t RNR; + uint32_t RBAR; + uint32_t RASR; +} MPU_TypeDef; +#define MPU ((MPU_TypeDef *) 0) +#define MPU_CTRL_ENABLE_Msk 0 +#define MPU_RASR_XN_Pos 0 +#define MPU_RASR_AP_Pos 0 +#define MPU_RASR_TEX_Pos 0 +#define MPU_RASR_S_Pos 0 +#define MPU_RASR_C_Pos 0 +#define MPU_RASR_B_Pos 0 +#define MPU_RASR_SRD_Pos 0 +#define MPU_RASR_SIZE_Pos 0 +#define MPU_RASR_ENA_Pos 0 + +#endif -- cgit v1.2.3 From 286af7f26e756cf47eac75f441f17012cedce44b Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 27 Apr 2012 14:10:29 +0200 Subject: new requirements form emlib and -examples --- include/libopencmsis/core_cm3.h | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index 999fc48..f27d781 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -6,6 +6,8 @@ /* needed by system_efm32.h:196, guessing */ #define __INLINE inline +/* new since emlib 3.0 */ +#define __STATIC_INLINE static inline /* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the * libopencm3 ones, "volatile" is all that's missing. */ @@ -48,20 +50,15 @@ typedef struct /* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 */ #define __REV(x) __builtin_bswap32(x) -/* stubs for efm32_cmu.c */ -#define SystemCoreClockGet() 1 -#define SystemHFClockGet() 1 - -uint32_t SystemLFRCOClockGet(void); -uint32_t SystemLFXOClockGet(void); - /* stubs for efm32_dbg.h */ typedef struct { uint32_t DHCSR; + uint32_t DEMCR; /* needed by efm32tg stk trace.c */ } CoreDebug_TypeDef; #define CoreDebug ((CoreDebug_TypeDef *) 0) #define CoreDebug_DHCSR_C_DEBUGEN_Msk 0 +#define CoreDebug_DEMCR_TRCENA_Msk 0 /* stubs for efm32_dma */ @@ -95,6 +92,18 @@ typedef struct #define MPU_RASR_B_Pos 0 #define MPU_RASR_SRD_Pos 0 #define MPU_RASR_SIZE_Pos 0 -#define MPU_RASR_ENA_Pos 0 +#define MPU_RASR_ENABLE_Pos 0 + +/* required for the blink example */ + +#define SysTick_Config(x) 0 + +/* stubs for efm32tg stk trace.c */ +typedef struct +{ + uint32_t LAR; + uint32_t TCR; +} ITM_TypeDef; +#define ITM ((ITM_TypeDef *) 0) #endif -- cgit v1.2.3 From c9b074a120baea1af4fa15fd678a3f1635fe4daa Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 27 Apr 2012 15:21:59 +0200 Subject: sys tick cmsis interface for blink example --- include/libopencmsis/core_cm3.h | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index f27d781..708fd48 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -96,7 +96,41 @@ typedef struct /* required for the blink example */ -#define SysTick_Config(x) 0 +/* if if (SysTick_Config(CMU_ClockFreqGet(cmuClock_CORE) / 1000)) while (1) ; + * configures the sys ticks to 1ms, then the argument to SysTick_Config + * describes how many cycles to wait between two systicks. + * + * the endless loop part looks like an "if it returns an error condition, + * rather loop here than continue"; every other solution would involve things + * that are dark magic to my understanding. + * + * implementation more or less copypasted from lib/stm32/systick.c, FIXME until + * the generic cm3 functionality is moved out from stm32 and can be used here + * easily (systick_set_reload, systick_interrupt_enable, systick_counter_enable + * and systick_set_clocksource). + * */ +#define SYS_TICK_BASE (SCS_BASE + 0x0010) +#define MMIO32(addr) (*(volatile uint32_t *)(addr)) +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) +#define STK_CTRL_TICKINT (1 << 1) +#define STK_CTRL_ENABLE (1 << 0) + +#define STK_CTRL_CLKSOURCE_LSB 2 +#define STK_CTRL_CLKSOURCE_AHB 1 +static inline uint32_t SysTick_Config(uint32_t n_ticks) +{ + if (n_ticks & ~0x00FFFFFF) return 1; + STK_LOAD = n_ticks; + + STK_CTRL |= (STK_CTRL_CLKSOURCE_AHB << STK_CTRL_CLKSOURCE_LSB); + + STK_CTRL |= STK_CTRL_TICKINT; + + STK_CTRL |= STK_CTRL_ENABLE; + + return 0; +} /* stubs for efm32tg stk trace.c */ typedef struct @@ -106,4 +140,9 @@ typedef struct } ITM_TypeDef; #define ITM ((ITM_TypeDef *) 0) +/* blink.h expects the isr for systicks to be named SysTick_Handler. with this, + * its Systick_Handler function gets renamed to the weak symbol exported by + * vector.c */ +#define SysTick_Handler sys_tick_handler + #endif -- cgit v1.2.3 From dfbb7912c35184b25953e33da0b7c31a44fc6a91 Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 27 Apr 2012 15:55:43 +0200 Subject: additions to opencmsis to make the clock example run --- include/libopencmsis/core_cm3.h | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index 708fd48..ddff8a1 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -1,6 +1,9 @@ #ifndef OPENCMSIS_CORECM3_H #define OPENCMSIS_CORECM3_H +/* needed in various places where we rather should include libopencm3 functionality */ +#define MMIO32(addr) (*(volatile uint32_t *)(addr)) + /* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant of the symbols efm32lib needs of CMSIS. */ #include @@ -62,9 +65,25 @@ typedef struct /* stubs for efm32_dma */ -#define NVIC_ClearPendingIRQ(irq) 1 -#define NVIC_EnableIRQ(irq) 1 -#define NVIC_DisableIRQ(irq) 1 +/* also used by the clock example. code taken from stm32's nvic.[hc], FIXME until + * the generic cm3 functionality is moved out from stm32 and can be used here + * easily (nvic_clear_pending_irq, nvic_enable_irq, nvic_disable_irq). */ +#define NVIC_BASE (SCS_BASE + 0x0100) +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) +static inline void NVIC_ClearPendingIRQ(uint8_t irqn) +{ + NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); +} +static inline void NVIC_EnableIRQ(uint8_t irqn) +{ + NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); +} +static inline void NVIC_DisableIRQ(uint8_t irqn) +{ + NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); +} /* stubs for efm32_int */ @@ -110,7 +129,6 @@ typedef struct * and systick_set_clocksource). * */ #define SYS_TICK_BASE (SCS_BASE + 0x0010) -#define MMIO32(addr) (*(volatile uint32_t *)(addr)) #define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) #define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) #define STK_CTRL_TICKINT (1 << 1) @@ -145,4 +163,9 @@ typedef struct * vector.c */ #define SysTick_Handler sys_tick_handler +/* likewise, clock.c defines GPIO_ODD_IRQHandler and GPIO_EVEN_IRQHandler */ +#define GPIO_ODD_IRQHandler gpio_odd_isr +#define GPIO_EVEN_IRQHandler gpio_even_isr +#define RTC_IRQHandler rtc_isr + #endif -- cgit v1.2.3 From 4a36d23d8c35a564337ac0dcf9de4f80ced0990b Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 27 Apr 2012 17:00:24 +0200 Subject: more irq/isr translations --- include/libopencmsis/core_cm3.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index ddff8a1..8de7c8b 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -168,4 +168,8 @@ typedef struct #define GPIO_EVEN_IRQHandler gpio_even_isr #define RTC_IRQHandler rtc_isr +/* for inttemp (i should really get a list and convert them all) */ + +#define ADC0_IRQHandler adc0_isr + #endif -- cgit v1.2.3 From 9324f00038c48e9522559c6e936e6d35aca65fad Mon Sep 17 00:00:00 2001 From: chrysn Date: Sun, 29 Apr 2012 00:18:03 +0200 Subject: enhanced cmsis again for other efm32tg examples --- include/libopencmsis/core_cm3.h | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index 8de7c8b..1f68464 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -127,10 +127,21 @@ typedef struct * the generic cm3 functionality is moved out from stm32 and can be used here * easily (systick_set_reload, systick_interrupt_enable, systick_counter_enable * and systick_set_clocksource). + * + * modified for CMSIS style array as the powertest example needs it. * */ #define SYS_TICK_BASE (SCS_BASE + 0x0010) -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */ +typedef struct +{ + uint32_t CTRL; + uint32_t LOAD; + uint32_t VAL; + uint32_t CALIB; +} SysTick_TypeDef; +#define SysTick ((SysTick_TypeDef *) SYS_TICK_BASE) + #define STK_CTRL_TICKINT (1 << 1) #define STK_CTRL_ENABLE (1 << 0) @@ -139,13 +150,13 @@ typedef struct static inline uint32_t SysTick_Config(uint32_t n_ticks) { if (n_ticks & ~0x00FFFFFF) return 1; - STK_LOAD = n_ticks; + SysTick->LOAD = n_ticks; - STK_CTRL |= (STK_CTRL_CLKSOURCE_AHB << STK_CTRL_CLKSOURCE_LSB); + SysTick->CTRL |= (STK_CTRL_CLKSOURCE_AHB << STK_CTRL_CLKSOURCE_LSB); - STK_CTRL |= STK_CTRL_TICKINT; + SysTick->CTRL |= STK_CTRL_TICKINT; - STK_CTRL |= STK_CTRL_ENABLE; + SysTick->CTRL |= STK_CTRL_ENABLE; return 0; } @@ -172,4 +183,9 @@ typedef struct #define ADC0_IRQHandler adc0_isr +/* for the lightsense example */ + +#define LESENSE_IRQHandler lesense_isr +#define PCNT0_IRQHandler pcnt0_isr + #endif -- cgit v1.2.3 From 99975d9a058690f6faa3077dccadbdd5353db4fe Mon Sep 17 00:00:00 2001 From: chrysn Date: Sun, 29 Apr 2012 03:05:27 +0200 Subject: comment updates --- include/libopencmsis/core_cm3.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index 1f68464..5ad1327 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -1,3 +1,9 @@ +/* big fat FIXME: this should use a consistent structure, and reference + * functionality from libopencm3 instead of copypasting. + * + * particularly unimplemented features are FIXME'd extra + * */ + #ifndef OPENCMSIS_CORECM3_H #define OPENCMSIS_CORECM3_H @@ -25,7 +31,7 @@ #define SCB_SCR_SLEEPDEEP_Msk (1 << 2) /* structure as in, for example, * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from - * libopencm3/stm32/f1/scb.h. incomplete. */ + * libopencm3/stm32/f1/scb.h. FIXME incomplete. */ typedef struct { __IO uint32_t CPUID; @@ -59,6 +65,7 @@ typedef struct uint32_t DHCSR; uint32_t DEMCR; /* needed by efm32tg stk trace.c */ } CoreDebug_TypeDef; +/* FIXME let's just hope writes to flash are protected */ #define CoreDebug ((CoreDebug_TypeDef *) 0) #define CoreDebug_DHCSR_C_DEBUGEN_Msk 0 #define CoreDebug_DEMCR_TRCENA_Msk 0 @@ -85,12 +92,13 @@ static inline void NVIC_DisableIRQ(uint8_t irqn) NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); } -/* stubs for efm32_int */ +/* stubs for efm32_int. FIXME: how do they do that? nvic documentation in the + * efm32 core manual doesn't tell anything of a global on/off switch */ #define __enable_irq() 1 #define __disable_irq() 1 -/* stubs for efm32_mpu */ +/* stubs for efm32_mpu FIXME */ #define SCB_SHCSR_MEMFAULTENA_Msk 0 @@ -101,6 +109,7 @@ typedef struct uint32_t RBAR; uint32_t RASR; } MPU_TypeDef; +/* FIXME struct at NULL */ #define MPU ((MPU_TypeDef *) 0) #define MPU_CTRL_ENABLE_Msk 0 #define MPU_RASR_XN_Pos 0 @@ -167,6 +176,7 @@ typedef struct uint32_t LAR; uint32_t TCR; } ITM_TypeDef; +/* FIXME struct at NULL */ #define ITM ((ITM_TypeDef *) 0) /* blink.h expects the isr for systicks to be named SysTick_Handler. with this, -- cgit v1.2.3 From 34beeae925798dc49ad79f2f8c47aeaee7d8262a Mon Sep 17 00:00:00 2001 From: Jason Kotzin Date: Thu, 16 Aug 2012 18:50:38 -0700 Subject: USB core updated for reentrance based on Christian Cier-Zniewski's branch --- examples/stm32/f1/lisa-m-1/usb_cdcacm/cdcacm.c | 28 +- examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c | 18 +- examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c | 29 +- examples/stm32/f1/other/usb_cdcacm/cdcacm.c | 28 +- examples/stm32/f1/other/usb_dfu/usbdfu.c | 18 +- examples/stm32/f1/other/usb_hid/usbhid.c | 30 +- examples/stm32/f1/stm32-h103/usb_cdcacm/cdcacm.c | 36 +- examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c | 22 +- examples/stm32/f1/stm32-h103/usb_hid/usbhid.c | 32 +- examples/stm32/f1/stm32-h103/usb_iap/usbiap.c | 22 +- .../stm32/f1/stm32-h107/usb_simple/usb_simple.c | 14 +- .../stm32/f4/stm32f4-discovery/usb_cdcacm/cdcacm.c | 32 +- include/libopencm3/stm32/otg_fs.h | 105 +++--- include/libopencm3/stm32/otg_hs.h | 396 +++++++++++++++++++++ include/libopencm3/usb/cdc.h | 2 +- include/libopencm3/usb/usbd.h | 60 ++-- lib/stm32/f1/Makefile | 2 +- lib/stm32/f4/Makefile | 3 +- lib/usb/usb.c | 105 +++--- lib/usb/usb_control.c | 194 +++++----- lib/usb/usb_f103.c | 99 +++--- lib/usb/usb_f107.c | 338 ++---------------- lib/usb/usb_f207.c | 91 +++++ lib/usb/usb_fx07_common.c | 318 +++++++++++++++++ lib/usb/usb_fx07_common.h | 38 ++ lib/usb/usb_private.h | 81 +++-- lib/usb/usb_standard.c | 129 ++++--- 27 files changed, 1497 insertions(+), 773 deletions(-) create mode 100644 include/libopencm3/stm32/otg_hs.h create mode 100644 lib/usb/usb_f207.c create mode 100644 lib/usb/usb_fx07_common.c create mode 100644 lib/usb/usb_fx07_common.h (limited to 'include') diff --git a/examples/stm32/f1/lisa-m-1/usb_cdcacm/cdcacm.c b/examples/stm32/f1/lisa-m-1/usb_cdcacm/cdcacm.c index 7ef9b62..08efa46 100644 --- a/examples/stm32/f1/lisa-m-1/usb_cdcacm/cdcacm.c +++ b/examples/stm32/f1/lisa-m-1/usb_cdcacm/cdcacm.c @@ -164,11 +164,12 @@ static const char *usb_strings[] = { "DEMO", }; -static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int cdcacm_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)complete; (void)buf; + (void)usbd_dev; switch (req->bRequest) { case USB_CDC_REQ_SET_CONTROL_LINE_STATE: { @@ -200,15 +201,15 @@ static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, return 0; } -static void cdcacm_data_rx_cb(u8 ep) +static void cdcacm_data_rx_cb(usbd_device *usbd_dev, u8 ep) { (void)ep; char buf[64]; - int len = usbd_ep_read_packet(0x01, buf, 64); + int len = usbd_ep_read_packet(usbd_dev, 0x01, buf, 64); if (len) { - while (usbd_ep_write_packet(0x82, buf, len) == 0) + while (usbd_ep_write_packet(usbd_dev, 0x82, buf, len) == 0) ; buf[len] = 0; } @@ -216,15 +217,16 @@ static void cdcacm_data_rx_cb(u8 ep) gpio_toggle(GPIOC, GPIO5); } -static void cdcacm_set_config(u16 wValue) +static void cdcacm_set_config(usbd_device *usbd_dev, u16 wValue) { (void)wValue; - usbd_ep_setup(0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); - usbd_ep_setup(0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); - usbd_ep_setup(0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + usbd_ep_setup(usbd_dev, 0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); + usbd_ep_setup(usbd_dev, 0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); + usbd_ep_setup(usbd_dev, 0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, cdcacm_control_request); @@ -234,6 +236,8 @@ int main(void) { int i; + usbd_device *usbd_dev; + rcc_clock_setup_in_hsi_out_48mhz(); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); @@ -246,13 +250,13 @@ int main(void) gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO5); - usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(cdcacm_set_config); + usbd_dev = usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(usbd_dev, cdcacm_set_config); for (i = 0; i < 0x800000; i++) __asm__("nop"); gpio_clear(GPIOC, GPIO2); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } diff --git a/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c b/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c index 4ffc0a1..71a9ac5 100644 --- a/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c @@ -130,10 +130,11 @@ static u8 usbdfu_getstatus(u32 *bwPollTimeout) } } -static void usbdfu_getstatus_complete(struct usb_setup_data *req) +static void usbdfu_getstatus_complete(usbd_device *usbd_dev, struct usb_setup_data *req) { int i; (void)req; + (void)usbd_dev; switch (usbdfu_state) { case STATE_DFU_DNBUSY: @@ -166,9 +167,11 @@ static void usbdfu_getstatus_complete(struct usb_setup_data *req) } } -static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int usbdfu_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { + (void)usbd_dev; + if ((req->bmRequestType & 0x7F) != 0x21) return 0; /* Only accept class request. */ @@ -221,6 +224,8 @@ static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, int main(void) { + usbd_device *usbd_dev; + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); if (!gpio_get(GPIOA, GPIO10)) { @@ -245,9 +250,10 @@ int main(void) gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO2); - usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); - usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); + usbd_dev = usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); + usbd_set_control_buffer_size(usbd_dev, sizeof(usbd_control_buffer)); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, usbdfu_control_request); @@ -255,5 +261,5 @@ int main(void) gpio_clear(GPIOC, GPIO2); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } diff --git a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c index 8d83896..9ef3f56 100644 --- a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c +++ b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c @@ -36,6 +36,8 @@ #include #endif +static usbd_device *usbd_dev; + const struct usb_device_descriptor dev = { .bLength = USB_DT_DEVICE_SIZE, .bDescriptorType = USB_DT_DEVICE, @@ -173,10 +175,11 @@ static const char *usb_strings[] = { "DEMO", }; -static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) +static int hid_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)complete; + (void)usbd_dev; if((req->bmRequestType != 0x81) || (req->bRequest != USB_REQ_GET_DESCRIPTOR) || @@ -191,9 +194,10 @@ static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, } #ifdef INCLUDE_DFU_INTERFACE -static void dfu_detach_complete(struct usb_setup_data *req) +static void dfu_detach_complete(usbd_device *usbd_dev, struct usb_setup_data *req) { (void)req; + (void)usbd_dev; gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, @@ -202,11 +206,12 @@ static void dfu_detach_complete(struct usb_setup_data *req) scb_reset_core(); } -static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) +static int dfu_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)buf; (void)len; + (void)usbd_dev; if ((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) return 0; /* Only accept class request. */ @@ -217,18 +222,20 @@ static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, } #endif -static void hid_set_config(u16 wValue) +static void hid_set_config(usbd_device *usbd_dev, u16 wValue) { (void)wValue; - usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); + usbd_ep_setup(usbd_dev, 0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, hid_control_request); #ifdef INCLUDE_DFU_INTERFACE usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, dfu_control_request); @@ -329,8 +336,8 @@ int main(void) gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO2); - usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(hid_set_config); + usbd_dev = usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(usbd_dev, hid_set_config); /* Delay some seconds to show that pull-up switch works. */ for (i = 0; i < 0x800000; i++) @@ -345,7 +352,7 @@ int main(void) // OTG_FS_GCCFG &= ~OTG_FS_GCCFG_VBUSBSEN; while (1) - usbd_poll(); + usbd_poll(usbd_dev); } void sys_tick_handler(void) @@ -357,5 +364,5 @@ void sys_tick_handler(void) buf[1] = x >> 9; buf[2] = y >> 9; - usbd_ep_write_packet(0x81, buf, 4); + usbd_ep_write_packet(usbd_dev, 0x81, buf, 4); } diff --git a/examples/stm32/f1/other/usb_cdcacm/cdcacm.c b/examples/stm32/f1/other/usb_cdcacm/cdcacm.c index 2038664..81250b5 100644 --- a/examples/stm32/f1/other/usb_cdcacm/cdcacm.c +++ b/examples/stm32/f1/other/usb_cdcacm/cdcacm.c @@ -164,11 +164,12 @@ static const char *usb_strings[] = { "DEMO", }; -static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int cdcacm_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)complete; (void)buf; + (void)usbd_dev; switch(req->bRequest) { case USB_CDC_REQ_SET_CONTROL_LINE_STATE: { @@ -200,28 +201,29 @@ static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, return 0; } -static void cdcacm_data_rx_cb(u8 ep) +static void cdcacm_data_rx_cb(usbd_device *usbd_dev, u8 ep) { (void)ep; char buf[64]; - int len = usbd_ep_read_packet(0x01, buf, 64); + int len = usbd_ep_read_packet(usbd_dev, 0x01, buf, 64); if (len) { - usbd_ep_write_packet(0x82, buf, len); + usbd_ep_write_packet(usbd_dev, 0x82, buf, len); buf[len] = 0; } } -static void cdcacm_set_config(u16 wValue) +static void cdcacm_set_config(usbd_device *usbd_dev, u16 wValue) { (void)wValue; - usbd_ep_setup(0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); - usbd_ep_setup(0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); - usbd_ep_setup(0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + usbd_ep_setup(usbd_dev, 0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); + usbd_ep_setup(usbd_dev, 0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); + usbd_ep_setup(usbd_dev, 0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, cdcacm_control_request); @@ -229,6 +231,8 @@ static void cdcacm_set_config(u16 wValue) int main(void) { + usbd_device *usbd_dev; + rcc_clock_setup_in_hsi_out_48mhz(); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); @@ -238,13 +242,13 @@ int main(void) gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(cdcacm_set_config); + usbd_dev = usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(usbd_dev, cdcacm_set_config); gpio_set(GPIOA, GPIO15); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } diff --git a/examples/stm32/f1/other/usb_dfu/usbdfu.c b/examples/stm32/f1/other/usb_dfu/usbdfu.c index 0211a47..5347c9d 100644 --- a/examples/stm32/f1/other/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/other/usb_dfu/usbdfu.c @@ -130,10 +130,11 @@ static u8 usbdfu_getstatus(u32 *bwPollTimeout) } } -static void usbdfu_getstatus_complete(struct usb_setup_data *req) +static void usbdfu_getstatus_complete(usbd_device *usbd_dev, struct usb_setup_data *req) { int i; (void)req; + (void)usbd_dev; switch (usbdfu_state) { case STATE_DFU_DNBUSY: @@ -166,9 +167,11 @@ static void usbdfu_getstatus_complete(struct usb_setup_data *req) } } -static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int usbdfu_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { + (void)usbd_dev; + if ((req->bmRequestType & 0x7F) != 0x21) return 0; /* Only accept class request. */ @@ -221,6 +224,8 @@ static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, int main(void) { + usbd_device *usbd_dev; + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); if (!gpio_get(GPIOA, GPIO10)) { @@ -244,9 +249,10 @@ int main(void) AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); - usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); + usbd_dev = usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); + usbd_set_control_buffer_size(usbd_dev, sizeof(usbd_control_buffer)); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, usbdfu_control_request); @@ -256,5 +262,5 @@ int main(void) GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } diff --git a/examples/stm32/f1/other/usb_hid/usbhid.c b/examples/stm32/f1/other/usb_hid/usbhid.c index dd3c57a..d681da4 100644 --- a/examples/stm32/f1/other/usb_hid/usbhid.c +++ b/examples/stm32/f1/other/usb_hid/usbhid.c @@ -32,6 +32,8 @@ #include #endif +static usbd_device *usbd_dev; + const struct usb_device_descriptor dev = { .bLength = USB_DT_DEVICE_SIZE, .bDescriptorType = USB_DT_DEVICE, @@ -169,10 +171,11 @@ static const char *usb_strings[] = { "DEMO", }; -static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) +static int hid_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)complete; + (void)usbd_dev; if((req->bmRequestType != 0x81) || (req->bRequest != USB_REQ_GET_DESCRIPTOR) || @@ -187,9 +190,10 @@ static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, } #ifdef INCLUDE_DFU_INTERFACE -static void dfu_detach_complete(struct usb_setup_data *req) +static void dfu_detach_complete(usbd_device *usbd_dev, struct usb_setup_data *req) { (void)req; + (void)usbd_dev; gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, @@ -198,11 +202,12 @@ static void dfu_detach_complete(struct usb_setup_data *req) scb_reset_core(); } -static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) +static int dfu_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)buf; (void)len; + (void)usbd_dev; if ((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) return 0; /* Only accept class request. */ @@ -213,18 +218,21 @@ static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, } #endif -static void hid_set_config(u16 wValue) +static void hid_set_config(usbd_device *usbd_dev, u16 wValue) { (void)wValue; + (void)usbd_dev; - usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); + usbd_ep_setup(usbd_dev, 0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, hid_control_request); #ifdef INCLUDE_DFU_INTERFACE usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, dfu_control_request); @@ -246,15 +254,15 @@ int main(void) AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(hid_set_config); + usbd_dev = usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(usbd_dev, hid_set_config); gpio_set(GPIOA, GPIO15); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } void sys_tick_handler(void) @@ -270,5 +278,5 @@ void sys_tick_handler(void) if (x < -30) dir = -dir; - usbd_ep_write_packet(0x81, buf, 4); + usbd_ep_write_packet(usbd_dev, 0x81, buf, 4); } diff --git a/examples/stm32/f1/stm32-h103/usb_cdcacm/cdcacm.c b/examples/stm32/f1/stm32-h103/usb_cdcacm/cdcacm.c index 779f659..3d25c29 100644 --- a/examples/stm32/f1/stm32-h103/usb_cdcacm/cdcacm.c +++ b/examples/stm32/f1/stm32-h103/usb_cdcacm/cdcacm.c @@ -41,7 +41,7 @@ static const struct usb_device_descriptor dev = { }; /* - * This notification endpoint isn't implemented. According to CDC spec its + * This notification endpoint isn't implemented. According to CDC spec its * optional, but its absence causes a NULL pointer dereference in Linux * cdc_acm driver. */ @@ -83,7 +83,7 @@ static const struct { .bcdCDC = 0x0110, }, .call_mgmt = { - .bFunctionLength = + .bFunctionLength = sizeof(struct usb_cdc_call_management_descriptor), .bDescriptorType = CS_INTERFACE, .bDescriptorSubtype = USB_CDC_TYPE_CALL_MANAGEMENT, @@ -101,7 +101,7 @@ static const struct { .bDescriptorType = CS_INTERFACE, .bDescriptorSubtype = USB_CDC_TYPE_UNION, .bControlInterface = 0, - .bSubordinateInterface0 = 1, + .bSubordinateInterface0 = 1, }, }; @@ -164,11 +164,12 @@ static const char *usb_strings[] = { "DEMO", }; -static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int cdcacm_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)complete; (void)buf; + (void)usbd_dev; switch (req->bRequest) { case USB_CDC_REQ_SET_CONTROL_LINE_STATE: { @@ -199,28 +200,31 @@ static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, return 0; } -static void cdcacm_data_rx_cb(u8 ep) +static void cdcacm_data_rx_cb(usbd_device *usbd_dev, u8 ep) { (void)ep; + (void)usbd_dev; char buf[64]; - int len = usbd_ep_read_packet(0x01, buf, 64); + int len = usbd_ep_read_packet(usbd_dev, 0x01, buf, 64); if (len) { - usbd_ep_write_packet(0x82, buf, len); + usbd_ep_write_packet(usbd_dev, 0x82, buf, len); buf[len] = 0; } } -static void cdcacm_set_config(u16 wValue) +static void cdcacm_set_config(usbd_device *usbd_dev, u16 wValue) { (void)wValue; + (void)usbd_dev; - usbd_ep_setup(0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); - usbd_ep_setup(0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); - usbd_ep_setup(0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + usbd_ep_setup(usbd_dev, 0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); + usbd_ep_setup(usbd_dev, 0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); + usbd_ep_setup(usbd_dev, 0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, cdcacm_control_request); @@ -230,6 +234,8 @@ int main(void) { int i; + usbd_device *usbd_dev; + rcc_clock_setup_in_hsi_out_48mhz(); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); @@ -238,13 +244,13 @@ int main(void) gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(cdcacm_set_config); + usbd_dev = usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(usbd_dev, cdcacm_set_config); for (i = 0; i < 0x800000; i++) __asm__("nop"); gpio_clear(GPIOC, GPIO11); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } diff --git a/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c b/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c index 49f265b..6282c4b 100644 --- a/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c @@ -114,8 +114,10 @@ static const char *usb_strings[] = { "@Internal Flash /0x08000000/8*001Ka,56*001Kg", }; -static u8 usbdfu_getstatus(u32 *bwPollTimeout) +static u8 usbdfu_getstatus(usbd_device *usbd_dev, u32 *bwPollTimeout) { + (void)usbd_dev; + switch (usbdfu_state) { case STATE_DFU_DNLOAD_SYNC: usbdfu_state = STATE_DFU_DNBUSY; @@ -130,10 +132,11 @@ static u8 usbdfu_getstatus(u32 *bwPollTimeout) } } -static void usbdfu_getstatus_complete(struct usb_setup_data *req) +static void usbdfu_getstatus_complete(usbd_device *usbd_dev, struct usb_setup_data *req) { int i; (void)req; + (void)usbd_dev; switch (usbdfu_state) { case STATE_DFU_DNBUSY: @@ -166,8 +169,8 @@ static void usbdfu_getstatus_complete(struct usb_setup_data *req) } } -static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int usbdfu_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { if ((req->bmRequestType & 0x7F) != 0x21) return 0; /* Only accept class request. */ @@ -199,7 +202,7 @@ static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, return 0; case DFU_GETSTATUS: { u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ - (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); + (*buf)[0] = usbdfu_getstatus(usbd_dev, &bwPollTimeout); (*buf)[1] = bwPollTimeout & 0xFF; (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; @@ -221,6 +224,8 @@ static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, int main(void) { + usbd_device *usbd_dev; + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); if (!gpio_get(GPIOA, GPIO10)) { @@ -244,9 +249,10 @@ int main(void) GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); gpio_set(GPIOC, GPIO11); - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); + usbd_dev = usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_set_control_buffer_size(usbd_dev, sizeof(usbd_control_buffer)); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, usbdfu_control_request); @@ -254,5 +260,5 @@ int main(void) gpio_clear(GPIOC, GPIO11); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } diff --git a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c index 9ed40d1..558e68d 100644 --- a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c +++ b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c @@ -169,10 +169,11 @@ static const char *usb_strings[] = { "DEMO", }; -static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) +static int hid_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)complete; + (void)usbd_dev; if ((req->bmRequestType != 0x81) || (req->bRequest != USB_REQ_GET_DESCRIPTOR) || @@ -187,9 +188,10 @@ static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, } #ifdef INCLUDE_DFU_INTERFACE -static void dfu_detach_complete(struct usb_setup_data *req) +static void dfu_detach_complete(usbd_device *usbd_dev, struct usb_setup_data *req) { (void)req; + (void)usbd_dev; gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, @@ -198,11 +200,12 @@ static void dfu_detach_complete(struct usb_setup_data *req) scb_reset_core(); } -static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) +static int dfu_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)buf; (void)len; + (void)usbd_dev; if ((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) return 0; /* Only accept class request. */ @@ -213,18 +216,21 @@ static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, } #endif -static void hid_set_config(u16 wValue) +static void hid_set_config(usbd_device *usbd_dev, u16 wValue) { (void)wValue; + (void)usbd_dev; - usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); + usbd_ep_setup(usbd_dev, 0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, hid_control_request); #ifdef INCLUDE_DFU_INTERFACE usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, dfu_control_request); @@ -240,6 +246,8 @@ int main(void) { int i; + usbd_device *usbd_dev; + rcc_clock_setup_in_hsi_out_48mhz(); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); @@ -248,8 +256,8 @@ int main(void) gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(hid_set_config); + usbd_dev = usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(usbd_dev, hid_set_config); for (i = 0; i < 0x80000; i++) __asm__("nop"); @@ -257,9 +265,10 @@ int main(void) gpio_clear(GPIOC, GPIO11); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } +#if 0 /* is this used? */ void sys_tick_handler(void) { static int x = 0; @@ -273,5 +282,6 @@ void sys_tick_handler(void) if (x < -30) dir = -dir; - usbd_ep_write_packet(0x81, buf, 4); + usbd_ep_write_packet(usbd_dev, 0x81, buf, 4); } +#endif diff --git a/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c b/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c index c5cc8ba..de3d6a3 100644 --- a/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c +++ b/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c @@ -114,8 +114,10 @@ static const char *usb_strings[] = { "@Internal Flash /0x08000000/8*001Ka,56*001Kg", }; -static u8 usbdfu_getstatus(u32 *bwPollTimeout) +static u8 usbdfu_getstatus(usbd_device *usbd_dev, u32 *bwPollTimeout) { + (void)usbd_dev; + switch (usbdfu_state) { case STATE_DFU_DNLOAD_SYNC: usbdfu_state = STATE_DFU_DNBUSY; @@ -130,10 +132,11 @@ static u8 usbdfu_getstatus(u32 *bwPollTimeout) } } -static void usbdfu_getstatus_complete(struct usb_setup_data *req) +static void usbdfu_getstatus_complete(usbd_device *usbd_dev, struct usb_setup_data *req) { int i; (void)req; + (void)usbd_dev; switch (usbdfu_state) { case STATE_DFU_DNBUSY: @@ -166,8 +169,8 @@ static void usbdfu_getstatus_complete(struct usb_setup_data *req) } } -static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int usbdfu_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { if ((req->bmRequestType & 0x7F) != 0x21) return 0; /* Only accept class request. */ @@ -199,7 +202,7 @@ static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, return 0; case DFU_GETSTATUS: { u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ - (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); + (*buf)[0] = usbdfu_getstatus(usbd_dev, &bwPollTimeout); (*buf)[1] = bwPollTimeout & 0xFF; (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; @@ -221,6 +224,8 @@ static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, int main(void) { + usbd_device *usbd_dev; + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); if (!gpio_get(GPIOA, GPIO10)) { @@ -244,9 +249,10 @@ int main(void) AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); + usbd_dev = usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_set_control_buffer_size(usbd_dev, sizeof(usbd_control_buffer)); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, usbdfu_control_request); @@ -256,5 +262,5 @@ int main(void) GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } diff --git a/examples/stm32/f1/stm32-h107/usb_simple/usb_simple.c b/examples/stm32/f1/stm32-h107/usb_simple/usb_simple.c index e9a52b2..fc0aecd 100644 --- a/examples/stm32/f1/stm32-h107/usb_simple/usb_simple.c +++ b/examples/stm32/f1/stm32-h107/usb_simple/usb_simple.c @@ -75,16 +75,17 @@ const char *usb_strings[] = { "1001", }; -static int simple_control_callback(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int simple_control_callback(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)buf; (void)len; (void)complete; + (void)usbd_dev; if (req->bmRequestType != 0x40) return 0; /* Only accept vendor request. */ - + if (req->wValue & 1) gpio_set(GPIOC, GPIO6); else @@ -95,6 +96,8 @@ static int simple_control_callback(struct usb_setup_data *req, u8 **buf, int main(void) { + usbd_device *usbd_dev; + rcc_clock_setup_in_hse_8mhz_out_72mhz(); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); @@ -105,13 +108,14 @@ int main(void) gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); + usbd_dev = usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_VENDOR, USB_REQ_TYPE_TYPE, simple_control_callback); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } diff --git a/examples/stm32/f4/stm32f4-discovery/usb_cdcacm/cdcacm.c b/examples/stm32/f4/stm32f4-discovery/usb_cdcacm/cdcacm.c index 4af1039..1a12267 100644 --- a/examples/stm32/f4/stm32f4-discovery/usb_cdcacm/cdcacm.c +++ b/examples/stm32/f4/stm32f4-discovery/usb_cdcacm/cdcacm.c @@ -22,6 +22,7 @@ #include #include #include +#include static const struct usb_device_descriptor dev = { .bLength = USB_DT_DEVICE_SIZE, @@ -164,11 +165,12 @@ static const char *usb_strings[] = { "DEMO", }; -static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) +static int cdcacm_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)) { (void)complete; (void)buf; + (void)usbd_dev; switch (req->bRequest) { case USB_CDC_REQ_SET_CONTROL_LINE_STATE: { @@ -188,30 +190,31 @@ static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, return 0; } -static void cdcacm_data_rx_cb(u8 ep) +static void cdcacm_data_rx_cb(usbd_device *usbd_dev, u8 ep) { (void)ep; char buf[64]; - int len = usbd_ep_read_packet(0x01, buf, 64); + int len = usbd_ep_read_packet(usbd_dev, 0x01, buf, 64); if (len) { - while (usbd_ep_write_packet(0x82, buf, len) == 0) + while (usbd_ep_write_packet(usbd_dev, 0x82, buf, len) == 0) ; } gpio_toggle(GPIOC, GPIO5); } -static void cdcacm_set_config(u16 wValue) +static void cdcacm_set_config(usbd_device *usbd_dev, u16 wValue) { (void)wValue; - usbd_ep_setup(0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); - usbd_ep_setup(0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); - usbd_ep_setup(0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + usbd_ep_setup(usbd_dev, 0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); + usbd_ep_setup(usbd_dev, 0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); + usbd_ep_setup(usbd_dev, 0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); usbd_register_control_callback( + usbd_dev, USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, cdcacm_control_request); @@ -219,19 +222,20 @@ static void cdcacm_set_config(u16 wValue) int main(void) { + usbd_device *usbd_dev; + rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_120MHZ]); rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN); rcc_peripheral_enable_clock(&RCC_AHB2ENR, RCC_AHB2ENR_OTGFSEN); - gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9 | GPIO11 | GPIO12); gpio_set_af(GPIOA, GPIO_AF10, GPIO9 | GPIO11 | GPIO12); - usbd_init(&otgfs_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(cdcacm_set_config); + usbd_dev = usbd_init(&otgfs_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(usbd_dev, cdcacm_set_config); while (1) - usbd_poll(); + usbd_poll(usbd_dev); } - diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h index 5680e43..d8ee393 100644 --- a/include/libopencm3/stm32/otg_fs.h +++ b/include/libopencm3/stm32/otg_fs.h @@ -24,7 +24,7 @@ #include /* Core Global Control and Status Registers */ -#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) +#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) #define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) #define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) #define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) @@ -42,40 +42,40 @@ #define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x-1)) /* Host-mode Control and Status Registers */ -#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) -#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) -#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) -#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) -#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) -#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) -#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) -#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) -#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) -#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) -#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) +#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) +#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) +#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) +#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) +#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) +#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) +#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) +#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) +#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) +#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) +#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) /* Device-mode Control and Status Registers */ -#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) -#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) -#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) -#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) -#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) -#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) -#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) -#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) -#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) -#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) -#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) -#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) -#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) -#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) -#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) -#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) -#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) -#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) -#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) -#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) -#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) +#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) +#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) +#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) +#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) +#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) +#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) +#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) +#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) +#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) +#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) +#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) +#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) +#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) +#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) +#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) +#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) +#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) +#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) +#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) +#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) +#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) /* Power and clock gating control and status register */ #define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) @@ -84,6 +84,18 @@ #define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) /* Global CSRs */ +/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */ +#define OTG_FS_GOTGCTL_BSVLD (1 << 19) +#define OTG_FS_GOTGCTL_ASVLD (1 << 18) +#define OTG_FS_GOTGCTL_DBCT (1 << 17) +#define OTG_FS_GOTGCTL_CIDSTS (1 << 16) +#define OTG_FS_GOTGCTL_DHNPEN (1 << 11) +#define OTG_FS_GOTGCTL_HSHNPEN (1 << 10) +#define OTG_FS_GOTGCTL_HNPRQ (1 << 9) +#define OTG_FS_GOTGCTL_HNGSCS (1 << 8) +#define OTG_FS_GOTGCTL_SRQ (1 << 1) +#define OTG_FS_GOTGCTL_SRQSCS (1 << 0) + /* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ #define OTG_FS_GAHBCFG_GINT 0x0001 #define OTG_FS_GAHBCFG_TXFELVL 0x0080 @@ -175,20 +187,20 @@ /* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ /* Bits 31:25 - Reserved */ -#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) -#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) -#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) #define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) -#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) -#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) -#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) -#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) +#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) /* OTG_FS general core configuration register (OTG_FS_GCCFG) */ /* Bits 31:21 - Reserved */ @@ -320,4 +332,3 @@ #define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) #endif - diff --git a/include/libopencm3/stm32/otg_hs.h b/include/libopencm3/stm32/otg_hs.h new file mode 100644 index 0000000..2f59ddd --- /dev/null +++ b/include/libopencm3/stm32/otg_hs.h @@ -0,0 +1,396 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_OTG_HS_H +#define LIBOPENCM3_OTG_HS_H + +#include +#include + +/* Core Global Control and Status Registers */ +#define OTG_GOTGCTL 0x000 +#define OTG_GOTGIN 0x004 +#define OTG_GAHBCFG 0x008 +#define OTG_GUSBCFG 0x00C +#define OTG_GRSTCTL 0x010 +#define OTG_GINTSTS 0x014 +#define OTG_GINTMSK 0x018 +#define OTG_GRXSTSR 0x01C +#define OTG_GRXSTSP 0x020 +#define OTG_GRXFSIZ 0x024 +#define OTG_GNPTXFSIZ 0x028 +#define OTG_GNPTXSTS 0x02C +#define OTG_GCCFG 0x038 +#define OTG_CID 0x03C +#define OTG_HPTXFSIZ 0x100 +#define OTG_DIEPTXF(x) (0x104 + 4*(x-1)) + +/* Host-mode Control and Status Registers */ +#define OTG_HCFG 0x400 +#define OTG_HFIR 0x404 +#define OTG_HFNUM 0x408 +#define OTG_HPTXSTS 0x410 +#define OTG_HAINT 0x414 +#define OTG_HAINTMSK 0x418 +#define OTG_HPRT 0x440 +#define OTG_HCCHARx 0x500 +#define OTG_HCINTx 0x508 +#define OTG_HCINTMSKx 0x50C +#define OTG_HCTSIZx 0x510 + +/* Device-mode Control and Status Registers */ +#define OTG_DCFG 0x800 +#define OTG_DCTL 0x804 +#define OTG_DSTS 0x808 +#define OTG_DIEPMSK 0x810 +#define OTG_DOEPMSK 0x814 +#define OTG_DAINT 0x818 +#define OTG_DAINTMSK 0x81C +#define OTG_DVBUSDIS 0x828 +#define OTG_DVBUSPULSE 0x82C +#define OTG_DIEPEMPMSK 0x834 +#define OTG_DIEPCTL0 0x900 +#define OTG_DIEPCTL(x) (0x900 + 0x20*(x)) +#define OTG_DOEPCTL0 0xB00 +#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x)) +#define OTG_DIEPINT(x) (0x908 + 0x20*(x)) +#define OTG_DOEPINT(x) (0xB08 + 0x20*(x)) +#define OTG_DIEPTSIZ0 0x910 +#define OTG_DOEPTSIZ0 0xB10 +#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x)) +#define OTG_DTXFSTS(x) (0x918 + 0x20*(x)) +#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x)) + +/* Power and clock gating control and status register */ +#define OTG_PCGCCTL 0xE00 + +/* Data FIFO */ +#define OTG_FIFO(x) (((x) + 1) << 12) + +/***********************************************************************/ + +/* Core Global Control and Status Registers */ +#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL) +#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT) +#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG) +#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG) +#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL) +#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS) +#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK) +#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR) +#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP) +#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ) +#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ) +#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS) +#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG) +#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID) +#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ) +#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x)) + +/* Host-mode Control and Status Registers */ +#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG) +#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR) +#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM) +#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS) +#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT) +#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK) +#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT) +#define OTG_HS_HCCHARx MMIO32(USB_OTG_HS_BASE + OTG_HCCHARx) +#define OTG_HS_HCINTx MMIO32(USB_OTG_HS_BASE + OTG_HCINTx) +#define OTG_HS_HCINTMSKx MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSKx) +#define OTG_HS_HCTSIZx MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZx) + +/* Device-mode Control and Status Registers */ +#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG) +#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL) +#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS) +#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK) +#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK) +#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT) +#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK) +#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS) +#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE) +#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK) +#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0) +#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x)) +#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0) +#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x)) +#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x)) +#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x)) +#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0) +#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0) +#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ(x))) +#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x)) +#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ(x)) + +/* Power and clock gating control and status register */ +#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL) + +/* Data FIFO */ +#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + OTG_FIFO(x))) + +/* Global CSRs */ +/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */ +#define OTG_HS_GOTGCTL_BSVLD (1 << 19) +#define OTG_HS_GOTGCTL_ASVLD (1 << 18) +#define OTG_HS_GOTGCTL_DBCT (1 << 17) +#define OTG_HS_GOTGCTL_CIDSTS (1 << 16) +#define OTG_HS_GOTGCTL_DHNPEN (1 << 11) +#define OTG_HS_GOTGCTL_HSHNPEN (1 << 10) +#define OTG_HS_GOTGCTL_HNPRQ (1 << 9) +#define OTG_HS_GOTGCTL_HNGSCS (1 << 8) +#define OTG_HS_GOTGCTL_SRQ (1 << 1) +#define OTG_HS_GOTGCTL_SRQSCS (1 << 0) + +/* OTG_FS AHB configuration register (OTG_HS_GAHBCFG) */ +#define OTG_HS_GAHBCFG_GINT 0x0001 +#define OTG_HS_GAHBCFG_TXFELVL 0x0080 +#define OTG_HS_GAHBCFG_PTXFELVL 0x0100 + +/* OTG_FS USB configuration register (OTG_HS_GUSBCFG) */ +#define OTG_HS_GUSBCFG_TOCAL 0x00000003 +#define OTG_HS_GUSBCFG_SRPCAP 0x00000100 +#define OTG_HS_GUSBCFG_HNPCAP 0x00000200 +#define OTG_HS_GUSBCFG_TRDT_MASK (0xf << 10) +#define OTG_HS_GUSBCFG_TRDT_16BIT (0x5 << 10) +#define OTG_HS_GUSBCFG_TRDT_8BIT (0x9 << 10) +#define OTG_HS_GUSBCFG_NPTXRWEN 0x00004000 +#define OTG_HS_GUSBCFG_FHMOD 0x20000000 +#define OTG_HS_GUSBCFG_FDMOD 0x40000000 +#define OTG_HS_GUSBCFG_CTXPKT 0x80000000 +#define OTG_HS_GUSBCFG_PHYSEL (1 << 6) + +/* OTG_FS reset register (OTG_HS_GRSTCTL) */ +#define OTG_HS_GRSTCTL_AHBIDL (1 << 31) +/* Bits 30:11 - Reserved */ +#define OTG_HS_GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define OTG_HS_GRSTCTL_TXFFLSH (1 << 5) +#define OTG_HS_GRSTCTL_RXFFLSH (1 << 4) +/* Bit 3 - Reserved */ +#define OTG_HS_GRSTCTL_FCRST (1 << 2) +#define OTG_HS_GRSTCTL_HSRST (1 << 1) +#define OTG_HS_GRSTCTL_CSRST (1 << 0) + +/* OTG_FS interrupt status register (OTG_HS_GINTSTS) */ +#define OTG_HS_GINTSTS_WKUPINT (1 << 31) +#define OTG_HS_GINTSTS_SRQINT (1 << 30) +#define OTG_HS_GINTSTS_DISCINT (1 << 29) +#define OTG_HS_GINTSTS_CIDSCHG (1 << 28) +/* Bit 27 - Reserved */ +#define OTG_HS_GINTSTS_PTXFE (1 << 26) +#define OTG_HS_GINTSTS_HCINT (1 << 25) +#define OTG_HS_GINTSTS_HPRTINT (1 << 24) +/* Bits 23:22 - Reserved */ +#define OTG_HS_GINTSTS_IPXFR (1 << 21) +#define OTG_HS_GINTSTS_INCOMPISOOUT (1 << 21) +#define OTG_HS_GINTSTS_IISOIXFR (1 << 20) +#define OTG_HS_GINTSTS_OEPINT (1 << 19) +#define OTG_HS_GINTSTS_IEPINT (1 << 18) +/* Bits 17:16 - Reserved */ +#define OTG_HS_GINTSTS_EOPF (1 << 15) +#define OTG_HS_GINTSTS_ISOODRP (1 << 14) +#define OTG_HS_GINTSTS_ENUMDNE (1 << 13) +#define OTG_HS_GINTSTS_USBRST (1 << 12) +#define OTG_HS_GINTSTS_USBSUSP (1 << 11) +#define OTG_HS_GINTSTS_ESUSP (1 << 10) +/* Bits 9:8 - Reserved */ +#define OTG_HS_GINTSTS_GONAKEFF (1 << 7) +#define OTG_HS_GINTSTS_GINAKEFF (1 << 6) +#define OTG_HS_GINTSTS_NPTXFE (1 << 5) +#define OTG_HS_GINTSTS_RXFLVL (1 << 4) +#define OTG_HS_GINTSTS_SOF (1 << 3) +#define OTG_HS_GINTSTS_OTGINT (1 << 2) +#define OTG_HS_GINTSTS_MMIS (1 << 1) +#define OTG_HS_GINTSTS_CMOD (1 << 0) + +/* OTG_FS interrupt mask register (OTG_HS_GINTMSK) */ +#define OTG_HS_GINTMSK_MMISM 0x00000002 +#define OTG_HS_GINTMSK_OTGINT 0x00000004 +#define OTG_HS_GINTMSK_SOFM 0x00000008 +#define OTG_HS_GINTMSK_RXFLVLM 0x00000010 +#define OTG_HS_GINTMSK_NPTXFEM 0x00000020 +#define OTG_HS_GINTMSK_GINAKEFFM 0x00000040 +#define OTG_HS_GINTMSK_GONAKEFFM 0x00000080 +#define OTG_HS_GINTMSK_ESUSPM 0x00000400 +#define OTG_HS_GINTMSK_USBSUSPM 0x00000800 +#define OTG_HS_GINTMSK_USBRST 0x00001000 +#define OTG_HS_GINTMSK_ENUMDNEM 0x00002000 +#define OTG_HS_GINTMSK_ISOODRPM 0x00004000 +#define OTG_HS_GINTMSK_EOPFM 0x00008000 +#define OTG_HS_GINTMSK_EPMISM 0x00020000 +#define OTG_HS_GINTMSK_IEPINT 0x00040000 +#define OTG_HS_GINTMSK_OEPINT 0x00080000 +#define OTG_HS_GINTMSK_IISOIXFRM 0x00100000 +#define OTG_HS_GINTMSK_IISOOXFRM 0x00200000 +#define OTG_HS_GINTMSK_IPXFRM 0x00200000 +#define OTG_HS_GINTMSK_PRTIM 0x01000000 +#define OTG_HS_GINTMSK_HCIM 0x02000000 +#define OTG_HS_GINTMSK_PTXFEM 0x04000000 +#define OTG_HS_GINTMSK_CIDSCHGM 0x10000000 +#define OTG_HS_GINTMSK_DISCINT 0x20000000 +#define OTG_HS_GINTMSK_SRQIM 0x40000000 +#define OTG_HS_GINTMSK_WUIM 0x80000000 + +/* OTG_FS Receive Status Pop Register (OTG_HS_GRXSTSP) */ +/* Bits 31:25 - Reserved */ +#define OTG_HS_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define OTG_HS_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define OTG_HS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define OTG_HS_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define OTG_HS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define OTG_HS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) +#define OTG_HS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define OTG_HS_GRXSTSP_DPID_MASK (0x3 << 15) +#define OTG_HS_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define OTG_HS_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define OTG_HS_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define OTG_HS_GRXSTSP_DPID_MDATA (0x3 << 15) +#define OTG_HS_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define OTG_HS_GRXSTSP_EPNUM_MASK (0xf << 0) + +/* OTG_FS general core configuration register (OTG_HS_GCCFG) */ +/* Bits 31:21 - Reserved */ +#define OTG_HS_GCCFG_SOFOUTEN (1 << 20) +#define OTG_HS_GCCFG_VBUSBSEN (1 << 19) +#define OTG_HS_GCCFG_VBUSASEN (1 << 18) +/* Bit 17 - Reserved */ +#define OTG_HS_GCCFG_PWRDWN (1 << 16) +/* Bits 15:0 - Reserved */ + + +/* Device-mode CSRs */ +/* OTG_FS device control register (OTG_HS_DCTL) */ +/* Bits 31:12 - Reserved */ +#define OTG_HS_DCTL_POPRGDNE (1 << 11) +#define OTG_HS_DCTL_CGONAK (1 << 10) +#define OTG_HS_DCTL_SGONAK (1 << 9) +#define OTG_HS_DCTL_SGINAK (1 << 8) +#define OTG_HS_DCTL_TCTL_MASK (7 << 4) +#define OTG_HS_DCTL_GONSTS (1 << 3) +#define OTG_HS_DCTL_GINSTS (1 << 2) +#define OTG_HS_DCTL_SDIS (1 << 1) +#define OTG_HS_DCTL_RWUSIG (1 << 0) + +/* OTG_FS device configuration register (OTG_HS_DCFG) */ +#define OTG_HS_DCFG_DSPD 0x0003 +#define OTG_HS_DCFG_NZLSOHSK 0x0004 +#define OTG_HS_DCFG_DAD 0x07F0 +#define OTG_HS_DCFG_PFIVL 0x1800 + +/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_HS_DIEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_HS_DIEPMSK_BIM (1 << 9) +#define OTG_HS_DIEPMSK_TXFURM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_HS_DIEPMSK_INEPNEM (1 << 6) +#define OTG_HS_DIEPMSK_INEPNMM (1 << 5) +#define OTG_HS_DIEPMSK_ITTXFEMSK (1 << 4) +#define OTG_HS_DIEPMSK_TOM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_HS_DIEPMSK_EPDM (1 << 1) +#define OTG_HS_DIEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_HS_DOEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_HS_DOEPMSK_BOIM (1 << 9) +#define OTG_HS_DOEPMSK_OPEM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_HS_DOEPMSK_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_HS_DOEPMSK_OTEPDM (1 << 4) +#define OTG_HS_DOEPMSK_STUPM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_HS_DOEPMSK_EPDM (1 << 1) +#define OTG_HS_DOEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_HS_DIEPCTL0) */ +#define OTG_HS_DIEPCTL0_EPENA (1 << 31) +#define OTG_HS_DIEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_HS_DIEPCTLX_SD0PID (1 << 28) +#define OTG_HS_DIEPCTL0_SNAK (1 << 27) +#define OTG_HS_DIEPCTL0_CNAK (1 << 26) +#define OTG_HS_DIEPCTL0_TXFNUM_MASK (0xf << 22) +#define OTG_HS_DIEPCTL0_STALL (1 << 21) +/* Bit 20 - Reserved */ +#define OTG_HS_DIEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_HS_DIEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_HS_DIEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_HS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_HS_DIEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_HS_DIEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_HS_DIEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_HS_DIEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_HS_DOEPCTL0) */ +#define OTG_HS_DOEPCTL0_EPENA (1 << 31) +#define OTG_HS_DOEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_HS_DOEPCTLX_SD0PID (1 << 28) +#define OTG_HS_DOEPCTL0_SNAK (1 << 27) +#define OTG_HS_DOEPCTL0_CNAK (1 << 26) +/* Bits 25:22 - Reserved */ +#define OTG_HS_DOEPCTL0_STALL (1 << 21) +#define OTG_HS_DOEPCTL0_SNPM (1 << 20) +#define OTG_HS_DOEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_HS_DOEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_HS_DOEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_HS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_HS_DOEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_HS_DOEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_HS_DOEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_HS_DOEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DIEPINTx) */ +/* Bits 31:8 - Reserved */ +#define OTG_HS_DIEPINTX_TXFE (1 << 7) +#define OTG_HS_DIEPINTX_INEPNE (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_HS_DIEPINTX_ITTXFE (1 << 4) +#define OTG_HS_DIEPINTX_TOC (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_HS_DIEPINTX_EPDISD (1 << 1) +#define OTG_HS_DIEPINTX_XFRC (1 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DOEPINTx) */ +/* Bits 31:7 - Reserved */ +#define OTG_HS_DOEPINTX_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_HS_DOEPINTX_OTEPDIS (1 << 4) +#define OTG_HS_DOEPINTX_STUP (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_HS_DOEPINTX_EPDISD (1 << 1) +#define OTG_HS_DOEPINTX_XFRC (1 << 0) + +/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_HS_DOEPTSIZ0) */ +/* Bit 31 - Reserved */ +#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) +#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) +#define OTG_HS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) +#define OTG_HS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) +/* Bits 28:20 - Reserved */ +#define OTG_HS_DIEPSIZ0_PKTCNT (1 << 19) +/* Bits 18:7 - Reserved */ +#define OTG_HS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) + +#endif diff --git a/include/libopencm3/usb/cdc.h b/include/libopencm3/usb/cdc.h index 4b54961..5036411 100644 --- a/include/libopencm3/usb/cdc.h +++ b/include/libopencm3/usb/cdc.h @@ -112,7 +112,7 @@ struct usb_cdc_line_coding { /* Table 30: Class-Specific Notification Codes for PSTN subclasses */ /* ... */ -#define USB_CDC_NOTIFY_SERIAL_STATE 0x20 +#define USB_CDC_NOTIFY_SERIAL_STATE 0x20 /* ... */ /* Notification Structure */ diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h index e4b3578..98bf6eb 100644 --- a/include/libopencm3/usb/usbd.h +++ b/include/libopencm3/usb/usbd.h @@ -25,9 +25,13 @@ BEGIN_DECLS typedef struct _usbd_driver usbd_driver; +typedef struct _usbd_device usbd_device; + extern const usbd_driver stm32f103_usb_driver; extern const usbd_driver stm32f107_usb_driver; +extern const usbd_driver stm32f207_usb_driver; #define otgfs_usb_driver stm32f107_usb_driver +#define otghs_usb_driver stm32f207_usb_driver /* Static buffer for control transactions: * This is defined as weak in the library, applicaiton @@ -35,45 +39,55 @@ extern const usbd_driver stm32f107_usb_driver; extern u8 usbd_control_buffer[]; /* */ -extern int usbd_init(const usbd_driver *driver, +extern usbd_device *usbd_init(const usbd_driver *driver, const struct usb_device_descriptor *dev, const struct usb_config_descriptor *conf, const char **strings); -extern void usbd_set_control_buffer_size(u16 size); - -extern void usbd_register_reset_callback(void (*callback)(void)); -extern void usbd_register_suspend_callback(void (*callback)(void)); -extern void usbd_register_resume_callback(void (*callback)(void)); -extern void usbd_register_sof_callback(void (*callback)(void)); - -typedef int (*usbd_control_callback)(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)); +extern void usbd_set_control_buffer_size(usbd_device *usbd_dev, u16 size); + +extern void usbd_register_reset_callback(usbd_device *usbd_dev, + void (*callback)(void)); +extern void usbd_register_suspend_callback(usbd_device *usbd_dev, + void (*callback)(void)); +extern void usbd_register_resume_callback(usbd_device *usbd_dev, + void (*callback)(void)); +extern void usbd_register_sof_callback(usbd_device *usbd_dev, + void (*callback)(void)); + +typedef int (*usbd_control_callback)(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(usbd_device *usbd_dev, + struct usb_setup_data *req)); /* */ -extern int usbd_register_control_callback(u8 type, u8 type_mask, - usbd_control_callback callback); +extern int usbd_register_control_callback(usbd_device *usbd_dev, u8 type, + u8 type_mask, + usbd_control_callback callback); /* */ -extern void usbd_register_set_config_callback(void (*callback)(u16 wValue)); +extern void usbd_register_set_config_callback(usbd_device *usbd_dev, + void (*callback)(usbd_device *usbd_dev, u16 wValue)); /* Functions to be provided by the hardware abstraction layer */ -extern void usbd_poll(void); -extern void usbd_disconnect(bool disconnected); +extern void usbd_poll(usbd_device *usbd_dev); +extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected); -extern void usbd_ep_setup(u8 addr, u8 type, u16 max_size, - void (*callback)(u8 ep)); +extern void usbd_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, + void (*callback)(usbd_device *usbd_dev, u8 ep)); -extern u16 usbd_ep_write_packet(u8 addr, const void *buf, u16 len); +extern u16 usbd_ep_write_packet(usbd_device *usbd_dev, u8 addr, + const void *buf, u16 len); -extern u16 usbd_ep_read_packet(u8 addr, void *buf, u16 len); +extern u16 usbd_ep_read_packet(usbd_device *usbd_dev, u8 addr, + void *buf, u16 len); -extern void usbd_ep_stall_set(u8 addr, u8 stall); -extern u8 usbd_ep_stall_get(u8 addr); +extern void usbd_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall); +extern u8 usbd_ep_stall_get(usbd_device *usbd_dev, u8 addr); -extern void usbd_ep_nak_set(u8 addr, u8 nak); +extern void usbd_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak); /* Optional */ -extern void usbd_cable_connect(u8 on); +extern void usbd_cable_connect(usbd_device *usbd_dev, u8 on); END_DECLS diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 3b4252b..1c7a079 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -31,7 +31,7 @@ ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o + timer.o usb_f107.o desig.o crc.o usb_fx07_common.o VPATH += ../../usb:../ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 5760d29..1d880c9 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -30,7 +30,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \ i2c.o systick.o exti.o scb.o pwr.o timer.o \ - usb.o usb_standard.o usb_control.o usb_f107.o \ + usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ + usb_f207.o \ VPATH += ../../usb:../ diff --git a/lib/usb/usb.c b/lib/usb/usb.c index 1ebb6ec..ecebde2 100644 --- a/lib/usb/usb.c +++ b/lib/usb/usb.c @@ -21,8 +21,6 @@ #include #include "usb_private.h" -struct _usbd_device _usbd_device; - u8 usbd_control_buffer[128] __attribute__((weak)); /** @@ -43,104 +41,111 @@ u8 usbd_control_buffer[128] __attribute__((weak)); * @param strings TODO * @return Zero on success (currently cannot fail). */ -int usbd_init(const usbd_driver *driver, - const struct usb_device_descriptor *dev, - const struct usb_config_descriptor *conf, const char **strings) +usbd_device *usbd_init(const usbd_driver *driver, + const struct usb_device_descriptor *dev, + const struct usb_config_descriptor *conf, + const char **strings) { - _usbd_device.driver = driver; - _usbd_device.desc = dev; - _usbd_device.config = conf; - _usbd_device.strings = strings; - _usbd_device.ctrl_buf = usbd_control_buffer; - _usbd_device.ctrl_buf_len = sizeof(usbd_control_buffer); + usbd_device *usbd_dev; + + usbd_dev = driver->init(); - _usbd_hw_init(); + usbd_dev->driver = driver; + usbd_dev->desc = dev; + usbd_dev->config = conf; + usbd_dev->strings = strings; + usbd_dev->ctrl_buf = usbd_control_buffer; + usbd_dev->ctrl_buf_len = sizeof(usbd_control_buffer); - _usbd_device.user_callback_ctr[0][USB_TRANSACTION_SETUP] = + usbd_dev->user_callback_ctr[0][USB_TRANSACTION_SETUP] = _usbd_control_setup; - _usbd_device.user_callback_ctr[0][USB_TRANSACTION_OUT] = + usbd_dev->user_callback_ctr[0][USB_TRANSACTION_OUT] = _usbd_control_out; - _usbd_device.user_callback_ctr[0][USB_TRANSACTION_IN] = + usbd_dev->user_callback_ctr[0][USB_TRANSACTION_IN] = _usbd_control_in; - return 0; + return usbd_dev; } -void usbd_register_reset_callback(void (*callback)(void)) +void usbd_register_reset_callback(usbd_device *usbd_dev, void (*callback)(void)) { - _usbd_device.user_callback_reset = callback; + usbd_dev->user_callback_reset = callback; } -void usbd_register_suspend_callback(void (*callback)(void)) +void usbd_register_suspend_callback(usbd_device *usbd_dev, + void (*callback)(void)) { - _usbd_device.user_callback_suspend = callback; + usbd_dev->user_callback_suspend = callback; } -void usbd_register_resume_callback(void (*callback)(void)) +void usbd_register_resume_callback(usbd_device *usbd_dev, + void (*callback)(void)) { - _usbd_device.user_callback_resume = callback; + usbd_dev->user_callback_resume = callback; } -void usbd_register_sof_callback(void (*callback)(void)) +void usbd_register_sof_callback(usbd_device *usbd_dev, void (*callback)(void)) { - _usbd_device.user_callback_sof = callback; + usbd_dev->user_callback_sof = callback; } -void usbd_set_control_buffer_size(u16 size) +void usbd_set_control_buffer_size(usbd_device *usbd_dev, u16 size) { - _usbd_device.ctrl_buf_len = size; + usbd_dev->ctrl_buf_len = size; } -void _usbd_reset(void) +void _usbd_reset(usbd_device *usbd_dev) { - _usbd_device.current_address = 0; - _usbd_device.current_config = 0; - usbd_ep_setup(0, USB_ENDPOINT_ATTR_CONTROL, 64, NULL); - _usbd_hw_set_address(0); + usbd_dev->current_address = 0; + usbd_dev->current_config = 0; + usbd_ep_setup(usbd_dev, 0, USB_ENDPOINT_ATTR_CONTROL, 64, NULL); + usbd_dev->driver->set_address(usbd_dev, 0); - if (_usbd_device.user_callback_reset) - _usbd_device.user_callback_reset(); + if (usbd_dev->user_callback_reset) + usbd_dev->user_callback_reset(); } /* Functions to wrap the low-level driver */ -void usbd_poll(void) +void usbd_poll(usbd_device *usbd_dev) { - _usbd_device.driver->poll(); + usbd_dev->driver->poll(usbd_dev); } -void usbd_disconnect(bool disconnected) +void usbd_disconnect(usbd_device *usbd_dev, bool disconnected) { /* not all drivers support disconnection */ - if (_usbd_device.driver->disconnect) - _usbd_device.driver->disconnect(disconnected); + if (usbd_dev->driver->disconnect) + usbd_dev->driver->disconnect(usbd_dev, disconnected); } -void usbd_ep_setup(u8 addr, u8 type, u16 max_size, void (*callback)(u8 ep)) +void usbd_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, + void (*callback)(usbd_device *usbd_dev, u8 ep)) { - _usbd_device.driver->ep_setup(addr, type, max_size, callback); + usbd_dev->driver->ep_setup(usbd_dev, addr, type, max_size, callback); } -u16 usbd_ep_write_packet(u8 addr, const void *buf, u16 len) +u16 usbd_ep_write_packet(usbd_device *usbd_dev, u8 addr, + const void *buf, u16 len) { - return _usbd_device.driver->ep_write_packet(addr, buf, len); + return usbd_dev->driver->ep_write_packet(usbd_dev, addr, buf, len); } -u16 usbd_ep_read_packet(u8 addr, void *buf, u16 len) +u16 usbd_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len) { - return _usbd_device.driver->ep_read_packet(addr, buf, len); + return usbd_dev->driver->ep_read_packet(usbd_dev, addr, buf, len); } -void usbd_ep_stall_set(u8 addr, u8 stall) +void usbd_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall) { - _usbd_device.driver->ep_stall_set(addr, stall); + usbd_dev->driver->ep_stall_set(usbd_dev, addr, stall); } -u8 usbd_ep_stall_get(u8 addr) +u8 usbd_ep_stall_get(usbd_device *usbd_dev, u8 addr) { - return _usbd_device.driver->ep_stall_get(addr); + return usbd_dev->driver->ep_stall_get(usbd_dev, addr); } -void usbd_ep_nak_set(u8 addr, u8 nak) +void usbd_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak) { - _usbd_device.driver->ep_nak_set(addr, nak); + usbd_dev->driver->ep_nak_set(usbd_dev, addr, nak); } diff --git a/lib/usb/usb_control.c b/lib/usb/usb_control.c index 0218837..245ab1c 100644 --- a/lib/usb/usb_control.c +++ b/lib/usb/usb_control.c @@ -21,77 +21,73 @@ #include #include "usb_private.h" -static struct usb_control_state { - enum { - IDLE, STALLED, - DATA_IN, LAST_DATA_IN, STATUS_IN, - DATA_OUT, LAST_DATA_OUT, STATUS_OUT, - } state; - struct usb_setup_data req __attribute__((aligned(4))); - u8 *ctrl_buf; - u16 ctrl_len; - void (*complete)(struct usb_setup_data *req); -} control_state; - /* Register application callback function for handling USB control requests. */ -int usbd_register_control_callback(u8 type, u8 type_mask, +int usbd_register_control_callback(usbd_device *usbd_dev, u8 type, u8 type_mask, usbd_control_callback callback) { int i; for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) { - if (_usbd_device.user_control_callback[i].cb) + if (usbd_dev->user_control_callback[i].cb) continue; - _usbd_device.user_control_callback[i].type = type; - _usbd_device.user_control_callback[i].type_mask = type_mask; - _usbd_device.user_control_callback[i].cb = callback; + usbd_dev->user_control_callback[i].type = type; + usbd_dev->user_control_callback[i].type_mask = type_mask; + usbd_dev->user_control_callback[i].cb = callback; return 0; } return -1; } -static void usb_control_send_chunk(void) +static void usb_control_send_chunk(usbd_device *usbd_dev) { - if (_usbd_device.desc->bMaxPacketSize0 < control_state.ctrl_len) { + if (usbd_dev->desc->bMaxPacketSize0 < usbd_dev->control_state.ctrl_len) { /* Data stage, normal transmission */ - usbd_ep_write_packet(0, control_state.ctrl_buf, - _usbd_device.desc->bMaxPacketSize0); - control_state.state = DATA_IN; - control_state.ctrl_buf += _usbd_device.desc->bMaxPacketSize0; - control_state.ctrl_len -= _usbd_device.desc->bMaxPacketSize0; + usbd_ep_write_packet(usbd_dev, 0, + usbd_dev->control_state.ctrl_buf, + usbd_dev->desc->bMaxPacketSize0); + usbd_dev->control_state.state = DATA_IN; + usbd_dev->control_state.ctrl_buf += + usbd_dev->desc->bMaxPacketSize0; + usbd_dev->control_state.ctrl_len -= + usbd_dev->desc->bMaxPacketSize0; } else { /* Data stage, end of transmission */ - usbd_ep_write_packet(0, control_state.ctrl_buf, - control_state.ctrl_len); - control_state.state = LAST_DATA_IN; - control_state.ctrl_len = 0; - control_state.ctrl_buf = NULL; + usbd_ep_write_packet(usbd_dev, 0, + usbd_dev->control_state.ctrl_buf, + usbd_dev->control_state.ctrl_len); + usbd_dev->control_state.state = LAST_DATA_IN; + usbd_dev->control_state.ctrl_len = 0; + usbd_dev->control_state.ctrl_buf = NULL; } } -static int usb_control_recv_chunk(void) +static int usb_control_recv_chunk(usbd_device *usbd_dev) { - u16 packetsize = MIN(_usbd_device.desc->bMaxPacketSize0, - control_state.req.wLength - control_state.ctrl_len); - u16 size = usbd_ep_read_packet(0, control_state.ctrl_buf + - control_state.ctrl_len, packetsize); + u16 packetsize = MIN(usbd_dev->desc->bMaxPacketSize0, + usbd_dev->control_state.req.wLength - + usbd_dev->control_state.ctrl_len); + u16 size = usbd_ep_read_packet(usbd_dev, 0, + usbd_dev->control_state.ctrl_buf + + usbd_dev->control_state.ctrl_len, + packetsize); if (size != packetsize) { - usbd_ep_stall_set(0, 1); + usbd_ep_stall_set(usbd_dev, 0, 1); return -1; } - control_state.ctrl_len += size; + usbd_dev->control_state.ctrl_len += size; return packetsize; } -static int usb_control_request_dispatch(struct usb_setup_data *req) +static int usb_control_request_dispatch(usbd_device *usbd_dev, + struct usb_setup_data *req) { int i, result = 0; - struct user_control_callback *cb = _usbd_device.user_control_callback; + struct user_control_callback *cb = usbd_dev->user_control_callback; /* Call user command hook function. */ for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) { @@ -99,140 +95,148 @@ static int usb_control_request_dispatch(struct usb_setup_data *req) break; if ((req->bmRequestType & cb[i].type_mask) == cb[i].type) { - result = cb[i].cb(req, &control_state.ctrl_buf, - &control_state.ctrl_len, - &control_state.complete); + result = cb[i].cb(usbd_dev, req, + &(usbd_dev->control_state.ctrl_buf), + &(usbd_dev->control_state.ctrl_len), + &(usbd_dev->control_state.complete)); if (result) return result; } } /* Try standard request if not already handled. */ - return _usbd_standard_request(req, &control_state.ctrl_buf, - &control_state.ctrl_len); + return _usbd_standard_request(usbd_dev, req, + &(usbd_dev->control_state.ctrl_buf), + &(usbd_dev->control_state.ctrl_len)); } /* Handle commands and read requests. */ -static void usb_control_setup_read(struct usb_setup_data *req) +static void usb_control_setup_read(usbd_device *usbd_dev, + struct usb_setup_data *req) { - control_state.ctrl_buf = _usbd_device.ctrl_buf; - control_state.ctrl_len = req->wLength; + usbd_dev->control_state.ctrl_buf = usbd_dev->ctrl_buf; + usbd_dev->control_state.ctrl_len = req->wLength; - if (usb_control_request_dispatch(req)) { - if (control_state.ctrl_len) { + if (usb_control_request_dispatch(usbd_dev, req)) { + if (usbd_dev->control_state.ctrl_len) { /* Go to data out stage if handled. */ - usb_control_send_chunk(); + usb_control_send_chunk(usbd_dev); } else { /* Go to status stage if handled. */ - usbd_ep_write_packet(0, NULL, 0); - control_state.state = STATUS_IN; + usbd_ep_write_packet(usbd_dev, 0, NULL, 0); + usbd_dev->control_state.state = STATUS_IN; } } else { /* Stall endpoint on failure. */ - usbd_ep_stall_set(0, 1); + usbd_ep_stall_set(usbd_dev, 0, 1); } } -static void usb_control_setup_write(struct usb_setup_data *req) +static void usb_control_setup_write(usbd_device *usbd_dev, + struct usb_setup_data *req) { - if (req->wLength > _usbd_device.ctrl_buf_len) { - usbd_ep_stall_set(0, 1); + if (req->wLength > usbd_dev->ctrl_buf_len) { + usbd_ep_stall_set(usbd_dev, 0, 1); return; } /* Buffer into which to write received data. */ - control_state.ctrl_buf = _usbd_device.ctrl_buf; - control_state.ctrl_len = 0; + usbd_dev->control_state.ctrl_buf = usbd_dev->ctrl_buf; + usbd_dev->control_state.ctrl_len = 0; /* Wait for DATA OUT stage. */ - if (req->wLength > _usbd_device.desc->bMaxPacketSize0) - control_state.state = DATA_OUT; + if (req->wLength > usbd_dev->desc->bMaxPacketSize0) + usbd_dev->control_state.state = DATA_OUT; else - control_state.state = LAST_DATA_OUT; + usbd_dev->control_state.state = LAST_DATA_OUT; } -void _usbd_control_setup(u8 ea) +void _usbd_control_setup(usbd_device *usbd_dev, u8 ea) { - struct usb_setup_data *req = &control_state.req; + struct usb_setup_data *req = &usbd_dev->control_state.req; (void)ea; - control_state.complete = NULL; + usbd_dev->control_state.complete = NULL; - if (usbd_ep_read_packet(0, req, 8) != 8) { - usbd_ep_stall_set(0, 1); + if (usbd_ep_read_packet(usbd_dev, 0, req, 8) != 8) { + usbd_ep_stall_set(usbd_dev, 0, 1); return; } if (req->wLength == 0) { - usb_control_setup_read(req); + usb_control_setup_read(usbd_dev, req); } else if (req->bmRequestType & 0x80) { - usb_control_setup_read(req); + usb_control_setup_read(usbd_dev, req); } else { - usb_control_setup_write(req); + usb_control_setup_write(usbd_dev, req); } } -void _usbd_control_out(u8 ea) +void _usbd_control_out(usbd_device *usbd_dev, u8 ea) { (void)ea; - switch (control_state.state) { + switch (usbd_dev->control_state.state) { case DATA_OUT: - if (usb_control_recv_chunk() < 0) + if (usb_control_recv_chunk(usbd_dev) < 0) break; - if ((control_state.req.wLength - control_state.ctrl_len) <= - _usbd_device.desc->bMaxPacketSize0) - control_state.state = LAST_DATA_OUT; + if ((usbd_dev->control_state.req.wLength - + usbd_dev->control_state.ctrl_len) <= + usbd_dev->desc->bMaxPacketSize0) + usbd_dev->control_state.state = LAST_DATA_OUT; break; case LAST_DATA_OUT: - if (usb_control_recv_chunk() < 0) + if (usb_control_recv_chunk(usbd_dev) < 0) break; /* * We have now received the full data payload. * Invoke callback to process. */ - if (usb_control_request_dispatch(&control_state.req)) { + if (usb_control_request_dispatch(usbd_dev, + &(usbd_dev->control_state.req))) { /* Got to status stage on success. */ - usbd_ep_write_packet(0, NULL, 0); - control_state.state = STATUS_IN; + usbd_ep_write_packet(usbd_dev, 0, NULL, 0); + usbd_dev->control_state.state = STATUS_IN; } else { - usbd_ep_stall_set(0, 1); + usbd_ep_stall_set(usbd_dev, 0, 1); } break; case STATUS_OUT: - usbd_ep_read_packet(0, NULL, 0); - control_state.state = IDLE; - if (control_state.complete) - control_state.complete(&control_state.req); - control_state.complete = NULL; + usbd_ep_read_packet(usbd_dev, 0, NULL, 0); + usbd_dev->control_state.state = IDLE; + if (usbd_dev->control_state.complete) + usbd_dev->control_state.complete(usbd_dev, + &(usbd_dev->control_state.req)); + usbd_dev->control_state.complete = NULL; break; default: - usbd_ep_stall_set(0, 1); + usbd_ep_stall_set(usbd_dev, 0, 1); } } -void _usbd_control_in(u8 ea) +void _usbd_control_in(usbd_device *usbd_dev, u8 ea) { (void)ea; - struct usb_setup_data *req = &control_state.req; + struct usb_setup_data *req = &(usbd_dev->control_state.req); - switch (control_state.state) { + switch (usbd_dev->control_state.state) { case DATA_IN: - usb_control_send_chunk(); + usb_control_send_chunk(usbd_dev); break; case LAST_DATA_IN: - control_state.state = STATUS_OUT; + usbd_dev->control_state.state = STATUS_OUT; break; case STATUS_IN: - if (control_state.complete) - control_state.complete(&control_state.req); + if (usbd_dev->control_state.complete) + usbd_dev->control_state.complete(usbd_dev, + &(usbd_dev->control_state.req)); /* Exception: Handle SET ADDRESS function here... */ if ((req->bmRequestType == 0) && (req->bRequest == USB_REQ_SET_ADDRESS)) - _usbd_hw_set_address(req->wValue); - control_state.state = IDLE; + usbd_dev->driver->set_address(usbd_dev, req->wValue); + usbd_dev->control_state.state = IDLE; break; default: - usbd_ep_stall_set(0, 1); + usbd_ep_stall_set(usbd_dev, 0, 1); } } diff --git a/lib/usb/usb_f103.c b/lib/usb/usb_f103.c index 22db8cc..aa323d9 100644 --- a/lib/usb/usb_f103.c +++ b/lib/usb/usb_f103.c @@ -24,19 +24,23 @@ #include #include "usb_private.h" -static void stm32f103_usbd_init(void); -static void stm32f103_set_address(u8 addr); -static void stm32f103_ep_setup(u8 addr, u8 type, u16 max_size, - void (*callback) (u8 ep)); -static void stm32f103_endpoints_reset(void); -static void stm32f103_ep_stall_set(u8 addr, u8 stall); -static u8 stm32f103_ep_stall_get(u8 addr); -static void stm32f103_ep_nak_set(u8 addr, u8 nak); -static u16 stm32f103_ep_write_packet(u8 addr, const void *buf, u16 len); -static u16 stm32f103_ep_read_packet(u8 addr, void *buf, u16 len); -static void stm32f103_poll(void); +static usbd_device *stm32f103_usbd_init(void); +static void stm32f103_set_address(usbd_device *usbd_dev, u8 addr); +static void stm32f103_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, + u16 max_size, + void (*callback) (usbd_device *usbd_dev, u8 ep)); +static void stm32f103_endpoints_reset(usbd_device *usbd_dev); +static void stm32f103_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall); +static u8 stm32f103_ep_stall_get(usbd_device *usbd_dev, u8 addr); +static void stm32f103_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak); +static u16 stm32f103_ep_write_packet(usbd_device *usbd_dev, u8 addr, + const void *buf, u16 len); +static u16 stm32f103_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, + u16 len); +static void stm32f103_poll(usbd_device *usbd_dev); static u8 force_nak[8]; +static struct _usbd_device usbd_dev; const struct _usbd_driver stm32f103_usb_driver = { .init = stm32f103_usbd_init, @@ -52,7 +56,7 @@ const struct _usbd_driver stm32f103_usb_driver = { }; /** Initialize the USB device controller hardware of the STM32. */ -static void stm32f103_usbd_init(void) +static usbd_device *stm32f103_usbd_init(void) { rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USBEN); SET_REG(USB_CNTR_REG, 0); @@ -62,10 +66,12 @@ static void stm32f103_usbd_init(void) /* Enable RESET, SUSPEND, RESUME and CTR interrupts. */ SET_REG(USB_CNTR_REG, USB_CNTR_RESETM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM); + return &usbd_dev; } -static void stm32f103_set_address(u8 addr) +static void stm32f103_set_address(usbd_device *usbd_dev, u8 addr) { + (void)usbd_dev; /* Set device address and enable. */ SET_REG(USB_DADDR_REG, (addr & USB_DADDR_ADDR) | USB_DADDR_ENABLE); } @@ -76,8 +82,9 @@ static void stm32f103_set_address(u8 addr) * @param ep Index of endpoint to configure. * @param size Size in bytes of the RX buffer. */ -static void usb_set_ep_rx_bufsize(u8 ep, u32 size) +static void usb_set_ep_rx_bufsize(usbd_device *usbd_dev, u8 ep, u32 size) { + (void)usbd_dev; if (size > 62) { if (size & 0x1f) size -= 32; @@ -89,8 +96,9 @@ static void usb_set_ep_rx_bufsize(u8 ep, u32 size) } } -static void stm32f103_ep_setup(u8 addr, u8 type, u16 max_size, - void (*callback) (u8 ep)) +static void stm32f103_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, + u16 max_size, + void (*callback) (usbd_device *usbd_dev, u8 ep)) { /* Translate USB standard type codes to STM32. */ const u16 typelookup[] = { @@ -107,32 +115,30 @@ static void stm32f103_ep_setup(u8 addr, u8 type, u16 max_size, USB_SET_EP_TYPE(addr, typelookup[type]); if (dir || (addr == 0)) { - USB_SET_EP_TX_ADDR(addr, _usbd_device.pm_top); + USB_SET_EP_TX_ADDR(addr, usbd_dev->pm_top); if (callback) { - _usbd_device. - user_callback_ctr[addr][USB_TRANSACTION_IN] = + usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_IN] = (void *)callback; } USB_CLR_EP_TX_DTOG(addr); USB_SET_EP_TX_STAT(addr, USB_EP_TX_STAT_NAK); - _usbd_device.pm_top += max_size; + usbd_dev->pm_top += max_size; } if (!dir) { - USB_SET_EP_RX_ADDR(addr, _usbd_device.pm_top); - usb_set_ep_rx_bufsize(addr, max_size); + USB_SET_EP_RX_ADDR(addr, usbd_dev->pm_top); + usb_set_ep_rx_bufsize(usbd_dev, addr, max_size); if (callback) { - _usbd_device. - user_callback_ctr[addr][USB_TRANSACTION_OUT] = + usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_OUT] = (void *)callback; } USB_CLR_EP_RX_DTOG(addr); USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_VALID); - _usbd_device.pm_top += max_size; + usbd_dev->pm_top += max_size; } } -static void stm32f103_endpoints_reset(void) +static void stm32f103_endpoints_reset(usbd_device *usbd_dev) { int i; @@ -141,11 +147,12 @@ static void stm32f103_endpoints_reset(void) USB_SET_EP_TX_STAT(i, USB_EP_TX_STAT_DISABLED); USB_SET_EP_RX_STAT(i, USB_EP_RX_STAT_DISABLED); } - _usbd_device.pm_top = 0x40 + (2 * _usbd_device.desc->bMaxPacketSize0); + usbd_dev->pm_top = 0x40 + (2 * usbd_dev->desc->bMaxPacketSize0); } -static void stm32f103_ep_stall_set(u8 addr, u8 stall) +static void stm32f103_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall) { + (void)usbd_dev; if (addr == 0) USB_SET_EP_TX_STAT(addr, stall ? USB_EP_TX_STAT_STALL : USB_EP_TX_STAT_NAK); @@ -169,8 +176,9 @@ static void stm32f103_ep_stall_set(u8 addr, u8 stall) } } -static u8 stm32f103_ep_stall_get(u8 addr) +static u8 stm32f103_ep_stall_get(usbd_device *usbd_dev, u8 addr) { + (void)usbd_dev; if (addr & 0x80) { if ((*USB_EP_REG(addr & 0x7F) & USB_EP_TX_STAT) == USB_EP_TX_STAT_STALL) @@ -183,8 +191,9 @@ static u8 stm32f103_ep_stall_get(u8 addr) return 0; } -static void stm32f103_ep_nak_set(u8 addr, u8 nak) +static void stm32f103_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak) { + (void)usbd_dev; /* It does not make sence to force NAK on IN endpoints. */ if (addr & 0x80) return; @@ -213,8 +222,10 @@ static void usb_copy_to_pm(volatile void *vPM, const void *buf, u16 len) *PM = *lbuf; } -static u16 stm32f103_ep_write_packet(u8 addr, const void *buf, u16 len) +static u16 stm32f103_ep_write_packet(usbd_device *usbd_dev, u8 addr, + const void *buf, u16 len) { + (void)usbd_dev; addr &= 0x7F; if ((*USB_EP_REG(addr) & USB_EP_TX_STAT) == USB_EP_TX_STAT_VALID) @@ -247,8 +258,10 @@ static void usb_copy_from_pm(void *buf, const volatile void *vPM, u16 len) *(u8 *) lbuf = *(u8 *) PM; } -static u16 stm32f103_ep_read_packet(u8 addr, void *buf, u16 len) +static u16 stm32f103_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, + u16 len) { + (void)usbd_dev; if ((*USB_EP_REG(addr) & USB_EP_RX_STAT) == USB_EP_RX_STAT_VALID) return 0; @@ -262,13 +275,13 @@ static u16 stm32f103_ep_read_packet(u8 addr, void *buf, u16 len) return len; } -static void stm32f103_poll(void) +static void stm32f103_poll(usbd_device *usbd_dev) { u16 istr = *USB_ISTR_REG; if (istr & USB_ISTR_RESET) { - _usbd_device.pm_top = 0x40; - _usbd_reset(); + usbd_dev->pm_top = 0x40; + _usbd_reset(usbd_dev); USB_CLR_ISTR_RESET(); return; } @@ -282,27 +295,27 @@ static void stm32f103_poll(void) else /* IN transaction */ USB_CLR_EP_TX_CTR(ep); - if (_usbd_device.user_callback_ctr[ep][type]) - _usbd_device.user_callback_ctr[ep][type] (ep); + if (usbd_dev->user_callback_ctr[ep][type]) + usbd_dev->user_callback_ctr[ep][type] (usbd_dev, ep); else USB_CLR_EP_RX_CTR(ep); } if (istr & USB_ISTR_SUSP) { USB_CLR_ISTR_SUSP(); - if (_usbd_device.user_callback_suspend) - _usbd_device.user_callback_suspend(); + if (usbd_dev->user_callback_suspend) + usbd_dev->user_callback_suspend(); } if (istr & USB_ISTR_WKUP) { USB_CLR_ISTR_WKUP(); - if (_usbd_device.user_callback_resume) - _usbd_device.user_callback_resume(); + if (usbd_dev->user_callback_resume) + usbd_dev->user_callback_resume(); } if (istr & USB_ISTR_SOF) { - if (_usbd_device.user_callback_sof) - _usbd_device.user_callback_sof(); + if (usbd_dev->user_callback_sof) + usbd_dev->user_callback_sof(); USB_CLR_ISTR_SOF(); } } diff --git a/lib/usb/usb_f107.c b/lib/usb/usb_f107.c index a5a4a6c..009979d 100644 --- a/lib/usb/usb_f107.c +++ b/lib/usb/usb_f107.c @@ -23,49 +23,34 @@ #include #include #include "usb_private.h" +#include "usb_fx07_common.h" /* Receive FIFO size in 32-bit words. */ #define RX_FIFO_SIZE 128 -static uint16_t fifo_mem_top; -static uint16_t fifo_mem_top_ep0; -static u8 force_nak[4]; +static usbd_device *stm32f107_usbd_init(void); -static void stm32f107_usbd_init(void); -static void stm32f107_set_address(u8 addr); -static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size, - void (*callback)(u8 ep)); -static void stm32f107_endpoints_reset(void); -static void stm32f107_ep_stall_set(u8 addr, u8 stall); -static u8 stm32f107_ep_stall_get(u8 addr); -static void stm32f107_ep_nak_set(u8 addr, u8 nak); -static u16 stm32f107_ep_write_packet(u8 addr, const void *buf, u16 len); -static u16 stm32f107_ep_read_packet(u8 addr, void *buf, u16 len); -static void stm32f107_poll(void); -static void stm32f107_disconnect(bool disconnected); - -/* - * We keep a backup copy of the out endpoint size registers to restore them - * after a transaction. - */ -static u32 doeptsiz[4]; +static struct _usbd_device usbd_dev; const struct _usbd_driver stm32f107_usb_driver = { .init = stm32f107_usbd_init, - .set_address = stm32f107_set_address, - .ep_setup = stm32f107_ep_setup, - .ep_reset = stm32f107_endpoints_reset, - .ep_stall_set = stm32f107_ep_stall_set, - .ep_stall_get = stm32f107_ep_stall_get, - .ep_nak_set = stm32f107_ep_nak_set, - .ep_write_packet = stm32f107_ep_write_packet, - .ep_read_packet = stm32f107_ep_read_packet, - .poll = stm32f107_poll, - .disconnect = stm32f107_disconnect, + .set_address = stm32fx07_set_address, + .ep_setup = stm32fx07_ep_setup, + .ep_reset = stm32fx07_endpoints_reset, + .ep_stall_set = stm32fx07_ep_stall_set, + .ep_stall_get = stm32fx07_ep_stall_get, + .ep_nak_set = stm32fx07_ep_nak_set, + .ep_write_packet = stm32fx07_ep_write_packet, + .ep_read_packet = stm32fx07_ep_read_packet, + .poll = stm32fx07_poll, + .disconnect = stm32fx07_disconnect, + .base_address = USB_OTG_FS_BASE, + .set_address_before_status = 1, + .rx_fifo_size = RX_FIFO_SIZE, }; /** Initialize the USB device controller hardware of the STM32. */ -static void stm32f107_usbd_init(void) +static usbd_device *stm32f107_usbd_init(void) { OTG_FS_GINTSTS = OTG_FS_GINTSTS_MMIS; @@ -88,8 +73,8 @@ static void stm32f107_usbd_init(void) /* Restart the PHY clock. */ OTG_FS_PCGCCTL = 0; - OTG_FS_GRXFSIZ = RX_FIFO_SIZE; - fifo_mem_top = RX_FIFO_SIZE; + OTG_FS_GRXFSIZ = stm32f107_usb_driver.rx_fifo_size; + usbd_dev.fifo_mem_top = stm32f107_usb_driver.rx_fifo_size; /* Unmask interrupts for TX and RX. */ OTG_FS_GAHBCFG |= OTG_FS_GAHBCFG_GINT; @@ -101,289 +86,6 @@ static void stm32f107_usbd_init(void) OTG_FS_GINTMSK_SOFM; OTG_FS_DAINTMSK = 0xF; OTG_FS_DIEPMSK = OTG_FS_DIEPMSK_XFRCM; -} - -static void stm32f107_set_address(u8 addr) -{ - OTG_FS_DCFG = (OTG_FS_DCFG & ~OTG_FS_DCFG_DAD) | (addr << 4); -} - -static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size, - void (*callback) (u8 ep)) -{ - /* - * Configure endpoint address and type. Allocate FIFO memory for - * endpoint. Install callback funciton. - */ - u8 dir = addr & 0x80; - addr &= 0x7f; - - if (addr == 0) { /* For the default control endpoint */ - /* Configure IN part. */ - if (max_size >= 64) { - OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_64; - } else if (max_size >= 32) { - OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_32; - } else if (max_size >= 16) { - OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_16; - } else { - OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_8; - } - OTG_FS_DIEPTSIZ0 = (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); - OTG_FS_DIEPCTL0 |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK; - - /* Configure OUT part. */ - doeptsiz[0] = OTG_FS_DIEPSIZ0_STUPCNT_1 | (1 << 19) | - (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); - OTG_FS_DOEPTSIZ(0) = doeptsiz[0]; - OTG_FS_DOEPCTL(0) |= - OTG_FS_DOEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK; - - OTG_FS_GNPTXFSIZ = ((max_size / 4) << 16) | RX_FIFO_SIZE; - fifo_mem_top += max_size / 4; - fifo_mem_top_ep0 = fifo_mem_top; - - return; - } - - if (dir) { - OTG_FS_DIEPTXF(addr) = ((max_size / 4) << 16) | fifo_mem_top; - fifo_mem_top += max_size / 4; - - OTG_FS_DIEPTSIZ(addr) = - (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); - OTG_FS_DIEPCTL(addr) |= - OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK | (type << 18) - | OTG_FS_DIEPCTL0_USBAEP | OTG_FS_DIEPCTLX_SD0PID - | (addr << 22) | max_size; - - if (callback) { - _usbd_device. - user_callback_ctr[addr][USB_TRANSACTION_IN] = - (void *)callback; - } - } - - if (!dir) { - doeptsiz[addr] = (1 << 19) | - (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); - OTG_FS_DOEPTSIZ(addr) = doeptsiz[addr]; - OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_EPENA | - OTG_FS_DOEPCTL0_USBAEP | OTG_FS_DIEPCTL0_CNAK | - OTG_FS_DOEPCTLX_SD0PID | (type << 18) | max_size; - - if (callback) { - _usbd_device. - user_callback_ctr[addr][USB_TRANSACTION_OUT] = - (void *)callback; - } - } -} - -static void stm32f107_endpoints_reset(void) -{ - /* The core resets the endpoints automatically on reset. */ - fifo_mem_top = fifo_mem_top_ep0; -} - -static void stm32f107_ep_stall_set(u8 addr, u8 stall) -{ - if (addr == 0) { - if (stall) - OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_STALL; - else - OTG_FS_DIEPCTL(addr) &= ~OTG_FS_DIEPCTL0_STALL; - } - - if (addr & 0x80) { - addr &= 0x7F; - - if (stall) { - OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_STALL; - } else { - OTG_FS_DIEPCTL(addr) &= ~OTG_FS_DIEPCTL0_STALL; - OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTLX_SD0PID; - } - } else { - if (stall) { - OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_STALL; - } else { - OTG_FS_DOEPCTL(addr) &= ~OTG_FS_DOEPCTL0_STALL; - OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTLX_SD0PID; - } - } -} - -static u8 stm32f107_ep_stall_get(u8 addr) -{ - /* Return non-zero if STALL set. */ - if (addr & 0x80) - return - (OTG_FS_DIEPCTL(addr & 0x7f) & OTG_FS_DIEPCTL0_STALL) ? 1 : 0; - else - return (OTG_FS_DOEPCTL(addr) & OTG_FS_DOEPCTL0_STALL) ? 1 : 0; -} - -static void stm32f107_ep_nak_set(u8 addr, u8 nak) -{ - /* It does not make sence to force NAK on IN endpoints. */ - if (addr & 0x80) - return; - - force_nak[addr] = nak; - - if (nak) - OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_SNAK; - else - OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_CNAK; -} -static u16 stm32f107_ep_write_packet(u8 addr, const void *buf, u16 len) -{ - const u32 *buf32 = buf; - int i; - - addr &= 0x7F; - - /* Return if endpoint is already enabled. */ - if (OTG_FS_DIEPTSIZ(addr) & OTG_FS_DIEPSIZ0_PKTCNT) - return 0; - - /* Enable endpoint for transmission. */ - OTG_FS_DIEPTSIZ(addr) = (1 << 19) | len; - OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_CNAK; - - /* Copy buffer to endpoint FIFO. */ - volatile u32 *fifo = OTG_FS_FIFO(addr); - for (i = len; i > 0; i -= 4) - *fifo++ = *buf32++; - - return len; -} - -/* - * Received packet size for each endpoint. This is assigned in - * stm32f107_poll() which reads the packet status push register GRXSTSP - * for use in stm32f107_ep_read_packet(). - */ -static uint16_t rxbcnt; - -static u16 stm32f107_ep_read_packet(u8 addr, void *buf, u16 len) -{ - int i; - u32 *buf32 = buf; - u32 extra; - - len = MIN(len, rxbcnt); - rxbcnt -= len; - - volatile u32 *fifo = OTG_FS_FIFO(addr); - for (i = len; i >= 4; i -= 4) - *buf32++ = *fifo++; - - if (i) { - extra = *fifo++; - memcpy(buf32, &extra, i); - } - - OTG_FS_DOEPTSIZ(addr) = doeptsiz[addr]; - OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_EPENA | - (force_nak[addr] ? OTG_FS_DOEPCTL0_SNAK : OTG_FS_DOEPCTL0_CNAK); - - return len; -} - -static void stm32f107_poll(void) -{ - /* Read interrupt status register. */ - u32 intsts = OTG_FS_GINTSTS; - int i; - - if (intsts & OTG_FS_GINTSTS_ENUMDNE) { - /* Handle USB RESET condition. */ - OTG_FS_GINTSTS = OTG_FS_GINTSTS_ENUMDNE; - fifo_mem_top = RX_FIFO_SIZE; - _usbd_reset(); - return; - } - - /* Note: RX and TX handled differently in this device. */ - if (intsts & OTG_FS_GINTSTS_RXFLVL) { - /* Receive FIFO non-empty. */ - u32 rxstsp = OTG_FS_GRXSTSP; - u32 pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK; - if ((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) && - (pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP)) - return; - - u8 ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK; - u8 type; - if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP) - type = USB_TRANSACTION_SETUP; - else - type = USB_TRANSACTION_OUT; - - /* Save packet size for stm32f107_ep_read_packet(). */ - rxbcnt = (rxstsp & OTG_FS_GRXSTSP_BCNT_MASK) >> 4; - - /* - * FIXME: Why is a delay needed here? - * This appears to fix a problem where the first 4 bytes - * of the DATA OUT stage of a control transaction are lost. - */ - for (i = 0; i < 1000; i++) - __asm__("nop"); - - if (_usbd_device.user_callback_ctr[ep][type]) - _usbd_device.user_callback_ctr[ep][type] (ep); - - /* Discard unread packet data. */ - for (i = 0; i < rxbcnt; i += 4) - (void)*OTG_FS_FIFO(ep); - - rxbcnt = 0; - } - - /* - * There is no global interrupt flag for transmit complete. - * The XFRC bit must be checked in each OTG_FS_DIEPINT(x). - */ - for (i = 0; i < 4; i++) { /* Iterate over endpoints. */ - if (OTG_FS_DIEPINT(i) & OTG_FS_DIEPINTX_XFRC) { - /* Transfer complete. */ - if (_usbd_device. - user_callback_ctr[i][USB_TRANSACTION_IN]) { - _usbd_device. - user_callback_ctr[i][USB_TRANSACTION_IN](i); - } - OTG_FS_DIEPINT(i) = OTG_FS_DIEPINTX_XFRC; - } - } - - if (intsts & OTG_FS_GINTSTS_USBSUSP) { - if (_usbd_device.user_callback_suspend) - _usbd_device.user_callback_suspend(); - OTG_FS_GINTSTS = OTG_FS_GINTSTS_USBSUSP; - } - - if (intsts & OTG_FS_GINTSTS_WKUPINT) { - if (_usbd_device.user_callback_resume) - _usbd_device.user_callback_resume(); - OTG_FS_GINTSTS = OTG_FS_GINTSTS_WKUPINT; - } - - if (intsts & OTG_FS_GINTSTS_SOF) { - if (_usbd_device.user_callback_sof) - _usbd_device.user_callback_sof(); - OTG_FS_GINTSTS = OTG_FS_GINTSTS_SOF; - } -} - -static void stm32f107_disconnect(bool disconnected) -{ - if (disconnected) { - OTG_FS_DCTL |= OTG_FS_DCTL_SDIS; - } else { - OTG_FS_DCTL &= ~OTG_FS_DCTL_SDIS; - } + return &usbd_dev; } diff --git a/lib/usb/usb_f207.c b/lib/usb/usb_f207.c new file mode 100644 index 0000000..b2509e5 --- /dev/null +++ b/lib/usb/usb_f207.c @@ -0,0 +1,91 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include "usb_private.h" +#include "usb_fx07_common.h" + +/* Receive FIFO size in 32-bit words. */ +#define RX_FIFO_SIZE 512 + +static usbd_device *stm32f207_usbd_init(void); + +static struct _usbd_device usbd_dev; + +const struct _usbd_driver stm32f207_usb_driver = { + .init = stm32f207_usbd_init, + .set_address = stm32fx07_set_address, + .ep_setup = stm32fx07_ep_setup, + .ep_reset = stm32fx07_endpoints_reset, + .ep_stall_set = stm32fx07_ep_stall_set, + .ep_stall_get = stm32fx07_ep_stall_get, + .ep_nak_set = stm32fx07_ep_nak_set, + .ep_write_packet = stm32fx07_ep_write_packet, + .ep_read_packet = stm32fx07_ep_read_packet, + .poll = stm32fx07_poll, + .disconnect = stm32fx07_disconnect, + .base_address = USB_OTG_HS_BASE, + .set_address_before_status = 1, + .rx_fifo_size = RX_FIFO_SIZE, +}; + +/** Initialize the USB device controller hardware of the STM32. */ +static usbd_device *stm32f207_usbd_init(void) +{ + OTG_HS_GINTSTS = OTG_HS_GINTSTS_MMIS; + + OTG_HS_GUSBCFG |= OTG_HS_GUSBCFG_PHYSEL; + /* Enable VBUS sensing in device mode and power down the PHY. */ + OTG_HS_GCCFG |= OTG_HS_GCCFG_VBUSBSEN | OTG_HS_GCCFG_PWRDWN; + + /* Wait for AHB idle. */ + while (!(OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_AHBIDL)) ; + /* Do core soft reset. */ + OTG_HS_GRSTCTL |= OTG_HS_GRSTCTL_CSRST; + while (OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_CSRST) ; + + /* Force peripheral only mode. */ + OTG_HS_GUSBCFG |= OTG_HS_GUSBCFG_FDMOD | OTG_HS_GUSBCFG_TRDT_MASK; + + /* Full speed device. */ + OTG_HS_DCFG |= OTG_HS_DCFG_DSPD; + + /* Restart the PHY clock. */ + OTG_HS_PCGCCTL = 0; + + OTG_HS_GRXFSIZ = stm32f207_usb_driver.rx_fifo_size; + usbd_dev.fifo_mem_top = stm32f207_usb_driver.rx_fifo_size; + + /* Unmask interrupts for TX and RX. */ + OTG_HS_GAHBCFG |= OTG_HS_GAHBCFG_GINT; + OTG_HS_GINTMSK = OTG_HS_GINTMSK_ENUMDNEM | + OTG_HS_GINTMSK_RXFLVLM | + OTG_HS_GINTMSK_IEPINT | + OTG_HS_GINTMSK_USBSUSPM | + OTG_HS_GINTMSK_WUIM | + OTG_HS_GINTMSK_SOFM; + OTG_HS_DAINTMSK = 0xF; + OTG_HS_DIEPMSK = OTG_HS_DIEPMSK_XFRCM; + + return &usbd_dev; +} diff --git a/lib/usb/usb_fx07_common.c b/lib/usb/usb_fx07_common.c new file mode 100644 index 0000000..9178092 --- /dev/null +++ b/lib/usb/usb_fx07_common.c @@ -0,0 +1,318 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include "usb_private.h" +#include "usb_fx07_common.h" + +/* The FS core and the HS core have the same register layout. + * As the code can be used on both cores, the registers offset is modified + * according to the selected cores base address. */ +#define dev_base_address (usbd_dev->driver->base_address) +#define REBASE(x) MMIO32((x)+(dev_base_address)) +#define REBASE_FIFO(x) ((volatile u32*)((dev_base_address) + (OTG_FIFO(x)))) + +void stm32fx07_set_address(usbd_device *usbd_dev, u8 addr) +{ + REBASE(OTG_DCFG) = (REBASE(OTG_DCFG) & ~OTG_FS_DCFG_DAD) | (addr << 4); +} + +void stm32fx07_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, + void (*callback) (usbd_device *usbd_dev, u8 ep)) +{ + /* + * Configure endpoint address and type. Allocate FIFO memory for + * endpoint. Install callback funciton. + */ + u8 dir = addr & 0x80; + addr &= 0x7f; + + if (addr == 0) { /* For the default control endpoint */ + /* Configure IN part. */ + if (max_size >= 64) { + REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_64; + } else if (max_size >= 32) { + REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_32; + } else if (max_size >= 16) { + REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_16; + } else { + REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_8; + } + REBASE(OTG_DIEPTSIZ0) = + (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); + REBASE(OTG_DIEPCTL0) |= + OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK; + + /* Configure OUT part. */ + usbd_dev->doeptsiz[0] = OTG_FS_DIEPSIZ0_STUPCNT_1 | + OTG_FS_DIEPSIZ0_PKTCNT | + (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); + REBASE(OTG_DOEPTSIZ(0)) = usbd_dev->doeptsiz[0]; + REBASE(OTG_DOEPCTL(0)) |= + OTG_FS_DOEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK; + + REBASE(OTG_GNPTXFSIZ) = ((max_size / 4) << 16) | + usbd_dev->driver->rx_fifo_size; + usbd_dev->fifo_mem_top += max_size / 4; + usbd_dev->fifo_mem_top_ep0 = usbd_dev->fifo_mem_top; + + return; + } + + if (dir) { + REBASE(OTG_DIEPTXF(addr)) = ((max_size / 4) << 16) | + usbd_dev->fifo_mem_top; + usbd_dev->fifo_mem_top += max_size / 4; + + REBASE(OTG_DIEPTSIZ(addr)) = + (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); + REBASE(OTG_DIEPCTL(addr)) |= + OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK | (type << 18) + | OTG_FS_DIEPCTL0_USBAEP | OTG_FS_DIEPCTLX_SD0PID + | (addr << 22) | max_size; + + if (callback) { + usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_IN] = + (void *)callback; + } + } + + if (!dir) { + usbd_dev->doeptsiz[addr] = OTG_FS_DIEPSIZ0_PKTCNT | + (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); + REBASE(OTG_DOEPTSIZ(addr)) = usbd_dev->doeptsiz[addr]; + REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_EPENA | + OTG_FS_DOEPCTL0_USBAEP | OTG_FS_DIEPCTL0_CNAK | + OTG_FS_DOEPCTLX_SD0PID | (type << 18) | max_size; + + if (callback) { + usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_OUT] = + (void *)callback; + } + } +} + +void stm32fx07_endpoints_reset(usbd_device *usbd_dev) +{ + /* The core resets the endpoints automatically on reset. */ + usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0; +} + +void stm32fx07_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall) +{ + if (addr == 0) { + if (stall) + REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_STALL; + else + REBASE(OTG_DIEPCTL(addr)) &= ~OTG_FS_DIEPCTL0_STALL; + } + + if (addr & 0x80) { + addr &= 0x7F; + + if (stall) { + REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_STALL; + } else { + REBASE(OTG_DIEPCTL(addr)) &= ~OTG_FS_DIEPCTL0_STALL; + REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTLX_SD0PID; + } + } else { + if (stall) { + REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_STALL; + } else { + REBASE(OTG_DOEPCTL(addr)) &= ~OTG_FS_DOEPCTL0_STALL; + REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTLX_SD0PID; + } + } +} + +u8 stm32fx07_ep_stall_get(usbd_device *usbd_dev, u8 addr) +{ + /* Return non-zero if STALL set. */ + if (addr & 0x80) + return (REBASE(OTG_DIEPCTL(addr & 0x7f)) & + OTG_FS_DIEPCTL0_STALL) ? 1 : 0; + else + return (REBASE(OTG_DOEPCTL(addr)) & + OTG_FS_DOEPCTL0_STALL) ? 1 : 0; +} + +void stm32fx07_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak) +{ + /* It does not make sence to force NAK on IN endpoints. */ + if (addr & 0x80) + return; + + usbd_dev->force_nak[addr] = nak; + + if (nak) + REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_SNAK; + else + REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_CNAK; +} + +u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr, + const void *buf, u16 len) +{ + const u32 *buf32 = buf; + int i; + + addr &= 0x7F; + + /* Return if endpoint is already enabled. */ + if (REBASE(OTG_DIEPTSIZ(addr)) & OTG_FS_DIEPSIZ0_PKTCNT) + return 0; + + /* Enable endpoint for transmission. */ + REBASE(OTG_DIEPTSIZ(addr)) = OTG_FS_DIEPSIZ0_PKTCNT | len; + REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_EPENA | + OTG_FS_DIEPCTL0_CNAK; + volatile u32 *fifo = REBASE_FIFO(addr); + + /* Copy buffer to endpoint FIFO, note - memcpy does not work */ + for (i = len; i > 0; i -= 4) + *fifo++ = *buf32++; + + return len; +} + +u16 stm32fx07_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len) +{ + int i; + u32 *buf32 = buf; + u32 extra; + + len = MIN(len, usbd_dev->rxbcnt); + usbd_dev->rxbcnt -= len; + + volatile u32 *fifo = REBASE_FIFO(addr); + for (i = len; i >= 4; i -= 4) + *buf32++ = *fifo++; + + if (i) { + extra = *fifo++; + memcpy(buf32, &extra, i); + } + + REBASE(OTG_DOEPTSIZ(addr)) = usbd_dev->doeptsiz[addr]; + REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_EPENA | + (usbd_dev->force_nak[addr] ? + OTG_FS_DOEPCTL0_SNAK : OTG_FS_DOEPCTL0_CNAK); + + return len; +} + +void stm32fx07_poll(usbd_device *usbd_dev) +{ + /* Read interrupt status register. */ + u32 intsts = REBASE(OTG_GINTSTS); + int i; + + if (intsts & OTG_FS_GINTSTS_ENUMDNE) { + /* Handle USB RESET condition. */ + REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_ENUMDNE; + usbd_dev->fifo_mem_top = usbd_dev->driver->rx_fifo_size; + _usbd_reset(usbd_dev); + return; + } + + /* Note: RX and TX handled differently in this device. */ + if (intsts & OTG_FS_GINTSTS_RXFLVL) { + /* Receive FIFO non-empty. */ + u32 rxstsp = REBASE(OTG_GRXSTSP); + u32 pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK; + if ((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) && + (pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP)) + return; + + u8 ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK; + u8 type; + if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP) + type = USB_TRANSACTION_SETUP; + else + type = USB_TRANSACTION_OUT; + + /* Save packet size for stm32f107_ep_read_packet(). */ + usbd_dev->rxbcnt = (rxstsp & OTG_FS_GRXSTSP_BCNT_MASK) >> 4; + + /* + * FIXME: Why is a delay needed here? + * This appears to fix a problem where the first 4 bytes + * of the DATA OUT stage of a control transaction are lost. + */ + for (i = 0; i < 1000; i++) + __asm__("nop"); + + if (usbd_dev->user_callback_ctr[ep][type]) + usbd_dev->user_callback_ctr[ep][type] (usbd_dev, ep); + + /* Discard unread packet data. */ + for (i = 0; i < usbd_dev->rxbcnt; i += 4) + (void)*REBASE_FIFO(ep); + + usbd_dev->rxbcnt = 0; + } + + /* + * There is no global interrupt flag for transmit complete. + * The XFRC bit must be checked in each OTG_FS_DIEPINT(x). + */ + for (i = 0; i < 4; i++) { /* Iterate over endpoints. */ + if (REBASE(OTG_DIEPINT(i)) & OTG_FS_DIEPINTX_XFRC) { + /* Transfer complete. */ + if (usbd_dev->user_callback_ctr[i][USB_TRANSACTION_IN]) + usbd_dev->user_callback_ctr[i] + [USB_TRANSACTION_IN](usbd_dev, i); + + REBASE(OTG_DIEPINT(i)) = OTG_FS_DIEPINTX_XFRC; + } + } + + if (intsts & OTG_FS_GINTSTS_USBSUSP) { + if (usbd_dev->user_callback_suspend) + usbd_dev->user_callback_suspend(); + REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_USBSUSP; + } + + if (intsts & OTG_FS_GINTSTS_WKUPINT) { + if (usbd_dev->user_callback_resume) + usbd_dev->user_callback_resume(); + REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_WKUPINT; + } + + if (intsts & OTG_FS_GINTSTS_SOF) { + if (usbd_dev->user_callback_sof) + usbd_dev->user_callback_sof(); + REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_SOF; + } +} + +void stm32fx07_disconnect(usbd_device *usbd_dev, bool disconnected) +{ + if (disconnected) { + REBASE(OTG_DCTL) |= OTG_FS_DCTL_SDIS; + } else { + REBASE(OTG_DCTL) &= ~OTG_FS_DCTL_SDIS; + } +} diff --git a/lib/usb/usb_fx07_common.h b/lib/usb/usb_fx07_common.h new file mode 100644 index 0000000..4d8d38e --- /dev/null +++ b/lib/usb/usb_fx07_common.h @@ -0,0 +1,38 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef __USB_FX07_COMMON_H_ +#define __USB_FX07_COMMON_H_ + +void stm32fx07_set_address(usbd_device *usbd_dev, u8 addr); +void stm32fx07_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, + void (*callback)(usbd_device *usbd_dev, u8 ep)); +void stm32fx07_endpoints_reset(usbd_device *usbd_dev); +void stm32fx07_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall); +u8 stm32fx07_ep_stall_get(usbd_device *usbd_dev, u8 addr); +void stm32fx07_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak); +u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr, const void *buf, + u16 len); +u16 stm32fx07_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, + u16 len); +void stm32fx07_poll(usbd_device *usbd_dev); +void stm32fx07_disconnect(usbd_device *usbd_dev, bool disconnected); + + +#endif /* __USB_FX07_COMMON_H_ */ diff --git a/lib/usb/usb_private.h b/lib/usb/usb_private.h index a1e5e4c..2506ba5 100644 --- a/lib/usb/usb_private.h +++ b/lib/usb/usb_private.h @@ -25,7 +25,7 @@ #define MIN(a, b) ((a)<(b) ? (a) : (b)) /** Internal collection of device information. */ -extern struct _usbd_device { +struct _usbd_device { const struct usb_device_descriptor *desc; const struct usb_config_descriptor *config; const char **strings; @@ -44,19 +44,49 @@ extern struct _usbd_device { void (*user_callback_resume)(void); void (*user_callback_sof)(void); + struct usb_control_state { + enum { + IDLE, STALLED, + DATA_IN, LAST_DATA_IN, STATUS_IN, + DATA_OUT, LAST_DATA_OUT, STATUS_OUT, + } state; + struct usb_setup_data req __attribute__((aligned(4))); + u8 *ctrl_buf; + u16 ctrl_len; + void (*complete)(usbd_device *usbd_dev, + struct usb_setup_data *req); + } control_state; + struct user_control_callback { usbd_control_callback cb; u8 type; u8 type_mask; } user_control_callback[MAX_USER_CONTROL_CALLBACK]; - void (*user_callback_ctr[8][3])(u8 ea); + void (*user_callback_ctr[8][3])(usbd_device *usbd_dev, u8 ea); /* User callback function for some standard USB function hooks */ - void (*user_callback_set_config)(u16 wValue); + void (*user_callback_set_config)(usbd_device *usbd_dev, u16 wValue); const struct _usbd_driver *driver; -} _usbd_device; + + /* private driver data */ + + uint16_t fifo_mem_top; + uint16_t fifo_mem_top_ep0; + u8 force_nak[4]; + /* + * We keep a backup copy of the out endpoint size registers to restore them + * after a transaction. + */ + u32 doeptsiz[4]; + /* + * Received packet size for each endpoint. This is assigned in + * stm32f107_poll() which reads the packet status push register GRXSTSP + * for use in stm32f107_ep_read_packet(). + */ + uint16_t rxbcnt; +}; enum _usbd_transaction { USB_TRANSACTION_IN, @@ -64,31 +94,34 @@ enum _usbd_transaction { USB_TRANSACTION_SETUP, }; -void _usbd_control_in(u8 ea); -void _usbd_control_out(u8 ea); -void _usbd_control_setup(u8 ea); +void _usbd_control_in(usbd_device *usbd_dev, u8 ea); +void _usbd_control_out(usbd_device *usbd_dev, u8 ea); +void _usbd_control_setup(usbd_device *usbd_dev, u8 ea); -int _usbd_standard_request(struct usb_setup_data *req, u8 **buf, u16 *len); +int _usbd_standard_request(usbd_device *usbd_dev, struct usb_setup_data *req, + u8 **buf, u16 *len); -void _usbd_reset(void); +void _usbd_reset(usbd_device *usbd_dev); /* Functions provided by the hardware abstraction. */ struct _usbd_driver { - void (*init)(void); - void (*set_address)(u8 addr); - void (*ep_setup)(u8 addr, u8 type, u16 max_size, void (*cb)(u8 ep)); - void (*ep_reset)(void); - void (*ep_stall_set)(u8 addr, u8 stall); - void (*ep_nak_set)(u8 addr, u8 nak); - u8 (*ep_stall_get)(u8 addr); - u16 (*ep_write_packet)(u8 addr, const void *buf, u16 len); - u16 (*ep_read_packet)(u8 addr, void *buf, u16 len); - void (*poll)(void); - void (*disconnect)(bool disconnected); + usbd_device *(*init)(void); + void (*set_address)(usbd_device *usbd_dev, u8 addr); + void (*ep_setup)(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, + void (*cb)(usbd_device *usbd_dev, u8 ep)); + void (*ep_reset)(usbd_device *usbd_dev); + void (*ep_stall_set)(usbd_device *usbd_dev, u8 addr, u8 stall); + void (*ep_nak_set)(usbd_device *usbd_dev, u8 addr, u8 nak); + u8 (*ep_stall_get)(usbd_device *usbd_dev, u8 addr); + u16 (*ep_write_packet)(usbd_device *usbd_dev, u8 addr, const void *buf, + u16 len); + u16 (*ep_read_packet)(usbd_device *usbd_dev, u8 addr, void *buf, + u16 len); + void (*poll)(usbd_device *usbd_dev); + void (*disconnect)(usbd_device *usbd_dev, bool disconnected); + u32 base_address; + bool set_address_before_status; + u16 rx_fifo_size; }; -#define _usbd_hw_init() _usbd_device.driver->init() -#define _usbd_hw_set_address(addr) _usbd_device.driver->set_address(addr) -#define _usbd_hw_endpoints_reset() _usbd_device.driver->ep_reset() - #endif diff --git a/lib/usb/usb_standard.c b/lib/usb/usb_standard.c index 2d7c619..5a92cd8 100644 --- a/lib/usb/usb_standard.c +++ b/lib/usb/usb_standard.c @@ -21,15 +21,18 @@ #include #include "usb_private.h" -void usbd_register_set_config_callback(void (*callback)(u16 wValue)) +void usbd_register_set_config_callback(usbd_device *usbd_dev, + void (*callback)(usbd_device *usbd_dev, + u16 wValue)) { - _usbd_device.user_callback_set_config = callback; + usbd_dev->user_callback_set_config = callback; } -static u16 build_config_descriptor(u8 index, u8 *buf, u16 len) +static u16 build_config_descriptor(usbd_device *usbd_dev, + u8 index, u8 *buf, u16 len) { u8 *tmpbuf = buf; - const struct usb_config_descriptor *cfg = &_usbd_device.config[index]; + const struct usb_config_descriptor *cfg = &usbd_dev->config[index]; u16 count, total = 0, totallen = 0; u16 i, j, k; @@ -43,7 +46,7 @@ static u16 build_config_descriptor(u8 index, u8 *buf, u16 len) for (i = 0; i < cfg->bNumInterfaces; i++) { /* Interface Association Descriptor, if any */ if (cfg->interface[i].iface_assoc) { - const struct usb_iface_assoc_descriptor *assoc = + const struct usb_iface_assoc_descriptor *assoc = cfg->interface[i].iface_assoc; memcpy(buf, assoc, count = MIN(len, assoc->bLength)); buf += count; @@ -87,7 +90,8 @@ static u16 build_config_descriptor(u8 index, u8 *buf, u16 len) return total; } -static int usb_standard_get_descriptor(struct usb_setup_data *req, +static int usb_standard_get_descriptor(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { int i; @@ -95,25 +99,26 @@ static int usb_standard_get_descriptor(struct usb_setup_data *req, switch (req->wValue >> 8) { case USB_DT_DEVICE: - *buf = (u8 *) _usbd_device.desc; - *len = MIN(*len, _usbd_device.desc->bLength); + *buf = (u8 *) usbd_dev->desc; + *len = MIN(*len, usbd_dev->desc->bLength); return 1; case USB_DT_CONFIGURATION: - *buf = _usbd_device.ctrl_buf; - *len = build_config_descriptor(req->wValue & 0xff, *buf, *len); + *buf = usbd_dev->ctrl_buf; + *len = build_config_descriptor(usbd_dev, req->wValue & 0xff, + *buf, *len); return 1; case USB_DT_STRING: - sd = (struct usb_string_descriptor *)_usbd_device.ctrl_buf; + sd = (struct usb_string_descriptor *)usbd_dev->ctrl_buf; - if (!_usbd_device.strings) + if (!usbd_dev->strings) return 0; /* Device doesn't support strings. */ /* Check that string index is in range. */ for (i = 0; i <= (req->wValue & 0xff); i++) - if (_usbd_device.strings[i] == NULL) + if (usbd_dev->strings[i] == NULL) return 0; - sd->bLength = strlen(_usbd_device.strings[req->wValue & 0xff]) + sd->bLength = strlen(usbd_dev->strings[req->wValue & 0xff]) * 2 + 2; sd->bDescriptorType = USB_DT_STRING; @@ -122,7 +127,7 @@ static int usb_standard_get_descriptor(struct usb_setup_data *req, for (i = 0; i < (*len / 2) - 1; i++) sd->wData[i] = - _usbd_device.strings[req->wValue & 0xff][i]; + usbd_dev->strings[req->wValue & 0xff][i]; /* Send sane Language ID descriptor... */ if ((req->wValue & 0xff) == 0) @@ -133,7 +138,8 @@ static int usb_standard_get_descriptor(struct usb_setup_data *req, return 0; } -static int usb_standard_set_address(struct usb_setup_data *req, u8 **buf, +static int usb_standard_set_address(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { (void)req; @@ -144,19 +150,20 @@ static int usb_standard_set_address(struct usb_setup_data *req, u8 **buf, if ((req->bmRequestType != 0) || (req->wValue >= 128)) return 0; - _usbd_device.current_address = req->wValue; + usbd_dev->current_address = req->wValue; /* * Special workaround for STM32F10[57] that require the address * to be set here. This is undocumented! */ - if (_usbd_device.driver == &stm32f107_usb_driver) - _usbd_device.driver->set_address(req->wValue); + if ( usbd_dev->driver->set_address_before_status) + usbd_dev->driver->set_address(usbd_dev, req->wValue); return 1; } -static int usb_standard_set_configuration(struct usb_setup_data *req, +static int usb_standard_set_configuration(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { int i; @@ -166,43 +173,46 @@ static int usb_standard_set_configuration(struct usb_setup_data *req, (void)len; /* Is this correct, or should we reset alternate settings. */ - if (req->wValue == _usbd_device.current_config) + if (req->wValue == usbd_dev->current_config) return 1; - _usbd_device.current_config = req->wValue; + usbd_dev->current_config = req->wValue; /* Reset all endpoints. */ - _usbd_hw_endpoints_reset(); + usbd_dev->driver->ep_reset(usbd_dev); - if (_usbd_device.user_callback_set_config) { + if (usbd_dev->user_callback_set_config) { /* * Flush control callbacks. These will be reregistered * by the user handler. */ for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) - _usbd_device.user_control_callback[i].cb = NULL; + usbd_dev->user_control_callback[i].cb = NULL; - _usbd_device.user_callback_set_config(req->wValue); + usbd_dev->user_callback_set_config(usbd_dev, req->wValue); } return 1; } -static int usb_standard_get_configuration(struct usb_setup_data *req, +static int usb_standard_get_configuration(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { (void)req; if (*len > 1) *len = 1; - (*buf)[0] = _usbd_device.current_config; + (*buf)[0] = usbd_dev->current_config; return 1; } -static int usb_standard_set_interface(struct usb_setup_data *req, +static int usb_standard_set_interface(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { + (void)usbd_dev; (void)req; (void)buf; @@ -214,9 +224,11 @@ static int usb_standard_set_interface(struct usb_setup_data *req, return 1; } -static int usb_standard_get_interface(struct usb_setup_data *req, +static int usb_standard_get_interface(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { + (void)usbd_dev; (void)req; (void)buf; @@ -227,9 +239,11 @@ static int usb_standard_get_interface(struct usb_setup_data *req, return 1; } -static int usb_standard_device_get_status(struct usb_setup_data *req, +static int usb_standard_device_get_status(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { + (void)usbd_dev; (void)req; /* bit 0: self powered */ @@ -242,9 +256,11 @@ static int usb_standard_device_get_status(struct usb_setup_data *req, return 1; } -static int usb_standard_interface_get_status(struct usb_setup_data *req, +static int usb_standard_interface_get_status(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { + (void)usbd_dev; (void)req; /* not defined */ @@ -256,45 +272,50 @@ static int usb_standard_interface_get_status(struct usb_setup_data *req, return 1; } -static int usb_standard_endpoint_get_status(struct usb_setup_data *req, +static int usb_standard_endpoint_get_status(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { (void)req; if (*len > 2) *len = 2; - (*buf)[0] = usbd_ep_stall_get(req->wIndex) ? 1 : 0; + (*buf)[0] = usbd_ep_stall_get(usbd_dev, req->wIndex) ? 1 : 0; (*buf)[1] = 0; return 1; } -static int usb_standard_endpoint_stall(struct usb_setup_data *req, +static int usb_standard_endpoint_stall(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { (void)buf; (void)len; - usbd_ep_stall_set(req->wIndex, 1); + usbd_ep_stall_set(usbd_dev, req->wIndex, 1); return 1; } -static int usb_standard_endpoint_unstall(struct usb_setup_data *req, +static int usb_standard_endpoint_unstall(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { (void)buf; (void)len; - usbd_ep_stall_set(req->wIndex, 0); + usbd_ep_stall_set(usbd_dev, req->wIndex, 0); return 1; } -int _usbd_standard_request_device(struct usb_setup_data *req, u8 **buf, +int _usbd_standard_request_device(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { - int (*command)(struct usb_setup_data *req, u8 **buf, u16 *len) = NULL; + int (*command)(usbd_device *usbd_dev, struct usb_setup_data *req, u8 + **buf, u16 *len) = NULL; switch (req->bRequest) { case USB_REQ_CLEAR_FEATURE: @@ -337,13 +358,15 @@ int _usbd_standard_request_device(struct usb_setup_data *req, u8 **buf, if (!command) return 0; - return command(req, buf, len); + return command(usbd_dev, req, buf, len); } -int _usbd_standard_request_interface(struct usb_setup_data *req, u8 **buf, +int _usbd_standard_request_interface(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { - int (*command)(struct usb_setup_data *req, u8 **buf, u16 *len) = NULL; + int (*command)(usbd_device *usbd_dev, struct usb_setup_data *req, + u8 **buf, u16 *len) = NULL; switch (req->bRequest) { case USB_REQ_CLEAR_FEATURE: @@ -364,13 +387,15 @@ int _usbd_standard_request_interface(struct usb_setup_data *req, u8 **buf, if (!command) return 0; - return command(req, buf, len); + return command(usbd_dev, req, buf, len); } -int _usbd_standard_request_endpoint(struct usb_setup_data *req, u8 **buf, +int _usbd_standard_request_endpoint(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { - int (*command) (struct usb_setup_data *req, u8 **buf, u16 *len) = NULL; + int (*command) (usbd_device *usbd_dev, struct usb_setup_data *req, + u8 **buf, u16 *len) = NULL; switch (req->bRequest) { case USB_REQ_CLEAR_FEATURE: @@ -396,10 +421,11 @@ int _usbd_standard_request_endpoint(struct usb_setup_data *req, u8 **buf, if (!command) return 0; - return command(req, buf, len); + return command(usbd_dev, req, buf, len); } -int _usbd_standard_request(struct usb_setup_data *req, u8 **buf, u16 *len) +int _usbd_standard_request(usbd_device *usbd_dev, + struct usb_setup_data *req, u8 **buf, u16 *len) { /* FIXME: Have class/vendor requests as well. */ if ((req->bmRequestType & USB_REQ_TYPE_TYPE) != USB_REQ_TYPE_STANDARD) @@ -407,11 +433,12 @@ int _usbd_standard_request(struct usb_setup_data *req, u8 **buf, u16 *len) switch (req->bmRequestType & USB_REQ_TYPE_RECIPIENT) { case USB_REQ_TYPE_DEVICE: - return _usbd_standard_request_device(req, buf, len); + return _usbd_standard_request_device(usbd_dev, req, buf, len); case USB_REQ_TYPE_INTERFACE: - return _usbd_standard_request_interface(req, buf, len); + return _usbd_standard_request_interface(usbd_dev, req, + buf, len); case USB_REQ_TYPE_ENDPOINT: - return _usbd_standard_request_endpoint(req, buf, len); + return _usbd_standard_request_endpoint(usbd_dev, req, buf, len); default: return 0; } -- cgit v1.2.3 From e8ec29e636ec78da27efd2a077125144039a73c5 Mon Sep 17 00:00:00 2001 From: Jason Kotzin Date: Wed, 22 Aug 2012 17:06:28 -0700 Subject: Adding vendor class definition --- include/libopencm3/usb/usbstd.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/libopencm3/usb/usbstd.h b/include/libopencm3/usb/usbstd.h index 8610fdb..5b1cea4 100644 --- a/include/libopencm3/usb/usbstd.h +++ b/include/libopencm3/usb/usbstd.h @@ -38,6 +38,9 @@ struct usb_setup_data { u16 wLength; } __attribute__((packed)); +/* Class Definition */ +#define USB_CLASS_VENDOR 0xFF + /* bmRequestType bit definitions */ #define USB_REQ_TYPE_IN 0x80 #define USB_REQ_TYPE_STANDARD 0x00 -- cgit v1.2.3 From 4a6f4c0f7d62858a4a9afba18f11289cb0bb8358 Mon Sep 17 00:00:00 2001 From: chrysn Date: Sat, 15 Sep 2012 01:29:31 +0200 Subject: remove the support libraries for efm32 i don't plan to extend or support them, and they'll just grow stale --- examples/efm32/tinygecko/Makefile.include | 97 --- .../tinygecko/efm32-tg-stk3300/Makefile.include | 29 - examples/efm32/tinygecko/efm32-tg-stk3300/README | 9 - .../tinygecko/efm32-tg-stk3300/lcd_demo/Makefile | 23 - .../tinygecko/efm32-tg-stk3300/lcd_demo/README | 8 - .../lcd_demo/generate_lcd_mapping.py | 76 --- .../tinygecko/efm32-tg-stk3300/lcd_demo/lcd_demo.c | 130 ---- .../efm32-tg-stk3300/lcd_demo/lcd_mapping.yaml | 192 ------ .../efm32-tg-stk3300/lightswitch/Makefile | 22 - .../tinygecko/efm32-tg-stk3300/lightswitch/README | 13 - .../lightswitch/lightswitch-busywait.c | 40 -- .../lightswitch/lightswitch-common.c | 88 --- .../lightswitch/lightswitch-interrupt.c | 71 --- .../efm32-tg-stk3300/lightswitch/lightswitch.c | 30 - .../tinygecko/efm32-tg-stk3300/miniblink/Makefile | 23 - .../tinygecko/efm32-tg-stk3300/miniblink/README | 9 - .../efm32-tg-stk3300/miniblink/miniblink.c | 71 --- include/libopencm3/efm32/tinygecko/README.dox | 14 - .../efm32/tinygecko/cmu.convenienceheaders | 63 -- include/libopencm3/efm32/tinygecko/cmu.h | 678 --------------------- include/libopencm3/efm32/tinygecko/cmu.yaml | 458 -------------- .../libopencm3/efm32/tinygecko/devicerevision.h | 49 -- .../efm32/tinygecko/emu.convenienceheaders | 18 - include/libopencm3/efm32/tinygecko/emu.h | 127 ---- include/libopencm3/efm32/tinygecko/emu.yaml | 50 -- .../efm32/tinygecko/generate-license.yaml | 19 - include/libopencm3/efm32/tinygecko/generate.py | 176 ------ include/libopencm3/efm32/tinygecko/generate.yaml | 3 - include/libopencm3/efm32/tinygecko/gpio.h | 498 --------------- include/libopencm3/efm32/tinygecko/irq.h | 55 -- .../efm32/tinygecko/lcd.convenienceheaders | 0 include/libopencm3/efm32/tinygecko/lcd.h | 295 --------- include/libopencm3/efm32/tinygecko/lcd.yaml | 241 -------- lib/efm32/tinygecko/devicerevision.c | 29 - lib/efm32/tinygecko/gpio.c | 42 -- 35 files changed, 3746 deletions(-) delete mode 100644 examples/efm32/tinygecko/Makefile.include delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/README delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/Makefile delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/README delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/generate_lcd_mapping.py delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/lcd_demo.c delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/lcd_mapping.yaml delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/Makefile delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/README delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-busywait.c delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch.c delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/README delete mode 100644 examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c delete mode 100644 include/libopencm3/efm32/tinygecko/README.dox delete mode 100644 include/libopencm3/efm32/tinygecko/cmu.convenienceheaders delete mode 100644 include/libopencm3/efm32/tinygecko/cmu.h delete mode 100644 include/libopencm3/efm32/tinygecko/cmu.yaml delete mode 100644 include/libopencm3/efm32/tinygecko/devicerevision.h delete mode 100644 include/libopencm3/efm32/tinygecko/emu.convenienceheaders delete mode 100644 include/libopencm3/efm32/tinygecko/emu.h delete mode 100644 include/libopencm3/efm32/tinygecko/emu.yaml delete mode 100644 include/libopencm3/efm32/tinygecko/generate-license.yaml delete mode 100644 include/libopencm3/efm32/tinygecko/generate.py delete mode 100644 include/libopencm3/efm32/tinygecko/generate.yaml delete mode 100644 include/libopencm3/efm32/tinygecko/gpio.h delete mode 100644 include/libopencm3/efm32/tinygecko/irq.h delete mode 100644 include/libopencm3/efm32/tinygecko/lcd.convenienceheaders delete mode 100644 include/libopencm3/efm32/tinygecko/lcd.h delete mode 100644 include/libopencm3/efm32/tinygecko/lcd.yaml delete mode 100644 lib/efm32/tinygecko/devicerevision.c delete mode 100644 lib/efm32/tinygecko/gpio.c (limited to 'include') diff --git a/examples/efm32/tinygecko/Makefile.include b/examples/efm32/tinygecko/Makefile.include deleted file mode 100644 index 8c42816..0000000 --- a/examples/efm32/tinygecko/Makefile.include +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## Copyright (C) 2010 Piotr Esden-Tempski -## Copyright (C) 2012 chrysn -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -LD = $(PREFIX)-gcc -OBJCOPY = $(PREFIX)-objcopy -OBJDUMP = $(PREFIX)-objdump -GDB = $(PREFIX)-gdb -# Uncomment this line if you want to use the installed (not local) library. -#TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) -TOOLCHAIN_DIR = ../../../../.. -CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ - -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD\ - -D$(FAMILY) -LDSCRIPT ?= ${TOOLCHAIN_DIR}/lib/efm32/tinygecko/$(MCU).ld -LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib/efm32/tinygecko \ - -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ - -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float -OBJS += $(BINARY).o - -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -NULL := 2>/dev/null -else -LDFLAGS += -Wl,--print-gc-sections -endif - -.SUFFIXES: .elf .bin .hex .srec .list .images -.SECONDEXPANSION: -.SECONDARY: - -all: images - -images: $(BINARY).images -flash: $(BINARY).flash - -%.images: %.bin %.hex %.srec %.list - @#echo "*** $* images generated ***" - -%.bin: %.elf - @#printf " OBJCOPY $(*).bin\n" - $(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin - -%.hex: %.elf - @#printf " OBJCOPY $(*).hex\n" - $(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex - -%.srec: %.elf - @#printf " OBJCOPY $(*).srec\n" - $(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec - -%.list: %.elf - @#printf " OBJDUMP $(*).list\n" - $(Q)$(OBJDUMP) -S $(*).elf > $(*).list - -%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/efm32/tinygecko/libopencm3_efm32tinygecko.a - @#printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_efm32tinygecko $(LDFLAGS) - -%.o: %.c Makefile - @#printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - $(Q)rm -f *.o - $(Q)rm -f *.d - $(Q)rm -f *.elf - $(Q)rm -f *.bin - $(Q)rm -f *.hex - $(Q)rm -f *.srec - $(Q)rm -f *.list - -.PHONY: images clean - --include $(OBJS:.o=.d) - diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include b/examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include deleted file mode 100644 index 218abd8..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/Makefile.include +++ /dev/null @@ -1,29 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2012 chrysn -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -MCU = EFM32TG840F32 -FAMILY = TINYGECKO - -EACOMMANDER = ~/energymicro/energymicro/eACommander.sh - -include $(dir $(lastword $(MAKEFILE_LIST)))../Makefile.include - -upload: $(BINARY).bin - # eacommander is just as nonfree as jlink.sh, but much less of a hasle - $(EACOMMANDER) --flash $< --verify --mode mcu --address 0 --reset diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/README b/examples/efm32/tinygecko/efm32-tg-stk3300/README deleted file mode 100644 index ffa3b59..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/README +++ /dev/null @@ -1,9 +0,0 @@ -========================= -EFM32-TG-STK3300 Examples -========================= - -Examples in this directory are designed to be run on the Energy Micro EFM32 -Tiny Gecko Starter Kit, which is based on the EFM32TG840F32 MCU, has an onboard -USB debug and power management interface, and a bunch of peripherials built in -that demonstrate the chip's low power capabilities (LED, LCD display, light -sensor, touch slider, LC sensor, push buttons). diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/Makefile b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/Makefile deleted file mode 100644 index 7ef06ad..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## Copyright (C) 2012 chrysn -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BINARY = lcd_demo - -include ../Makefile.include diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/README b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/README deleted file mode 100644 index 207ed10..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/README +++ /dev/null @@ -1,8 +0,0 @@ -========================================= -EFM32-TG-STK3300 Examples LCD Demo README -========================================= - -This is an example on how to use the LCD peripherial on Energy Micro Tiny Gecko -chips. - -It's intended for the EFM32-TG-STK3300 eval board. diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/generate_lcd_mapping.py b/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/generate_lcd_mapping.py deleted file mode 100644 index 1b6405f..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lcd_demo/generate_lcd_mapping.py +++ /dev/null @@ -1,76 +0,0 @@ -#!/usr/bin/env python - -import yaml - -class Font(dict): - def __init__(self, letterdict): - for (k, v) in letterdict.items(): - self[k] = set(v.split()) - -class Display(object): - def __init__(self, data): - self.mapping = {} - - for c, segs in enumerate(data['coms']): - for s, name in enumerate(segs): - self.mapping[name] = (c, s) - - def render_text(self, text, symbols, font): - cursor = 1 - segments = set() - for letter in text: - if letter == '.': - segments.add("a%s_dp"%(cursor-1)) - elif letter == ':': - segments.add("a%s_colon"%(cursor-1)) - elif letter in font: - for segment in font[letter]: - segments.add("a%s_%s"%(cursor, segment)) - cursor += 1 - - for s in symbols: - segments.add(s) - - coms = {} - for segment in segments: - com, seg = self.mapping[segment] - coms[com] = coms.get(com, 0) | (1< - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * Demo of the LCD display aboard the EFM32-TG-STK330 eval board. - */ - -#include -#include -#include -#include "../lightswitch/lightswitch-common.c" -void led_toggle(void) { gpio_toggle(GPIO_PD, GPIO7); } - -void delay(void) -{ - int x; - - /* Start up delay until we mess with clock stuff, so the debugger can catch up. */ - for(x = 0; x < 10000000; ++x) led_on(); -} - -void lcd_init(void) -{ - /* LCD is a LE module. We're constantly powered on for now, so using - * HFCORECLK/2 */ - CMU_HFCORECLKEN0 |= CMU_HFCORECLKEN0_LE; - CMU_LFCLKSEL = (CMU_LFCLKSEL & ~CMU_LFCLKSEL_LFA_MASK) | CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; - /* We need to get this down to reasonable 100Hz from 14MHz, 7MHz at - * LFACLK, 70kHz after LFA prescaler, 10kHz after FDIV. Octaplexing - * brings us down to about 500Hz. */ - CMU_LFAPRESC0 |= CMU_LFAPRESC0_LCD_DIV128; - CMU_LCDCTRL |= CMU_LCDCTRL_FDIV_MASK; /* factor 7+1 */ - - /* If we don't wait for the prescaler to become ready, the "Do it" step - * won't pass. */ - while (CMU_SYNCBUSY & CMU_SYNCBUSY_LFAPRESC0); - - CMU_LFACLKEN0 |= CMU_LFACLKEN0_LCD; - - while (CMU_SYNCBUSY & CMU_SYNCBUSY_LFACLKEN0); - - /* Voltage is around 3.3V anyway, we don't need voltage boosting, - * leaving it disabled. I don't fully understand the implications of - * biasing yet, but it seems like he more biased the better, and will - * just affect frame rate negatively. */ - LCD_DISPCTRL = (LCD_DISPCTRL & ~(LCD_DISPCTRL_BIAS_MASK | LCD_DISPCTRL_MUX_MASK)) | LCD_DISPCTRL_BIAS_ONEFOURTH | LCD_DISPCTRL_MUX_OCTAPLEX; - - /* Segments default to disabled, enable the 20 relevant ones */ - LCD_SEGEN = ~(~0<<5); - - /* Do it */ - LCD_CTRL |= LCD_CTRL_EN; - - while (LCD_SYNCBUSY & LCD_SYNCBUSY_CTRL) led_off(); - led_on(); -} - -void set_bank(u8 com, u32 data) -{ - switch(com) - { - case 0: LCD_SEGD0L = data; break; - case 1: LCD_SEGD1L = data; break; - case 2: LCD_SEGD2L = data; break; - case 3: LCD_SEGD3L = data; break; - case 4: LCD_SEGD4L = data; break; - case 5: LCD_SEGD5L = data; break; - case 6: LCD_SEGD6L = data; break; - case 7: LCD_SEGD7L = data; break; - } -} - -int main(void) -{ - u8 active_bit = 0; - u8 active_com = 0; - - gpio_setup(); - -// delay(); - - lcd_init(); - - /* "{FNORD}" with a gecko as generated by current generate_lcd_mapping.py */ -set_bank(0, 0x000a00); -set_bank(1, 0x0031cb); -set_bank(2, 0x004622); -set_bank(3, 0x0012a8); -set_bank(4, 0x00481a); -set_bank(5, 0x001140); -set_bank(6, 0x004642); -set_bank(7, 0x0051ac); - - while(1) - { - if (pb0_get()) - { - while(pb0_get()); - - set_bank(active_com, ~0); - active_bit = (active_bit + 1) % 21; /* one more to see where 0 is */ - set_bank(active_com, ~(1< -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BINARY = lightswitch - -include ../Makefile.include diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/README b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/README deleted file mode 100644 index 41943dc..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/README +++ /dev/null @@ -1,13 +0,0 @@ -============================================ -EFM32-TG-STK3300 Examples lightswitch README -============================================ - -This is a small example program for GPIO input and output, and how the device -can be configured to use minimal power (although the example is merely -scratching the surface of what is possible powersaving-wise). - -It's intended for the EFM32-TG-STK3300 eval board. It turn the User LED on when -PB0 is pressed, and off when PB1 is pressed. - -Various implementations are offered (-busywait, -interrupt), and can configured -in lightswitch.c. diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-busywait.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-busywait.c deleted file mode 100644 index d78d0e1..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-busywait.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#define ISER0 MMIO32(0xE000E100) -#define ICER0 MMIO32(0xE000E180) -#define ISPR0 MMIO32(0XE000E200) -#define ICPR0 MMIO32(0XE000E280) - -/** @file Simplest implementation of the lightswitch mechanism. */ - -int main(void) -{ - gpio_setup(); - - while(1) { - if (pb0_get()) - led_on(); - if (pb1_get()) - led_off(); - }; -} diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c deleted file mode 100644 index dcc5984..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-common.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file Common definitions used by all lightswitch implementations */ - -#include -#include - -/** The User LED is connected to PD7 to the plus side of the LED according to - * t0011_efm32_tiny_gecko_stk_user_manual.pdf figures 16.2 and 16.3 (called - * UIF_LED0) - */ -#define LED_PORT GPIO_PD -#define LED_PIN GPIO7 - -#define BUTTON0_PORT GPIO_PD -#define BUTTON0_PORT_EXTIPSEL GPIO_EXTIPSEL_PORTD -#define BUTTON0_PIN_NUMBER 8 -#define BUTTON0_PIN GPIO8 -#define BUTTON1_PORT GPIO_PB -#define BUTTON1_PORT_EXTIPSEL GPIO_EXTIPSEL_PORTB -#define BUTTON1_PIN_NUMBER 11 -#define BUTTON1_PIN GPIO11 - -void gpio_setup(void); -void led_on(void); -void led_off(void); - -bool pb0_get(void); -bool pb1_get(void); - -/** - * Enable GPIO, and set up port D7 as an output pin and D8 and B11 as input. - */ - -void gpio_setup(void) -{ - // Before GPIO works, according to d0034_efm32tg_reference_manual.pdf - // note in section 28.3.7, we'll have to enable GPIO in CMU_HFPERCLKEN0 - - CMU_HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; - - gpio_set_mode(LED_PORT, GPIO_MODE_PUSHPULL, LED_PIN); - - // Button PB0 is connected to pin PD8 and pulled low when pushed, - // Botton PB1 to pin PB11 (sources as for LED). Pullups and debouncing - // are alreay in place in hardware, so no filtering or pullup is - // needed. - - gpio_set_mode(BUTTON0_PORT, GPIO_MODE_INPUT, BUTTON0_PIN); - gpio_set_mode(BUTTON1_PORT, GPIO_MODE_INPUT, BUTTON1_PIN); -} - -void led_on(void) -{ - gpio_set(LED_PORT, LED_PIN); -} - -void led_off(void) -{ - gpio_clear(LED_PORT, LED_PIN); -} - -bool pb0_get(void) -{ - return !gpio_get(GPIO_PD, GPIO8); -} - -bool pb1_get(void) -{ - return !gpio_get(GPIO_PB, GPIO11); -} diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c b/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c deleted file mode 100644 index 71a1008..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/lightswitch/lightswitch-interrupt.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#define ISER0 MMIO32(0xE000E100) - -void interrupt_setup() -{ - // These are the ports the pin interrupts for 8 and 11 are to be - // configured to, and they should trigger on falling edge. - - GPIO_EXTIPSELH = (BUTTON0_PORT_EXTIPSEL << ((BUTTON0_PIN_NUMBER-8)*4)) | - (BUTTON1_PORT_EXTIPSEL << ((BUTTON1_PIN_NUMBER-8)*4)); - - GPIO_EXTIFALL = BUTTON0_PIN | BUTTON1_PIN; - - // Enable interrupts on the GPIO side - - GPIO_INSENSE = GPIO_INSENSE_INT; - GPIO_IEN = BUTTON0_PIN | BUTTON1_PIN; - - // Enable GPIO interrupts in NVIC - - ISER0 = (1< - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * Example for switching the User LED of the EFM32-TG-STK330 eval board on and - * off using the buttons. - */ - -#include "lightswitch-common.c" - -/** Change this include to -busywait, -interrupt, or -prs (not implemented - * yet). The overall behavior will not change, but different implementations - * will be used. */ -#include "lightswitch-busywait.c" diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile deleted file mode 100644 index 760b99b..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## Copyright (C) 2012 chrysn -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BINARY = miniblink - -include ../Makefile.include diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/README b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/README deleted file mode 100644 index d19e4fe..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/README +++ /dev/null @@ -1,9 +0,0 @@ -========================================== -EFM32-TG-STK3300 Examples miniblink README -========================================== - -This is the smallest-possible example program using libopencm3. - -It's intended for the EFM32-TG-STK3300 eval board. It should blink -the user LED on the board. - diff --git a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c b/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c deleted file mode 100644 index 0269847..0000000 --- a/examples/efm32/tinygecko/efm32-tg-stk3300/miniblink/miniblink.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -void led_setup(void); -void led_toggle(void); - -/** @file - * Minimal example for making the User LED of the EFM32-TG-STK330 eval board blink. - */ - -/** - * Toggle the User LED in an infinite loop, with time between the toggling - * determined by a busy loop stupidly counting up. - */ - -int main(void) -{ - int x; - - led_setup(); - - while(1) { - for(x = 0; x < 200000; ++x) asm("mov r0,r0"); /* no-op, prevent compiler from optimizing this away */ - led_toggle(); - }; -} - -/** - * Enable GPIO, and set up port D7 as an output pin. - */ - -void led_setup(void) -{ - // Before GPIO works, according to d0034_efm32tg_reference_manual.pdf - // note in section 28.3.7, we'll have to enable GPIO in CMU_HFPERCLKEN0 - - CMU_HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; - - // The User LED is connected to PD7 to the plus side of the LED - // according to t0011_efm32_tiny_gecko_stk_user_manual.pdf figures 16.2 - // and 16.3 (called UIF_LED0) - - gpio_set_mode(GPIO_PD, GPIO_MODE_PUSHPULL, GPIO7); - // GPIO_PD_MODEL = GPIO_MODE_PUSHPULL<<(7*4); -} - -void led_toggle(void) -{ - gpio_toggle(GPIO_PD, GPIO7); - // GPIO_PD_DOUTTGL = 1<<7; -} diff --git a/include/libopencm3/efm32/tinygecko/README.dox b/include/libopencm3/efm32/tinygecko/README.dox deleted file mode 100644 index 04da755..0000000 --- a/include/libopencm3/efm32/tinygecko/README.dox +++ /dev/null @@ -1,14 +0,0 @@ -/** - -@brief EFM32 Tiny Gecko headers - -This directory contains all headers specific to the Tiny Gecko family of the -Energy Micro EFM32 series. - -The individual peripherials described here all include hints at where the -information was taken from, but usually it stems from -d0034_efm32tg_reference_manual.pdf. - -@defgroup EFM32TG EFM32 Tiny Gecko - -*/ diff --git a/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders b/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders deleted file mode 100644 index 212405d..0000000 --- a/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders +++ /dev/null @@ -1,63 +0,0 @@ -/** CMU convenience functions - * - * These functions assist in clock switching, and are intended to be safer to - * use than direct fiddling with registers. They try to be suitable for typical - * applications, and will invest some bytes of code in order to minimize power - * consumption. - * - * @todo Work on this module is stalled until I can figure out if there is a - * way to have a cmu_shutdown_unused function at all. - * - * @defgroup EFM32TG_CMU_convenience CMU convenience functions - * @{ - */ - -/** Disable all oscillators not currently in use. - * - * The implementation follows d0034_efm32tg_reference_manual.pdf figure 11.1. - * The clock out pin configurations are not depicted there, but described in - * section 11.3.4. - * - * @todo This function is ignorant of ongoing calibrations. - * - * @todo This doesn't work at all: Fields like HFCLKSEL are write-only. - * */ -static void cmu_shutdown_unused(void) -{ - /* Is HFXO needed? */ - if (!( - (CMU_CMD & CMU_CMD_HFCLKSEL_MASK) == CMU_CMD_HFCLKSEL_HFXO || - ( - (CMU_CTRL & CMU_CTRL_CLKOUTSEL1_MASK) == CMU_CTRL_CLKOUTSEL1_HFXOQ && - (CMU_ROUTE & CMU_ROUTE_CLKOUT1PEN) - ) || ( - (CMU_CTRL & CMU_CTRL_CLKOUTSEL0_MASK) == CMU_CTRL_CLKOUTSEL0_HFXO && - (CMU_ROUTE & CMU_ROUTE_CLKOUT0PEN) - ))) - CMU_OSCENCMD = CMU_OSCENCMD_HFXODIS; - - /* Is HFRCO neede? */ - if (!( - (CMU_CMD & CMU_CMD_HFCLKSEL_MASK) == CMU_CMD_HFCLKSEL_HFRCO || - ( - (CMU_CTRL & CMU_CTRL_CLKOUTSEL1_MASK) == CMU_CTRL_CLKOUTSEL1_HFRCOQ && - (CMU_ROUTE & CMU_ROUTE_CLKOUT1PEN) - ) || ( - (CMU_CTRL & CMU_CTRL_CLKOUTSEL0_MASK) == CMU_CTRL_CLKOUTSEL0_HFRCO && - (CMU_ROUTE & CMU_ROUTE_CLKOUT0PEN) - ))) - {} -// CMU_OSCENCMD = CMU_OSCENCMD_HFRCODIS; -} - -/** Switch HFCLK to LFRC. This call is not only blocking, but even freezes - * everything depending on HFCLK until LFRC is stable. The procedure is - * sketched in d0034_efm32tg_reference_manual.pdf figure 11.2. */ -static void cmu_hfclk_switch_blocking(void) -{ - CMU_OSCENCMD = CMU_OSCENCMD_LFRCOEN; - CMU_CMD = CMU_CMD_HFCLKSEL_LFRCO; - CMU_OSCENCMD = CMU_OSCENCMD_HFRCODIS; -} - -/** @} */ diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h deleted file mode 100644 index 80c959f..0000000 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ /dev/null @@ -1,678 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * @see EFM32TG_CMU - */ - -/** Definitions for the CMU subsystem (Clock Management Unit). - * - * This corresponds to the description in d0034_efm32tg_reference_manual.pdf - * section 11. - * - * @ingroup EFM32TG - * @defgroup EFM32TG_CMU CMU (Clock Management Unit) - * @{ - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_CMU_H -#define LIBOPENCM3_EFM32_TINYGECKO_CMU_H - -#include -#include - -/** Register definitions and register value definitions for the CMU subsystem - * - * @defgroup EFM32TG_CMU_regsandvals CMU registers and values - * @{ - */ - -/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4 - * - * @defgroup EFM32TG_CMU_registers CMU registers - * @{ - */ - -#define CMU_CTRL MMIO32(CMU_BASE + 0x000) /**< @see EFM32TG_CMU_CTRL_bits */ -#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) /**< @see EFM32TG_CMU_HFCORECLKDIV_values */ -#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) /**< @see EFM32TG_CMU_HFPERCLKDIV_bits */ -#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00c) /**< @see EFM32TG_CMU_HFRCOCTRL_bits */ -#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) -#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) /**< @see EFM32TG_CMU_AUXHFRCOCTRL_bits */ -#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) /**< @see EFM32TG_CMU_CALCTRL_bits */ -#define CMU_CALCNT MMIO32(CMU_BASE + 0x01c) -#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) /**< @see EFM32TG_CMU_OSCENCMD_bits */ -#define CMU_CMD MMIO32(CMU_BASE + 0x024) /**< @see EFM32TG_CMU_CMD_bits */ -#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) /**< @see EFM32TG_CMU_LFCLKSEL_bits */ -#define CMU_STATUS MMIO32(CMU_BASE + 0x02c) /**< @see EFM32TG_CMU_STATUS_bits */ -#define CMU_IF MMIO32(CMU_BASE + 0x030) /**< @see EFM32TG_CMU_I_bits */ -#define CMU_IFS MMIO32(CMU_BASE + 0x034) /**< @see EFM32TG_CMU_I_bits */ -#define CMU_IFC MMIO32(CMU_BASE + 0x038) /**< @see EFM32TG_CMU_I_bits */ -#define CMU_IEN MMIO32(CMU_BASE + 0x03c) /**< @see EFM32TG_CMU_I_bits */ -#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) /**< @see EFM32TG_CMU_HFCORECLKEN0_bits */ -#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) /**< @see EFM32TG_CMU_HFPERCLKEN0_bits */ -#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) /**< @see EFM32TG_CMU_SYNCBUSY_bits */ -#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) /**< @see EFM32TG_CMU_FREEZE_bits */ -#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) /**< @see EFM32TG_CMU_LFACLKEN0_bits */ -#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) /**< @see EFM32TG_CMU_LFBCLKEN0_bits */ -#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) /**< @see EFM32TG_CMU_LFAPRESC0_bits */ -#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) /**< @see EFM32TG_CMU_LFBPRESC0_bits */ -#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) /**< @see EFM32TG_CMU_PCNTCTRL_bits */ -#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07c) /**< @see EFM32TG_CMU_LCDCTRL_bits */ -#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) /**< @see EFM32TG_CMU_ROUTE_bits */ -#define CMU_LOCK MMIO32(CMU_BASE + 0x084) /**< @see EFM32TG_CMU_LOCK_values */ - -/** @} */ - -/** Bit states for the CMU_CTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.1 for definitions. - * - * @defgroup EFM32TG_CMU_CTRL_bits CMU CTRL bits - * @{ - */ - -#define CMU_CTRL_DBGCLK_AUXHFRCO (0<<28) -#define CMU_CTRL_DBGCLK_HFCLK (1<<28) -#define CMU_CTRL_DBGCLK_MASK (0x1<<28) -#define CMU_CTRL_CLKOUTSEL1_LFRCO (0<<23) -#define CMU_CTRL_CLKOUTSEL1_LFXO (1<<23) -#define CMU_CTRL_CLKOUTSEL1_HFCLK (2<<23) -#define CMU_CTRL_CLKOUTSEL1_LFXOQ (3<<23) -#define CMU_CTRL_CLKOUTSEL1_HFXOQ (4<<23) -#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (5<<23) -#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (6<<23) -#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (7<<23) -#define CMU_CTRL_CLKOUTSEL1_MASK (0x7<<23) -#define CMU_CTRL_CLKOUTSEL0_HFRCO (0<<20) -#define CMU_CTRL_CLKOUTSEL0_HFXO (1<<20) -#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (2<<20) -#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (3<<20) -#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (4<<20) -#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (5<<20) -#define CMU_CTRL_CLKOUTSEL0_ULFRCO (6<<20) -#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (7<<20) -#define CMU_CTRL_CLKOUTSEL0_MASK (0x7<<20) -#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (0<<18) -#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (1<<18) -#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (2<<18) -#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (3<<18) -#define CMU_CTRL_LFXOTIMEOUT_MASK (0x3<<18) -#define CMU_CTRL_LFXOBUFCUR (1<<17) -#define CMU_CTRL_LXFOBOOST_70PCENT (0<<13) -#define CMU_CTRL_LXFOBOOST_100PCENT (1<<13) -#define CMU_CTRL_LXFOBOOST_MASK (0x1<<13) -#define CMU_CTRL_LFXOMODE_XTAL (0<<11) -#define CMU_CTRL_LFXOMODE_BUFEXTCLK (1<<11) -#define CMU_CTRL_LFXOMODE_DIGEXTCLK (2<<11) -#define CMU_CTRL_LFXOMODE_MASK (0x3<<11) -#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (0<<9) -#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (1<<9) -#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (2<<9) -#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (3<<9) -#define CMU_CTRL_HFXOTIMEOUT_MASK (0x3<<9) -#define CMU_CTRL_HFXOGLITCHDETEN (1<<7) -#define CMU_CTRL_HFXOBUFCUR_MASK (0x3<<5) -#define CMU_CTRL_HFXOBOOST_50PCENT (0<<2) -#define CMU_CTRL_HFXOBOOST_70PCENT (1<<2) -#define CMU_CTRL_HFXOBOOST_80PCENT (2<<2) -#define CMU_CTRL_HFXOBOOST_100PCENT (3<<2) -#define CMU_CTRL_HFXOBOOST_MASK (0x3<<2) -#define CMU_CTRL_HFXOMODE_XTAL (0<<0) -#define CMU_CTRL_HFXOMODE_BUFEXTCLK (1<<0) -#define CMU_CTRL_HFXOMODE_DIGEXTCLK (2<<0) -#define CMU_CTRL_HFXOMODE_MASK (0x3<<0) - -/** @} */ - -/** Values for the CMU_HFCORECLKDIV register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.2 for definitions. - * - * @defgroup EFM32TG_CMU_HFCORECLKDIV_values CMU HFCORECLKDIV values - * @{ - */ - -#define CMU_HFCORECLKDIV_HFCLK 0 -#define CMU_HFCORECLKDIV_HFCLK2 1 -#define CMU_HFCORECLKDIV_HFCLK4 2 -#define CMU_HFCORECLKDIV_HFCLK8 3 -#define CMU_HFCORECLKDIV_HFCLK16 4 -#define CMU_HFCORECLKDIV_HFCLK32 5 -#define CMU_HFCORECLKDIV_HFCLK64 6 -#define CMU_HFCORECLKDIV_HFCLK128 7 -#define CMU_HFCORECLKDIV_HFCLK256 8 -#define CMU_HFCORECLKDIV_HFCLK512 9 - -/** @} */ - -/** Bit states for the CMU_HFPERCLKDIV register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.3 for definitions. - * - * @defgroup EFM32TG_CMU_HFPERCLKDIV_bits CMU HFPERCLKDIV bits - * @{ - */ - -#define CMU_HFPERCLKDIV_HFPERCLKEN (1<<8) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (0<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (1<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (2<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (3<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (4<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (5<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (6<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (7<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (8<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (9<<0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK (0x7<<0) - -/** @} */ - -/** Bit states for the CMU_HFRCOCTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.4 for definitions. - * - * @defgroup EFM32TG_CMU_HFRCOCTRL_bits CMU HFRCOCTRL bits - * @{ - */ - -#define CMU_HFRCOCTRL_SUDELAY_MASK (0x1f<<12) -#define CMU_HFRCOCTRL_BAND_1MHZ (0<<8) -#define CMU_HFRCOCTRL_BAND_7MHZ (1<<8) -#define CMU_HFRCOCTRL_BAND_11MHZ (2<<8) -#define CMU_HFRCOCTRL_BAND_14MHZ (3<<8) -#define CMU_HFRCOCTRL_BAND_21MHZ (4<<8) -#define CMU_HFRCOCTRL_BAND_28MHZ (5<<8) -#define CMU_HFRCOCTRL_BAND_MASK (0x7<<8) -#define CMU_HFRCOCTRL_TUNING_MASK (0xff<<0) - -/** @} */ - -/** Bit states for the CMU_AUXHFRCOCTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.6 for definitions. - * - * @defgroup EFM32TG_CMU_AUXHFRCOCTRL_bits CMU AUXHFRCOCTRL bits - * @{ - */ - -#define CMU_AUXHFRCOCTRL_BAND_14MHZ (0<<8) -#define CMU_AUXHFRCOCTRL_BAND_11MHZ (1<<8) -#define CMU_AUXHFRCOCTRL_BAND_7MHZ (2<<8) -#define CMU_AUXHFRCOCTRL_BAND_1MHZ (3<<8) -#define CMU_AUXHFRCOCTRL_BAND_28MHZ (6<<8) -#define CMU_AUXHFRCOCTRL_BAND_21MHZ (7<<8) -#define CMU_AUXHFRCOCTRL_BAND_MASK (0x7<<8) -#define CMU_AUXHFRCOCTRL_TUNING_MASK (0xff<<0) - -/** @} */ - -/** Bit states for the CMU_CALCTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 11.6.7 for definitions. - * - * @defgroup EFM32TG_CMU_CALCTRL_bits CMU CALCTRL bits - * @{ - */ - -#define CMU_CALCTRL_CONT (1<<6) -#define CMU_CALCTRL_DOWNSEL_HFCLK (0<<3) -#define CMU_CALCTRL_DOWNSEL_HFXO (1<<3) -#define CMU_CALCTRL_DOWNSEL_LFXO (2<<3) -#define CMU_CALCTRL_DOWNSEL_HFRCO (3<<3) -#define CMU_CALCTRL_DOWNSEL_LFRCO (4<<3) -#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (5<<3) -#define CMU_CALCTRL_DOWNSEL_MASK (0x7<<3) -#define CMU_CALCTRL_UPSEL_HFXO (0<<0) -#define CMU_CALCTRL_UPSEL_LFXO (1<<0) -#define CMU_CALCTRL_UPSEL_HFRCO (2<<0) -#define CMU_CALCTRL_UPSEL_LFRCO (3<<0) -#define CMU_CALCTRL_UPSEL_AUXHFRCO (4<<0) -#define CMU_CALCTRL_UPSEL_MASK (0x7<<0) - -/** @} */ - -/** Bit states for the CMU_OSCENCMD register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.9 for definitions. - * - * @defgroup EFM32TG_CMU_OSCENCMD_bits CMU OSCENCMD bits - * @{ - */ - -#define CMU_OSCENCMD_LFXODIS (1<<9) -#define CMU_OSCENCMD_LFXOEN (1<<8) -#define CMU_OSCENCMD_LFRCODIS (1<<7) -#define CMU_OSCENCMD_LFRCOEN (1<<6) -#define CMU_OSCENCMD_AUXHFRCODIS (1<<5) -#define CMU_OSCENCMD_AUXHFRCOEN (1<<4) -#define CMU_OSCENCMD_HFXODIS (1<<3) -#define CMU_OSCENCMD_HFXOEN (1<<2) -#define CMU_OSCENCMD_HFRCODIS (1<<1) -#define CMU_OSCENCMD_HFRCOEN (1<<0) - -/** @} */ - -/** Bit states for the CMU_CMD register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.10 for definitions. - * - * @defgroup EFM32TG_CMU_CMD_bits CMU CMD bits - * @{ - */ - -#define CMU_CMD_CALSTOP (1<<4) -#define CMU_CMD_CALSTART (1<<3) -#define CMU_CMD_HFCLKSEL_HFRCO (1<<0) -#define CMU_CMD_HFCLKSEL_HFXO (2<<0) -#define CMU_CMD_HFCLKSEL_LFRCO (3<<0) -#define CMU_CMD_HFCLKSEL_LFXO (4<<0) -#define CMU_CMD_HFCLKSEL_MASK (0x7<<0) - -/** @} */ - -/** Bit states for the CMU_LFCLKSEL register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.11 for definitions. - * - * @defgroup EFM32TG_CMU_LFCLKSEL_bits CMU LFCLKSEL bits - * @{ - */ - -#define CMU_LFCLKSEL_LFBE_DISABLED (0<<20) -#define CMU_LFCLKSEL_LFBE_ULFRCO (1<<20) -#define CMU_LFCLKSEL_LFBE_MASK (0x1<<20) -#define CMU_LFCLKSEL_LFAE_DISABLED (0<<16) -#define CMU_LFCLKSEL_LFAE_ULFRCO (1<<16) -#define CMU_LFCLKSEL_LFAE_MASK (0x1<<16) -#define CMU_LFCLKSEL_LFB_DISABLED (0<<2) -#define CMU_LFCLKSEL_LFB_LFRCO (1<<2) -#define CMU_LFCLKSEL_LFB_LFXO (2<<2) -#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2) -#define CMU_LFCLKSEL_LFB_MASK (0x3<<2) -#define CMU_LFCLKSEL_LFA_DISABLED (0<<0) -#define CMU_LFCLKSEL_LFA_LFRCO (1<<0) -#define CMU_LFCLKSEL_LFA_LFXO (2<<0) -#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (3<<0) -#define CMU_LFCLKSEL_LFA_MASK (0x3<<0) - -/** @} */ - -/** Bit states for the CMU_STATUS register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.12 for definitions. - * - * @defgroup EFM32TG_CMU_STATUS_bits CMU STATUS bits - * @{ - */ - -#define CMU_STATUS_CALBSY (1<<14) -#define CMU_STATUS_LFXOSEL (1<<13) -#define CMU_STATUS_LFRCOSEL (1<<12) -#define CMU_STATUS_HFXOSEL (1<<11) -#define CMU_STATUS_HFRCOSEL (1<<10) -#define CMU_STATUS_LFXORDY (1<<9) -#define CMU_STATUS_LFXOENS (1<<8) -#define CMU_STATUS_LFRCORDY (1<<7) -#define CMU_STATUS_LFRCOENS (1<<6) -#define CMU_STATUS_AUXHFRCORDY (1<<5) -#define CMU_STATUS_AUXHFRCOENS (1<<4) -#define CMU_STATUS_HFXORDY (1<<3) -#define CMU_STATUS_HFXOENS (1<<2) -#define CMU_STATUS_HFRCORDY (1<<1) -#define CMU_STATUS_HFRCOENS (1<<0) - -/** @} */ - -/** Bit states for the CMU_HFCORECLKEN0 register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.17 for definitions. - * - * @defgroup EFM32TG_CMU_HFCORECLKEN0_bits CMU HFCORECLKEN0 bits - * @{ - */ - -#define CMU_HFCORECLKEN0_LE (1<<2) -#define CMU_HFCORECLKEN0_DMA (1<<1) -#define CMU_HFCORECLKEN0_AES (1<<0) - -/** @} */ - -/** Bit states for the CMU_HFPERCLKEN0 register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.18 for definitions. - * - * @defgroup EFM32TG_CMU_HFPERCLKEN0_bits CMU HFPERCLKEN0 bits - * @{ - */ - -#define CMU_HFPERCLKEN0_I2C0 (1<<11) -#define CMU_HFPERCLKEN0_DAC0 (1<<10) -#define CMU_HFPERCLKEN0_ADC0 (1<<9) -#define CMU_HFPERCLKEN0_PRS (1<<8) -#define CMU_HFPERCLKEN0_VCMP (1<<7) -#define CMU_HFPERCLKEN0_GPIO (1<<6) -#define CMU_HFPERCLKEN0_TIMER1 (1<<5) -#define CMU_HFPERCLKEN0_TIMER0 (1<<4) -#define CMU_HFPERCLKEN0_USART1 (1<<3) -#define CMU_HFPERCLKEN0_USART0 (1<<2) -#define CMU_HFPERCLKEN0_ACMP1 (1<<1) -#define CMU_HFPERCLKEN0_ACMP0 (1<<0) - -/** @} */ - -/** Bit states for the CMU_SYNCBUSY register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.19 for definitions. - * - * @defgroup EFM32TG_CMU_SYNCBUSY_bits CMU SYNCBUSY bits - * @{ - */ - -#define CMU_SYNCBUSY_LFBPRESC0 (1<<6) -#define CMU_SYNCBUSY_LFBCLKEN0 (1<<4) -#define CMU_SYNCBUSY_LFAPRESC0 (1<<2) -#define CMU_SYNCBUSY_LFACLKEN0 (1<<0) - -/** @} */ - -/** Bit states for the CMU_FREEZE register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.20 for definitions. - * - * @defgroup EFM32TG_CMU_FREEZE_bits CMU FREEZE bits - * @{ - */ - -#define CMU_FREEZE_REGFREEZE_UPDATE (0<<0) -#define CMU_FREEZE_REGFREEZE_FREEZE (1<<0) -#define CMU_FREEZE_REGFREEZE_MASK (0x1<<0) - -/** @} */ - -/** Bit states for the CMU_LFACLKEN0 register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.21 for definitions. - * - * @defgroup EFM32TG_CMU_LFACLKEN0_bits CMU LFACLKEN0 bits - * @{ - */ - -#define CMU_LFACLKEN0_LCD (1<<3) -#define CMU_LFACLKEN0_LETIMER0 (1<<2) -#define CMU_LFACLKEN0_RTC (1<<1) -#define CMU_LFACLKEN0_LESENSE (1<<0) - -/** @} */ - -/** Bit states for the CMU_LFBCLKEN0 register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.22 for definitions. - * - * @defgroup EFM32TG_CMU_LFBCLKEN0_bits CMU LFBCLKEN0 bits - * @{ - */ - -#define CMU_LFBCLKEN0_LEUART0 (1<<0) - -/** @} */ - -/** Bit states for the CMU_LFAPRESC0 register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.23 for definitions. - * - * @defgroup EFM32TG_CMU_LFAPRESC0_bits CMU LFAPRESC0 bits - * @{ - */ - -#define CMU_LFAPRESC0_LCD_DIV16 (0<<12) -#define CMU_LFAPRESC0_LCD_DIV32 (1<<12) -#define CMU_LFAPRESC0_LCD_DIV64 (2<<12) -#define CMU_LFAPRESC0_LCD_DIV128 (3<<12) -#define CMU_LFAPRESC0_LCD_MASK (0x3<<12) -#define CMU_LFAPRESC0_LETIMER0_DIV1 (0<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV2 (1<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV4 (2<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV8 (3<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV16 (4<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV32 (5<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV64 (6<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV128 (7<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV256 (8<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV512 (9<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV1024 (10<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV2048 (11<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV4096 (12<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV8192 (13<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV16384 (14<<8) -#define CMU_LFAPRESC0_LETIMER0_DIV32768 (15<<8) -#define CMU_LFAPRESC0_LETIMER0_MASK (0xf<<8) -#define CMU_LFAPRESC0_RTC_DIV1 (0<<4) -#define CMU_LFAPRESC0_RTC_DIV2 (1<<4) -#define CMU_LFAPRESC0_RTC_DIV4 (2<<4) -#define CMU_LFAPRESC0_RTC_DIV8 (3<<4) -#define CMU_LFAPRESC0_RTC_DIV16 (4<<4) -#define CMU_LFAPRESC0_RTC_DIV32 (5<<4) -#define CMU_LFAPRESC0_RTC_DIV64 (6<<4) -#define CMU_LFAPRESC0_RTC_DIV128 (7<<4) -#define CMU_LFAPRESC0_RTC_DIV256 (8<<4) -#define CMU_LFAPRESC0_RTC_DIV512 (9<<4) -#define CMU_LFAPRESC0_RTC_DIV1024 (10<<4) -#define CMU_LFAPRESC0_RTC_DIV2048 (11<<4) -#define CMU_LFAPRESC0_RTC_DIV4096 (12<<4) -#define CMU_LFAPRESC0_RTC_DIV8192 (13<<4) -#define CMU_LFAPRESC0_RTC_DIV16384 (14<<4) -#define CMU_LFAPRESC0_RTC_DIV32768 (15<<4) -#define CMU_LFAPRESC0_RTC_MASK (0xf<<4) -#define CMU_LFAPRESC0_LESENSE_DIV1 (0<<0) -#define CMU_LFAPRESC0_LESENSE_DIV2 (1<<0) -#define CMU_LFAPRESC0_LESENSE_DIV4 (2<<0) -#define CMU_LFAPRESC0_LESENSE_DIV8 (3<<0) -#define CMU_LFAPRESC0_LESENSE_MASK (0x3<<0) - -/** @} */ - -/** Bit states for the CMU_LFBPRESC0 register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.24 for definitions. - * - * @defgroup EFM32TG_CMU_LFBPRESC0_bits CMU LFBPRESC0 bits - * @{ - */ - -#define CMU_LFBPRESC0_LEUART0_DIV1 (0<<0) -#define CMU_LFBPRESC0_LEUART0_DIV2 (1<<0) -#define CMU_LFBPRESC0_LEUART0_DIV4 (2<<0) -#define CMU_LFBPRESC0_LEUART0_DIV8 (3<<0) -#define CMU_LFBPRESC0_LEUART0_MASK (0x3<<0) - -/** @} */ - -/** Bit states for the CMU_PCNTCTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.25 for definitions. - * - * @defgroup EFM32TG_CMU_PCNTCTRL_bits CMU PCNTCTRL bits - * @{ - */ - -#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (0<<1) -#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (1<<1) -#define CMU_PCNTCTRL_PCNT0CLKSEL_MASK (0x1<<1) -#define CMU_PCNTCTRL_PCNT0CLKEN (1<<0) - -/** @} */ - -/** Bit states for the CMU_LCDCTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.26 for definitions. - * - * @defgroup EFM32TG_CMU_LCDCTRL_bits CMU LCDCTRL bits - * @{ - */ - -#define CMU_LCDCTRL_VBFDIV_DIV1 (0<<4) -#define CMU_LCDCTRL_VBFDIV_DIV2 (1<<4) -#define CMU_LCDCTRL_VBFDIV_DIV4 (2<<4) -#define CMU_LCDCTRL_VBFDIV_DIV8 (3<<4) -#define CMU_LCDCTRL_VBFDIV_DIV16 (4<<4) -#define CMU_LCDCTRL_VBFDIV_DIV32 (5<<4) -#define CMU_LCDCTRL_VBFDIV_DIV64 (6<<4) -#define CMU_LCDCTRL_VBFDIV_DIV128 (7<<4) -#define CMU_LCDCTRL_VBFDIV_MASK (0x7<<4) -#define CMU_LCDCTRL_VBOOSTEN (1<<3) -#define CMU_LCDCTRL_FDIV_MASK (0x7<<0) - -/** @} */ - -/** Bit states for the CMU_ROUTE register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.27 for definitions. - * - * @defgroup EFM32TG_CMU_ROUTE_bits CMU ROUTE bits - * @{ - */ - -#define CMU_ROUTE_LOCATION_LOC0 (0<<4) -#define CMU_ROUTE_LOCATION_LOC1 (1<<4) -#define CMU_ROUTE_LOCATION_MASK (0x7<<4) -#define CMU_ROUTE_CLKOUT1PEN (1<<1) -#define CMU_ROUTE_CLKOUT0PEN (1<<0) - -/** @} */ - -/** Values for the CMU_LOCK register - * - * See d0034_efm32tg_reference_manual.pdf section 11.5.28 for definitions. - * - * @defgroup EFM32TG_CMU_LOCK_values CMU LOCK values - * @{ - */ - -#define CMU_LOCK_IS_UNLOCKED 0 -#define CMU_LOCK_IS_LOCKED 1 -#define CMU_LOCK_SET_LOCKED 0 -#define CMU_LOCK_SET_UNLOCKED 0x580E - -/** @} */ - -/** Bit states for the CMU "I" group of registers (IF, IFS, IFC, IEN) - * - * These registers use this: - * - *
      - * - *
    • The CMU_IF register; see d0034_efm32tg_reference_manual.pdf section - * 11.5.13 for definitions.
    • - * - *
    • The CMU_IFS register; see d0034_efm32tg_reference_manual.pdf section - * 11.5.14 for definitions.
    • - * - *
    • The CMU_IFC register; see d0034_efm32tg_reference_manual.pdf section - * 11.5.15 for definitions.
    • - * - *
    • The CMU_IEN register; see d0034_efm32tg_reference_manual.pdf section - * 11.5.16 for definitions.
    • - * - *
    - * - * @defgroup EFM32TG_CMU_I_bits CMU I bits group - * @{ - */ - -#define CMU_I_CALOF (1<<6) -#define CMU_I_CALRDY (1<<5) -#define CMU_I_AUXHFRCORDY (1<<4) -#define CMU_I_LFXORDY (1<<3) -#define CMU_I_LFRCORDY (1<<2) -#define CMU_I_HFXORDY (1<<1) -#define CMU_I_HFRCORDY (1<<0) - -/** @} */ - -/** @} */ - -/** CMU convenience functions - * - * These functions assist in clock switching, and are intended to be safer to - * use than direct fiddling with registers. They try to be suitable for typical - * applications, and will invest some bytes of code in order to minimize power - * consumption. - * - * @todo Work on this module is stalled until I can figure out if there is a - * way to have a cmu_shutdown_unused function at all. - * - * @defgroup EFM32TG_CMU_convenience CMU convenience functions - * @{ - */ - -/** Disable all oscillators not currently in use. - * - * The implementation follows d0034_efm32tg_reference_manual.pdf figure 11.1. - * The clock out pin configurations are not depicted there, but described in - * section 11.3.4. - * - * @todo This function is ignorant of ongoing calibrations. - * - * @todo This doesn't work at all: Fields like HFCLKSEL are write-only. - * */ -static void cmu_shutdown_unused(void) -{ - /* Is HFXO needed? */ - if (!( - (CMU_CMD & CMU_CMD_HFCLKSEL_MASK) == CMU_CMD_HFCLKSEL_HFXO || - ( - (CMU_CTRL & CMU_CTRL_CLKOUTSEL1_MASK) == CMU_CTRL_CLKOUTSEL1_HFXOQ && - (CMU_ROUTE & CMU_ROUTE_CLKOUT1PEN) - ) || ( - (CMU_CTRL & CMU_CTRL_CLKOUTSEL0_MASK) == CMU_CTRL_CLKOUTSEL0_HFXO && - (CMU_ROUTE & CMU_ROUTE_CLKOUT0PEN) - ))) - CMU_OSCENCMD = CMU_OSCENCMD_HFXODIS; - - /* Is HFRCO neede? */ - if (!( - (CMU_CMD & CMU_CMD_HFCLKSEL_MASK) == CMU_CMD_HFCLKSEL_HFRCO || - ( - (CMU_CTRL & CMU_CTRL_CLKOUTSEL1_MASK) == CMU_CTRL_CLKOUTSEL1_HFRCOQ && - (CMU_ROUTE & CMU_ROUTE_CLKOUT1PEN) - ) || ( - (CMU_CTRL & CMU_CTRL_CLKOUTSEL0_MASK) == CMU_CTRL_CLKOUTSEL0_HFRCO && - (CMU_ROUTE & CMU_ROUTE_CLKOUT0PEN) - ))) - {} -// CMU_OSCENCMD = CMU_OSCENCMD_HFRCODIS; -} - -/** Switch HFCLK to LFRC. This call is not only blocking, but even freezes - * everything depending on HFCLK until LFRC is stable. The procedure is - * sketched in d0034_efm32tg_reference_manual.pdf figure 11.2. */ -static void cmu_hfclk_switch_blocking(void) -{ - CMU_OSCENCMD = CMU_OSCENCMD_LFRCOEN; - CMU_CMD = CMU_CMD_HFCLKSEL_LFRCO; - CMU_OSCENCMD = CMU_OSCENCMD_HFRCODIS; -} - -/** @} */ - -/** @} */ - -#endif diff --git a/include/libopencm3/efm32/tinygecko/cmu.yaml b/include/libopencm3/efm32/tinygecko/cmu.yaml deleted file mode 100644 index 7b83b7f..0000000 --- a/include/libopencm3/efm32/tinygecko/cmu.yaml +++ /dev/null @@ -1,458 +0,0 @@ -copyright: "2012 chrysn " -license: lgpl-3+ -ingroup: EFM32TG -shortdocname: EFM32TG_CMU -shortname: CMU -longname: Clock Management Unit -baseref: d0034_efm32tg_reference_manual.pdf section 11 -registers_baserefext: ".4" -templateregs: - - name: I - comment: Bits for the various CMU interrupt registers - fields: - - {name: CALOF, shift: 6} - - {name: CALRDY, shift: 5} - - {name: AUXHFRCORDY, shift: 4} - - {name: LFXORDY, shift: 3} - - {name: LFRCORDY, shift: 2} - - {name: HFXORDY, shift: 1} - - {name: HFRCORDY, shift: 0} -registers: - - name: CTRL - offset: 0x000 - definition_baserefext: ".5.1" - fields: - - name: DBGCLK - shift: 28 - values: - - {name: AUXHFRCO, value: 0} - - {name: HFCLK, value: 1} - - name: CLKOUTSEL1 - shift: 23 - length: 3 - values: - - {name: LFRCO, value: 0} - - {name: LFXO, value: 1} - - {name: HFCLK, value: 2} - - {name: LFXOQ, value: 3} - - {name: HFXOQ, value: 4} - - {name: LFRCOQ, value: 5} - - {name: HFRCOQ, value: 6} - - {name: AUXHFRCOQ, value: 7} - - name: CLKOUTSEL0 - shift: 20 - length: 3 - values: - - {name: HFRCO, value: 0} - - {name: HFXO, value: 1} - - {name: HFCLK2, value: 2} - - {name: HFCLK4, value: 3} - - {name: HFCLK8, value: 4} - - {name: HFCLK16, value: 5} - - {name: ULFRCO, value: 6} - - {name: AUXHFRCO, value: 7} - - name: LFXOTIMEOUT - shift: 18 - length: 2 - values: - - {name: 8CYCLES, value: 0} - - {name: 1KCYCLES, value: 1} - - {name: 16KCYCLES, value: 2} - - {name: 32KCYCLES, value: 3} - - name: LFXOBUFCUR - shift: 17 - - name: LXFOBOOST - shift: 13 - values: - - {name: 70PCENT, value: 0} - - {name: 100PCENT, value: 1} - - name: LFXOMODE - shift: 11 - length: 2 - values: - - {name: XTAL, value: 0} - - {name: BUFEXTCLK, value: 1} - - {name: DIGEXTCLK, value: 2} - - name: HFXOTIMEOUT - shift: 9 - length: 2 - values: - - {name: 8CYCLES, value: 0} - - {name: 256CYCLES, value: 1} - - {name: 1KCYCLES, value: 2} - - {name: 16KCYCLES, value: 3} - - name: HFXOGLITCHDETEN - shift: 7 - - name: HFXOBUFCUR - shift: 5 - length: 2 - type: undocumented - - name: HFXOBOOST - shift: 2 - length: 2 - values: - - {name: 50PCENT, value: 0} - - {name: 70PCENT, value: 1} - - {name: 80PCENT, value: 2} - - {name: 100PCENT, value: 3} - - name: HFXOMODE - shift: 0 - length: 2 - values: - - {name: XTAL, value: 0} - - {name: BUFEXTCLK, value: 1} - - {name: DIGEXTCLK, value: 2} - - name: HFCORECLKDIV - offset: 0x004 - definition_baserefext: ".5.2" - values: &HFCORECLKDIV_values - - {value: 0, name: HFCLK} - - {value: 1, name: HFCLK2} - - {value: 2, name: HFCLK4} - - {value: 3, name: HFCLK8} - - {value: 4, name: HFCLK16} - - {value: 5, name: HFCLK32} - - {value: 6, name: HFCLK64} - - {value: 7, name: HFCLK128} - - {value: 8, name: HFCLK256} - - {value: 9, name: HFCLK512} - - name: HFPERCLKDIV - offset: 0x008 - definition_baserefext: ".5.3" - fields: - - name: HFPERCLKEN - shift: 8 - - name: HFPERCLKDIV - shift: 0 - length: 3 - # not using generically named values here due to different register structure - values: *HFCORECLKDIV_values - - name: HFRCOCTRL - offset: 0x00c - definition_baserefext: ".5.4" - fields: - - name: SUDELAY - shift: 12 - length: 5 - type: undocumented - - name: BAND - shift: 8 - length: 3 - values: - - {value: 0, name: 1MHZ} - - {value: 1, name: 7MHZ} - - {value: 2, name: 11MHZ} - - {value: 3, name: 14MHZ} - - {value: 4, name: 21MHZ} - - {value: 5, name: 28MHZ} - - name: TUNING - shift: 0 - length: 8 - type: uint - - name: LFRCOCTRL - offset: 0x010 - definition_baserefext: ".5.5" - length: 7 - type: uint - - name: AUXHFRCOCTRL - offset: 0x014 - definition_baserefext: ".5.6" - fields: - - name: BAND - shift: 8 - length: 3 - values: - - {value: 0, name: 14MHZ} - - {value: 1, name: 11MHZ} - - {value: 2, name: 7MHZ} - - {value: 3, name: 1MHZ} - - {value: 6, name: 28MHZ} - - {value: 7, name: 21MHZ} - - name: TUNING - shift: 0 - length: 8 - type: uint - - name: CALCTRL - offset: 0x018 - definition_baserefext: ".6.7" - fields: - - name: CONT - shift: 6 - - name: DOWNSEL - shift: 3 - length: 3 - values: - - {value: 0, name: HFCLK} - - {value: 1, name: HFXO} - - {value: 2, name: LFXO} - - {value: 3, name: HFRCO} - - {value: 4, name: LFRCO} - - {value: 5, name: AUXHFRCO} - - name: UPSEL - shift: 0 - length: 3 - values: - - {value: 0, name: HFXO} - - {value: 1, name: LFXO} - - {value: 2, name: HFRCO} - - {value: 3, name: LFRCO} - - {value: 4, name: AUXHFRCO} - - name: CALCNT - offset: 0x01c - definition_baserefext: ".5.8" - length: 19 - type: uint - - name: OSCENCMD - offset: 0x020 - definition_baserefext: ".5.9" - fields: - - {name: LFXODIS, shift: 9} - - {name: LFXOEN, shift: 8} - - {name: LFRCODIS, shift: 7} - - {name: LFRCOEN, shift: 6} - - {name: AUXHFRCODIS, shift: 5} - - {name: AUXHFRCOEN, shift: 4} - - {name: HFXODIS, shift: 3} - - {name: HFXOEN, shift: 2} - - {name: HFRCODIS, shift: 1} - - {name: HFRCOEN, shift: 0} - - name: CMD - offset: 0x024 - definition_baserefext: ".5.10" - fields: - - name: CALSTOP - shift: 4 - - name: CALSTART - shift: 3 - - name: HFCLKSEL - shift: 0 - length: 3 - values: - - {value: 1, name: HFRCO} - - {value: 2, name: HFXO} - - {value: 3, name: LFRCO} - - {value: 4, name: LFXO} - - name: LFCLKSEL - offset: 0x028 - definition_baserefext: ".5.11" - fields: - - name: LFBE - shift: 20 - values: &LFCLKSEL_LFBE - - {value: 0, name: DISABLED} - - {value: 1, name: ULFRCO} - - name: LFAE - shift: 16 - values: *LFCLKSEL_LFBE - - name: LFB - shift: 2 - length: 2 - values: &LFCLKSEL_LFB - - {value: 0, name: DISABLED} - - {value: 1, name: LFRCO} - - {value: 2, name: LFXO} - - {value: 3, name: HFCORECLKLEDIV2} - - name: LFA - shift: 0 - length: 2 - values: *LFCLKSEL_LFB - - name: STATUS - offset: 0x02c - definition_baserefext: ".5.12" - fields: - - {name: CALBSY, shift: 14} - - {name: LFXOSEL, shift: 13} - - {name: LFRCOSEL, shift: 12} - - {name: HFXOSEL, shift: 11} - - {name: HFRCOSEL, shift: 10} - - {name: LFXORDY, shift: 9} - - {name: LFXOENS, shift: 8} - - {name: LFRCORDY, shift: 7} - - {name: LFRCOENS, shift: 6} - - {name: AUXHFRCORDY, shift: 5} - - {name: AUXHFRCOENS, shift: 4} - - {name: HFXORDY, shift: 3} - - {name: HFXOENS, shift: 2} - - {name: HFRCORDY, shift: 1} - - {name: HFRCOENS, shift: 0} - - name: IF - offset: 0x030 - definition_baserefext: ".5.13" - fields: I - - name: IFS - offset: 0x034 - definition_baserefext: ".5.14" - fields: I - - name: IFC - offset: 0x038 - definition_baserefext: ".5.15" - fields: I - - name: IEN - offset: 0x03c - definition_baserefext: ".5.16" - fields: I - - name: HFCORECLKEN0 - offset: 0x040 - definition_baserefext: ".5.17" - fields: - - {name: LE, shift: 2} - - {name: DMA, shift: 1} - - {name: AES, shift: 0} - - name: HFPERCLKEN0 - offset: 0x044 - definition_baserefext: ".5.18" - fields: - - {name: I2C0, shift: 11} - - {name: DAC0, shift: 10} - - {name: ADC0, shift: 9} - - {name: PRS, shift: 8} - - {name: VCMP, shift: 7} - - {name: GPIO, shift: 6} - - {name: TIMER1, shift: 5} - - {name: TIMER0, shift: 4} - - {name: USART1, shift: 3} - - {name: USART0, shift: 2} - - {name: ACMP1, shift: 1} - - {name: ACMP0, shift: 0} - - name: SYNCBUSY - offset: 0x050 - definition_baserefext: ".5.19" - fields: - - {name: LFBPRESC0, shift: 6} - - {name: LFBCLKEN0, shift: 4} - - {name: LFAPRESC0, shift: 2} - - {name: LFACLKEN0, shift: 0} - - name: FREEZE - offset: 0x054 - definition_baserefext: ".5.20" - fields: - - name: REGFREEZE - shift: 0 - values: - - {value: 0, name: UPDATE} - - {value: 1, name: FREEZE} - - name: LFACLKEN0 - offset: 0x058 - definition_baserefext: ".5.21" - fields: - - {name: LCD, shift: 3} - - {name: LETIMER0, shift: 2} - - {name: RTC, shift: 1} - - {name: LESENSE, shift: 0} - - name: LFBCLKEN0 - offset: 0x060 - definition_baserefext: ".5.22" - fields: - - {name: LEUART0, shift: 0} - - name: LFAPRESC0 - offset: 0x068 - definition_baserefext: ".5.23" - fields: - - name: LCD - shift: 12 - length: 2 - values: - - {value: 0, name: DIV16} - - {value: 1, name: DIV32} - - {value: 2, name: DIV64} - - {value: 3, name: DIV128} - - name: LETIMER0 - shift: 8 - length: 4 - values: &LFAPRESC0_LETIMER0_values - - {value: 0, name: DIV1} - - {value: 1, name: DIV2} - - {value: 2, name: DIV4} - - {value: 3, name: DIV8} - - {value: 4, name: DIV16} - - {value: 5, name: DIV32} - - {value: 6, name: DIV64} - - {value: 7, name: DIV128} - - {value: 8, name: DIV256} - - {value: 9, name: DIV512} - - {value: 10, name: DIV1024} - - {value: 11, name: DIV2048} - - {value: 12, name: DIV4096} - - {value: 13, name: DIV8192} - - {value: 14, name: DIV16384} - - {value: 15, name: DIV32768} - - name: RTC - shift: 4 - length: 4 - values: *LFAPRESC0_LETIMER0_values - - name: LESENSE - shift: 0 - length: 2 - values: - - {value: 0, name: DIV1} - - {value: 1, name: DIV2} - - {value: 2, name: DIV4} - - {value: 3, name: DIV8} - - name: LFBPRESC0 - offset: 0x070 - definition_baserefext: ".5.24" - fields: - - name: LEUART0 - shift: 0 - length: 2 - values: - - {value: 0, name: DIV1} - - {value: 1, name: DIV2} - - {value: 2, name: DIV4} - - {value: 3, name: DIV8} - - name: PCNTCTRL - offset: 0x078 - definition_baserefext: ".5.25" - fields: - - name: PCNT0CLKSEL - shift: 1 - values: - - {value: 0, name: LFACLK} - - {value: 1, name: PCNT0S0} - - name: PCNT0CLKEN - shift: 0 - - name: LCDCTRL - offset: 0x07c - definition_baserefext: ".5.26" - fields: - - name: VBFDIV - shift: 4 - length: 3 - values: - - {value: 0, name: DIV1} - - {value: 1, name: DIV2} - - {value: 2, name: DIV4} - - {value: 3, name: DIV8} - - {value: 4, name: DIV16} - - {value: 5, name: DIV32} - - {value: 6, name: DIV64} - - {value: 7, name: DIV128} - - name: VBOOSTEN - shift: 3 - - name: FDIV - shift: 0 - length: 3 - type: uint - - name: ROUTE - offset: 0x080 - definition_baserefext: ".5.27" - fields: - - name: LOCATION - shift: 4 - length: 3 - values: - - {value: 0, name: LOC0} - - {value: 1, name: LOC1} - - name: CLKOUT1PEN - shift: 1 - - name: CLKOUT0PEN - shift: 0 - - name: LOCK - offset: 0x084 - definition_baserefext: ".5.28" - length: 16 - values: - - {name: IS_UNLOCKED, value: 0} - - {name: IS_LOCKED, value: 1} - - {name: SET_LOCKED, value: 0} - - {name: SET_UNLOCKED, value: "0x580E"} diff --git a/include/libopencm3/efm32/tinygecko/devicerevision.h b/include/libopencm3/efm32/tinygecko/devicerevision.h deleted file mode 100644 index 45da408..0000000 --- a/include/libopencm3/efm32/tinygecko/devicerevision.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* FIXME: proper documentation, see where this fits, if we need this at all - * etc. this was just a first attempt at implementing something easy with - * MMIO32. */ - -/* this implements d0034_efm32tg_reference_manual.pdf's 7.3.4 "Device Revision" - * section */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_DEVICEREVISION_H -#define LIBOPENCM3_EFM32_TINYGECKO_DEVICEREVISION_H - -#include - -#define DEVICEREVISION_PID2 MMIO32(0xE00FFFE8) -#define DEVICEREVISION_PID3 MMIO32(0xE00FFFEC) - -/* devicerevision_revision_get has a comment that would make these definitions - * obsolete; i'm not sure how far it is reasonable to parameterize everythin - * g*/ -#define DEVICEREVISION_REVISION_LENGTH 4 -#define DEVICEREVISION_REVISION_SHIFT 4 -#define DEVICEREVISION_REVISION_MASK (~(~0< - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * @see EFM32TG_EMU - */ - -/** Definitions for the EMU subsystem (Energy Management Unit). - * - * This corresponds to the description in d0034_efm32tg_reference_manual.pdf - * section 10. - * - * @ingroup EFM32TG - * @defgroup EFM32TG_EMU EMU (Energy Management Unit) - * @{ - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_EMU_H -#define LIBOPENCM3_EFM32_TINYGECKO_EMU_H - -#include -#include - -/** Register definitions and register value definitions for the EMU subsystem - * - * @defgroup EFM32TG_EMU_regsandvals EMU registers and values - * @{ - */ - -/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 10.4 - * - * @defgroup EFM32TG_EMU_registers EMU registers - * @{ - */ - -#define EMU_CTRL MMIO32(EMU_BASE + 0x000) /**< @see EFM32TG_EMU_CTRL_bits */ -#define EMU_LOCK MMIO32(EMU_BASE + 0x008) /**< @see EFM32TG_EMU_LOCK_values */ -#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) /**< @see EFM32TG_EMU_AUXCTRL_bits */ - -/** @} */ - -/** Bit states for the EMU_CTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 10.5.1 for definitions, and - * 10.3.2 for details (especially on why EM4CTRL_TWO and _THREE are defined). - * - * @defgroup EFM32TG_EMU_CTRL_bits EMU CTRL bits - * @{ - */ - -#define EMU_CTRL_EM4CTRL_TWO (2<<2) -#define EMU_CTRL_EM4CTRL_THREE (3<<2) -#define EMU_CTRL_EM4CTRL_MASK (0x3<<2) -#define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */ -#define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */ - -/** @} */ - -/** Values for the EMU_LOCK register - * - * See d0034_efm32tg_reference_manual.pdf section 10.5.2 for definitions. There - * seems not to be another mention of it. - * - * @defgroup EFM32TG_EMU_LOCK_values EMU LOCK values - * @{ - */ - -#define EMU_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */ -#define EMU_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */ -#define EMU_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock the EMU */ -#define EMU_LOCK_SET_UNLOCKED 0xade8 /**< Write this to the LOCK register to unlock the EMU */ - -/** @} */ - -/** Bit states for the EMU_AUXCTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 10.5.3 for definitions, and - * 9.5.3 for details. - * - * @defgroup EFM32TG_EMU_AUXCTRL_bits EMU AUXCTRL bits - * @{ - */ - -#define EMU_AUXCTRL_HRCCLR (1<<0) - -/** @} */ - -/** @} */ - -/** EMU convenience functions - * - * These functions can be used to send the chip to low energy modes. - * - * @todo Implement other sleep modes than EM1. Implement WFI vs WFE waits. - * - * @defgroup EFM32TG_EMU_convenience EMU convenience functions - * @{ - */ - -/** Put the system into EM1 low energy mode. */ -static void emu_sleep_em1(void) -{ - /* FIXME: set SLEEPDEEP to 0 */ - __asm__("wfi"); -} - -/** @} */ - -/** @} */ - -#endif diff --git a/include/libopencm3/efm32/tinygecko/emu.yaml b/include/libopencm3/efm32/tinygecko/emu.yaml deleted file mode 100644 index 4e0b30e..0000000 --- a/include/libopencm3/efm32/tinygecko/emu.yaml +++ /dev/null @@ -1,50 +0,0 @@ -copyright: "2012 chrysn " -license: lgpl-3+ -ingroup: EFM32TG -shortdocname: EFM32TG_EMU -shortname: EMU -longname: Energy Management Unit -baseref: d0034_efm32tg_reference_manual.pdf section 10 -registers_baserefext: ".4" -registers: - - name: CTRL - definition_baserefext: .5.1 - details: ", and 10.3.2 for details (especially on why EM4CTRL_TWO and _THREE are defined)." - offset: 0x000 - fields: - - name: EM4CTRL - shift: 2 - length: 2 - values: - - {name: TWO, value: 2} - - {name: THREE, value: 3} - - name: EM2BLOCK - shift: 1 - doc: When this bit is set, no mode lower than EM1 will be entered - - name: EMVREG - shift: 0 - doc: When this bit is set, the voltage regulator will stay on in modes lower than EM1 - - name: LOCK - definition_baserefext: .5.2 - details: ". There seems not to be another mention of it." - offset: 0x008 - values: - - name: IS_UNLOCKED - value: 0 - doc: When the LOCK register reads as this value, it is open - - name: IS_LOCKED - value: 1 - doc: When the LOCK register reads as this value, it is locked - - name: SET_LOCKED - value: 0 - doc: Write this to the LOCK register to lock the EMU - - name: SET_UNLOCKED - value: "0xade8" - doc: Write this to the LOCK register to unlock the EMU - - name: AUXCTRL - definition_baserefext: .5.3 - details: ", and 9.5.3 for details." - offset: 0x024 - fields: - - name: HRCCLR - shift: 0 diff --git a/include/libopencm3/efm32/tinygecko/generate-license.yaml b/include/libopencm3/efm32/tinygecko/generate-license.yaml deleted file mode 100644 index baeef88..0000000 --- a/include/libopencm3/efm32/tinygecko/generate-license.yaml +++ /dev/null @@ -1,19 +0,0 @@ -"lgpl-3+": | - /* - * This file is part of the {projectname} project. - * - * Copyright (C) {copyright} - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ diff --git a/include/libopencm3/efm32/tinygecko/generate.py b/include/libopencm3/efm32/tinygecko/generate.py deleted file mode 100644 index 7f426a4..0000000 --- a/include/libopencm3/efm32/tinygecko/generate.py +++ /dev/null @@ -1,176 +0,0 @@ -#!/usr/bin/env python - -import yaml -import logging -import textwrap - -def commentblock(*textblocks, **formatargs): - ret = [] - nowrapcommands = set("@defgroup") - ret.extend(textwrap.wrap(textblocks[0].format(**formatargs), 80, initial_indent="/** ", subsequent_indent=" * ")) - last_block_was_at = textblocks[0].startswith('@') - for b in textblocks[1:]: - formatted = b.format(**formatargs) - - if not (last_block_was_at and b.startswith('@')): - ret.append(" *") - if any(b.startswith(c) for c in nowrapcommands): - ret.append(" * " + formatted) - else: - ret.extend(textwrap.wrap(formatted, 80, initial_indent=" * ", subsequent_indent=" * ")) - last_block_was_at = b.startswith('@') - return "\n".join(ret) + "\n */\n" - -def yaml2h(filenamebase): - headername = "%s.h"%filenamebase - yamlname = "%s.yaml"%filenamebase - conveniencename = "%s.convenienceheaders"%filenamebase - - logging.info("Generating %s from %s", headername, yamlname) - - data = yaml.load(open(yamlname)) - # some defaults - data.setdefault("projectname", "libopencm3") - data.setdefault("includeguard", "LIBOPENCM3_EFM32_TINYGECKO_%s_H"%data['shortname']) - - with open(headername, 'w') as outfile: - def wc(*args, **kwargs): # wrap "outfile" and "data" (as default) arguments -- i'm a lazy typer - final_kwargs = data.copy() - final_kwargs.update(kwargs) - outfile.write(commentblock(*args, **final_kwargs)) - def wc_close(): - outfile.write("/** @} */\n") - def nl(): outfile.write("\n") - def define(key, value, comment=None): - outfile.write("#define ") - outfile.write(key) - outfile.write(" "*max(24-len(key), 1)) - outfile.write(str(value)) - if comment is not None: - outfile.write(" /**< %s */"%comment) - nl() - - outfile.write(licensedata[data['license']].format(**data)) - nl() - wc("@file", "@see {shortdocname}") - nl() - wc("Definitions for the {shortname} subsystem ({longname}).", "This corresponds to the description in {baseref}.", "@ingroup {ingroup}", "@defgroup {shortdocname} {shortname} ({longname})", "@{{") - nl() - outfile.write("#ifndef {includeguard}\n#define {includeguard}\n".format(**data)) - nl() - outfile.write("#include \n#include \n") - nl() - wc("Register definitions and register value definitions for the {shortname} subsystem", "@defgroup {shortdocname}_regsandvals {shortname} registers and values", "@{{") - nl() - - regs = data['registers'] - - for template in data.get('templateregs', []): - template['is_template'] = [] - regs.append(template) - - regs_dict = dict((x['name'], x) for x in regs) # for easier access. they've got to be a list in yaml to preserve order - - wc("These definitions reflect {baseref}{registers_baserefext}", "@defgroup {shortdocname}_registers {shortname} registers", "@{{") - nl() - - for regdata in regs: - has_bits = "fields" in regdata - has_values = "values" in regdata - is_template = "is_template" in regdata - if is_template: - # this isn't a real register, just a template - continue - secondcomponent_name = regdata['name'] - if (has_bits and isinstance(regdata['fields'], str)) or (has_values and isinstance(regdata['values'], str)): - # uses a template - secondcomponent_name = regdata['fields'] if has_bits else regdata['values'] - regs_dict[secondcomponent_name]['is_template'].append(regdata['name']) - - define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], secondcomponent_name, 'values' if 'values' in regdata else 'bits') if has_bits or has_values else None) - nl() - wc_close() # close register definitions - nl() - - for regdata in regs: - has_bits = "fields" in regdata - has_values = "values" in regdata - is_template = "is_template" in regdata - if not has_bits and not has_values: - continue - - if (has_bits and isinstance(regdata['fields'], str)) or (has_values and isinstance(regdata['values'], str)): - # uses a template, doesn't need own section - continue - - commentlines = [] - if is_template: - commentlines.append("%s for the {shortname} \"{name}\" group of registers (%s)"%("Bit states" if has_bits else "Values", ", ".join(regdata['is_template']))) - assert len(regdata['is_template']) > 0, "What should I talk about when nobody uses this template?" - if 'override_backref' in regdata: - commentlines.append(regdata['override_backref']) - else: - commentlines.append("These registers use this:") - commentlines.append("
      ") # FIXME: once we're using markdown 1.8, this can be changed to markdown - for user in regdata['is_template']: - userdata = regs_dict[user] - # FIXME: this is an ugly hack around this being in a single wc() line which doesn't take per-line contexts - mergeddata = data.copy() - mergeddata.update(userdata) - commentlines.append(("
    • The {shortname}_{name} register; see {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."+"
    • ")).format(**mergeddata)) - commentlines.append("
    ") - commentlines.append('@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values', 'bits group' if has_bits else 'values group'))) - else: - commentlines.append("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values")) - commentlines.append("See {baseref}{definition_baserefext} for definitions"+regdata.get("details", ".")) - commentlines.append('@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values',)*2)) - commentlines.append('@{{') - wc(*commentlines, **regdata) - nl() - - if has_bits: - for field in regdata['fields']: - #shiftdefine = "_%s_%s_%s_shift"%(shortname, regdata['name'], field['name']) - #define(shiftdefine, field['shift']) - - # there is one condition under which field's doc would get shown; show it immediately otherwise - if 'doc' in field and not ("values" not in field and field.get("length", 1) == 1): - wc(field['doc']) - - if "values" in field: - for value in field.get("values"): - define("%s_%s_%s_%s"%(data['shortname'], regdata['name'], field['name'], value['name']), value['value'] if "mask" in field else "(%s<<%s)"%(value['value'], field['shift']), value.get('doc', None)) - else: - if field.get('length', 1) == 1: - define("%s_%s_%s"%(data['shortname'], regdata['name'], field['name']), "(1<<%s)"%field['shift'], field.get('doc', None)) - else: - # FIXME: this should require the 'type' parameter to be set on this field - pass - - if "values" in field or field.get("length", 1) != 1: - if "mask" in field: - mask = field['mask'] - else: - mask = "(%#x<<%s)"%(~(~0< - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * @see EFM32TG_GPIO - */ - -/** Definitions for the GPIO subsystem (General Purpose Input Output). - * - * This corresponds to the description in d0034_efm32tg_reference_manual.pdf - * section 28. - * - * @ingroup EFM32TG - * @defgroup EFM32TG_GPIO GPIO (General Purpose Input Output) - * @{ - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_GPIO_H -#define LIBOPENCM3_EFM32_TINYGECKO_GPIO_H - -#include -#include - -/** Register definitions and register value definitions for the GPIO subsystem - * - * @defgroup EFM32TG_GPIO_regsandvals GPIO registers and values - * @{ - */ - -/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 28.4 - * - * The bulk of the registers defined here (like GPIO_PA_CTRL) will not be used - * inside the convenience functions, but are provided for direct access. - * - * @todo This section could profit from bit-banding. - * - * @defgroup EFM32TG_GPIO_registers GPIO registers - * @{ - */ -#define GPIO_Px_CTRL(port) MMIO32(port + 0x000) /**< @see EFM32TG_GPIO_Px_CTRL_bits */ -#define GPIO_Px_MODEL(port) MMIO32(port + 0x004) /**< @see EFM32TG_GPIO_MODE_values */ -#define GPIO_Px_MODEH(port) MMIO32(port + 0x008) /**< @see EFM32TG_GPIO_MODE_values */ -#define GPIO_Px_DOUT(port) MMIO32(port + 0x00C) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_Px_DOUTSET(port) MMIO32(port + 0x010) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_Px_DOUTCLR(port) MMIO32(port + 0x014) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_Px_DOUTTGL(port) MMIO32(port + 0x018) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_Px_DIN(port) MMIO32(port + 0x01C) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_Px_PINLOCKN(port) MMIO32(port + 0x020) /**< @see EFM32TG_GPIO_pinnumberbits */ - -#define GPIO_PA (GPIO_BASE + 0x000) -#define GPIO_PA_CTRL GPIO_Px_CTRL(GPIO_PA) -#define GPIO_PA_MODEL GPIO_Px_MODEL(GPIO_PA) -#define GPIO_PA_MODEH GPIO_Px_MODEH(GPIO_PA) -#define GPIO_PA_DOUT GPIO_Px_DOUT(GPIO_PA) -#define GPIO_PA_DOUTSET GPIO_Px_DOUTSET(GPIO_PA) -#define GPIO_PA_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PA) -#define GPIO_PA_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PA) -#define GPIO_PA_DIN GPIO_Px_DIN(GPIO_PA) -#define GPIO_PA_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PA) - -#define GPIO_PB (GPIO_BASE + 0x024) -#define GPIO_PB_CTRL GPIO_Px_CTRL(GPIO_PB) -#define GPIO_PB_MODEL GPIO_Px_MODEL(GPIO_PB) -#define GPIO_PB_MODEH GPIO_Px_MODEH(GPIO_PB) -#define GPIO_PB_DOUT GPIO_Px_DOUT(GPIO_PB) -#define GPIO_PB_DOUTSET GPIO_Px_DOUTSET(GPIO_PB) -#define GPIO_PB_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PB) -#define GPIO_PB_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PB) -#define GPIO_PB_DIN GPIO_Px_DIN(GPIO_PB) -#define GPIO_PB_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PB) - -#define GPIO_PC (GPIO_BASE + 0x048) -#define GPIO_PC_CTRL GPIO_Px_CTRL(GPIO_PC) -#define GPIO_PC_MODEL GPIO_Px_MODEL(GPIO_PC) -#define GPIO_PC_MODEH GPIO_Px_MODEH(GPIO_PC) -#define GPIO_PC_DOUT GPIO_Px_DOUT(GPIO_PC) -#define GPIO_PC_DOUTSET GPIO_Px_DOUTSET(GPIO_PC) -#define GPIO_PC_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PC) -#define GPIO_PC_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PC) -#define GPIO_PC_DIN GPIO_Px_DIN(GPIO_PC) -#define GPIO_PC_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PC) - -#define GPIO_PD (GPIO_BASE + 0x06C) -#define GPIO_PD_CTRL GPIO_Px_CTRL(GPIO_PD) -#define GPIO_PD_MODEL GPIO_Px_MODEL(GPIO_PD) -#define GPIO_PD_MODEH GPIO_Px_MODEH(GPIO_PD) -#define GPIO_PD_DOUT GPIO_Px_DOUT(GPIO_PD) -#define GPIO_PD_DOUTSET GPIO_Px_DOUTSET(GPIO_PD) -#define GPIO_PD_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PD) -#define GPIO_PD_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PD) -#define GPIO_PD_DIN GPIO_Px_DIN(GPIO_PD) -#define GPIO_PD_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PD) - -#define GPIO_PE (GPIO_BASE + 0x090) -#define GPIO_PE_CTRL GPIO_Px_CTRL(GPIO_PE) -#define GPIO_PE_MODEL GPIO_Px_MODEL(GPIO_PE) -#define GPIO_PE_MODEH GPIO_Px_MODEH(GPIO_PE) -#define GPIO_PE_DOUT GPIO_Px_DOUT(GPIO_PE) -#define GPIO_PE_DOUTSET GPIO_Px_DOUTSET(GPIO_PE) -#define GPIO_PE_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PE) -#define GPIO_PE_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PE) -#define GPIO_PE_DIN GPIO_Px_DIN(GPIO_PE) -#define GPIO_PE_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PE) - -#define GPIO_PF (GPIO_BASE + 0x0B4) -#define GPIO_PF_CTRL GPIO_Px_CTRL(GPIO_PF) -#define GPIO_PF_MODEL GPIO_Px_MODEL(GPIO_PF) -#define GPIO_PF_MODEH GPIO_Px_MODEH(GPIO_PF) -#define GPIO_PF_DOUT GPIO_Px_DOUT(GPIO_PF) -#define GPIO_PF_DOUTSET GPIO_Px_DOUTSET(GPIO_PF) -#define GPIO_PF_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PF) -#define GPIO_PF_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PF) -#define GPIO_PF_DIN GPIO_Px_DIN(GPIO_PF) -#define GPIO_PF_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PF) - -#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) /**< @see EFM32TG_GPIO_EXTIP_values */ -#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) /**< @see EFM32TG_GPIO_EXTIP_values */ -#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_IF MMIO32(GPIO_BASE + 0x114) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) /**< @see EFM32TG_GPIO_pinnumberbits */ -#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) /**< @see EFM32TG_GPIO_ROUTE_bits */ -#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) /**< @see EFM32TG_GPIO_INSENSE_bits */ -#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) /**< @see EFM32TG_GPIO_LOCK_values */ -#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) /**< @see EFM32TG_GPIO_CTRL_bits */ -#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) /**< @see EFM32TG_GPIO_CMD_bits */ -#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) /**< @see EFM32TG_GPIO_EM4WUEN_bits */ -#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) /**< @see EFM32TG_GPIO_EM4WUPOL_bits */ -#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) /**< @see EFM32TG_GPIO_EM4WUCAUSE_bits */ - -/** @} */ - -/** Pin number bits - * - * Provided for convenience. They can be used on the GPIO_Px_DOUT, - * GPIO_Px_DOUTSET, GPIO_Px_DOUTCLR, GPIO_Px_DOUTTGL, GPIO_Px_DIN, - * GPIO_Px_PINLOCKN, GPIO_Px_EXTIRISE, GPIO_Px_EXTIFALL, GPIO_IEN, GPIO_IF, - * GPIO_IFS, and GPIO_IFC registers. - * - * @defgroup EFM32TG_GPIO_pinnumberbits GPIO pin number bits - * @{ - */ - -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO10 (1 << 10) -#define GPIO11 (1 << 11) -#define GPIO12 (1 << 12) -#define GPIO13 (1 << 13) -#define GPIO14 (1 << 14) -#define GPIO15 (1 << 15) -#define GPIO_ALL 0xffff - -/** @} */ - -/** Bit states for the GPIO_Px_CTRL register - * - * They are named as in d0034_efm32tg_reference_manual.pdf's section - * 28.5.1. - * - * @defgroup EFM32TG_GPIO_Px_CTRL_bits GPIO Px CTRL bits - * @{ - */ - -#define GPIO_CTRL_DRIVEMODE_STANDARD 0 /**< 6mA drive current */ -#define GPIO_CTRL_DRIVEMODE_LOWEST 1 /**< 0.5mA drive current */ -#define GPIO_CTRL_DRIVEMODE_HIGH 2 /**< 20mA drive current */ -#define GPIO_CTRL_DRIVEMODE_LOW 3 /**< 2mA drive current */ - -/** @} */ - -/** These are the modes defined for the MODEx fields in the GPIO_Px_MODEL and - * GPIO_Px_MODEH registers. - * - * These bit state definitions are not localized, meaning that they have to be - * bitshifted by multiples of 4 to configure other pins than 0; configurations - * for pins 0 to 7 go to GPIO_Px_MODEL (shifted by 4*pin), configurations for - * pins 8 to 15 go to GPIO_Px_MODEH (shifted by 4*(pin-8)). - * - * For example, to set the mode for the 3rd pin of port A to pushpull, set - * `GPIO_PA_MODEL = GPIO_MODE_PUSHPULL << (3*4);`. - * - * @todo Update the example as soon as there are convenience functions to do - * this properly. - * - * They are named as in d0034_efm32tg_reference_manual.pdf's sections - * 28.5.2/28.5.3. For explanations of what they really do, rather see section - * 28.3.1. - * - * @defgroup EFM32TG_GPIO_MODE_values GPIO MODE values - * @{ - */ - -#define GPIO_MODE_DISABLED 0 -#define GPIO_MODE_INPUT 1 -#define GPIO_MODE_INPUTPULL 2 -#define GPIO_MODE_INPUTPULLFILTER 3 -#define GPIO_MODE_PUSHPULL 4 -#define GPIO_MODE_PUSHPULLDRIVE 5 -#define GPIO_MODE_WIREDOR 6 -#define GPIO_MODE_WIREDORPULLDOWN 7 -#define GPIO_MODE_WIREDAND 8 -#define GPIO_MODE_WIREDANDFILTER 9 -#define GPIO_MODE_WIREDANDPULLUP 10 -#define GPIO_MODE_WIREDANDPULLUPFILTER 11 -#define GPIO_MODE_WIREDANDDRIVE 12 -#define GPIO_MODE_WIREDANDDRIVEFILTER 13 -#define GPIO_MODE_WIREDANDDRIVEPULLUP 14 -#define GPIO_MODE_WIREDANDDRIVEPULLUPFILTER 15 -#define GPIO_MODE_MASK 0x0f - -/** @} */ - -/** These are the modes defined for the EXTIPSELx fields in the GPIO_EXTIPSELL - * and GPIO_EXTIPSELH registers. - * - * These bit state definitions are not localized, meaning that they have to be - * bitshifted by multiples of 4 to configure other pins than 0; configurations - * for pins 0 to 7 go to GPIO_EXTIPSELL (shifted by 4*pin), configurations for - * pins 8 to 15 go to GPIO_EXTIPSELH (shifted by 4*(pin-8)). - * - * They are named as in d0034_efm32tg_reference_manual.pdf's sections - * 28.5.10/28.5.11. For explanations of what they do, rather see section - * 28.3.5. - * - * @defgroup EFM32TG_GPIO_EXTIP_values GPIO EXTIPSEL values - * @{ - */ - -#define GPIO_EXTIPSEL_PORTA 0 /**< Port A pin x selected for external interrupt x */ -#define GPIO_EXTIPSEL_PORTB 1 /**< Port B pin x selected for external interrupt x */ -#define GPIO_EXTIPSEL_PORTC 2 /**< Port C pin x selected for external interrupt x */ -#define GPIO_EXTIPSEL_PORTD 3 /**< Port D pin x selected for external interrupt x */ -#define GPIO_EXTIPSEL_PORTE 4 /**< Port E pin x selected for external interrupt x */ -#define GPIO_EXTIPSEL_PORTF 5 /**< Port F pin x selected for external interrupt x */ - -/** @} */ - -/** Bit states for the GPIO_ROUTE register - * - * See d0034_efm32tg_reference_manual.pdf section 28.5.18 for definitions, and - * 28.3.4.1 for explanations. - * - * @defgroup EFM32TG_GPIO_ROUTE_bits GPIO ROUTE bits - * @{ - */ - -#define GPIO_ROUTE_SWLOCATION_MASK (0x03<<8) -#define GPIO_ROUTE_SWLOCATION_LOC0 (0<<8) /**< Route SW pins to location 0 (see chip data sheet for exact pins */ -#define GPIO_ROUTE_SWLOCATION_LOC1 (1<<8) /**< Route SW pins to location 1 (see chip data sheet for exact pins */ -#define GPIO_ROUTE_SWLOCATION_LOC2 (2<<8) /**< Route SW pins to location 2 (see chip data sheet for exact pins */ -#define GPIO_ROUTE_SWLOCATION_LOC3 (3<<8) /**< Route SW pins to location 3 (see chip data sheet for exact pins */ - -#define GPIO_ROUTE_SWOPEN (1<<2) /**< Serial Wire Viewer Output pin enabled */ -#define GPIO_ROUTE_SWDIOPEN (1<<1) /**< Serial Wire Data pin enabled */ -#define GPIO_ROUTE_SWCLKPEN (1<<0) /**< Serial Wire Clock pin enabled */ - -/** @} */ - -/** Bit states for the GPIO_INSENSE register - * - * See d0034_efm32tg_reference_manual.pdf section 28.5.19 for definitions, and - * 28.3.7 for details. - * - * @defgroup EFM32TG_GPIO_INSENSE_bits GPIO INSENSE bits - * @{ - */ - -#define GPIO_INSENSE_PRS (1<<1) /**< Input sensing for PRS enabled */ -#define GPIO_INSENSE_INT (1<<0) /**< Input sensing for interrupts enabled */ - -/** @} */ - -/** Values for the GPIO_LOCK register - * - * See d0034_efm32tg_reference_manual.pdf section 28.5.20 for definitions, and - * 28.3.1.1 for explanations. - * - * @defgroup EFM32TG_GPIO_LOCK_values GPIO LOCK bits - * @{ - */ - -#define GPIO_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */ -#define GPIO_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */ -#define GPIO_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock down GPIO */ -#define GPIO_LOCK_SET_UNLOCKED 0xa543 /**< Write this to the LOCK register to unlock the GPIO */ - -/** @} */ - -/** Bit states for the GPIO_CTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 28.5.21 for definitions, and - * 28.3.4 for explanations. - * - * @defgroup EFM32TG_GPIO_CTRL_bits GPIO CTRL bits - * @{ - */ - -#define GPIO_CTRL_EM4RET (1<<0) /**< Retention of states in EM4 */ - -/** @} */ - -/** Bit states for the GPIO_CMD register - * - * See d0034_efm32tg_reference_manual.pdf section 28.5.22 for definitions and - * figure 28.5 in case you wonder if that register is mentioned anywhere else - * at all. - * - * @defgroup EFM32TG_GPIO_CMD_bits GPIO CMD bits - * @{ - */ - -#define GPIO_CMD_EM4WUCLR (1<<0) /**< Write this flag to clear EM4 wakeup requests */ - -/** @} */ - -/** Bit states for the GPIO_EM4WUEN register - * - * See d0034_efm32tg_reference_manual.pdf section 28.5.23 for definitions, and - * 28.3.2 for explanations. - * - * @defgroup EFM32TG_GPIO_EM4WUEN_bits GPIO EM4WUEN bits - * @{ - */ - -#define GPIO_EM4WUEN_A0 0x01 /**< Wake up from EM4 on A0 activity */ -#define GPIO_EM4WUEN_A6 0x02 /**< Wake up from EM4 on A6 activity */ -#define GPIO_EM4WUEN_C9 0x04 /**< Wake up from EM4 on C9 activity */ -#define GPIO_EM4WUEN_F1 0x08 /**< Wake up from EM4 on F1 activity */ -#define GPIO_EM4WUEN_F3 0x10 /**< Wake up from EM4 on F3 activity */ -#define GPIO_EM4WUEN_E13 0x20 /**< Wake up from EM4 on E13 activity */ - -/** @} */ - -/** Bit states for the GPIO_EM4WUPOL register - * - * See d0034_efm32tg_reference_manual.pdf section 28.5.24 for definitions, and - * 28.3.2 for explanations. - * - * @defgroup EFM32TG_GPIO_EM4WUPOL_bits GPIO EM4WUPOL bits - * @{ - */ - -#define GPIO_EM4WUPOL_A0 0x01 /**< High wake up from EM4 on A0 */ -#define GPIO_EM4WUPOL_A6 0x02 /**< High wake up from EM4 on A6 */ -#define GPIO_EM4WUPOL_C9 0x04 /**< High wake up from EM4 on C9 */ -#define GPIO_EM4WUPOL_F1 0x08 /**< High wake up from EM4 on F1 */ -#define GPIO_EM4WUPOL_F3 0x10 /**< High wake up from EM4 on F3 */ -#define GPIO_EM4WUPOL_E13 0x20 /**< High wake up from EM4 on E13 */ - -/** @} */ - -/** Bit states for the GPIO_EM4WUCAUSE register - * - * See d0034_efm32tg_reference_manual.pdf section 28.5.25 for definitions, and - * 28.3.2 for explanations. - * - * @defgroup EFM32TG_GPIO_EM4WUCAUSE_bits GPIO EM4WUCAUSE bits - * @{ - */ - -#define GPIO_EM4WUCAUSE_A0 0x01 /**< Woke up from EM4 on A0 */ -#define GPIO_EM4WUCAUSE_A6 0x02 /**< Woke up from EM4 on A6 */ -#define GPIO_EM4WUCAUSE_C9 0x04 /**< Woke up from EM4 on C9 */ -#define GPIO_EM4WUCAUSE_F1 0x08 /**< Woke up from EM4 on F1 */ -#define GPIO_EM4WUCAUSE_F3 0x10 /**< Woke up from EM4 on F3 */ -#define GPIO_EM4WUCAUSE_E13 0x20 /**< Woke up from EM4 on E13 */ - -/** @} */ - -/** @} */ - -/** GPIO convenience functions - * - * These functions try to be close to the STM32 F1 utility functions where - * possible. - * - * The functions intentionally don't cover all the possible read- and write - * operations to the GPIO registers. For example, reading the configured output - * strength for a port is rarely required. - * - * Many convenience functions are static to allow inlining by the compiler. - * - * @todo Implement all the non-trivial but useful convenience functions. - * - * @defgroup EFM32TG_GPIO_convenience GPIO convenience functions - * @{ - */ - -/** Set a whole GPIO port's out data to a particular value - * - * \param gpioport Address of a GPIO port to use (eg GPIO_PA) - * \param gpios Bit pattern the output of the port will be configured to (eg GPIO6|GPIO3 to switch pins 6 and 3 to high and all the others to low) - */ -static void gpio_port_write(u32 gpioport, u16 data) -{ - GPIO_Px_DOUT(gpioport) = data; -} -/** Set some bits in a GPIO port's out data - * - * \param gpioport Address of a GPIO port to use (eg GPIO_PA) - * \param gpios GPIO pin(s) to be set to 1 (eg GPIO6|GPIO3 to switch pins 6 and 3 to high and leave all the others in their previous state) - */ -static void gpio_set(u32 gpioport, u16 gpios) -{ - GPIO_Px_DOUTSET(gpioport) = gpios; -} -/** Clear some bits in a GPIO port's out data - * - * \param gpioport Address of a GPIO port to use (eg GPIO_PA) - * \param gpios GPIO pin(s) to be set to 0 (eg GPIO6|GPIO3 to switch pins 6 and 3 to low and leave all the others in their previous state) - */ -static void gpio_clear(u32 gpioport, u16 gpios) -{ - GPIO_Px_DOUTCLR(gpioport) = gpios; -} -/** Toggle some bits in a GPIO port's out data - * - * \param gpioport Address of a GPIO port to use (eg GPIO_PA) - * \param gpios GPIO pin(s) that will be toggled (eg GPIO6|GPIO3 to toggle the output directions of pins 6 and 3 and leave all the others in their previous state) - */ -static void gpio_toggle(u32 gpioport, u16 gpios) -{ - GPIO_Px_DOUTTGL(gpioport) = gpios; -} - -/** Read input bits from a GPIO's port in data - * - * \param gpioport Address of a GPIO port to use (eg GPIO_PA) - * \returns Current value of the in register of the given port - */ -static u16 gpio_port_read(u32 gpioport) -{ - return GPIO_Px_DIN(gpioport); -} -/** Read input bits from a GPIO's port in data - * - * \param gpioport Address of a GPIO port to use (eg GPIO_PA) - * \param gpios Bits that will be read (eg GPIO6|GPIO3 to read pins 6 and 3) - * \returns Bit pattern that contains 1 in all pin positions that currently read as high (eg GPIO6 if port A's 6th pin is currently high and the 3rd pin is low) - */ -static u16 gpio_get(u32 gpioport, u16 gpios) -{ - return gpio_port_read(gpioport) & gpios; -} - -/** Configure a particular pin configuration on one or more pins - * - * This function is not atomic. It has to be made sure that it is not - * interrupted by other code that modifies the port's configuration. - * - * \param gpioport Address of a GPIO port to use (eg GPIO_PA) - * \param mode Pin configuration mode to set (eg GPIO_MODE_INPUT) - * \param gpios Pins to configure (eg GPIO6|GPIO3 to set the mode on pins 6 and 3) - */ -void gpio_set_mode(u32 gpioport, u8 mode, u16 gpios); - -/** Configure the alternate drive strength for a port - * - * \param gpioport Address of a GPIO port to use (eg GPIO_PA) - * \param strength Alternate drive strength to configure for the port (eg GPIO_CTRL_DRIVEMODE_HIGH) - */ -static void gpio_set_strength(u32 gpioport, u8 strength) -{ - GPIO_Px_CTRL(gpioport) = strength; -} - -/** @} */ - -/** @} */ - -#endif diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h deleted file mode 100644 index 1b0a484..0000000 --- a/include/libopencm3/efm32/tinygecko/irq.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Definitions of interrupt names on EFM32 Tiny Gecko systems - * - * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H -#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H - -#define IRQ_DMA 0 -#define IRQ_GPIO_EVEN 1 -#define IRQ_TIMER0 2 -#define IRQ_USART0_RX 3 -#define IRQ_USART0_TX 4 -#define IRQ_ACMP01 5 -#define IRQ_ADC0 6 -#define IRQ_DAC0 7 -#define IRQ_I2C0 8 -#define IRQ_GPIO_ODD 9 -#define IRQ_TIMER1 10 -#define IRQ_USART1_RX 11 -#define IRQ_USART1_TX 12 -#define IRQ_LESENSE 13 -#define IRQ_LEUART0 14 -#define IRQ_LETIMER0 15 -#define IRQ_PCNT0 16 -#define IRQ_RTC 17 -#define IRQ_CMU 18 -#define IRQ_VCMP 19 -#define IRQ_LCD 20 -#define IRQ_MSC 21 -#define IRQ_AES 22 -#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ - -#endif diff --git a/include/libopencm3/efm32/tinygecko/lcd.convenienceheaders b/include/libopencm3/efm32/tinygecko/lcd.convenienceheaders deleted file mode 100644 index e69de29..0000000 diff --git a/include/libopencm3/efm32/tinygecko/lcd.h b/include/libopencm3/efm32/tinygecko/lcd.h deleted file mode 100644 index d46ef24..0000000 --- a/include/libopencm3/efm32/tinygecko/lcd.h +++ /dev/null @@ -1,295 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * @see EFM32TG_LCD - */ - -/** Definitions for the LCD subsystem (Liquid Crystal Display driver). - * - * This corresponds to the description in d0034_efm32tg_reference_manual.pdf - * section 29. - * - * @ingroup EFM32TG - * @defgroup EFM32TG_LCD LCD (Liquid Crystal Display driver) - * @{ - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_LCD_H -#define LIBOPENCM3_EFM32_TINYGECKO_LCD_H - -#include -#include - -/** Register definitions and register value definitions for the LCD subsystem - * - * @defgroup EFM32TG_LCD_regsandvals LCD registers and values - * @{ - */ - -/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 29.4 - * - * @defgroup EFM32TG_LCD_registers LCD registers - * @{ - */ - -#define LCD_CTRL MMIO32(LCD_BASE + 0x000) /**< @see EFM32TG_LCD_CTRL_bits */ -#define LCD_DISPCTRL MMIO32(LCD_BASE + 0x004) /**< @see EFM32TG_LCD_DISPCTRL_bits */ -#define LCD_SEGEN MMIO32(LCD_BASE + 0x008) -#define LCD_BACTRL MMIO32(LCD_BASE + 0x00c) /**< @see EFM32TG_LCD_BACTRL_bits */ -#define LCD_STATUS MMIO32(LCD_BASE + 0x010) /**< @see EFM32TG_LCD_STATUS_bits */ -#define LCD_AREGA MMIO32(LCD_BASE + 0x014) -#define LCD_AREGB MMIO32(LCD_BASE + 0x018) -#define LCD_IF MMIO32(LCD_BASE + 0x01c) /**< @see EFM32TG_LCD_I_bits */ -#define LCD_IFS MMIO32(LCD_BASE + 0x020) /**< @see EFM32TG_LCD_I_bits */ -#define LCD_IFC MMIO32(LCD_BASE + 0x024) /**< @see EFM32TG_LCD_I_bits */ -#define LCD_IEN MMIO32(LCD_BASE + 0x028) /**< @see EFM32TG_LCD_I_bits */ -#define LCD_SEGD0L MMIO32(LCD_BASE + 0x040) /**< @see EFM32TG_LCD_SEG_bits */ -#define LCD_SEGD1L MMIO32(LCD_BASE + 0x044) /**< @see EFM32TG_LCD_SEG_bits */ -#define LCD_SEGD2L MMIO32(LCD_BASE + 0x048) /**< @see EFM32TG_LCD_SEG_bits */ -#define LCD_SEGD3L MMIO32(LCD_BASE + 0x04c) /**< @see EFM32TG_LCD_SEG_bits */ -#define LCD_FREEZE MMIO32(LCD_BASE + 0x060) /**< @see EFM32TG_LCD_FREEZE_bits */ -#define LCD_SYNCBUSY MMIO32(LCD_BASE + 0x064) /**< @see EFM32TG_LCD_SYNCBUSY_bits */ -#define LCD_SEGD4L MMIO32(LCD_BASE + 0x0cc) /**< @see EFM32TG_LCD_SEG_bits */ -#define LCD_SEGD5L MMIO32(LCD_BASE + 0x0d0) /**< @see EFM32TG_LCD_SEG_bits */ -#define LCD_SEGD6L MMIO32(LCD_BASE + 0x0d4) /**< @see EFM32TG_LCD_SEG_bits */ -#define LCD_SEGD7L MMIO32(LCD_BASE + 0x0d8) /**< @see EFM32TG_LCD_SEG_bits */ - -/** @} */ - -/** Bit states for the LCD_CTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 29.5.1 for definitions. - * - * @defgroup EFM32TG_LCD_CTRL_bits LCD CTRL bits - * @{ - */ - -#define LCD_CTRL_DSC (1<<23) -#define LCD_CTRL_UDCTRL_REGULAR (0<<1) -#define LCD_CTRL_UDCTRL_FCEVENT (1<<1) -#define LCD_CTRL_UDCTRL_FRAMESTART (2<<1) -#define LCD_CTRL_UDCTRL_MASK (0x3<<1) -#define LCD_CTRL_EN (1<<0) - -/** @} */ - -/** Bit states for the LCD_DISPCTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 29.5.2 for definitions. - * - * @defgroup EFM32TG_LCD_DISPCTRL_bits LCD DISPCTRL bits - * @{ - */ - -#define LCD_DISPCTRL_VBLEV_LEVEL0 (0<<18) -#define LCD_DISPCTRL_VBLEV_LEVEL1 (1<<18) -#define LCD_DISPCTRL_VBLEV_LEVEL2 (2<<18) -#define LCD_DISPCTRL_VBLEV_LEVEL3 (3<<18) -#define LCD_DISPCTRL_VBLEV_LEVEL4 (4<<18) -#define LCD_DISPCTRL_VBLEV_LEVEL5 (5<<18) -#define LCD_DISPCTRL_VBLEV_LEVEL6 (6<<18) -#define LCD_DISPCTRL_VBLEV_LEVEL7 (7<<18) -#define LCD_DISPCTRL_VBLEV_MASK (0x7<<18) -#define LCD_DISPCTRL_VLCDSEL_VDD (0<<16) -#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (1<<16) -#define LCD_DISPCTRL_VLCDSEL_MASK (0x1<<16) -#define LCD_DISPCTRL_CONCONF_VLCD (0<<15) -#define LCD_DISPCTRL_CONCONF_GND (1<<15) -#define LCD_DISPCTRL_CONCONF_MASK (0x1<<15) -/** By this parameter, the voltage V_LCD_OUT is interpolated linearly from - * 0.5V_LCD to V_LCD. - */ -#define LCD_DISPCTRL_CONLEV_MIN (0<<8) -#define LCD_DISPCTRL_CONLEV_MAX (31<<8) -#define LCD_DISPCTRL_CONLEV_MASK (0x1f<<8) -#define LCD_DISPCTRL_WAVE_LOWPOWER (0<<4) -#define LCD_DISPCTRL_WAVE_NORMAL (1<<4) -#define LCD_DISPCTRL_WAVE_MASK (0x1<<4) -#define LCD_DISPCTRL_BIAS_STATIC (0<<2) -#define LCD_DISPCTRL_BIAS_ONEHALF (1<<2) -#define LCD_DISPCTRL_BIAS_ONETHIRD (2<<2) -#define LCD_DISPCTRL_BIAS_ONEFOURTH (3<<2) -#define LCD_DISPCTRL_BIAS_MASK (0x3<<2) -/** These definitions munge the MUX and the MUXE fields, as they are described - * in the documentation only together too. - */ -#define LCD_DISPCTRL_MUX_STATIC 0x00000000 -#define LCD_DISPCTRL_MUX_DUPLEX 0x00000001 -#define LCD_DISPCTRL_MUX_TRIPLEX 0x00000002 -#define LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003 -#define LCD_DISPCTRL_MUX_SEXTAPLEX 0x00400001 -#define LCD_DISPCTRL_MUX_OCTAPLEX 0x00400003 -#define LCD_DISPCTRL_MUX_MASK 0x00400003 - -/** @} */ - -/** Bit states for the LCD_BACTRL register - * - * See d0034_efm32tg_reference_manual.pdf section 29.5.4 for definitions. - * - * @defgroup EFM32TG_LCD_BACTRL_bits LCD BACTRL bits - * @{ - */ - -#define LCD_BACTRL_FCTOP_MASK (0x3f<<18) -#define LCD_BACTRL_FCPRESC_DIV1 (0<<16) -#define LCD_BACTRL_FCPRESC_DIV2 (1<<16) -#define LCD_BACTRL_FCPRESC_DIV4 (2<<16) -#define LCD_BACTRL_FCPRESC_DIV8 (3<<16) -#define LCD_BACTRL_FCPRESC_MASK (0x3<<16) -#define LCD_BACTRL_FCEN (1<<8) -#define LCD_BACTRL_ALGOSEL_AND (0<<7) -#define LCD_BACTRL_ALGOSEL_OR (1<<7) -#define LCD_BACTRL_ALGOSEL_MASK (0x1<<7) -#define LCD_BACTRL_AREGBSC_NOSHIFT (0<<5) -#define LCD_BACTRL_AREGBSC_SHIFTLEFT (1<<5) -#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (2<<5) -#define LCD_BACTRL_AREGBSC_MASK (0x3<<5) -#define LCD_BACTRL_AREGASC_NOSHIFT (0<<3) -#define LCD_BACTRL_AREGASC_SHIFTLEFT (1<<3) -#define LCD_BACTRL_AREGASC_SHIFTRIGHT (2<<3) -#define LCD_BACTRL_AREGASC_MASK (0x3<<3) -#define LCD_BACTRL_AEN (1<<2) -#define LCD_BACTRL_BLANK (1<<1) -#define LCD_BACTRL_BLINKEN (1<<0) - -/** @} */ - -/** Bit states for the LCD_STATUS register - * - * See d0034_efm32tg_reference_manual.pdf section 29.5.5 for definitions. - * - * @defgroup EFM32TG_LCD_STATUS_bits LCD STATUS bits - * @{ - */ - -#define LCD_STATUS_BLINK (1<<8) -#define LCD_STATUS_ASTATE_MASK (0xf<<0) - -/** @} */ - -/** Bit states for the LCD_FREEZE register - * - * See d0034_efm32tg_reference_manual.pdf section 29.5.16 for definitions. - * - * @defgroup EFM32TG_LCD_FREEZE_bits LCD FREEZE bits - * @{ - */ - -#define LCD_FREEZE_REGFREEZE_UPDATE (0<<0) -#define LCD_FREEZE_REGFREEZE_FREEZE (1<<0) -#define LCD_FREEZE_REGFREEZE_MASK (0x1<<0) - -/** @} */ - -/** Bit states for the LCD_SYNCBUSY register - * - * See d0034_efm32tg_reference_manual.pdf section 29.5.17 for definitions. - * - * @defgroup EFM32TG_LCD_SYNCBUSY_bits LCD SYNCBUSY bits - * @{ - */ - -#define LCD_SYNCBUSY_SEGD7L (1<<19) -#define LCD_SYNCBUSY_SEGD6L (1<<18) -#define LCD_SYNCBUSY_SEGD5L (1<<17) -#define LCD_SYNCBUSY_SEGD4L (1<<16) -#define LCD_SYNCBUSY_SEGD3L (1<<7) -#define LCD_SYNCBUSY_SEGD2L (1<<6) -#define LCD_SYNCBUSY_SEGD1L (1<<5) -#define LCD_SYNCBUSY_SEGD0L (1<<4) -#define LCD_SYNCBUSY_AREGB (1<<3) -#define LCD_SYNCBUSY_AREGA (1<<2) -#define LCD_SYNCBUSY_BACTRL (1<<1) -#define LCD_SYNCBUSY_CTRL (1<<0) - -/** @} */ - -/** Bit states for the LCD "I" group of registers (IF, IFS, IFC, IEN) - * - * These registers use this: - * - *
      - * - *
    • The LCD_IF register; see d0034_efm32tg_reference_manual.pdf section - * 29.5.8 for definitions.
    • - * - *
    • The LCD_IFS register; see d0034_efm32tg_reference_manual.pdf section - * 29.5.9 for definitions.
    • - * - *
    • The LCD_IFC register; see d0034_efm32tg_reference_manual.pdf section - * 29.5.10 for definitions.
    • - * - *
    • The LCD_IEN register; see d0034_efm32tg_reference_manual.pdf section - * 29.5.11 for definitions.
    • - * - *
    - * - * @defgroup EFM32TG_LCD_I_bits LCD I bits group - * @{ - */ - -#define LCD_I_FC (1<<0) - -/** @} */ - -/** Bit states for the LCD "SEG" group of registers (SEGD0L, SEGD1L, SEGD2L, - * SEGD3L, SEGD4L, SEGD5L, SEGD6L, SEGD7L) - * - * These values are used by the SEGDxL registers, as defined in - * d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21. - * - * @defgroup EFM32TG_LCD_SEG_bits LCD SEG bits group - * @{ - */ - -#define LCD_SEG_23 (1<<23) -#define LCD_SEG_22 (1<<22) -#define LCD_SEG_21 (1<<21) -#define LCD_SEG_20 (1<<20) -#define LCD_SEG_19 (1<<19) -#define LCD_SEG_18 (1<<18) -#define LCD_SEG_17 (1<<17) -#define LCD_SEG_16 (1<<16) -#define LCD_SEG_15 (1<<15) -#define LCD_SEG_14 (1<<14) -#define LCD_SEG_13 (1<<13) -#define LCD_SEG_12 (1<<12) -#define LCD_SEG_11 (1<<11) -#define LCD_SEG_10 (1<<10) -#define LCD_SEG_9 (1<<9) -#define LCD_SEG_8 (1<<8) -#define LCD_SEG_7 (1<<7) -#define LCD_SEG_6 (1<<6) -#define LCD_SEG_5 (1<<5) -#define LCD_SEG_4 (1<<4) -#define LCD_SEG_3 (1<<3) -#define LCD_SEG_2 (1<<2) -#define LCD_SEG_1 (1<<1) -#define LCD_SEG_0 (1<<0) - -/** @} */ - -/** @} */ - - -/** @} */ - -#endif diff --git a/include/libopencm3/efm32/tinygecko/lcd.yaml b/include/libopencm3/efm32/tinygecko/lcd.yaml deleted file mode 100644 index 0e003bd..0000000 --- a/include/libopencm3/efm32/tinygecko/lcd.yaml +++ /dev/null @@ -1,241 +0,0 @@ -copyright: "2012 chrysn " -license: lgpl-3+ -ingroup: EFM32TG -shortdocname: EFM32TG_LCD -shortname: LCD -longname: Liquid Crystal Display driver -baseref: d0034_efm32tg_reference_manual.pdf section 29 -registers_baserefext: ".4" -templateregs: - - name: I - comment: Bits for the various LCD interrupt registers - fields: - - {name: FC, shift: 0} - - name: SEG - comment: Bits for the individual SEG pins - override_backref: These values are used by the SEGDxL registers, as defined in d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21. - fields: - - {name: 23, shift: 23} - - {name: 22, shift: 22} - - {name: 21, shift: 21} - - {name: 20, shift: 20} - - {name: 19, shift: 19} - - {name: 18, shift: 18} - - {name: 17, shift: 17} - - {name: 16, shift: 16} - - {name: 15, shift: 15} - - {name: 14, shift: 14} - - {name: 13, shift: 13} - - {name: 12, shift: 12} - - {name: 11, shift: 11} - - {name: 10, shift: 10} - - {name: 9, shift: 9} - - {name: 8, shift: 8} - - {name: 7, shift: 7} - - {name: 6, shift: 6} - - {name: 5, shift: 5} - - {name: 4, shift: 4} - - {name: 3, shift: 3} - - {name: 2, shift: 2} - - {name: 1, shift: 1} - - {name: 0, shift: 0} -registers: - - name: CTRL - offset: 0x000 - definition_baserefext: .5.1 - fields: - - name: DSC - shift: 23 - - name: UDCTRL - shift: 1 - length: 2 - values: - - {name: REGULAR, value: 0} - - {name: FCEVENT, value: 1} - - {name: FRAMESTART, value: 2} - - name: EN - shift: 0 - - name: DISPCTRL - offset: 0x004 - definition_baserefext: .5.2 - fields: - # MUXE left out and defined manually at the end - - name: VBLEV - shift: 18 - length: 3 - values: - - {name: LEVEL0, value: 0} - - {name: LEVEL1, value: 1} - - {name: LEVEL2, value: 2} - - {name: LEVEL3, value: 3} - - {name: LEVEL4, value: 4} - - {name: LEVEL5, value: 5} - - {name: LEVEL6, value: 6} - - {name: LEVEL7, value: 7} - - name: VLCDSEL - shift: 16 - values: - - {name: VDD, value: 0} - - {name: VEXTBOOST, value: 1} - - name: CONCONF - shift: 15 - values: - - {value: 0, name: VLCD} - - {value: 1, name: GND} - - name: CONLEV - shift: 8 - length: 5 - type: uint - doc: "By this parameter, the voltage V_LCD_OUT is interpolated linearly from 0.5V_LCD to V_LCD." - values: - - {value: 0, name: MIN} - - {value: 31, name: MAX} - - name: WAVE - shift: 4 - values: - - {value: 0, name: LOWPOWER} - - {value: 1, name: NORMAL} - - name: BIAS - shift: 2 - length: 2 - values: - - {value: 0, name: STATIC} - - {value: 1, name: ONEHALF} - - {value: 2, name: ONETHIRD} - - {value: 3, name: ONEFOURTH} - - name: MUX - mask: "0x00400003" - values: - - {value: "0x00000000", name: STATIC} - - {value: "0x00000001", name: DUPLEX} - - {value: "0x00000002", name: TRIPLEX} - - {value: "0x00000003", name: QUADRUPLEX} - - {value: "0x00400001", name: SEXTAPLEX} - - {value: "0x00400003", name: OCTAPLEX} - doc: These definitions munge the MUX and the MUXE fields, as they are described in the documentation only together too. - - name: SEGEN - offset: 0x008 - definition_baserefext: .5.3 - # FIXME how do we reperesent this best? - - name: BACTRL - offset: 0x00c - definition_baserefext: .5.4 - fields: - - name: FCTOP - shift: 18 - length: 6 - type: uint - - name: FCPRESC - shift: 16 - length: 2 - values: - - {value: 0, name: DIV1} - - {value: 1, name: DIV2} - - {value: 2, name: DIV4} - - {value: 3, name: DIV8} - - name: FCEN - shift: 8 - - name: ALGOSEL - shift: 7 - values: - - {value: 0, name: AND} - - {value: 1, name: OR} - - name: AREGBSC - shift: 5 - length: 2 - values: &BACTRL_AREGBSC - - {value: 0, name: NOSHIFT} - - {value: 1, name: SHIFTLEFT} - - {value: 2, name: SHIFTRIGHT} - - name: AREGASC - shift: 3 - length: 2 - values: *BACTRL_AREGBSC - - name: AEN - shift: 2 - - name: BLANK - shift: 1 - - name: BLINKEN - shift: 0 - - name: STATUS - offset: 0x010 - definition_baserefext: .5.5 - fields: - - name: BLINK - shift: 8 - - name: ASTATE - shift: 0 - length: 4 - type: uint - - name: AREGA - offset: 0x014 - # FIXME: how do we represent this in the header? - - name: AREGB - offset: 0x018 - # FIXME: how do we represent this in the header? - - name: IF - offset: 0x01c - definition_baserefext: .5.8 - fields: I - - name: IFS - offset: 0x020 - definition_baserefext: .5.9 - fields: I - - name: IFC - offset: 0x024 - definition_baserefext: .5.10 - fields: I - - name: IEN - offset: 0x028 - definition_baserefext: .5.11 - fields: I - - name: SEGD0L - offset: 0x040 - fields: SEG - - name: SEGD1L - offset: 0x044 - fields: SEG - - name: SEGD2L - offset: 0x048 - fields: SEG - - name: SEGD3L - offset: 0x04c - fields: SEG - - name: FREEZE - offset: 0x060 - definition_baserefext: .5.16 - fields: - - name: REGFREEZE - shift: 0 - values: - - {value: 0, name: UPDATE} - - {value: 1, name: FREEZE} - # FIXME: this seems to be a typical FREEZE register - - name: SYNCBUSY - offset: 0x064 - definition_baserefext: .5.17 - fields: - - {name: SEGD7L, shift: 19} - - {name: SEGD6L, shift: 18} - - {name: SEGD5L, shift: 17} - - {name: SEGD4L, shift: 16} - - {name: SEGD3L, shift: 7} - - {name: SEGD2L, shift: 6} - - {name: SEGD1L, shift: 5} - - {name: SEGD0L, shift: 4} - - {name: AREGB, shift: 3} - - {name: AREGA, shift: 2} - - {name: BACTRL, shift: 1} - - {name: CTRL, shift: 0} - - name: SEGD4L - offset: 0x0CC - fields: SEG - - name: SEGD5L - offset: 0x0D0 - fields: SEG - - name: SEGD6L - offset: 0x0D4 - fields: SEG - - name: SEGD7L - offset: 0x0D8 - fields: SEG diff --git a/lib/efm32/tinygecko/devicerevision.c b/lib/efm32/tinygecko/devicerevision.c deleted file mode 100644 index 0af3e90..0000000 --- a/lib/efm32/tinygecko/devicerevision.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -u8 devicerevision_revision_get(void) -{ - /* probably this is more elegant, more readable and closer to the spec, - * and i'll just get used to doing things like that: - return (DEVICEREVISION_PID2 & 0xf0) | ((DEVICEREVISION_PID3 & 0xf0) >> 4); - */ - return ((DEVICEREVISION_PID2 & DEVICEREVISION_REVISION_MASK) >> DEVICEREVISION_REVISION_SHIFT << DEVICEREVISION_REVISION_LENGTH) | ((DEVICEREVISION_PID3 & DEVICEREVISION_REVISION_MASK) >> DEVICEREVISION_REVISION_SHIFT); -} diff --git a/lib/efm32/tinygecko/gpio.c b/lib/efm32/tinygecko/gpio.c deleted file mode 100644 index 839d1b8..0000000 --- a/lib/efm32/tinygecko/gpio.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void gpio_set_mode(u32 gpioport, u8 mode, u16 gpios) -{ - u8 i; - u32 modemaskl = 0, modesetl = 0, modemaskh = 0, modeseth = 0; - - for (i = 0; i < 8; ++i) - { - if (gpios & (1< + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions of interrupt names on EFM32 Tiny Gecko systems + * + * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. + */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H + +#define IRQ_DMA 0 +#define IRQ_GPIO_EVEN 1 +#define IRQ_TIMER0 2 +#define IRQ_USART0_RX 3 +#define IRQ_USART0_TX 4 +#define IRQ_ACMP01 5 +#define IRQ_ADC0 6 +#define IRQ_DAC0 7 +#define IRQ_I2C0 8 +#define IRQ_GPIO_ODD 9 +#define IRQ_TIMER1 10 +#define IRQ_USART1_RX 11 +#define IRQ_USART1_TX 12 +#define IRQ_LESENSE 13 +#define IRQ_LEUART0 14 +#define IRQ_LETIMER0 15 +#define IRQ_PCNT0 16 +#define IRQ_RTC 17 +#define IRQ_CMU 18 +#define IRQ_VCMP 19 +#define IRQ_LCD 20 +#define IRQ_MSC 21 +#define IRQ_AES 22 +#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ + +#endif diff --git a/lib/efm32/tinygecko/Makefile b/lib/efm32/tinygecko/Makefile index b910509..934508d 100644 --- a/lib/efm32/tinygecko/Makefile +++ b/lib/efm32/tinygecko/Makefile @@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -D$(FAMILY) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o devicerevision.o gpio.o +OBJS = vector.o VPATH += ../ -- cgit v1.2.3 From a69d83d312396ee604426dce5341a54316c7c9b5 Mon Sep 17 00:00:00 2001 From: chrysn Date: Wed, 3 Oct 2012 18:15:20 +0200 Subject: unified vector table initialization the cortex generic interrupts get moved to lib/cm3/vector.c, the platorms' individual irq names, initialization and handler prototypes go to platoform specific irq.h files. as the vector.c file heavily depends on platoform specific headers, it can't be built once-and-for-all in lib/cm3/, so there are inclusion stubs in the various architecture dirs; this might be better solved with Makefile / include path handling. one particular file is lib/lpc43xx/vector.c; that platform's initialization code contains an additional section to copy everything from flash to ram (which probably performs better there). that code still resides in the inclusion stub, and gets mashed in using defines. would need a cleaner implementation together with the Makefile solution. this commit contains some files of the upcoming efm32 branch, from which it was cherry-picked. the .bin files produced from before and after this commit only differ in lpc43xx, where the startup sequence was subtly modified. --- include/libopencm3/cm3/vector.h | 65 ++++++ include/libopencm3/efm32/tinygecko/irq.h | 130 +++++++++++ include/libopencm3/lm3s/irq.h | 33 +++ include/libopencm3/lpc17xx/irq.h | 33 +++ include/libopencm3/lpc43xx/irq.h | 234 ++++++++++++++++++++ include/libopencm3/stm32/f1/irq.h | 306 ++++++++++++++++++++++++++ include/libopencm3/stm32/f2/irq.h | 359 +++++++++++++++++++++++++++++++ include/libopencm3/stm32/f4/irq.h | 359 +++++++++++++++++++++++++++++++ lib/cm3/vector.c | 95 ++++++++ lib/efm32/tinygecko/vector.c | 2 + lib/lm3s/vector.c | 98 +-------- lib/lpc17xx/vector.c | 97 +-------- lib/lpc43xx/vector.c | 224 +------------------ lib/stm32/f1/vector.c | 298 +------------------------ lib/stm32/f2/vector.c | 338 +---------------------------- lib/stm32/f4/vector.c | 338 +---------------------------- 16 files changed, 1633 insertions(+), 1376 deletions(-) create mode 100644 include/libopencm3/cm3/vector.h create mode 100644 include/libopencm3/efm32/tinygecko/irq.h create mode 100644 include/libopencm3/lm3s/irq.h create mode 100644 include/libopencm3/lpc17xx/irq.h create mode 100644 include/libopencm3/lpc43xx/irq.h create mode 100644 include/libopencm3/stm32/f1/irq.h create mode 100644 include/libopencm3/stm32/f2/irq.h create mode 100644 include/libopencm3/stm32/f4/irq.h create mode 100644 lib/cm3/vector.c create mode 100644 lib/efm32/tinygecko/vector.c (limited to 'include') diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h new file mode 100644 index 0000000..198992b --- /dev/null +++ b/include/libopencm3/cm3/vector.h @@ -0,0 +1,65 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions for handling vector tables. + * + * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2 + * (from the EFM32 documentation at + * http://www.energymicro.com/downloads/datasheets), and was seen analogously + * in other ARM implementations' libopencm3 files. + * + * The structure of the vector table is implemented independently of the system + * vector table starting at memory position 0x0, as it can be relocated to + * other memory locations too. + * + * The exact size of a vector interrupt table depends on the number of + * interrupts IRQ_COUNT, which is defined per family. + */ + +#ifndef LIBOPENCM3_VECTOR_H +#define LIBOPENCM3_VECTOR_H + +#include + +// #include "irq.h" /* we'll nede some definitions */ + +/** Type of an interrupt function. Only used to avoid hard-to-read function + * pointers in the efm32_vector_table_t struct. */ +typedef void (*vector_table_entry_t)(void); + +typedef struct { + unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ + vector_table_entry_t reset; + vector_table_entry_t nmi; + vector_table_entry_t hard_fault; + vector_table_entry_t memory_manage_fault; + vector_table_entry_t bus_fault; + vector_table_entry_t usage_fault; + vector_table_entry_t reserved_x001c[4]; + vector_table_entry_t sv_call; + vector_table_entry_t debug_monitor; + vector_table_entry_t reserved_x0034; + vector_table_entry_t pend_sv; + vector_table_entry_t systick; + vector_table_entry_t irq[IRQ_COUNT]; +} vector_table_t; + +#endif diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h new file mode 100644 index 0000000..f5263ae --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq.h @@ -0,0 +1,130 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions of interrupt names on EFM32 Tiny Gecko systems + * + * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. + */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H + +#define IRQ_DMA 0 +#define IRQ_GPIO_EVEN 1 +#define IRQ_TIMER0 2 +#define IRQ_USART0_RX 3 +#define IRQ_USART0_TX 4 +#define IRQ_ACMP01 5 +#define IRQ_ADC0 6 +#define IRQ_DAC0 7 +#define IRQ_I2C0 8 +#define IRQ_GPIO_ODD 9 +#define IRQ_TIMER1 10 +#define IRQ_USART1_RX 11 +#define IRQ_USART1_TX 12 +#define IRQ_LESENSE 13 +#define IRQ_LEUART0 14 +#define IRQ_LETIMER0 15 +#define IRQ_PCNT0 16 +#define IRQ_RTC 17 +#define IRQ_CMU 18 +#define IRQ_VCMP 19 +#define IRQ_LCD 20 +#define IRQ_MSC 21 +#define IRQ_AES 22 +#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ + +#define WEAK __attribute__ ((weak)) + +void WEAK dma_isr(void); +void WEAK gpio_even_isr(void); +void WEAK timer0_isr(void); +void WEAK usart0_rx_isr(void); +void WEAK usart0_tx_isr(void); +void WEAK acmp01_isr(void); +void WEAK adc0_isr(void); +void WEAK dac0_isr(void); +void WEAK i2c0_isr(void); +void WEAK gpio_odd_isr(void); +void WEAK timer1_isr(void); +void WEAK usart1_rx_isr(void); +void WEAK usart1_tx_isr(void); +void WEAK lesense_isr(void); +void WEAK leuart0_isr(void); +void WEAK letimer0_isr(void); +void WEAK pcnt0_isr(void); +void WEAK rtc_isr(void); +void WEAK cmu_isr(void); +void WEAK vcmp_isr(void); +void WEAK lcd_isr(void); +void WEAK msc_isr(void); +void WEAK aes_isr(void); + +#pragma weak dma_isr = blocking_handler +#pragma weak gpio_even_isr = blocking_handler +#pragma weak timer0_isr = blocking_handler +#pragma weak usart0_rx_isr = blocking_handler +#pragma weak usart0_tx_isr = blocking_handler +#pragma weak acmp01_isr = blocking_handler +#pragma weak adc0_isr = blocking_handler +#pragma weak dac0_isr = blocking_handler +#pragma weak i2c0_isr = blocking_handler +#pragma weak gpio_odd_isr = blocking_handler +#pragma weak timer1_isr = blocking_handler +#pragma weak usart1_rx_isr = blocking_handler +#pragma weak usart1_tx_isr = blocking_handler +#pragma weak lesense_isr = blocking_handler +#pragma weak leuart0_isr = blocking_handler +#pragma weak letimer0_isr = blocking_handler +#pragma weak pcnt0_isr = blocking_handler +#pragma weak rtc_isr = blocking_handler +#pragma weak cmu_isr = blocking_handler +#pragma weak vcmp_isr = blocking_handler +#pragma weak lcd_isr = blocking_handler +#pragma weak msc_isr = blocking_handler +#pragma weak aes_isr = blocking_handler + +#define IRQ_HANDLERS \ + [IRQ_DMA] = dma_isr, \ + [IRQ_GPIO_EVEN] = gpio_even_isr, \ + [IRQ_TIMER0] = timer0_isr, \ + [IRQ_USART0_RX] = usart0_rx_isr, \ + [IRQ_USART0_TX] = usart0_tx_isr, \ + [IRQ_ACMP01] = acmp01_isr, \ + [IRQ_ADC0] = adc0_isr, \ + [IRQ_DAC0] = dac0_isr, \ + [IRQ_I2C0] = i2c0_isr, \ + [IRQ_GPIO_ODD] = gpio_odd_isr, \ + [IRQ_TIMER1] = timer1_isr, \ + [IRQ_USART1_RX] = usart1_rx_isr, \ + [IRQ_USART1_TX] = usart1_tx_isr, \ + [IRQ_LESENSE] = lesense_isr, \ + [IRQ_LEUART0] = leuart0_isr, \ + [IRQ_LETIMER0] = letimer0_isr, \ + [IRQ_PCNT0] = pcnt0_isr, \ + [IRQ_RTC] = rtc_isr, \ + [IRQ_CMU] = cmu_isr, \ + [IRQ_VCMP] = vcmp_isr, \ + [IRQ_LCD] = lcd_isr, \ + [IRQ_MSC] = msc_isr, \ + [IRQ_AES] = aes_isr, + +#endif diff --git a/include/libopencm3/lm3s/irq.h b/include/libopencm3/lm3s/irq.h new file mode 100644 index 0000000..948c563 --- /dev/null +++ b/include/libopencm3/lm3s/irq.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LM3S_IRQ_H +#define LIBOPENCM3_LM3S_IRQ_H + +/* TODO: Interrupt definitions */ +#define IRQ_COUNT 0 + +/* TODO: Interrupt handler prototypes */ + +/* TODO: Interrupt handler weak aliases */ + +#define IRQ_HANDLERS + +#endif diff --git a/include/libopencm3/lpc17xx/irq.h b/include/libopencm3/lpc17xx/irq.h new file mode 100644 index 0000000..9c31267 --- /dev/null +++ b/include/libopencm3/lpc17xx/irq.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LPC17xx_IRQ_H +#define LIBOPENCM3_LPC17xx_IRQ_H + +/* TODO: Interrupt definitions */ +#define IRQ_COUNT 0 + +/* TODO: Interrupt handler prototypes */ + +/* TODO: Interrupt handler weak aliases */ + +#define IRQ_HANDLERS + +#endif diff --git a/include/libopencm3/lpc43xx/irq.h b/include/libopencm3/lpc43xx/irq.h new file mode 100644 index 0000000..a83a8d7 --- /dev/null +++ b/include/libopencm3/lpc43xx/irq.h @@ -0,0 +1,234 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LPC43XX_IRQ_H +#define LIBOPENCM3_LPC43XX_IRQ_H + +#define IRQ_DAC 0 +#define IRQ_M0CORE 1 +#define IRQ_DMA 2 +/* reserved: 3 */ +/* reserved: 4 */ +#define IRQ_ETHERNET 5 +#define IRQ_SDIO 6 +#define IRQ_LCD 7 +#define IRQ_USB0 8 +#define IRQ_USB1 9 +#define IRQ_SCT 10 +#define IRQ_RITIMER 11 +#define IRQ_TIMER0 12 +#define IRQ_TIMER1 13 +#define IRQ_TIMER2 14 +#define IRQ_TIMER3 15 +#define IRQ_MCPWM 16 +#define IRQ_ADC0 17 +#define IRQ_I2C0 18 +#define IRQ_I2C1 19 +#define IRQ_SPI 20 +#define IRQ_ADC1 21 +#define IRQ_SSP0 22 +#define IRQ_SSP1 23 +#define IRQ_USART0 24 +#define IRQ_UART1 25 +#define IRQ_USART2 26 +#define IRQ_USART3 27 +#define IRQ_I2S0 28 +#define IRQ_I2S1 29 +#define IRQ_SPIFI 30 +#define IRQ_SGPIO 31 +#define IRQ_PIN_INT0 32 +#define IRQ_PIN_INT1 33 +#define IRQ_PIN_INT2 34 +#define IRQ_PIN_INT3 35 +#define IRQ_PIN_INT4 36 +#define IRQ_PIN_INT5 37 +#define IRQ_PIN_INT6 38 +#define IRQ_PIN_INT7 39 +#define IRQ_GINT0 40 +#define IRQ_GINT1 41 +#define IRQ_EVENTROUTER 42 +#define IRQ_C_CAN1 43 +/* reserved: 44 */ +/* reserved: 45 */ +#define IRQ_ATIMER 46 +#define IRQ_RTC 47 +/* reserved: 48 */ +#define IRQ_WWDT 49 +/* reserved: 50 */ +#define IRQ_C_CAN0 51 +#define IRQ_QEI 52 + +#define IRQ_COUNT 53 + +#define WEAK __attribute__ ((weak)) + +void WEAK dac_irqhandler(void); +void WEAK m0core_irqhandler(void); +void WEAK dma_irqhandler(void); +void WEAK ethernet_irqhandler(void); +void WEAK sdio_irqhandler(void); +void WEAK lcd_irqhandler(void); +void WEAK usb0_irqhandler(void); +void WEAK usb1_irqhandler(void); +void WEAK sct_irqhandler(void); +void WEAK ritimer_irqhandler(void); +void WEAK timer0_irqhandler(void); +void WEAK timer1_irqhandler(void); +void WEAK timer2_irqhandler(void); +void WEAK timer3_irqhandler(void); +void WEAK mcpwm_irqhandler(void); +void WEAK adc0_irqhandler(void); +void WEAK i2c0_irqhandler(void); +void WEAK i2c1_irqhandler(void); +void WEAK spi_irqhandler(void); +void WEAK adc1_irqhandler(void); +void WEAK ssp0_irqhandler(void); +void WEAK ssp1_irqhandler(void); +void WEAK usart0_irqhandler(void); +void WEAK uart1_irqhandler(void); +void WEAK usart2_irqhandler(void); +void WEAK usart3_irqhandler(void); +void WEAK i2s0_irqhandler(void); +void WEAK i2s1_irqhandler(void); +void WEAK spifi_irqhandler(void); +void WEAK sgpio_irqhandler(void); +void WEAK pin_int0_irqhandler(void); +void WEAK pin_int1_irqhandler(void); +void WEAK pin_int2_irqhandler(void); +void WEAK pin_int3_irqhandler(void); +void WEAK pin_int4_irqhandler(void); +void WEAK pin_int5_irqhandler(void); +void WEAK pin_int6_irqhandler(void); +void WEAK pin_int7_irqhandler(void); +void WEAK gint0_irqhandler(void); +void WEAK gint1_irqhandler(void); +void WEAK eventrouter_irqhandler(void); +void WEAK c_can1_irqhandler(void); +void WEAK atimer_irqhandler(void); +void WEAK rtc_irqhandler(void); +void WEAK wwdt_irqhandler(void); +void WEAK c_can0_irqhandler(void); +void WEAK qei_irqhandler(void); + +#pragma weak dac_irqhandler = null_handler +#pragma weak m0core_irqhandler = null_handler +#pragma weak dma_irqhandler = null_handler +#pragma weak ethernet_irqhandler = null_handler +#pragma weak sdio_irqhandler = null_handler +#pragma weak lcd_irqhandler = null_handler +#pragma weak usb0_irqhandler = null_handler +#pragma weak usb1_irqhandler = null_handler +#pragma weak sct_irqhandler = null_handler +#pragma weak ritimer_irqhandler = null_handler +#pragma weak timer0_irqhandler = null_handler +#pragma weak timer1_irqhandler = null_handler +#pragma weak timer2_irqhandler = null_handler +#pragma weak timer3_irqhandler = null_handler +#pragma weak mcpwm_irqhandler = null_handler +#pragma weak adc0_irqhandler = null_handler +#pragma weak i2c0_irqhandler = null_handler +#pragma weak i2c1_irqhandler = null_handler +#pragma weak spi_irqhandler = null_handler +#pragma weak adc1_irqhandler = null_handler +#pragma weak ssp0_irqhandler = null_handler +#pragma weak ssp1_irqhandler = null_handler +#pragma weak usart0_irqhandler = null_handler +#pragma weak uart1_irqhandler = null_handler +#pragma weak usart2_irqhandler = null_handler +#pragma weak usart3_irqhandler = null_handler +#pragma weak i2s0_irqhandler = null_handler +#pragma weak i2s1_irqhandler = null_handler +#pragma weak spifi_irqhandler = null_handler +#pragma weak sgpio_irqhandler = null_handler +#pragma weak pin_int0_irqhandler = null_handler +#pragma weak pin_int1_irqhandler = null_handler +#pragma weak pin_int2_irqhandler = null_handler +#pragma weak pin_int3_irqhandler = null_handler +#pragma weak pin_int4_irqhandler = null_handler +#pragma weak pin_int5_irqhandler = null_handler +#pragma weak pin_int6_irqhandler = null_handler +#pragma weak pin_int7_irqhandler = null_handler +#pragma weak gint0_irqhandler = null_handler +#pragma weak gint1_irqhandler = null_handler +#pragma weak eventrouter_irqhandler = null_handler +#pragma weak c_can1_irqhandler = null_handler +#pragma weak atimer_irqhandler = null_handler +#pragma weak rtc_irqhandler = null_handler +#pragma weak wwdt_irqhandler = null_handler +#pragma weak c_can0_irqhandler = null_handler +#pragma weak qei_irqhandler = null_handler + +#define IRQ_HANDLERS \ + dac_irqhandler, \ + m0core_irqhandler, \ + dma_irqhandler, \ + 0, /* reserved */ \ + 0, /* reserved */ \ + ethernet_irqhandler, \ + sdio_irqhandler, \ + lcd_irqhandler, \ + usb0_irqhandler, \ + usb1_irqhandler, \ + sct_irqhandler, \ + ritimer_irqhandler, \ + timer0_irqhandler, \ + timer1_irqhandler, \ + timer2_irqhandler, \ + timer3_irqhandler, \ + mcpwm_irqhandler, \ + adc0_irqhandler, \ + i2c0_irqhandler, \ + i2c1_irqhandler, \ + spi_irqhandler, \ + adc1_irqhandler, \ + ssp0_irqhandler, \ + ssp1_irqhandler, \ + usart0_irqhandler, \ + uart1_irqhandler, \ + usart2_irqhandler, \ + usart3_irqhandler, \ + i2s0_irqhandler, \ + i2s1_irqhandler, \ + spifi_irqhandler, \ + sgpio_irqhandler, \ + pin_int0_irqhandler, \ + pin_int1_irqhandler, \ + pin_int2_irqhandler, \ + pin_int3_irqhandler, \ + pin_int4_irqhandler, \ + pin_int5_irqhandler, \ + pin_int6_irqhandler, \ + pin_int7_irqhandler, \ + gint0_irqhandler, \ + gint1_irqhandler, \ + eventrouter_irqhandler, \ + c_can1_irqhandler, \ + 0, /* reserved */ \ + 0, /* reserved */ \ + atimer_irqhandler, \ + rtc_irqhandler, \ + 0, /* reserved */ \ + wwdt_irqhandler, \ + 0, /* reserved */ \ + c_can0_irqhandler, \ + qei_irqhandler, + +#endif diff --git a/include/libopencm3/stm32/f1/irq.h b/include/libopencm3/stm32/f1/irq.h new file mode 100644 index 0000000..cfa07f1 --- /dev/null +++ b/include/libopencm3/stm32/f1/irq.h @@ -0,0 +1,306 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F1_IRQ_H +#define LIBOPENCM3_STM32_F1_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMPER 2 +#define IRQ_RTC 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_CHANNEL1 11 +#define IRQ_DMA1_CHANNEL2 12 +#define IRQ_DMA1_CHANNEL3 13 +#define IRQ_DMA1_CHANNEL4 14 +#define IRQ_DMA1_CHANNEL5 15 +#define IRQ_DMA1_CHANNEL6 16 +#define IRQ_DMA1_CHANNEL7 17 +#define IRQ_ADC1_2 18 +#define IRQ_USB_HP_CAN_TX 19 +#define IRQ_USB_LP_CAN_RX0 20 +#define IRQ_CAN_RX1 21 +#define IRQ_CAN_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK 24 +#define IRQ_TIM1_UP 25 +#define IRQ_TIM1_TRG_COM 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_WAKEUP 42 +#define IRQ_TIM8_BRK 43 +#define IRQ_TIM8_UP 44 +#define IRQ_TIM8_TRG_COM 45 +#define IRQ_TIM8_CC 46 +#define IRQ_ADC3 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_CHANNEL1 56 +#define IRQ_DMA2_CHANNEL2 57 +#define IRQ_DMA2_CHANNEL3 58 +#define IRQ_DMA2_CHANNEL4_5 59 +#define IRQ_DMA2_CHANNEL5 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 + +/* FIXME: number from list in lib/stm32/f1/vector.c, might miss irqs */ +#define IRQ_COUNT 68 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamper_isr(void); +void WEAK rtc_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_channel1_isr(void); +void WEAK dma1_channel2_isr(void); +void WEAK dma1_channel3_isr(void); +void WEAK dma1_channel4_isr(void); +void WEAK dma1_channel5_isr(void); +void WEAK dma1_channel6_isr(void); +void WEAK dma1_channel7_isr(void); +void WEAK adc1_2_isr(void); +void WEAK usb_hp_can_tx_isr(void); +void WEAK usb_lp_can_rx0_isr(void); +void WEAK can_rx1_isr(void); +void WEAK can_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_isr(void); +void WEAK tim1_up_isr(void); +void WEAK tim1_trg_com_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_wakeup_isr(void); +void WEAK tim8_brk_isr(void); +void WEAK tim8_up_isr(void); +void WEAK tim8_trg_com_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK adc3_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_channel1_isr(void); +void WEAK dma2_channel2_isr(void); +void WEAK dma2_channel3_isr(void); +void WEAK dma2_channel4_5_isr(void); +void WEAK dma2_channel5_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamper_isr = null_handler +#pragma weak rtc_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_channel1_isr = null_handler +#pragma weak dma1_channel2_isr = null_handler +#pragma weak dma1_channel3_isr = null_handler +#pragma weak dma1_channel4_isr = null_handler +#pragma weak dma1_channel5_isr = null_handler +#pragma weak dma1_channel6_isr = null_handler +#pragma weak dma1_channel7_isr = null_handler +#pragma weak adc1_2_isr = null_handler +#pragma weak usb_hp_can_tx_isr = null_handler +#pragma weak usb_lp_can_rx0_isr = null_handler +#pragma weak can_rx1_isr = null_handler +#pragma weak can_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_isr = null_handler +#pragma weak tim1_up_isr = null_handler +#pragma weak tim1_trg_com_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_wakeup_isr = null_handler +#pragma weak tim8_brk_isr = null_handler +#pragma weak tim8_up_isr = null_handler +#pragma weak tim8_trg_com_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak adc3_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_channel1_isr = null_handler +#pragma weak dma2_channel2_isr = null_handler +#pragma weak dma2_channel3_isr = null_handler +#pragma weak dma2_channel4_5_isr = null_handler +#pragma weak dma2_channel5_isr +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamper_isr, \ + rtc_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_channel1_isr, \ + dma1_channel2_isr, \ + dma1_channel3_isr, \ + dma1_channel4_isr, \ + dma1_channel5_isr, \ + dma1_channel6_isr, \ + dma1_channel7_isr, \ + adc1_2_isr, \ + usb_hp_can_tx_isr, \ + usb_lp_can_rx0_isr, \ + can_rx1_isr, \ + can_sce_isr, \ + exti9_5_isr, \ + tim1_brk_isr, \ + tim1_up_isr, \ + tim1_trg_com_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_wakeup_isr, \ + tim8_brk_isr, \ + tim8_up_isr, \ + tim8_trg_com_isr, \ + tim8_cc_isr, \ + adc3_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_isr, \ + tim7_isr, \ + dma2_channel1_isr, \ + dma2_channel2_isr, \ + dma2_channel3_isr, \ + dma2_channel4_5_isr, \ + dma2_channel5_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + +#endif diff --git a/include/libopencm3/stm32/f2/irq.h b/include/libopencm3/stm32/f2/irq.h new file mode 100644 index 0000000..7aec142 --- /dev/null +++ b/include/libopencm3/stm32/f2/irq.h @@ -0,0 +1,359 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F2_IRQ_H +#define LIBOPENCM3_STM32_F2_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMP_STAMP 2 +#define IRQ_RTC_WKUP 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_STREAM0 11 +#define IRQ_DMA1_STREAM1 12 +#define IRQ_DMA1_STREAM2 13 +#define IRQ_DMA1_STREAM3 14 +#define IRQ_DMA1_STREAM4 15 +#define IRQ_DMA1_STREAM5 16 +#define IRQ_DMA1_STREAM6 17 +#define IRQ_ADC 18 +#define IRQ_CAN1_TX 19 +#define IRQ_CAN1_RX0 20 +#define IRQ_CAN1_RX1 21 +#define IRQ_CAN1_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK_TIM9 24 +#define IRQ_TIM1_UP_TIM10 25 +#define IRQ_TIM1_TRG_COM_TIM11 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_FS_WKUP 42 +#define IRQ_TIM8_BRK_TIM12 43 +#define IRQ_TIM8_UP_TIM13 44 +#define IRQ_TIM8_TRG_COM_TIM14 45 +#define IRQ_TIM8_CC 46 +#define IRQ_DMA1_STREAM7 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6_DAC 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_STREAM0 56 +#define IRQ_DMA2_STREAM1 57 +#define IRQ_DMA2_STREAM2 58 +#define IRQ_DMA2_STREAM3 59 +#define IRQ_DMA2_STREAM4 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 +#define IRQ_DMA2_STREAM5 68 +#define IRQ_DMA2_STREAM6 69 +#define IRQ_DMA2_STREAM7 70 +#define IRQ_USART6 71 +#define IRQ_I2C3_EV 72 +#define IRQ_I2C3_ER 73 +#define IRQ_OTG_HS_EP1_OUT 74 +#define IRQ_OTG_HS_EP1_IN 75 +#define IRQ_OTG_HS_WKUP 76 +#define IRQ_OTG_HS 77 +#define IRQ_DCMI 78 +#define IRQ_CRYP 79 +#define IRQ_HASH_RNG 80 + +/* FIXME: number from list in lib/stm32/f2/vector.c, might miss irqs */ +#define IRQ_COUNT 81 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamp_stamp_isr, \ + rtc_wkup_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_stream0_isr, \ + dma1_stream1_isr, \ + dma1_stream2_isr, \ + dma1_stream3_isr, \ + dma1_stream4_isr, \ + dma1_stream5_isr, \ + dma1_stream6_isr, \ + adc_isr, \ + can1_tx_isr, \ + can1_rx0_isr, \ + can1_rx1_isr, \ + can1_sce_isr, \ + exti9_5_isr, \ + tim1_brk_tim9_isr, \ + tim1_up_tim10_isr, \ + tim1_trg_com_tim11_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_fs_wkup_isr, \ + tim8_brk_tim12_isr, \ + tim8_up_tim13_isr, \ + tim8_trg_com_tim14_isr, \ + tim8_cc_isr, \ + dma1_stream7_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_dac_isr, \ + tim7_isr, \ + dma2_stream0_isr, \ + dma2_stream1_isr, \ + dma2_stream2_isr, \ + dma2_stream3_isr, \ + dma2_stream4_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + dma2_stream5_isr, \ + dma2_stream6_isr, \ + dma2_stream7_isr, \ + usart6_isr, \ + i2c3_ev_isr, \ + i2c3_er_isr, \ + otg_hs_ep1_out_isr, \ + otg_hs_ep1_in_isr, \ + otg_hs_wkup_isr, \ + otg_hs_isr, \ + dcmi_isr, \ + cryp_isr, \ + hash_rng_isr, + +#endif diff --git a/include/libopencm3/stm32/f4/irq.h b/include/libopencm3/stm32/f4/irq.h new file mode 100644 index 0000000..4f4f5e5 --- /dev/null +++ b/include/libopencm3/stm32/f4/irq.h @@ -0,0 +1,359 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F4_IRQ_H +#define LIBOPENCM3_STM32_F4_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMP_STAMP 2 +#define IRQ_RTC_WKUP 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_STREAM0 11 +#define IRQ_DMA1_STREAM1 12 +#define IRQ_DMA1_STREAM2 13 +#define IRQ_DMA1_STREAM3 14 +#define IRQ_DMA1_STREAM4 15 +#define IRQ_DMA1_STREAM5 16 +#define IRQ_DMA1_STREAM6 17 +#define IRQ_ADC 18 +#define IRQ_CAN1_TX 19 +#define IRQ_CAN1_RX0 20 +#define IRQ_CAN1_RX1 21 +#define IRQ_CAN1_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK_TIM9 24 +#define IRQ_TIM1_UP_TIM10 25 +#define IRQ_TIM1_TRG_COM_TIM11 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_FS_WKUP 42 +#define IRQ_TIM8_BRK_TIM12 43 +#define IRQ_TIM8_UP_TIM13 44 +#define IRQ_TIM8_TRG_COM_TIM14 45 +#define IRQ_TIM8_CC 46 +#define IRQ_DMA1_STREAM7 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6_DAC 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_STREAM0 56 +#define IRQ_DMA2_STREAM1 57 +#define IRQ_DMA2_STREAM2 58 +#define IRQ_DMA2_STREAM3 59 +#define IRQ_DMA2_STREAM4 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 +#define IRQ_DMA2_STREAM5 68 +#define IRQ_DMA2_STREAM6 69 +#define IRQ_DMA2_STREAM7 70 +#define IRQ_USART6 71 +#define IRQ_I2C3_EV 72 +#define IRQ_I2C3_ER 73 +#define IRQ_OTG_HS_EP1_OUT 74 +#define IRQ_OTG_HS_EP1_IN 75 +#define IRQ_OTG_HS_WKUP 76 +#define IRQ_OTG_HS 77 +#define IRQ_DCMI 78 +#define IRQ_CRYP 79 +#define IRQ_HASH_RNG 80 + +/* FIXME: number from list in lib/stm32/f4/vector.c, might miss irqs */ +#define IRQ_COUNT 81 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamp_stamp_isr, \ + rtc_wkup_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_stream0_isr, \ + dma1_stream1_isr, \ + dma1_stream2_isr, \ + dma1_stream3_isr, \ + dma1_stream4_isr, \ + dma1_stream5_isr, \ + dma1_stream6_isr, \ + adc_isr, \ + can1_tx_isr, \ + can1_rx0_isr, \ + can1_rx1_isr, \ + can1_sce_isr, \ + exti9_5_isr, \ + tim1_brk_tim9_isr, \ + tim1_up_tim10_isr, \ + tim1_trg_com_tim11_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_fs_wkup_isr, \ + tim8_brk_tim12_isr, \ + tim8_up_tim13_isr, \ + tim8_trg_com_tim14_isr, \ + tim8_cc_isr, \ + dma1_stream7_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_dac_isr, \ + tim7_isr, \ + dma2_stream0_isr, \ + dma2_stream1_isr, \ + dma2_stream2_isr, \ + dma2_stream3_isr, \ + dma2_stream4_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + dma2_stream5_isr, \ + dma2_stream6_isr, \ + dma2_stream7_isr, \ + usart6_isr, \ + i2c3_ev_isr, \ + i2c3_er_isr, \ + otg_hs_ep1_out_isr, \ + otg_hs_ep1_in_isr, \ + otg_hs_wkup_isr, \ + otg_hs_isr, \ + dcmi_isr, \ + cryp_isr, \ + hash_rng_isr, + +#endif diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c new file mode 100644 index 0000000..200e8e5 --- /dev/null +++ b/lib/cm3/vector.c @@ -0,0 +1,95 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski , + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by the linker script(s): */ +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; + +void main(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK reset_handler(void); +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); + +__attribute__ ((section(".vectors"))) +vector_table_t vector_table = { + .initial_sp_value = &_stack, + .reset = reset_handler, + .nmi = nmi_handler, + .hard_fault = hard_fault_handler, + .memory_manage_fault = mem_manage_handler, + .bus_fault = bus_fault_handler, + .usage_fault = usage_fault_handler, + .debug_monitor = debug_monitor_handler, + .sv_call = sv_call_handler, + .pend_sv = pend_sv_handler, + .systick = sys_tick_handler, + .irq = { + IRQ_HANDLERS + } +}; + +void WEAK reset_handler(void) +{ + volatile unsigned *src, *dest; + + __asm__("MSR msp, %0" : : "r"(&_stack)); + + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c new file mode 100644 index 0000000..d6da5a2 --- /dev/null +++ b/lib/efm32/tinygecko/vector.c @@ -0,0 +1,2 @@ +#include +#include "../../cm3/vector.c" diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c index 3a1c4d1..e9e7e06 100644 --- a/lib/lm3s/vector.c +++ b/lib/lm3s/vector.c @@ -1,96 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); - -/* TODO: Interrupt handler prototypes */ - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - - /* TODO: Interrupt handlers */ -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#include +#include "../cm3/vector.c" diff --git a/lib/lpc17xx/vector.c b/lib/lpc17xx/vector.c index 518f562..61342f4 100644 --- a/lib/lpc17xx/vector.c +++ b/lib/lpc17xx/vector.c @@ -1,95 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); - -/* TODO: Interrupt handler prototypes */ - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void*)&_stack, /* Addr: 0x0000_0000 */ - reset_handler, /* Addr: 0x0000_0004 */ - nmi_handler, /* Addr: 0x0000_0008 */ - hard_fault_handler, /* Addr: 0x0000_000C */ - mem_manage_handler, /* Addr: 0x0000_0010 */ - bus_fault_handler, /* Addr: 0x0000_0014 */ - usage_fault_handler, /* Addr: 0x0000_0018 */ - 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ - sv_call_handler, /* Addr: 0x0000_002C */ - debug_monitor_handler, /* Addr: 0x0000_0030 */ - 0, /* Reserved Addr: 0x0000_00034 */ - pend_sv_handler, /* Addr: 0x0000_0038 */ - sys_tick_handler, /* Addr: 0x0000_003C */ -}; - - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#include +#include "../cm3/vector.c" diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 23008bc..66e9b63 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -18,156 +18,20 @@ * along with this library. If not, see . */ -#define WEAK __attribute__ ((weak)) +#include +#define reset_handler original_reset_handler +#include "../cm3/vector.c" +#undef reset_handler +#include -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; extern unsigned _etext_ram, _text_ram, _etext_rom; -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK dac_irqhandler(void); -void WEAK m0core_irqhandler(void); -void WEAK dma_irqhandler(void); -void WEAK ethernet_irqhandler(void); -void WEAK sdio_irqhandler(void); -void WEAK lcd_irqhandler(void); -void WEAK usb0_irqhandler(void); -void WEAK usb1_irqhandler(void); -void WEAK sct_irqhandler(void); -void WEAK ritimer_irqhandler(void); -void WEAK timer0_irqhandler(void); -void WEAK timer1_irqhandler(void); -void WEAK timer2_irqhandler(void); -void WEAK timer3_irqhandler(void); -void WEAK mcpwm_irqhandler(void); -void WEAK adc0_irqhandler(void); -void WEAK i2c0_irqhandler(void); -void WEAK i2c1_irqhandler(void); -void WEAK spi_irqhandler(void); -void WEAK adc1_irqhandler(void); -void WEAK ssp0_irqhandler(void); -void WEAK ssp1_irqhandler(void); -void WEAK usart0_irqhandler(void); -void WEAK uart1_irqhandler(void); -void WEAK usart2_irqhandler(void); -void WEAK usart3_irqhandler(void); -void WEAK i2s0_irqhandler(void); -void WEAK i2s1_irqhandler(void); -void WEAK spifi_irqhandler(void); -void WEAK sgpio_irqhandler(void); -void WEAK pin_int0_irqhandler(void); -void WEAK pin_int1_irqhandler(void); -void WEAK pin_int2_irqhandler(void); -void WEAK pin_int3_irqhandler(void); -void WEAK pin_int4_irqhandler(void); -void WEAK pin_int5_irqhandler(void); -void WEAK pin_int6_irqhandler(void); -void WEAK pin_int7_irqhandler(void); -void WEAK gint0_irqhandler(void); -void WEAK gint1_irqhandler(void); -void WEAK eventrouter_irqhandler(void); -void WEAK c_can1_irqhandler(void); -void WEAK atimer_irqhandler(void); -void WEAK rtc_irqhandler(void); -void WEAK wwdt_irqhandler(void); -void WEAK c_can0_irqhandler(void); -void WEAK qei_irqhandler(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - /* Cortex-M4 interrupts */ - (void*)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* reserved */ - pend_sv_handler, - sys_tick_handler, - - /* LPC43xx interrupts */ - dac_irqhandler, - m0core_irqhandler, - dma_irqhandler, - 0, /* reserved */ - 0, /* reserved */ - ethernet_irqhandler, - sdio_irqhandler, - lcd_irqhandler, - usb0_irqhandler, - usb1_irqhandler, - sct_irqhandler, - ritimer_irqhandler, - timer0_irqhandler, - timer1_irqhandler, - timer2_irqhandler, - timer3_irqhandler, - mcpwm_irqhandler, - adc0_irqhandler, - i2c0_irqhandler, - i2c1_irqhandler, - spi_irqhandler, - adc1_irqhandler, - ssp0_irqhandler, - ssp1_irqhandler, - usart0_irqhandler, - uart1_irqhandler, - usart2_irqhandler, - usart3_irqhandler, - i2s0_irqhandler, - i2s1_irqhandler, - spifi_irqhandler, - sgpio_irqhandler, - pin_int0_irqhandler, - pin_int1_irqhandler, - pin_int2_irqhandler, - pin_int3_irqhandler, - pin_int4_irqhandler, - pin_int5_irqhandler, - pin_int6_irqhandler, - pin_int7_irqhandler, - gint0_irqhandler, - gint1_irqhandler, - eventrouter_irqhandler, - c_can1_irqhandler, - 0, /* reserved */ - 0, /* reserved */ - atimer_irqhandler, - rtc_irqhandler, - 0, /* reserved */ - wwdt_irqhandler, - 0, /* reserved */ - c_can0_irqhandler, - qei_irqhandler, -}; - -#define MMIO32(addr) (*(volatile unsigned long*)(addr)) #define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) ) -void reset_handler(void) +void WEAK reset_handler(void) { volatile unsigned *src, *dest; - __asm__("MSR msp, %0" : : "r"(&_stack)); - /* Copy the code from ROM to Real RAM (if enabled) */ if( (&_etext_ram-&_text_ram) > 0 ) { @@ -186,79 +50,5 @@ void reset_handler(void) /* Continue Execution in RAM */ } - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); + original_reset_handler(); } - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak dac_irqhandler = null_handler -#pragma weak m0core_irqhandler = null_handler -#pragma weak dma_irqhandler = null_handler -#pragma weak ethernet_irqhandler = null_handler -#pragma weak sdio_irqhandler = null_handler -#pragma weak lcd_irqhandler = null_handler -#pragma weak usb0_irqhandler = null_handler -#pragma weak usb1_irqhandler = null_handler -#pragma weak sct_irqhandler = null_handler -#pragma weak ritimer_irqhandler = null_handler -#pragma weak timer0_irqhandler = null_handler -#pragma weak timer1_irqhandler = null_handler -#pragma weak timer2_irqhandler = null_handler -#pragma weak timer3_irqhandler = null_handler -#pragma weak mcpwm_irqhandler = null_handler -#pragma weak adc0_irqhandler = null_handler -#pragma weak i2c0_irqhandler = null_handler -#pragma weak i2c1_irqhandler = null_handler -#pragma weak spi_irqhandler = null_handler -#pragma weak adc1_irqhandler = null_handler -#pragma weak ssp0_irqhandler = null_handler -#pragma weak ssp1_irqhandler = null_handler -#pragma weak usart0_irqhandler = null_handler -#pragma weak uart1_irqhandler = null_handler -#pragma weak usart2_irqhandler = null_handler -#pragma weak usart3_irqhandler = null_handler -#pragma weak i2s0_irqhandler = null_handler -#pragma weak i2s1_irqhandler = null_handler -#pragma weak spifi_irqhandler = null_handler -#pragma weak sgpio_irqhandler = null_handler -#pragma weak pin_int0_irqhandler = null_handler -#pragma weak pin_int1_irqhandler = null_handler -#pragma weak pin_int2_irqhandler = null_handler -#pragma weak pin_int3_irqhandler = null_handler -#pragma weak pin_int4_irqhandler = null_handler -#pragma weak pin_int5_irqhandler = null_handler -#pragma weak pin_int6_irqhandler = null_handler -#pragma weak pin_int7_irqhandler = null_handler -#pragma weak gint0_irqhandler = null_handler -#pragma weak gint1_irqhandler = null_handler -#pragma weak eventrouter_irqhandler = null_handler -#pragma weak c_can1_irqhandler = null_handler -#pragma weak atimer_irqhandler = null_handler -#pragma weak rtc_irqhandler = null_handler -#pragma weak wwdt_irqhandler = null_handler -#pragma weak c_can0_irqhandler = null_handler -#pragma weak qei_irqhandler = null_handler diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c index f496ae4..795773b 100644 --- a/lib/stm32/f1/vector.c +++ b/lib/stm32/f1/vector.c @@ -1,296 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamper_isr(void); -void WEAK rtc_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_channel1_isr(void); -void WEAK dma1_channel2_isr(void); -void WEAK dma1_channel3_isr(void); -void WEAK dma1_channel4_isr(void); -void WEAK dma1_channel5_isr(void); -void WEAK dma1_channel6_isr(void); -void WEAK dma1_channel7_isr(void); -void WEAK adc1_2_isr(void); -void WEAK usb_hp_can_tx_isr(void); -void WEAK usb_lp_can_rx0_isr(void); -void WEAK can_rx1_isr(void); -void WEAK can_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_isr(void); -void WEAK tim1_up_isr(void); -void WEAK tim1_trg_com_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_wakeup_isr(void); -void WEAK tim8_brk_isr(void); -void WEAK tim8_up_isr(void); -void WEAK tim8_trg_com_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK adc3_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_channel1_isr(void); -void WEAK dma2_channel2_isr(void); -void WEAK dma2_channel3_isr(void); -void WEAK dma2_channel4_5_isr(void); -void WEAK dma2_channel5_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); - - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void*)&_stack, /* Addr: 0x0000_0000 */ - reset_handler, /* Addr: 0x0000_0004 */ - nmi_handler, /* Addr: 0x0000_0008 */ - hard_fault_handler, /* Addr: 0x0000_000C */ - mem_manage_handler, /* Addr: 0x0000_0010 */ - bus_fault_handler, /* Addr: 0x0000_0014 */ - usage_fault_handler, /* Addr: 0x0000_0018 */ - 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ - sv_call_handler, /* Addr: 0x0000_002C */ - debug_monitor_handler, /* Addr: 0x0000_0030*/ - 0, /* Reserved Addr: 0x0000_00034 */ - pend_sv_handler, /* Addr: 0x0000_0038 */ - sys_tick_handler, /* Addr: 0x0000_003C */ - wwdg_isr, /* Addr: 0x0000_0040 */ - pvd_isr, /* Addr: 0x0000_0044 */ - tamper_isr, /* Addr: 0x0000_0048 */ - rtc_isr, /* Addr: 0x0000_004C */ - flash_isr, /* Addr: 0x0000_0050 */ - rcc_isr, /* Addr: 0x0000_0054 */ - exti0_isr, /* Addr: 0x0000_0058 */ - exti1_isr, /* Addr: 0x0000_005C */ - exti2_isr, /* Addr: 0x0000_0060 */ - exti3_isr, /* Addr: 0x0000_0064 */ - exti4_isr, /* Addr: 0x0000_0068 */ - dma1_channel1_isr, /* Addr: 0x0000_006C */ - dma1_channel2_isr, /* Addr: 0x0000_0070 */ - dma1_channel3_isr, /* Addr: 0x0000_0074 */ - dma1_channel4_isr, /* Addr: 0x0000_0078 */ - dma1_channel5_isr, /* Addr: 0x0000_007C */ - dma1_channel6_isr, /* Addr: 0x0000_0080 */ - dma1_channel7_isr, /* Addr: 0x0000_0084 */ - adc1_2_isr, /* Addr: 0x0000_0088 */ - usb_hp_can_tx_isr, /* Addr: 0x0000_008C */ - usb_lp_can_rx0_isr, /* Addr: 0x0000_0090 */ - can_rx1_isr, /* Addr: 0x0000_0094 */ - can_sce_isr, /* Addr: 0x0000_0098 */ - exti9_5_isr, /* Addr: 0x0000_009C */ - tim1_brk_isr, /* Addr: 0x0000_00A0 */ - tim1_up_isr, /* Addr: 0x0000_00A4 */ - tim1_trg_com_isr, /* Addr: 0x0000_00A8 */ - tim1_cc_isr, /* Addr: 0x0000_00AC */ - tim2_isr, /* Addr: 0x0000_00B0 */ - tim3_isr, /* Addr: 0x0000_00B4 */ - tim4_isr, /* Addr: 0x0000_00B8 */ - i2c1_ev_isr, /* Addr: 0x0000_00BC */ - i2c1_er_isr, /* Addr: 0x0000_00C0 */ - i2c2_ev_isr, /* Addr: 0x0000_00C4 */ - i2c2_er_isr, /* Addr: 0x0000_00C8 */ - spi1_isr, /* Addr: 0x0000_00CC */ - spi2_isr, /* Addr: 0x0000_00D0 */ - usart1_isr, /* Addr: 0x0000_00D4 */ - usart2_isr, /* Addr: 0x0000_00D8 */ - usart3_isr, /* Addr: 0x0000_00DC */ - exti15_10_isr, /* Addr: 0x0000_00E0 */ - rtc_alarm_isr, /* Addr: 0x0000_00E4 */ - usb_wakeup_isr, /* Addr: 0x0000_00E8 */ - tim8_brk_isr, /* Addr: 0x0000_00EC */ - tim8_up_isr, /* Addr: 0x0000_00F0 */ - tim8_trg_com_isr, /* Addr: 0x0000_00F4 */ - tim8_cc_isr, /* Addr: 0x0000_00F8 */ - adc3_isr, /* Addr: 0x0000_00FC */ - fsmc_isr, /* Addr: 0x0000_0100 */ - sdio_isr, /* Addr: 0x0000_0104 */ - tim5_isr, /* Addr: 0x0000_0108 */ - spi3_isr, /* Addr: 0x0000_010C */ - uart4_isr, /* Addr: 0x0000_0110 */ - uart5_isr, /* Addr: 0x0000_0114 */ - tim6_isr, /* Addr: 0x0000_0118 */ - tim7_isr, /* Addr: 0x0000_011C */ - dma2_channel1_isr, /* Addr: 0x0000_0120 */ - dma2_channel2_isr, /* Addr: 0x0000_0124 */ - dma2_channel3_isr, /* Addr: 0x0000_0128 */ - dma2_channel4_5_isr, /* Addr: 0x0000_012C */ - dma2_channel5_isr, /* Addr: 0x0000_0130 */ - eth_isr, /* Addr: 0x0000_0134 */ - eth_wkup_isr, /* Addr: 0x0000_0138 */ - can2_tx_isr, /* Addr: 0x0000_013C */ - can2_rx0_isr, /* Addr: 0x0000_0140 */ - can2_rx1_isr, /* Addr: 0x0000_0144 */ - can2_sce_isr, /* Addr: 0x0000_0148 */ - otg_fs_isr, /* Addr: 0x0000_014C */ -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamper_isr = null_handler -#pragma weak rtc_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_channel1_isr = null_handler -#pragma weak dma1_channel2_isr = null_handler -#pragma weak dma1_channel3_isr = null_handler -#pragma weak dma1_channel4_isr = null_handler -#pragma weak dma1_channel5_isr = null_handler -#pragma weak dma1_channel6_isr = null_handler -#pragma weak dma1_channel7_isr = null_handler -#pragma weak adc1_2_isr = null_handler -#pragma weak usb_hp_can_tx_isr = null_handler -#pragma weak usb_lp_can_rx0_isr = null_handler -#pragma weak can_rx1_isr = null_handler -#pragma weak can_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_isr = null_handler -#pragma weak tim1_up_isr = null_handler -#pragma weak tim1_trg_com_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_wakeup_isr = null_handler -#pragma weak tim8_brk_isr = null_handler -#pragma weak tim8_up_isr = null_handler -#pragma weak tim8_trg_com_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak adc3_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_channel1_isr = null_handler -#pragma weak dma2_channel2_isr = null_handler -#pragma weak dma2_channel3_isr = null_handler -#pragma weak dma2_channel4_5_isr = null_handler -#pragma weak dma2_channel5_isr -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler +#include +#include "../../cm3/vector.c" diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c index 3429bfb..24d1185 100644 --- a/lib/stm32/f2/vector.c +++ b/lib/stm32/f2/vector.c @@ -1,336 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK reset_handler(void); -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - wwdg_isr, - pvd_isr, - tamp_stamp_isr, - rtc_wkup_isr, - flash_isr, - rcc_isr, - exti0_isr, - exti1_isr, - exti2_isr, - exti3_isr, - exti4_isr, - dma1_stream0_isr, - dma1_stream1_isr, - dma1_stream2_isr, - dma1_stream3_isr, - dma1_stream4_isr, - dma1_stream5_isr, - dma1_stream6_isr, - adc_isr, - can1_tx_isr, - can1_rx0_isr, - can1_rx1_isr, - can1_sce_isr, - exti9_5_isr, - tim1_brk_tim9_isr, - tim1_up_tim10_isr, - tim1_trg_com_tim11_isr, - tim1_cc_isr, - tim2_isr, - tim3_isr, - tim4_isr, - i2c1_ev_isr, - i2c1_er_isr, - i2c2_ev_isr, - i2c2_er_isr, - spi1_isr, - spi2_isr, - usart1_isr, - usart2_isr, - usart3_isr, - exti15_10_isr, - rtc_alarm_isr, - usb_fs_wkup_isr, - tim8_brk_tim12_isr, - tim8_up_tim13_isr, - tim8_trg_com_tim14_isr, - tim8_cc_isr, - dma1_stream7_isr, - fsmc_isr, - sdio_isr, - tim5_isr, - spi3_isr, - uart4_isr, - uart5_isr, - tim6_dac_isr, - tim7_isr, - dma2_stream0_isr, - dma2_stream1_isr, - dma2_stream2_isr, - dma2_stream3_isr, - dma2_stream4_isr, - eth_isr, - eth_wkup_isr, - can2_tx_isr, - can2_rx0_isr, - can2_rx1_isr, - can2_sce_isr, - otg_fs_isr, - dma2_stream5_isr, - dma2_stream6_isr, - dma2_stream7_isr, - usart6_isr, - i2c3_ev_isr, - i2c3_er_isr, - otg_hs_ep1_out_isr, - otg_hs_ep1_in_isr, - otg_hs_wkup_isr, - otg_hs_isr, - dcmi_isr, - cryp_isr, - hash_rng_isr, -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler +#include +#include "../../cm3/vector.c" diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c index 3429bfb..8d158a6 100644 --- a/lib/stm32/f4/vector.c +++ b/lib/stm32/f4/vector.c @@ -1,336 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK reset_handler(void); -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - wwdg_isr, - pvd_isr, - tamp_stamp_isr, - rtc_wkup_isr, - flash_isr, - rcc_isr, - exti0_isr, - exti1_isr, - exti2_isr, - exti3_isr, - exti4_isr, - dma1_stream0_isr, - dma1_stream1_isr, - dma1_stream2_isr, - dma1_stream3_isr, - dma1_stream4_isr, - dma1_stream5_isr, - dma1_stream6_isr, - adc_isr, - can1_tx_isr, - can1_rx0_isr, - can1_rx1_isr, - can1_sce_isr, - exti9_5_isr, - tim1_brk_tim9_isr, - tim1_up_tim10_isr, - tim1_trg_com_tim11_isr, - tim1_cc_isr, - tim2_isr, - tim3_isr, - tim4_isr, - i2c1_ev_isr, - i2c1_er_isr, - i2c2_ev_isr, - i2c2_er_isr, - spi1_isr, - spi2_isr, - usart1_isr, - usart2_isr, - usart3_isr, - exti15_10_isr, - rtc_alarm_isr, - usb_fs_wkup_isr, - tim8_brk_tim12_isr, - tim8_up_tim13_isr, - tim8_trg_com_tim14_isr, - tim8_cc_isr, - dma1_stream7_isr, - fsmc_isr, - sdio_isr, - tim5_isr, - spi3_isr, - uart4_isr, - uart5_isr, - tim6_dac_isr, - tim7_isr, - dma2_stream0_isr, - dma2_stream1_isr, - dma2_stream2_isr, - dma2_stream3_isr, - dma2_stream4_isr, - eth_isr, - eth_wkup_isr, - can2_tx_isr, - can2_rx0_isr, - can2_rx1_isr, - can2_sce_isr, - otg_fs_isr, - dma2_stream5_isr, - dma2_stream6_isr, - dma2_stream7_isr, - usart6_isr, - i2c3_ev_isr, - i2c3_er_isr, - otg_hs_ep1_out_isr, - otg_hs_ep1_in_isr, - otg_hs_wkup_isr, - otg_hs_isr, - dcmi_isr, - cryp_isr, - hash_rng_isr, -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler +#include +#include "../../cm3/vector.c" -- cgit v1.2.3 From 837de3ff9771ea03b5b54dda8ba7f77d404bdcdf Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 10:27:51 +0200 Subject: nvic.h factored out (incomplete) --- include/libopencm3/cm3/nvic.h | 123 +++++++++++++++++++++++++++++++++++++ include/libopencm3/lpc43xx/nvic.h | 85 -------------------------- include/libopencm3/stm32/nvic.h | 124 -------------------------------------- 3 files changed, 123 insertions(+), 209 deletions(-) create mode 100644 include/libopencm3/cm3/nvic.h (limited to 'include') diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h new file mode 100644 index 0000000..3a3aa2f --- /dev/null +++ b/include/libopencm3/cm3/nvic.h @@ -0,0 +1,123 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_nvic_defines NVIC Defines + +@brief libopencm3 Cortex Nested Vectored Interrupt Controller + +@ingroup CM3_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/**@{*/ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 and M4 System Interrupts */ +/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts +@ingroup CM3_nvic_defines + +IRQ numbers -3 and -6 to -9 are reserved +@{*/ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 +/**@}*/ + +/* Note: User interrupts are family specific and are defined in a family + * specific header file in the corresponding subfolder. + */ + +/* --- NVIC functions ------------------------------------------------------ */ + +BEGIN_DECLS + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u16 irqn); + +END_DECLS + +#endif diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index cdbf070..597e21a 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -1,70 +1,3 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_NVIC_H -#define LPC43XX_NVIC_H - -#include -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M4 System Interrupts */ @@ -131,21 +64,3 @@ /* LPC43xx M0 specific user interrupts */ //TODO - -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h index 694fab8..b8c22a2 100644 --- a/include/libopencm3/stm32/nvic.h +++ b/include/libopencm3/stm32/nvic.h @@ -1,108 +1,3 @@ -/** @defgroup STM32F_nvic_defines NVIC Defines - -@brief libopencm3 STM32F Nested Vectored Interrupt Controller - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -/** @defgroup nvic_sysint Cortex M3 System Interrupts -@ingroup STM32F_nvic_defines - -IRQ numbers -3 and -6 to -9 are reserved -@{*/ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 -/**@}*/ - - -/* Note: User interrupts are family specific and are defined in a family - * specific header file in the corresponding subfolder. - */ - #if defined(STM32F1) # include #elif defined(STM32F2) @@ -114,22 +9,3 @@ IRQ numbers -3 and -6 to -9 are reserved #endif -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u16 irqn); - -END_DECLS - -#endif -/**@}*/ - -- cgit v1.2.3 From a7f5f9f576977f97988b739fd98ff7f164edf156 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 12:26:41 +0200 Subject: merge irq and nvic code using a script --- include/libopencm3/efm32/tinygecko/Makefile | 2 + include/libopencm3/efm32/tinygecko/irq.h | 130 -------------------------- include/libopencm3/efm32/tinygecko/irq.yaml | 28 ++++++ include/libopencm3/efm32/tinygecko/irq2nvic_h | 92 ++++++++++++++++++ 4 files changed, 122 insertions(+), 130 deletions(-) create mode 100644 include/libopencm3/efm32/tinygecko/Makefile delete mode 100644 include/libopencm3/efm32/tinygecko/irq.h create mode 100644 include/libopencm3/efm32/tinygecko/irq.yaml create mode 100755 include/libopencm3/efm32/tinygecko/irq2nvic_h (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/Makefile b/include/libopencm3/efm32/tinygecko/Makefile new file mode 100644 index 0000000..4ac5347 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/Makefile @@ -0,0 +1,2 @@ +nvic.h: irq.yaml + ./irq2nvic_h diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h deleted file mode 100644 index f5263ae..0000000 --- a/include/libopencm3/efm32/tinygecko/irq.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Definitions of interrupt names on EFM32 Tiny Gecko systems - * - * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H -#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H - -#define IRQ_DMA 0 -#define IRQ_GPIO_EVEN 1 -#define IRQ_TIMER0 2 -#define IRQ_USART0_RX 3 -#define IRQ_USART0_TX 4 -#define IRQ_ACMP01 5 -#define IRQ_ADC0 6 -#define IRQ_DAC0 7 -#define IRQ_I2C0 8 -#define IRQ_GPIO_ODD 9 -#define IRQ_TIMER1 10 -#define IRQ_USART1_RX 11 -#define IRQ_USART1_TX 12 -#define IRQ_LESENSE 13 -#define IRQ_LEUART0 14 -#define IRQ_LETIMER0 15 -#define IRQ_PCNT0 16 -#define IRQ_RTC 17 -#define IRQ_CMU 18 -#define IRQ_VCMP 19 -#define IRQ_LCD 20 -#define IRQ_MSC 21 -#define IRQ_AES 22 -#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ - -#define WEAK __attribute__ ((weak)) - -void WEAK dma_isr(void); -void WEAK gpio_even_isr(void); -void WEAK timer0_isr(void); -void WEAK usart0_rx_isr(void); -void WEAK usart0_tx_isr(void); -void WEAK acmp01_isr(void); -void WEAK adc0_isr(void); -void WEAK dac0_isr(void); -void WEAK i2c0_isr(void); -void WEAK gpio_odd_isr(void); -void WEAK timer1_isr(void); -void WEAK usart1_rx_isr(void); -void WEAK usart1_tx_isr(void); -void WEAK lesense_isr(void); -void WEAK leuart0_isr(void); -void WEAK letimer0_isr(void); -void WEAK pcnt0_isr(void); -void WEAK rtc_isr(void); -void WEAK cmu_isr(void); -void WEAK vcmp_isr(void); -void WEAK lcd_isr(void); -void WEAK msc_isr(void); -void WEAK aes_isr(void); - -#pragma weak dma_isr = blocking_handler -#pragma weak gpio_even_isr = blocking_handler -#pragma weak timer0_isr = blocking_handler -#pragma weak usart0_rx_isr = blocking_handler -#pragma weak usart0_tx_isr = blocking_handler -#pragma weak acmp01_isr = blocking_handler -#pragma weak adc0_isr = blocking_handler -#pragma weak dac0_isr = blocking_handler -#pragma weak i2c0_isr = blocking_handler -#pragma weak gpio_odd_isr = blocking_handler -#pragma weak timer1_isr = blocking_handler -#pragma weak usart1_rx_isr = blocking_handler -#pragma weak usart1_tx_isr = blocking_handler -#pragma weak lesense_isr = blocking_handler -#pragma weak leuart0_isr = blocking_handler -#pragma weak letimer0_isr = blocking_handler -#pragma weak pcnt0_isr = blocking_handler -#pragma weak rtc_isr = blocking_handler -#pragma weak cmu_isr = blocking_handler -#pragma weak vcmp_isr = blocking_handler -#pragma weak lcd_isr = blocking_handler -#pragma weak msc_isr = blocking_handler -#pragma weak aes_isr = blocking_handler - -#define IRQ_HANDLERS \ - [IRQ_DMA] = dma_isr, \ - [IRQ_GPIO_EVEN] = gpio_even_isr, \ - [IRQ_TIMER0] = timer0_isr, \ - [IRQ_USART0_RX] = usart0_rx_isr, \ - [IRQ_USART0_TX] = usart0_tx_isr, \ - [IRQ_ACMP01] = acmp01_isr, \ - [IRQ_ADC0] = adc0_isr, \ - [IRQ_DAC0] = dac0_isr, \ - [IRQ_I2C0] = i2c0_isr, \ - [IRQ_GPIO_ODD] = gpio_odd_isr, \ - [IRQ_TIMER1] = timer1_isr, \ - [IRQ_USART1_RX] = usart1_rx_isr, \ - [IRQ_USART1_TX] = usart1_tx_isr, \ - [IRQ_LESENSE] = lesense_isr, \ - [IRQ_LEUART0] = leuart0_isr, \ - [IRQ_LETIMER0] = letimer0_isr, \ - [IRQ_PCNT0] = pcnt0_isr, \ - [IRQ_RTC] = rtc_isr, \ - [IRQ_CMU] = cmu_isr, \ - [IRQ_VCMP] = vcmp_isr, \ - [IRQ_LCD] = lcd_isr, \ - [IRQ_MSC] = msc_isr, \ - [IRQ_AES] = aes_isr, - -#endif diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/tinygecko/irq.yaml new file mode 100644 index 0000000..16fa69c --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq.yaml @@ -0,0 +1,28 @@ +includeguard: LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +partname_humanreadable: EFM32 Tiny Gecko series +partname_doxygen: EFM32TG +# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. +irqs: + - dma + - gpio_even + - timer0 + - usart0_rx + - usart0_tx + - acmp01 + - adc0 + - dac0 + - i2c0 + - gpio_odd + - timer1 + - usart1_rx + - usart1_tx + - lesense + - leuart0 + - letimer0 + - pcnt0 + - rtc + - cmu + - vcmp + - lcd + - msc + - aes diff --git a/include/libopencm3/efm32/tinygecko/irq2nvic_h b/include/libopencm3/efm32/tinygecko/irq2nvic_h new file mode 100755 index 0000000..a7df16e --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq2nvic_h @@ -0,0 +1,92 @@ +#!/usr/bin/env python + +# This file is part of the libopencm3 project. +# +# Copyright (C) 2012 chrysn +# +# This library is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this library. If not, see . + +import sys +import yaml + +template = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + */ + +#ifndef {includeguard} +#define {includeguard} + +/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} + @ingroup CM3_nvic_defines + + @{{*/ + +{irqdefinitions} + +#define NVIC_IRQ_COUNT {irqcount} + +/**@}}*/ + +#define WEAK __attribute__ ((weak)) + +/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} + @ingroup CM3_nvic_isrprototypes + + @{{*/ + +{isrprototypes} + +/**@}}*/ + +/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} + @ingroup CM3_nvic_isrpragmas + + @{{*/ + +{isrpragmas} + +/**@}}*/ + +/* Initialization template for the interrupt vector table. This definition is + * used by the startup code generator (vector.c) to set the initial values for + * the interrupt handling routines to the chip family specific _isr weak + * symbols. */ + +#define IRQ_HANDLERS \\ + {vectortableinitialization} + +#endif /* {includeguard} */ +''' + +def convert(infile, outfile): + data = yaml.load(infile) + + irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) + irqnames = [v for (k,v) in irq2name] + + data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) + data['irqcount'] = len(irq2name) # FIXME: what if it's a sparse dictionary? + data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) + data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) + data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) + + outfile.write(template.format(**data)) + +def main(): + convert(open('irq.yaml'), open('nvic.h', 'w')) + +if __name__ == "__main__": + main() -- cgit v1.2.3 From f705d1cd6ec77f6610046c3d9a009c263b526f25 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 12:46:30 +0200 Subject: dispatch for chip specific nvic --- include/libopencm3/cm3/nvic.h | 2 ++ include/libopencm3/cm3/vector.h | 5 ++--- include/libopencm3/dispatch/nvic.h | 16 ++++++++++++++++ include/libopencm3/stm32/nvic.h | 11 ----------- 4 files changed, 20 insertions(+), 14 deletions(-) create mode 100644 include/libopencm3/dispatch/nvic.h delete mode 100644 include/libopencm3/stm32/nvic.h (limited to 'include') diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h index 3a3aa2f..3f83285 100644 --- a/include/libopencm3/cm3/nvic.h +++ b/include/libopencm3/cm3/nvic.h @@ -104,6 +104,8 @@ IRQ numbers -3 and -6 to -9 are reserved * specific header file in the corresponding subfolder. */ +#include + /* --- NVIC functions ------------------------------------------------------ */ BEGIN_DECLS diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h index 198992b..f78e9d8 100644 --- a/include/libopencm3/cm3/vector.h +++ b/include/libopencm3/cm3/vector.h @@ -38,8 +38,7 @@ #define LIBOPENCM3_VECTOR_H #include - -// #include "irq.h" /* we'll nede some definitions */ +#include /** Type of an interrupt function. Only used to avoid hard-to-read function * pointers in the efm32_vector_table_t struct. */ @@ -59,7 +58,7 @@ typedef struct { vector_table_entry_t reserved_x0034; vector_table_entry_t pend_sv; vector_table_entry_t systick; - vector_table_entry_t irq[IRQ_COUNT]; + vector_table_entry_t irq[NVIC_IRQ_COUNT]; } vector_table_t; #endif diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h new file mode 100644 index 0000000..322ec29 --- /dev/null +++ b/include/libopencm3/dispatch/nvic.h @@ -0,0 +1,16 @@ +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include + +#elif defined(TINYGECKO) +# include + +#elif defined(LPC43XX) +# include + +#else +# error "no chipset defined." +#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h deleted file mode 100644 index b8c22a2..0000000 --- a/include/libopencm3/stm32/nvic.h +++ /dev/null @@ -1,11 +0,0 @@ -#if defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#else -# error "stm32 family not defined." -#endif - - -- cgit v1.2.3 From a8a6eb39e9dfa25a9934298c6321b912337c0621 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:19:55 +0200 Subject: add irq cound to existing nvic.h files --- include/libopencm3/lpc43xx/nvic.h | 2 ++ include/libopencm3/stm32/f1/nvic_f1.h | 2 ++ include/libopencm3/stm32/f2/nvic_f2.h | 2 ++ include/libopencm3/stm32/f4/nvic_f4.h | 2 ++ 4 files changed, 8 insertions(+) (limited to 'include') diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index 597e21a..0fc5cc6 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -62,5 +62,7 @@ #define NVIC_M4_C_CAN0_IRQ 51 #define NVIC_M4_QEI_IRQ 52 +#define NVIC_IRQ_COUNT 53 + /* LPC43xx M0 specific user interrupts */ //TODO diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h index 5223bb6..1544e4f 100644 --- a/include/libopencm3/stm32/f1/nvic_f1.h +++ b/include/libopencm3/stm32/f1/nvic_f1.h @@ -109,6 +109,8 @@ LGPL License Terms @ref lgpl_license #define NVIC_CAN2_RX1_IRQ 65 #define NVIC_CAN2_SCE_IRQ 66 #define NVIC_OTG_FS_IRQ 67 + +#define NVIC_IRQ_COUNT 68 /**@}*/ #endif diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h index 2bf2997..65a990d 100644 --- a/include/libopencm3/stm32/f2/nvic_f2.h +++ b/include/libopencm3/stm32/f2/nvic_f2.h @@ -109,4 +109,6 @@ #define NVIC_CRYP_IRQ 79 #define NVIC_HASH_RNG_IRQ 80 +#define NVIC_IRQ_COUNT 81 + #endif diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h index 91b6c25..013e3b5 100644 --- a/include/libopencm3/stm32/f4/nvic_f4.h +++ b/include/libopencm3/stm32/f4/nvic_f4.h @@ -109,4 +109,6 @@ #define NVIC_CRYP_IRQ 79 #define NVIC_HASH_RNG_IRQ 80 +#define NVIC_IRQ_COUNT 81 + #endif -- cgit v1.2.3 From 1684ffe18d4f8e54ebcec204b965bd1052ad7885 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:27:33 +0200 Subject: fallback for unknown chips --- include/libopencm3/dispatch/nvic.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 322ec29..a405b5d 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -12,5 +12,9 @@ # include #else -# error "no chipset defined." +# warning"no chipset defined; user interrupts are disabled" + +#define NVIC_IRQ_COUNT 0 +#define IRQ_HANDLERS + #endif -- cgit v1.2.3 From 5ceb377a378203c80580fbe5160000fca998b635 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 16:52:48 +0200 Subject: switch all interrupt lists to yaml format --- include/libopencm3/dispatch/nvic.h | 6 +- include/libopencm3/efm32/tinygecko/irq.yaml | 2 +- include/libopencm3/efm32/tinygecko/irq2nvic_h | 92 ----- include/libopencm3/lm3s/irq.h | 505 -------------------------- include/libopencm3/lm3s/irq.yaml | 120 ++++++ include/libopencm3/lpc17xx/irq.h | 33 -- include/libopencm3/lpc43xx/irq.h | 234 ------------ include/libopencm3/lpc43xx/irq.yaml | 55 +++ include/libopencm3/lpc43xx/nvic.h | 68 ---- include/libopencm3/stm32/f1/irq.h | 306 ---------------- include/libopencm3/stm32/f1/irq.yaml | 72 ++++ include/libopencm3/stm32/f1/nvic_f1.h | 116 ------ include/libopencm3/stm32/f2/irq.h | 359 ------------------ include/libopencm3/stm32/f2/irq.yaml | 85 +++++ include/libopencm3/stm32/f2/nvic_f2.h | 114 ------ include/libopencm3/stm32/f4/irq.h | 359 ------------------ include/libopencm3/stm32/f4/irq.yaml | 85 +++++ include/libopencm3/stm32/f4/nvic_f4.h | 114 ------ scripts/irq2nvic_h | 105 ++++++ 19 files changed, 526 insertions(+), 2304 deletions(-) delete mode 100755 include/libopencm3/efm32/tinygecko/irq2nvic_h delete mode 100644 include/libopencm3/lm3s/irq.h create mode 100644 include/libopencm3/lm3s/irq.yaml delete mode 100644 include/libopencm3/lpc17xx/irq.h delete mode 100644 include/libopencm3/lpc43xx/irq.h create mode 100644 include/libopencm3/lpc43xx/irq.yaml delete mode 100644 include/libopencm3/lpc43xx/nvic.h delete mode 100644 include/libopencm3/stm32/f1/irq.h create mode 100644 include/libopencm3/stm32/f1/irq.yaml delete mode 100644 include/libopencm3/stm32/f1/nvic_f1.h delete mode 100644 include/libopencm3/stm32/f2/irq.h create mode 100644 include/libopencm3/stm32/f2/irq.yaml delete mode 100644 include/libopencm3/stm32/f2/nvic_f2.h delete mode 100644 include/libopencm3/stm32/f4/irq.h create mode 100644 include/libopencm3/stm32/f4/irq.yaml delete mode 100644 include/libopencm3/stm32/f4/nvic_f4.h create mode 100755 scripts/irq2nvic_h (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index a405b5d..67ba544 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -1,9 +1,9 @@ #if defined(STM32F1) -# include +# include #elif defined(STM32F2) -# include +# include #elif defined(STM32F4) -# include +# include #elif defined(TINYGECKO) # include diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/tinygecko/irq.yaml index 16fa69c..da954f6 100644 --- a/include/libopencm3/efm32/tinygecko/irq.yaml +++ b/include/libopencm3/efm32/tinygecko/irq.yaml @@ -1,4 +1,4 @@ -includeguard: LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +includeguard: LIBOPENCM3_EFM32_TINYGECKO_NVIC_H partname_humanreadable: EFM32 Tiny Gecko series partname_doxygen: EFM32TG # The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. diff --git a/include/libopencm3/efm32/tinygecko/irq2nvic_h b/include/libopencm3/efm32/tinygecko/irq2nvic_h deleted file mode 100755 index a7df16e..0000000 --- a/include/libopencm3/efm32/tinygecko/irq2nvic_h +++ /dev/null @@ -1,92 +0,0 @@ -#!/usr/bin/env python - -# This file is part of the libopencm3 project. -# -# Copyright (C) 2012 chrysn -# -# This library is free software: you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this library. If not, see . - -import sys -import yaml - -template = '''\ -/* This file is part of the libopencm3 project. - * - * It was generated by the irq2nvic_h script. - */ - -#ifndef {includeguard} -#define {includeguard} - -/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} - @ingroup CM3_nvic_defines - - @{{*/ - -{irqdefinitions} - -#define NVIC_IRQ_COUNT {irqcount} - -/**@}}*/ - -#define WEAK __attribute__ ((weak)) - -/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} - @ingroup CM3_nvic_isrprototypes - - @{{*/ - -{isrprototypes} - -/**@}}*/ - -/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} - @ingroup CM3_nvic_isrpragmas - - @{{*/ - -{isrpragmas} - -/**@}}*/ - -/* Initialization template for the interrupt vector table. This definition is - * used by the startup code generator (vector.c) to set the initial values for - * the interrupt handling routines to the chip family specific _isr weak - * symbols. */ - -#define IRQ_HANDLERS \\ - {vectortableinitialization} - -#endif /* {includeguard} */ -''' - -def convert(infile, outfile): - data = yaml.load(infile) - - irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) - irqnames = [v for (k,v) in irq2name] - - data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) - data['irqcount'] = len(irq2name) # FIXME: what if it's a sparse dictionary? - data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) - data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) - data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) - - outfile.write(template.format(**data)) - -def main(): - convert(open('irq.yaml'), open('nvic.h', 'w')) - -if __name__ == "__main__": - main() diff --git a/include/libopencm3/lm3s/irq.h b/include/libopencm3/lm3s/irq.h deleted file mode 100644 index 331ee51..0000000 --- a/include/libopencm3/lm3s/irq.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LM3S_IRQ_H -#define LIBOPENCM3_LM3S_IRQ_H - -#define IRQ_GPIOA 0 -#define IRQ_GPIOB 1 -#define IRQ_GPIOC 2 -#define IRQ_GPIOD 3 -#define IRQ_GPIOE 4 -#define IRQ_UART0 5 -#define IRQ_UART1 6 -#define IRQ_SSI0 7 -#define IRQ_I2C0 8 -#define IRQ_PWM0_FAULT 9 -#define IRQ_PWM0_0 10 -#define IRQ_PWM0_1 11 -#define IRQ_PWM0_2 12 -#define IRQ_QEI0 13 -#define IRQ_ADC0SS0 14 -#define IRQ_ADC0SS1 15 -#define IRQ_ADC0SS2 16 -#define IRQ_ADC0SS3 17 -#define IRQ_WATCHDOG 18 -#define IRQ_TIMER0A 19 -#define IRQ_TIMER0B 20 -#define IRQ_TIMER1A 21 -#define IRQ_TIMER1B 22 -#define IRQ_TIMER2A 23 -#define IRQ_TIMER2B 24 -#define IRQ_COMP0 25 -#define IRQ_COMP1 26 -#define IRQ_COMP2 27 -#define IRQ_SYSCTL 28 -#define IRQ_FLASH 29 -#define IRQ_GPIOF 30 -#define IRQ_GPIOG 31 -#define IRQ_GPIOH 32 -#define IRQ_UART2 33 -#define IRQ_SSI1 34 -#define IRQ_TIMER3A 35 -#define IRQ_TIMER3B 36 -#define IRQ_I2C1 37 -#define IRQ_QEI1 38 -#define IRQ_CAN0 39 -#define IRQ_CAN1 40 -#define IRQ_CAN2 41 -#define IRQ_ETH 42 -#define IRQ_HIBERNATE 43 -#define IRQ_USB0 44 -#define IRQ_PWM0_3 45 -#define IRQ_UDMA 46 -#define IRQ_UDMAERR 47 -#define IRQ_ADC1SS0 48 -#define IRQ_ADC1SS1 49 -#define IRQ_ADC1SS2 50 -#define IRQ_ADC1SS3 51 -#define IRQ_I2S0 52 -#define IRQ_EPI0 53 -#define IRQ_GPIOJ 54 -#define IRQ_GPIOK 55 -#define IRQ_GPIOL 56 -#define IRQ_SSI2 57 -#define IRQ_SSI3 58 -#define IRQ_UART3 59 -#define IRQ_UART4 60 -#define IRQ_UART5 61 -#define IRQ_UART6 62 -#define IRQ_UART7 63 -/* undefined: slot 64 */ -/* undefined: slot 65 */ -/* undefined: slot 66 */ -/* undefined: slot 67 */ -#define IRQ_I2C2 68 -#define IRQ_I2C3 69 -#define IRQ_TIMER4A 70 -#define IRQ_TIMER4B 71 -/* undefined: slot 72 */ -/* undefined: slot 73 */ -/* undefined: slot 74 */ -/* undefined: slot 75 */ -/* undefined: slot 76 */ -/* undefined: slot 77 */ -/* undefined: slot 78 */ -/* undefined: slot 79 */ -/* undefined: slot 80 */ -/* undefined: slot 81 */ -/* undefined: slot 82 */ -/* undefined: slot 83 */ -/* undefined: slot 84 */ -/* undefined: slot 85 */ -/* undefined: slot 86 */ -/* undefined: slot 87 */ -/* undefined: slot 88 */ -/* undefined: slot 89 */ -/* undefined: slot 90 */ -/* undefined: slot 91 */ -#define IRQ_TIMER5A 92 -#define IRQ_TIMER5B 93 -#define IRQ_WTIMER0A 94 -#define IRQ_WTIMER0B 95 -#define IRQ_WTIMER1A 96 -#define IRQ_WTIMER1B 97 -#define IRQ_WTIMER2A 98 -#define IRQ_WTIMER2B 99 -#define IRQ_WTIMER3A 100 -#define IRQ_WTIMER3B 101 -#define IRQ_WTIMER4A 102 -#define IRQ_WTIMER4B 103 -#define IRQ_WTIMER5A 104 -#define IRQ_WTIMER5B 105 -#define IRQ_SYSEXC 106 -#define IRQ_PECI0 107 -#define IRQ_LPC0 108 -#define IRQ_I2C4 109 -#define IRQ_I2C5 110 -#define IRQ_GPIOM 111 -#define IRQ_GPION 112 -/* undefined: slot 113 */ -#define IRQ_FAN0 114 -/* undefined: slot 115 */ -#define IRQ_GPIOP0 116 -#define IRQ_GPIOP1 117 -#define IRQ_GPIOP2 118 -#define IRQ_GPIOP3 119 -#define IRQ_GPIOP4 120 -#define IRQ_GPIOP5 121 -#define IRQ_GPIOP6 122 -#define IRQ_GPIOP7 123 -#define IRQ_GPIOQ0 124 -#define IRQ_GPIOQ1 125 -#define IRQ_GPIOQ2 126 -#define IRQ_GPIOQ3 127 -#define IRQ_GPIOQ4 128 -#define IRQ_GPIOQ5 129 -#define IRQ_GPIOQ6 130 -#define IRQ_GPIOQ7 131 -/* undefined: slot 132 */ -/* undefined: slot 133 */ -#define IRQ_PWM1_0 134 -#define IRQ_PWM1_1 135 -#define IRQ_PWM1_2 136 -#define IRQ_PWM1_3 137 -#define IRQ_PWM1_FAULT 138 - -#define IRQ_COUNT 139 - -#define WEAK __attribute__ ((weak)) - -void WEAK gpioa_isr(void); -void WEAK gpiob_isr(void); -void WEAK gpioc_isr(void); -void WEAK gpiod_isr(void); -void WEAK gpioe_isr(void); -void WEAK uart0_isr(void); -void WEAK uart1_isr(void); -void WEAK ssi0_isr(void); -void WEAK i2c0_isr(void); -void WEAK pwm0_fault_isr(void); -void WEAK pwm0_0_isr(void); -void WEAK pwm0_1_isr(void); -void WEAK pwm0_2_isr(void); -void WEAK qei0_isr(void); -void WEAK adc0ss0_isr(void); -void WEAK adc0ss1_isr(void); -void WEAK adc0ss2_isr(void); -void WEAK adc0ss3_isr(void); -void WEAK watchdog_isr(void); -void WEAK timer0a_isr(void); -void WEAK timer0b_isr(void); -void WEAK timer1a_isr(void); -void WEAK timer1b_isr(void); -void WEAK timer2a_isr(void); -void WEAK timer2b_isr(void); -void WEAK comp0_isr(void); -void WEAK comp1_isr(void); -void WEAK comp2_isr(void); -void WEAK sysctl_isr(void); -void WEAK flash_isr(void); -void WEAK gpiof_isr(void); -void WEAK gpiog_isr(void); -void WEAK gpioh_isr(void); -void WEAK uart2_isr(void); -void WEAK ssi1_isr(void); -void WEAK timer3a_isr(void); -void WEAK timer3b_isr(void); -void WEAK i2c1_isr(void); -void WEAK qei1_isr(void); -void WEAK can0_isr(void); -void WEAK can1_isr(void); -void WEAK can2_isr(void); -void WEAK eth_isr(void); -void WEAK hibernate_isr(void); -void WEAK usb0_isr(void); -void WEAK pwm0_3_isr(void); -void WEAK udma_isr(void); -void WEAK udmaerr_isr(void); -void WEAK adc1ss0_isr(void); -void WEAK adc1ss1_isr(void); -void WEAK adc1ss2_isr(void); -void WEAK adc1ss3_isr(void); -void WEAK i2s0_isr(void); -void WEAK epi0_isr(void); -void WEAK gpioj_isr(void); -void WEAK gpiok_isr(void); -void WEAK gpiol_isr(void); -void WEAK ssi2_isr(void); -void WEAK ssi3_isr(void); -void WEAK uart3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK uart6_isr(void); -void WEAK uart7_isr(void); -void WEAK i2c2_isr(void); -void WEAK i2c3_isr(void); -void WEAK timer4a_isr(void); -void WEAK timer4b_isr(void); -void WEAK timer5a_isr(void); -void WEAK timer5b_isr(void); -void WEAK wtimer0a_isr(void); -void WEAK wtimer0b_isr(void); -void WEAK wtimer1a_isr(void); -void WEAK wtimer1b_isr(void); -void WEAK wtimer2a_isr(void); -void WEAK wtimer2b_isr(void); -void WEAK wtimer3a_isr(void); -void WEAK wtimer3b_isr(void); -void WEAK wtimer4a_isr(void); -void WEAK wtimer4b_isr(void); -void WEAK wtimer5a_isr(void); -void WEAK wtimer5b_isr(void); -void WEAK sysexc_isr(void); -void WEAK peci0_isr(void); -void WEAK lpc0_isr(void); -void WEAK i2c4_isr(void); -void WEAK i2c5_isr(void); -void WEAK gpiom_isr(void); -void WEAK gpion_isr(void); -void WEAK fan0_isr(void); -void WEAK gpiop0_isr(void); -void WEAK gpiop1_isr(void); -void WEAK gpiop2_isr(void); -void WEAK gpiop3_isr(void); -void WEAK gpiop4_isr(void); -void WEAK gpiop5_isr(void); -void WEAK gpiop6_isr(void); -void WEAK gpiop7_isr(void); -void WEAK gpioq0_isr(void); -void WEAK gpioq1_isr(void); -void WEAK gpioq2_isr(void); -void WEAK gpioq3_isr(void); -void WEAK gpioq4_isr(void); -void WEAK gpioq5_isr(void); -void WEAK gpioq6_isr(void); -void WEAK gpioq7_isr(void); -void WEAK pwm1_0_isr(void); -void WEAK pwm1_1_isr(void); -void WEAK pwm1_2_isr(void); -void WEAK pwm1_3_isr(void); -void WEAK pwm1_fault_isr(void); - -#pragma weak gpioa_isr = blocking_handler -#pragma weak gpiob_isr = blocking_handler -#pragma weak gpioc_isr = blocking_handler -#pragma weak gpiod_isr = blocking_handler -#pragma weak gpioe_isr = blocking_handler -#pragma weak uart0_isr = blocking_handler -#pragma weak uart1_isr = blocking_handler -#pragma weak ssi0_isr = blocking_handler -#pragma weak i2c0_isr = blocking_handler -#pragma weak pwm0_fault_isr = blocking_handler -#pragma weak pwm0_0_isr = blocking_handler -#pragma weak pwm0_1_isr = blocking_handler -#pragma weak pwm0_2_isr = blocking_handler -#pragma weak qei0_isr = blocking_handler -#pragma weak adc0ss0_isr = blocking_handler -#pragma weak adc0ss1_isr = blocking_handler -#pragma weak adc0ss2_isr = blocking_handler -#pragma weak adc0ss3_isr = blocking_handler -#pragma weak watchdog_isr = blocking_handler -#pragma weak timer0a_isr = blocking_handler -#pragma weak timer0b_isr = blocking_handler -#pragma weak timer1a_isr = blocking_handler -#pragma weak timer1b_isr = blocking_handler -#pragma weak timer2a_isr = blocking_handler -#pragma weak timer2b_isr = blocking_handler -#pragma weak comp0_isr = blocking_handler -#pragma weak comp1_isr = blocking_handler -#pragma weak comp2_isr = blocking_handler -#pragma weak sysctl_isr = blocking_handler -#pragma weak flash_isr = blocking_handler -#pragma weak gpiof_isr = blocking_handler -#pragma weak gpiog_isr = blocking_handler -#pragma weak gpioh_isr = blocking_handler -#pragma weak uart2_isr = blocking_handler -#pragma weak ssi1_isr = blocking_handler -#pragma weak timer3a_isr = blocking_handler -#pragma weak timer3b_isr = blocking_handler -#pragma weak i2c1_isr = blocking_handler -#pragma weak qei1_isr = blocking_handler -#pragma weak can0_isr = blocking_handler -#pragma weak can1_isr = blocking_handler -#pragma weak can2_isr = blocking_handler -#pragma weak eth_isr = blocking_handler -#pragma weak hibernate_isr = blocking_handler -#pragma weak usb0_isr = blocking_handler -#pragma weak pwm0_3_isr = blocking_handler -#pragma weak udma_isr = blocking_handler -#pragma weak udmaerr_isr = blocking_handler -#pragma weak adc1ss0_isr = blocking_handler -#pragma weak adc1ss1_isr = blocking_handler -#pragma weak adc1ss2_isr = blocking_handler -#pragma weak adc1ss3_isr = blocking_handler -#pragma weak i2s0_isr = blocking_handler -#pragma weak epi0_isr = blocking_handler -#pragma weak gpioj_isr = blocking_handler -#pragma weak gpiok_isr = blocking_handler -#pragma weak gpiol_isr = blocking_handler -#pragma weak ssi2_isr = blocking_handler -#pragma weak ssi3_isr = blocking_handler -#pragma weak uart3_isr = blocking_handler -#pragma weak uart4_isr = blocking_handler -#pragma weak uart5_isr = blocking_handler -#pragma weak uart6_isr = blocking_handler -#pragma weak uart7_isr = blocking_handler -#pragma weak i2c2_isr = blocking_handler -#pragma weak i2c3_isr = blocking_handler -#pragma weak timer4a_isr = blocking_handler -#pragma weak timer4b_isr = blocking_handler -#pragma weak timer5a_isr = blocking_handler -#pragma weak timer5b_isr = blocking_handler -#pragma weak wtimer0a_isr = blocking_handler -#pragma weak wtimer0b_isr = blocking_handler -#pragma weak wtimer1a_isr = blocking_handler -#pragma weak wtimer1b_isr = blocking_handler -#pragma weak wtimer2a_isr = blocking_handler -#pragma weak wtimer2b_isr = blocking_handler -#pragma weak wtimer3a_isr = blocking_handler -#pragma weak wtimer3b_isr = blocking_handler -#pragma weak wtimer4a_isr = blocking_handler -#pragma weak wtimer4b_isr = blocking_handler -#pragma weak wtimer5a_isr = blocking_handler -#pragma weak wtimer5b_isr = blocking_handler -#pragma weak sysexc_isr = blocking_handler -#pragma weak peci0_isr = blocking_handler -#pragma weak lpc0_isr = blocking_handler -#pragma weak i2c4_isr = blocking_handler -#pragma weak i2c5_isr = blocking_handler -#pragma weak gpiom_isr = blocking_handler -#pragma weak gpion_isr = blocking_handler -#pragma weak fan0_isr = blocking_handler -#pragma weak gpiop0_isr = blocking_handler -#pragma weak gpiop1_isr = blocking_handler -#pragma weak gpiop2_isr = blocking_handler -#pragma weak gpiop3_isr = blocking_handler -#pragma weak gpiop4_isr = blocking_handler -#pragma weak gpiop5_isr = blocking_handler -#pragma weak gpiop6_isr = blocking_handler -#pragma weak gpiop7_isr = blocking_handler -#pragma weak gpioq0_isr = blocking_handler -#pragma weak gpioq1_isr = blocking_handler -#pragma weak gpioq2_isr = blocking_handler -#pragma weak gpioq3_isr = blocking_handler -#pragma weak gpioq4_isr = blocking_handler -#pragma weak gpioq5_isr = blocking_handler -#pragma weak gpioq6_isr = blocking_handler -#pragma weak gpioq7_isr = blocking_handler -#pragma weak pwm1_0_isr = blocking_handler -#pragma weak pwm1_1_isr = blocking_handler -#pragma weak pwm1_2_isr = blocking_handler -#pragma weak pwm1_3_isr = blocking_handler -#pragma weak pwm1_fault_isr = blocking_handler - -#define IRQ_HANDLERS \ - [IRQ_GPIOA] = gpioa_isr, \ - [IRQ_GPIOB] = gpiob_isr, \ - [IRQ_GPIOC] = gpioc_isr, \ - [IRQ_GPIOD] = gpiod_isr, \ - [IRQ_GPIOE] = gpioe_isr, \ - [IRQ_UART0] = uart0_isr, \ - [IRQ_UART1] = uart1_isr, \ - [IRQ_SSI0] = ssi0_isr, \ - [IRQ_I2C0] = i2c0_isr, \ - [IRQ_PWM0_FAULT] = pwm0_fault_isr, \ - [IRQ_PWM0_0] = pwm0_0_isr, \ - [IRQ_PWM0_1] = pwm0_1_isr, \ - [IRQ_PWM0_2] = pwm0_2_isr, \ - [IRQ_QEI0] = qei0_isr, \ - [IRQ_ADC0SS0] = adc0ss0_isr, \ - [IRQ_ADC0SS1] = adc0ss1_isr, \ - [IRQ_ADC0SS2] = adc0ss2_isr, \ - [IRQ_ADC0SS3] = adc0ss3_isr, \ - [IRQ_WATCHDOG] = watchdog_isr, \ - [IRQ_TIMER0A] = timer0a_isr, \ - [IRQ_TIMER0B] = timer0b_isr, \ - [IRQ_TIMER1A] = timer1a_isr, \ - [IRQ_TIMER1B] = timer1b_isr, \ - [IRQ_TIMER2A] = timer2a_isr, \ - [IRQ_TIMER2B] = timer2b_isr, \ - [IRQ_COMP0] = comp0_isr, \ - [IRQ_COMP1] = comp1_isr, \ - [IRQ_COMP2] = comp2_isr, \ - [IRQ_SYSCTL] = sysctl_isr, \ - [IRQ_FLASH] = flash_isr, \ - [IRQ_GPIOF] = gpiof_isr, \ - [IRQ_GPIOG] = gpiog_isr, \ - [IRQ_GPIOH] = gpioh_isr, \ - [IRQ_UART2] = uart2_isr, \ - [IRQ_SSI1] = ssi1_isr, \ - [IRQ_TIMER3A] = timer3a_isr, \ - [IRQ_TIMER3B] = timer3b_isr, \ - [IRQ_I2C1] = i2c1_isr, \ - [IRQ_QEI1] = qei1_isr, \ - [IRQ_CAN0] = can0_isr, \ - [IRQ_CAN1] = can1_isr, \ - [IRQ_CAN2] = can2_isr, \ - [IRQ_ETH] = eth_isr, \ - [IRQ_HIBERNATE] = hibernate_isr, \ - [IRQ_USB0] = usb0_isr, \ - [IRQ_PWM0_3] = pwm0_3_isr, \ - [IRQ_UDMA] = udma_isr, \ - [IRQ_UDMAERR] = udmaerr_isr, \ - [IRQ_ADC1SS0] = adc1ss0_isr, \ - [IRQ_ADC1SS1] = adc1ss1_isr, \ - [IRQ_ADC1SS2] = adc1ss2_isr, \ - [IRQ_ADC1SS3] = adc1ss3_isr, \ - [IRQ_I2S0] = i2s0_isr, \ - [IRQ_EPI0] = epi0_isr, \ - [IRQ_GPIOJ] = gpioj_isr, \ - [IRQ_GPIOK] = gpiok_isr, \ - [IRQ_GPIOL] = gpiol_isr, \ - [IRQ_SSI2] = ssi2_isr, \ - [IRQ_SSI3] = ssi3_isr, \ - [IRQ_UART3] = uart3_isr, \ - [IRQ_UART4] = uart4_isr, \ - [IRQ_UART5] = uart5_isr, \ - [IRQ_UART6] = uart6_isr, \ - [IRQ_UART7] = uart7_isr, \ - [IRQ_I2C2] = i2c2_isr, \ - [IRQ_I2C3] = i2c3_isr, \ - [IRQ_TIMER4A] = timer4a_isr, \ - [IRQ_TIMER4B] = timer4b_isr, \ - [IRQ_TIMER5A] = timer5a_isr, \ - [IRQ_TIMER5B] = timer5b_isr, \ - [IRQ_WTIMER0A] = wtimer0a_isr, \ - [IRQ_WTIMER0B] = wtimer0b_isr, \ - [IRQ_WTIMER1A] = wtimer1a_isr, \ - [IRQ_WTIMER1B] = wtimer1b_isr, \ - [IRQ_WTIMER2A] = wtimer2a_isr, \ - [IRQ_WTIMER2B] = wtimer2b_isr, \ - [IRQ_WTIMER3A] = wtimer3a_isr, \ - [IRQ_WTIMER3B] = wtimer3b_isr, \ - [IRQ_WTIMER4A] = wtimer4a_isr, \ - [IRQ_WTIMER4B] = wtimer4b_isr, \ - [IRQ_WTIMER5A] = wtimer5a_isr, \ - [IRQ_WTIMER5B] = wtimer5b_isr, \ - [IRQ_SYSEXC] = sysexc_isr, \ - [IRQ_PECI0] = peci0_isr, \ - [IRQ_LPC0] = lpc0_isr, \ - [IRQ_I2C4] = i2c4_isr, \ - [IRQ_I2C5] = i2c5_isr, \ - [IRQ_GPIOM] = gpiom_isr, \ - [IRQ_GPION] = gpion_isr, \ - [IRQ_FAN0] = fan0_isr, \ - [IRQ_GPIOP0] = gpiop0_isr, \ - [IRQ_GPIOP1] = gpiop1_isr, \ - [IRQ_GPIOP2] = gpiop2_isr, \ - [IRQ_GPIOP3] = gpiop3_isr, \ - [IRQ_GPIOP4] = gpiop4_isr, \ - [IRQ_GPIOP5] = gpiop5_isr, \ - [IRQ_GPIOP6] = gpiop6_isr, \ - [IRQ_GPIOP7] = gpiop7_isr, \ - [IRQ_GPIOQ0] = gpioq0_isr, \ - [IRQ_GPIOQ1] = gpioq1_isr, \ - [IRQ_GPIOQ2] = gpioq2_isr, \ - [IRQ_GPIOQ3] = gpioq3_isr, \ - [IRQ_GPIOQ4] = gpioq4_isr, \ - [IRQ_GPIOQ5] = gpioq5_isr, \ - [IRQ_GPIOQ6] = gpioq6_isr, \ - [IRQ_GPIOQ7] = gpioq7_isr, \ - [IRQ_PWM1_0] = pwm1_0_isr, \ - [IRQ_PWM1_1] = pwm1_1_isr, \ - [IRQ_PWM1_2] = pwm1_2_isr, \ - [IRQ_PWM1_3] = pwm1_3_isr, \ - [IRQ_PWM1_FAULT] = pwm1_fault_isr, - -#endif diff --git a/include/libopencm3/lm3s/irq.yaml b/include/libopencm3/lm3s/irq.yaml new file mode 100644 index 0000000..7d5ff3a --- /dev/null +++ b/include/libopencm3/lm3s/irq.yaml @@ -0,0 +1,120 @@ +includeguard: LIBOPENCM3_LM3S_NVIC_H +partname_humanreadable: LM3S series +partname_doxygen: LM3S +irqs: + 0: GPIOA + 1: GPIOB + 2: GPIOC + 3: GPIOD + 4: GPIOE + 5: UART0 + 6: UART1 + 7: SSI0 + 8: I2C0 + 9: PWM0_FAULT + 10: PWM0_0 + 11: PWM0_1 + 12: PWM0_2 + 13: QEI0 + 14: ADC0SS0 + 15: ADC0SS1 + 16: ADC0SS2 + 17: ADC0SS3 + 18: WATCHDOG + 19: TIMER0A + 20: TIMER0B + 21: TIMER1A + 22: TIMER1B + 23: TIMER2A + 24: TIMER2B + 25: COMP0 + 26: COMP1 + 27: COMP2 + 28: SYSCTL + 29: FLASH + 30: GPIOF + 31: GPIOG + 32: GPIOH + 33: UART2 + 34: SSI1 + 35: TIMER3A + 36: TIMER3B + 37: I2C1 + 38: QEI1 + 39: CAN0 + 40: CAN1 + 41: CAN2 + 42: ETH + 43: HIBERNATE + 44: USB0 + 45: PWM0_3 + 46: UDMA + 47: UDMAERR + 48: ADC1SS0 + 49: ADC1SS1 + 50: ADC1SS2 + 51: ADC1SS3 + 52: I2S0 + 53: EPI0 + 54: GPIOJ + 55: GPIOK + 56: GPIOL + 57: SSI2 + 58: SSI3 + 59: UART3 + 60: UART4 + 61: UART5 + 62: UART6 + 63: UART7 +# undefined: slot 64 - 67 + 68: I2C2 + 69: I2C3 + 70: TIMER4A + 71: TIMER4B +# undefined: slot 72 - 91 + 92: TIMER5A + 93: TIMER5B + 94: WTIMER0A + 95: WTIMER0B + 96: WTIMER1A + 97: WTIMER1B + 98: WTIMER2A + 99: WTIMER2B + 100: WTIMER3A + 101: WTIMER3B + 102: WTIMER4A + 103: WTIMER4B + 104: WTIMER5A + 105: WTIMER5B + 106: SYSEXC + 107: PECI0 + 108: LPC0 + 109: I2C4 + 110: I2C5 + 111: GPIOM + 112: GPION +# undefined: slot 113 + 114: FAN0 +# undefined: slot 115 + 116: GPIOP0 + 117: GPIOP1 + 118: GPIOP2 + 119: GPIOP3 + 120: GPIOP4 + 121: GPIOP5 + 122: GPIOP6 + 123: GPIOP7 + 124: GPIOQ0 + 125: GPIOQ1 + 126: GPIOQ2 + 127: GPIOQ3 + 128: GPIOQ4 + 129: GPIOQ5 + 130: GPIOQ6 + 131: GPIOQ7 +# undefined: slot 132 - 133 + 134: PWM1_0 + 135: PWM1_1 + 136: PWM1_2 + 137: PWM1_3 + 138: PWM1_FAULT diff --git a/include/libopencm3/lpc17xx/irq.h b/include/libopencm3/lpc17xx/irq.h deleted file mode 100644 index 9c31267..0000000 --- a/include/libopencm3/lpc17xx/irq.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPC17xx_IRQ_H -#define LIBOPENCM3_LPC17xx_IRQ_H - -/* TODO: Interrupt definitions */ -#define IRQ_COUNT 0 - -/* TODO: Interrupt handler prototypes */ - -/* TODO: Interrupt handler weak aliases */ - -#define IRQ_HANDLERS - -#endif diff --git a/include/libopencm3/lpc43xx/irq.h b/include/libopencm3/lpc43xx/irq.h deleted file mode 100644 index a83a8d7..0000000 --- a/include/libopencm3/lpc43xx/irq.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPC43XX_IRQ_H -#define LIBOPENCM3_LPC43XX_IRQ_H - -#define IRQ_DAC 0 -#define IRQ_M0CORE 1 -#define IRQ_DMA 2 -/* reserved: 3 */ -/* reserved: 4 */ -#define IRQ_ETHERNET 5 -#define IRQ_SDIO 6 -#define IRQ_LCD 7 -#define IRQ_USB0 8 -#define IRQ_USB1 9 -#define IRQ_SCT 10 -#define IRQ_RITIMER 11 -#define IRQ_TIMER0 12 -#define IRQ_TIMER1 13 -#define IRQ_TIMER2 14 -#define IRQ_TIMER3 15 -#define IRQ_MCPWM 16 -#define IRQ_ADC0 17 -#define IRQ_I2C0 18 -#define IRQ_I2C1 19 -#define IRQ_SPI 20 -#define IRQ_ADC1 21 -#define IRQ_SSP0 22 -#define IRQ_SSP1 23 -#define IRQ_USART0 24 -#define IRQ_UART1 25 -#define IRQ_USART2 26 -#define IRQ_USART3 27 -#define IRQ_I2S0 28 -#define IRQ_I2S1 29 -#define IRQ_SPIFI 30 -#define IRQ_SGPIO 31 -#define IRQ_PIN_INT0 32 -#define IRQ_PIN_INT1 33 -#define IRQ_PIN_INT2 34 -#define IRQ_PIN_INT3 35 -#define IRQ_PIN_INT4 36 -#define IRQ_PIN_INT5 37 -#define IRQ_PIN_INT6 38 -#define IRQ_PIN_INT7 39 -#define IRQ_GINT0 40 -#define IRQ_GINT1 41 -#define IRQ_EVENTROUTER 42 -#define IRQ_C_CAN1 43 -/* reserved: 44 */ -/* reserved: 45 */ -#define IRQ_ATIMER 46 -#define IRQ_RTC 47 -/* reserved: 48 */ -#define IRQ_WWDT 49 -/* reserved: 50 */ -#define IRQ_C_CAN0 51 -#define IRQ_QEI 52 - -#define IRQ_COUNT 53 - -#define WEAK __attribute__ ((weak)) - -void WEAK dac_irqhandler(void); -void WEAK m0core_irqhandler(void); -void WEAK dma_irqhandler(void); -void WEAK ethernet_irqhandler(void); -void WEAK sdio_irqhandler(void); -void WEAK lcd_irqhandler(void); -void WEAK usb0_irqhandler(void); -void WEAK usb1_irqhandler(void); -void WEAK sct_irqhandler(void); -void WEAK ritimer_irqhandler(void); -void WEAK timer0_irqhandler(void); -void WEAK timer1_irqhandler(void); -void WEAK timer2_irqhandler(void); -void WEAK timer3_irqhandler(void); -void WEAK mcpwm_irqhandler(void); -void WEAK adc0_irqhandler(void); -void WEAK i2c0_irqhandler(void); -void WEAK i2c1_irqhandler(void); -void WEAK spi_irqhandler(void); -void WEAK adc1_irqhandler(void); -void WEAK ssp0_irqhandler(void); -void WEAK ssp1_irqhandler(void); -void WEAK usart0_irqhandler(void); -void WEAK uart1_irqhandler(void); -void WEAK usart2_irqhandler(void); -void WEAK usart3_irqhandler(void); -void WEAK i2s0_irqhandler(void); -void WEAK i2s1_irqhandler(void); -void WEAK spifi_irqhandler(void); -void WEAK sgpio_irqhandler(void); -void WEAK pin_int0_irqhandler(void); -void WEAK pin_int1_irqhandler(void); -void WEAK pin_int2_irqhandler(void); -void WEAK pin_int3_irqhandler(void); -void WEAK pin_int4_irqhandler(void); -void WEAK pin_int5_irqhandler(void); -void WEAK pin_int6_irqhandler(void); -void WEAK pin_int7_irqhandler(void); -void WEAK gint0_irqhandler(void); -void WEAK gint1_irqhandler(void); -void WEAK eventrouter_irqhandler(void); -void WEAK c_can1_irqhandler(void); -void WEAK atimer_irqhandler(void); -void WEAK rtc_irqhandler(void); -void WEAK wwdt_irqhandler(void); -void WEAK c_can0_irqhandler(void); -void WEAK qei_irqhandler(void); - -#pragma weak dac_irqhandler = null_handler -#pragma weak m0core_irqhandler = null_handler -#pragma weak dma_irqhandler = null_handler -#pragma weak ethernet_irqhandler = null_handler -#pragma weak sdio_irqhandler = null_handler -#pragma weak lcd_irqhandler = null_handler -#pragma weak usb0_irqhandler = null_handler -#pragma weak usb1_irqhandler = null_handler -#pragma weak sct_irqhandler = null_handler -#pragma weak ritimer_irqhandler = null_handler -#pragma weak timer0_irqhandler = null_handler -#pragma weak timer1_irqhandler = null_handler -#pragma weak timer2_irqhandler = null_handler -#pragma weak timer3_irqhandler = null_handler -#pragma weak mcpwm_irqhandler = null_handler -#pragma weak adc0_irqhandler = null_handler -#pragma weak i2c0_irqhandler = null_handler -#pragma weak i2c1_irqhandler = null_handler -#pragma weak spi_irqhandler = null_handler -#pragma weak adc1_irqhandler = null_handler -#pragma weak ssp0_irqhandler = null_handler -#pragma weak ssp1_irqhandler = null_handler -#pragma weak usart0_irqhandler = null_handler -#pragma weak uart1_irqhandler = null_handler -#pragma weak usart2_irqhandler = null_handler -#pragma weak usart3_irqhandler = null_handler -#pragma weak i2s0_irqhandler = null_handler -#pragma weak i2s1_irqhandler = null_handler -#pragma weak spifi_irqhandler = null_handler -#pragma weak sgpio_irqhandler = null_handler -#pragma weak pin_int0_irqhandler = null_handler -#pragma weak pin_int1_irqhandler = null_handler -#pragma weak pin_int2_irqhandler = null_handler -#pragma weak pin_int3_irqhandler = null_handler -#pragma weak pin_int4_irqhandler = null_handler -#pragma weak pin_int5_irqhandler = null_handler -#pragma weak pin_int6_irqhandler = null_handler -#pragma weak pin_int7_irqhandler = null_handler -#pragma weak gint0_irqhandler = null_handler -#pragma weak gint1_irqhandler = null_handler -#pragma weak eventrouter_irqhandler = null_handler -#pragma weak c_can1_irqhandler = null_handler -#pragma weak atimer_irqhandler = null_handler -#pragma weak rtc_irqhandler = null_handler -#pragma weak wwdt_irqhandler = null_handler -#pragma weak c_can0_irqhandler = null_handler -#pragma weak qei_irqhandler = null_handler - -#define IRQ_HANDLERS \ - dac_irqhandler, \ - m0core_irqhandler, \ - dma_irqhandler, \ - 0, /* reserved */ \ - 0, /* reserved */ \ - ethernet_irqhandler, \ - sdio_irqhandler, \ - lcd_irqhandler, \ - usb0_irqhandler, \ - usb1_irqhandler, \ - sct_irqhandler, \ - ritimer_irqhandler, \ - timer0_irqhandler, \ - timer1_irqhandler, \ - timer2_irqhandler, \ - timer3_irqhandler, \ - mcpwm_irqhandler, \ - adc0_irqhandler, \ - i2c0_irqhandler, \ - i2c1_irqhandler, \ - spi_irqhandler, \ - adc1_irqhandler, \ - ssp0_irqhandler, \ - ssp1_irqhandler, \ - usart0_irqhandler, \ - uart1_irqhandler, \ - usart2_irqhandler, \ - usart3_irqhandler, \ - i2s0_irqhandler, \ - i2s1_irqhandler, \ - spifi_irqhandler, \ - sgpio_irqhandler, \ - pin_int0_irqhandler, \ - pin_int1_irqhandler, \ - pin_int2_irqhandler, \ - pin_int3_irqhandler, \ - pin_int4_irqhandler, \ - pin_int5_irqhandler, \ - pin_int6_irqhandler, \ - pin_int7_irqhandler, \ - gint0_irqhandler, \ - gint1_irqhandler, \ - eventrouter_irqhandler, \ - c_can1_irqhandler, \ - 0, /* reserved */ \ - 0, /* reserved */ \ - atimer_irqhandler, \ - rtc_irqhandler, \ - 0, /* reserved */ \ - wwdt_irqhandler, \ - 0, /* reserved */ \ - c_can0_irqhandler, \ - qei_irqhandler, - -#endif diff --git a/include/libopencm3/lpc43xx/irq.yaml b/include/libopencm3/lpc43xx/irq.yaml new file mode 100644 index 0000000..bc9536b --- /dev/null +++ b/include/libopencm3/lpc43xx/irq.yaml @@ -0,0 +1,55 @@ +includeguard: LIBOPENCM3_LPC43xx_NVIC_H +partname_humanreadable: LPC 43xx series +partname_doxygen: LPC43xx +irqs: + 0: dac + 1: m0core + 2: dma +# reserved: 3, 4 + 5: ethernet + 6: sdio + 7: lcd + 8: usb0 + 9: usb1 + 10: sct + 11: ritimer + 12: timer0 + 13: timer1 + 14: timer2 + 15: timer3 + 16: mcpwm + 17: adc0 + 18: i2c0 + 19: i2c1 + 20: spi + 21: adc1 + 22: ssp0 + 23: ssp1 + 24: usart0 + 25: uart1 + 26: usart2 + 27: usart3 + 28: i2s0 + 29: i2s1 + 30: spifi + 31: sgpio + 32: pin_int0 + 33: pin_int1 + 34: pin_int2 + 35: pin_int3 + 36: pin_int4 + 37: pin_int5 + 38: pin_int6 + 39: pin_int7 + 40: gint0 + 41: gint1 + 42: eventrouter + 43: c_can1 +# reserved: 44, 45 + 46: atimer + 47: rtc +# reserved: 48 + 49: wwdt +# reserved: 50 + 51: c_can0 + 52: qei diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h deleted file mode 100644 index 0fc5cc6..0000000 --- a/include/libopencm3/lpc43xx/nvic.h +++ /dev/null @@ -1,68 +0,0 @@ -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M4 System Interrupts */ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 - -/* LPC43xx M4 specific user interrupts */ -#define NVIC_M4_DAC_IRQ 0 -#define NVIC_M4_M0CORE_IRQ 1 -#define NVIC_M4_DMA_IRQ 2 -#define NVIC_M4_ETHERNET_IRQ 5 -#define NVIC_M4_SDIO_IRQ 6 -#define NVIC_M4_LCD_IRQ 7 -#define NVIC_M4_USB0_IRQ 8 -#define NVIC_M4_USB1_IRQ 9 -#define NVIC_M4_SCT_IRQ 10 -#define NVIC_M4_RITIMER_IRQ 11 -#define NVIC_M4_TIMER0_IRQ 12 -#define NVIC_M4_TIMER1_IRQ 13 -#define NVIC_M4_TIMER2_IRQ 14 -#define NVIC_M4_TIMER3_IRQ 15 -#define NVIC_M4_MCPWM_IRQ 16 -#define NVIC_M4_ADC0_IRQ 17 -#define NVIC_M4_I2C0_IRQ 18 -#define NVIC_M4_I2C1_IRQ 19 -#define NVIC_M4_SPI_IRQ 20 -#define NVIC_M4_ADC1_IRQ 21 -#define NVIC_M4_SSP0_IRQ 22 -#define NVIC_M4_SSP1_IRQ 23 -#define NVIC_M4_USART0_IRQ 24 -#define NVIC_M4_UART1_IRQ 25 -#define NVIC_M4_USART2_IRQ 26 -#define NVIC_M4_USART3_IRQ 27 -#define NVIC_M4_I2S0_IRQ 28 -#define NVIC_M4_I2S1_IRQ 29 -#define NVIC_M4_SPIFI_IRQ 30 -#define NVIC_M4_SGPIO_IRQ 31 -#define NVIC_M4_PIN_INT0_IRQ 32 -#define NVIC_M4_PIN_INT1_IRQ 33 -#define NVIC_M4_PIN_INT2_IRQ 34 -#define NVIC_M4_PIN_INT3_IRQ 35 -#define NVIC_M4_PIN_INT4_IRQ 36 -#define NVIC_M4_PIN_INT5_IRQ 37 -#define NVIC_M4_PIN_INT6_IRQ 38 -#define NVIC_M4_PIN_INT7_IRQ 39 -#define NVIC_M4_GINT0_IRQ 40 -#define NVIC_M4_GINT1_IRQ 41 -#define NVIC_M4_EVENTROUTER_IRQ 42 -#define NVIC_M4_C_CAN1_IRQ 43 -#define NVIC_M4_ATIMER_IRQ 46 -#define NVIC_M4_RTC_IRQ 47 -#define NVIC_M4_WWDT_IRQ 49 -#define NVIC_M4_C_CAN0_IRQ 51 -#define NVIC_M4_QEI_IRQ 52 - -#define NVIC_IRQ_COUNT 53 - -/* LPC43xx M0 specific user interrupts */ -//TODO diff --git a/include/libopencm3/stm32/f1/irq.h b/include/libopencm3/stm32/f1/irq.h deleted file mode 100644 index cfa07f1..0000000 --- a/include/libopencm3/stm32/f1/irq.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F1_IRQ_H -#define LIBOPENCM3_STM32_F1_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMPER 2 -#define IRQ_RTC 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_CHANNEL1 11 -#define IRQ_DMA1_CHANNEL2 12 -#define IRQ_DMA1_CHANNEL3 13 -#define IRQ_DMA1_CHANNEL4 14 -#define IRQ_DMA1_CHANNEL5 15 -#define IRQ_DMA1_CHANNEL6 16 -#define IRQ_DMA1_CHANNEL7 17 -#define IRQ_ADC1_2 18 -#define IRQ_USB_HP_CAN_TX 19 -#define IRQ_USB_LP_CAN_RX0 20 -#define IRQ_CAN_RX1 21 -#define IRQ_CAN_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK 24 -#define IRQ_TIM1_UP 25 -#define IRQ_TIM1_TRG_COM 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_WAKEUP 42 -#define IRQ_TIM8_BRK 43 -#define IRQ_TIM8_UP 44 -#define IRQ_TIM8_TRG_COM 45 -#define IRQ_TIM8_CC 46 -#define IRQ_ADC3 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_CHANNEL1 56 -#define IRQ_DMA2_CHANNEL2 57 -#define IRQ_DMA2_CHANNEL3 58 -#define IRQ_DMA2_CHANNEL4_5 59 -#define IRQ_DMA2_CHANNEL5 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 - -/* FIXME: number from list in lib/stm32/f1/vector.c, might miss irqs */ -#define IRQ_COUNT 68 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamper_isr(void); -void WEAK rtc_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_channel1_isr(void); -void WEAK dma1_channel2_isr(void); -void WEAK dma1_channel3_isr(void); -void WEAK dma1_channel4_isr(void); -void WEAK dma1_channel5_isr(void); -void WEAK dma1_channel6_isr(void); -void WEAK dma1_channel7_isr(void); -void WEAK adc1_2_isr(void); -void WEAK usb_hp_can_tx_isr(void); -void WEAK usb_lp_can_rx0_isr(void); -void WEAK can_rx1_isr(void); -void WEAK can_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_isr(void); -void WEAK tim1_up_isr(void); -void WEAK tim1_trg_com_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_wakeup_isr(void); -void WEAK tim8_brk_isr(void); -void WEAK tim8_up_isr(void); -void WEAK tim8_trg_com_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK adc3_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_channel1_isr(void); -void WEAK dma2_channel2_isr(void); -void WEAK dma2_channel3_isr(void); -void WEAK dma2_channel4_5_isr(void); -void WEAK dma2_channel5_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamper_isr = null_handler -#pragma weak rtc_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_channel1_isr = null_handler -#pragma weak dma1_channel2_isr = null_handler -#pragma weak dma1_channel3_isr = null_handler -#pragma weak dma1_channel4_isr = null_handler -#pragma weak dma1_channel5_isr = null_handler -#pragma weak dma1_channel6_isr = null_handler -#pragma weak dma1_channel7_isr = null_handler -#pragma weak adc1_2_isr = null_handler -#pragma weak usb_hp_can_tx_isr = null_handler -#pragma weak usb_lp_can_rx0_isr = null_handler -#pragma weak can_rx1_isr = null_handler -#pragma weak can_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_isr = null_handler -#pragma weak tim1_up_isr = null_handler -#pragma weak tim1_trg_com_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_wakeup_isr = null_handler -#pragma weak tim8_brk_isr = null_handler -#pragma weak tim8_up_isr = null_handler -#pragma weak tim8_trg_com_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak adc3_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_channel1_isr = null_handler -#pragma weak dma2_channel2_isr = null_handler -#pragma weak dma2_channel3_isr = null_handler -#pragma weak dma2_channel4_5_isr = null_handler -#pragma weak dma2_channel5_isr -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamper_isr, \ - rtc_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_channel1_isr, \ - dma1_channel2_isr, \ - dma1_channel3_isr, \ - dma1_channel4_isr, \ - dma1_channel5_isr, \ - dma1_channel6_isr, \ - dma1_channel7_isr, \ - adc1_2_isr, \ - usb_hp_can_tx_isr, \ - usb_lp_can_rx0_isr, \ - can_rx1_isr, \ - can_sce_isr, \ - exti9_5_isr, \ - tim1_brk_isr, \ - tim1_up_isr, \ - tim1_trg_com_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_wakeup_isr, \ - tim8_brk_isr, \ - tim8_up_isr, \ - tim8_trg_com_isr, \ - tim8_cc_isr, \ - adc3_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_isr, \ - tim7_isr, \ - dma2_channel1_isr, \ - dma2_channel2_isr, \ - dma2_channel3_isr, \ - dma2_channel4_5_isr, \ - dma2_channel5_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - -#endif diff --git a/include/libopencm3/stm32/f1/irq.yaml b/include/libopencm3/stm32/f1/irq.yaml new file mode 100644 index 0000000..14cbcc0 --- /dev/null +++ b/include/libopencm3/stm32/f1/irq.yaml @@ -0,0 +1,72 @@ +includeguard: LIBOPENCM3_STM32_F1_NVIC_H +partname_humanreadable: STM32 F1 series +partname_doxygen: STM32F1 +irqs: + - wwdg + - pvd + - tamper + - rtc + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_channel1 + - dma1_channel2 + - dma1_channel3 + - dma1_channel4 + - dma1_channel5 + - dma1_channel6 + - dma1_channel7 + - adc1_2 + - usb_hp_can_tx + - usb_lp_can_rx0 + - can_rx1 + - can_sce + - exti9_5 + - tim1_brk + - tim1_up + - tim1_trg_com + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_wakeup + - tim8_brk + - tim8_up + - tim8_trg_com + - tim8_cc + - adc3 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6 + - tim7 + - dma2_channel1 + - dma2_channel2 + - dma2_channel3 + - dma2_channel4_5 + - dma2_channel5 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h deleted file mode 100644 index 1544e4f..0000000 --- a/include/libopencm3/stm32/f1/nvic_f1.h +++ /dev/null @@ -1,116 +0,0 @@ -/** @brief Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F1_H -#define LIBOPENCM3_NVIC_F1_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F1 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts -@ingroup STM32F_nvic_defines - -@{*/ -#define NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMPER_IRQ 2 -#define NVIC_RTC_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_CHANNEL1_IRQ 11 -#define NVIC_DMA1_CHANNEL2_IRQ 12 -#define NVIC_DMA1_CHANNEL3_IRQ 13 -#define NVIC_DMA1_CHANNEL4_IRQ 14 -#define NVIC_DMA1_CHANNEL5_IRQ 15 -#define NVIC_DMA1_CHANNEL6_IRQ 16 -#define NVIC_DMA1_CHANNEL7_IRQ 17 -#define NVIC_ADC1_2_IRQ 18 -#define NVIC_USB_HP_CAN_TX_IRQ 19 -#define NVIC_USB_LP_CAN_RX0_IRQ 20 -#define NVIC_CAN_RX1_IRQ 21 -#define NVIC_CAN_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_IRQ 24 -#define NVIC_TIM1_UP_IRQ 25 -#define NVIC_TIM1_TRG_COM_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_WAKEUP_IRQ 42 -#define NVIC_TIM8_BRK_IRQ 43 -#define NVIC_TIM8_UP_IRQ 44 -#define NVIC_TIM8_TRG_COM_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_ADC3_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_CHANNEL1_IRQ 56 -#define NVIC_DMA2_CHANNEL2_IRQ 57 -#define NVIC_DMA2_CHANNEL3_IRQ 58 -#define NVIC_DMA2_CHANNEL4_5_IRQ 59 -#define NVIC_DMA2_CHANNEL5_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 - -#define NVIC_IRQ_COUNT 68 -/**@}*/ - -#endif diff --git a/include/libopencm3/stm32/f2/irq.h b/include/libopencm3/stm32/f2/irq.h deleted file mode 100644 index 7aec142..0000000 --- a/include/libopencm3/stm32/f2/irq.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F2_IRQ_H -#define LIBOPENCM3_STM32_F2_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMP_STAMP 2 -#define IRQ_RTC_WKUP 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_STREAM0 11 -#define IRQ_DMA1_STREAM1 12 -#define IRQ_DMA1_STREAM2 13 -#define IRQ_DMA1_STREAM3 14 -#define IRQ_DMA1_STREAM4 15 -#define IRQ_DMA1_STREAM5 16 -#define IRQ_DMA1_STREAM6 17 -#define IRQ_ADC 18 -#define IRQ_CAN1_TX 19 -#define IRQ_CAN1_RX0 20 -#define IRQ_CAN1_RX1 21 -#define IRQ_CAN1_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK_TIM9 24 -#define IRQ_TIM1_UP_TIM10 25 -#define IRQ_TIM1_TRG_COM_TIM11 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_FS_WKUP 42 -#define IRQ_TIM8_BRK_TIM12 43 -#define IRQ_TIM8_UP_TIM13 44 -#define IRQ_TIM8_TRG_COM_TIM14 45 -#define IRQ_TIM8_CC 46 -#define IRQ_DMA1_STREAM7 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6_DAC 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_STREAM0 56 -#define IRQ_DMA2_STREAM1 57 -#define IRQ_DMA2_STREAM2 58 -#define IRQ_DMA2_STREAM3 59 -#define IRQ_DMA2_STREAM4 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 -#define IRQ_DMA2_STREAM5 68 -#define IRQ_DMA2_STREAM6 69 -#define IRQ_DMA2_STREAM7 70 -#define IRQ_USART6 71 -#define IRQ_I2C3_EV 72 -#define IRQ_I2C3_ER 73 -#define IRQ_OTG_HS_EP1_OUT 74 -#define IRQ_OTG_HS_EP1_IN 75 -#define IRQ_OTG_HS_WKUP 76 -#define IRQ_OTG_HS 77 -#define IRQ_DCMI 78 -#define IRQ_CRYP 79 -#define IRQ_HASH_RNG 80 - -/* FIXME: number from list in lib/stm32/f2/vector.c, might miss irqs */ -#define IRQ_COUNT 81 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_stream0_isr, \ - dma1_stream1_isr, \ - dma1_stream2_isr, \ - dma1_stream3_isr, \ - dma1_stream4_isr, \ - dma1_stream5_isr, \ - dma1_stream6_isr, \ - adc_isr, \ - can1_tx_isr, \ - can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim9_isr, \ - tim1_up_tim10_isr, \ - tim1_trg_com_tim11_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_fs_wkup_isr, \ - tim8_brk_tim12_isr, \ - tim8_up_tim13_isr, \ - tim8_trg_com_tim14_isr, \ - tim8_cc_isr, \ - dma1_stream7_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_stream0_isr, \ - dma2_stream1_isr, \ - dma2_stream2_isr, \ - dma2_stream3_isr, \ - dma2_stream4_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - dma2_stream5_isr, \ - dma2_stream6_isr, \ - dma2_stream7_isr, \ - usart6_isr, \ - i2c3_ev_isr, \ - i2c3_er_isr, \ - otg_hs_ep1_out_isr, \ - otg_hs_ep1_in_isr, \ - otg_hs_wkup_isr, \ - otg_hs_isr, \ - dcmi_isr, \ - cryp_isr, \ - hash_rng_isr, - -#endif diff --git a/include/libopencm3/stm32/f2/irq.yaml b/include/libopencm3/stm32/f2/irq.yaml new file mode 100644 index 0000000..c3600b3 --- /dev/null +++ b/include/libopencm3/stm32/f2/irq.yaml @@ -0,0 +1,85 @@ +includeguard: LIBOPENCM3_STM32_F2_NVIC_H +partname_humanreadable: STM32 F2 series +partname_doxygen: STM32F2 +irqs: + - nvic_wwdg + - pvd + - tamp_stamp + - rtc_wkup + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_stream0 + - dma1_stream1 + - dma1_stream2 + - dma1_stream3 + - dma1_stream4 + - dma1_stream5 + - dma1_stream6 + - adc + - can1_tx + - can1_rx0 + - can1_rx1 + - can1_sce + - exti9_5 + - tim1_brk_tim9 + - tim1_up_tim10 + - tim1_trg_com_tim11 + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_fs_wkup + - tim8_brk_tim12 + - tim8_up_tim13 + - tim8_trg_com_tim14 + - tim8_cc + - dma1_stream7 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6_dac + - tim7 + - dma2_stream0 + - dma2_stream1 + - dma2_stream2 + - dma2_stream3 + - dma2_stream4 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs + - dma2_stream5 + - dma2_stream6 + - dma2_stream7 + - usart6 + - i2c3_ev + - i2c3_er + - otg_hs_ep1_out + - otg_hs_ep1_in + - otg_hs_wkup + - otg_hs + - dcmi + - cryp + - hash_rng diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h deleted file mode 100644 index 65a990d..0000000 --- a/include/libopencm3/stm32/f2/nvic_f2.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F2_H -#define LIBOPENCM3_NVIC_F2_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F2 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -#define NVIC_NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMP_STAMP_IRQ 2 -#define NVIC_RTC_WKUP_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_STREAM0_IRQ 11 -#define NVIC_DMA1_STREAM1_IRQ 12 -#define NVIC_DMA1_STREAM2_IRQ 13 -#define NVIC_DMA1_STREAM3_IRQ 14 -#define NVIC_DMA1_STREAM4_IRQ 15 -#define NVIC_DMA1_STREAM5_IRQ 16 -#define NVIC_DMA1_STREAM6_IRQ 17 -#define NVIC_ADC_IRQ 18 -#define NVIC_CAN1_TX_IRQ 19 -#define NVIC_CAN1_RX0_IRQ 20 -#define NVIC_CAN1_RX1_IRQ 21 -#define NVIC_CAN1_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_TIM9_IRQ 24 -#define NVIC_TIM1_UP_TIM10_IRQ 25 -#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_FS_WKUP_IRQ 42 -#define NVIC_TIM8_BRK_TIM12_IRQ 43 -#define NVIC_TIM8_UP_TIM13_IRQ 44 -#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_DMA1_STREAM7_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_DAC_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_STREAM0_IRQ 56 -#define NVIC_DMA2_STREAM1_IRQ 57 -#define NVIC_DMA2_STREAM2_IRQ 58 -#define NVIC_DMA2_STREAM3_IRQ 59 -#define NVIC_DMA2_STREAM4_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 -#define NVIC_DMA2_STREAM5_IRQ 68 -#define NVIC_DMA2_STREAM6_IRQ 69 -#define NVIC_DMA2_STREAM7_IRQ 70 -#define NVIC_USART6_IRQ 71 -#define NVIC_I2C3_EV_IRQ 72 -#define NVIC_I2C3_ER_IRQ 73 -#define NVIC_OTG_HS_EP1_OUT_IRQ 74 -#define NVIC_OTG_HS_EP1_IN_IRQ 75 -#define NVIC_OTG_HS_WKUP_IRQ 76 -#define NVIC_OTG_HS_IRQ 77 -#define NVIC_DCMI_IRQ 78 -#define NVIC_CRYP_IRQ 79 -#define NVIC_HASH_RNG_IRQ 80 - -#define NVIC_IRQ_COUNT 81 - -#endif diff --git a/include/libopencm3/stm32/f4/irq.h b/include/libopencm3/stm32/f4/irq.h deleted file mode 100644 index 4f4f5e5..0000000 --- a/include/libopencm3/stm32/f4/irq.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F4_IRQ_H -#define LIBOPENCM3_STM32_F4_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMP_STAMP 2 -#define IRQ_RTC_WKUP 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_STREAM0 11 -#define IRQ_DMA1_STREAM1 12 -#define IRQ_DMA1_STREAM2 13 -#define IRQ_DMA1_STREAM3 14 -#define IRQ_DMA1_STREAM4 15 -#define IRQ_DMA1_STREAM5 16 -#define IRQ_DMA1_STREAM6 17 -#define IRQ_ADC 18 -#define IRQ_CAN1_TX 19 -#define IRQ_CAN1_RX0 20 -#define IRQ_CAN1_RX1 21 -#define IRQ_CAN1_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK_TIM9 24 -#define IRQ_TIM1_UP_TIM10 25 -#define IRQ_TIM1_TRG_COM_TIM11 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_FS_WKUP 42 -#define IRQ_TIM8_BRK_TIM12 43 -#define IRQ_TIM8_UP_TIM13 44 -#define IRQ_TIM8_TRG_COM_TIM14 45 -#define IRQ_TIM8_CC 46 -#define IRQ_DMA1_STREAM7 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6_DAC 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_STREAM0 56 -#define IRQ_DMA2_STREAM1 57 -#define IRQ_DMA2_STREAM2 58 -#define IRQ_DMA2_STREAM3 59 -#define IRQ_DMA2_STREAM4 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 -#define IRQ_DMA2_STREAM5 68 -#define IRQ_DMA2_STREAM6 69 -#define IRQ_DMA2_STREAM7 70 -#define IRQ_USART6 71 -#define IRQ_I2C3_EV 72 -#define IRQ_I2C3_ER 73 -#define IRQ_OTG_HS_EP1_OUT 74 -#define IRQ_OTG_HS_EP1_IN 75 -#define IRQ_OTG_HS_WKUP 76 -#define IRQ_OTG_HS 77 -#define IRQ_DCMI 78 -#define IRQ_CRYP 79 -#define IRQ_HASH_RNG 80 - -/* FIXME: number from list in lib/stm32/f4/vector.c, might miss irqs */ -#define IRQ_COUNT 81 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_stream0_isr, \ - dma1_stream1_isr, \ - dma1_stream2_isr, \ - dma1_stream3_isr, \ - dma1_stream4_isr, \ - dma1_stream5_isr, \ - dma1_stream6_isr, \ - adc_isr, \ - can1_tx_isr, \ - can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim9_isr, \ - tim1_up_tim10_isr, \ - tim1_trg_com_tim11_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_fs_wkup_isr, \ - tim8_brk_tim12_isr, \ - tim8_up_tim13_isr, \ - tim8_trg_com_tim14_isr, \ - tim8_cc_isr, \ - dma1_stream7_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_stream0_isr, \ - dma2_stream1_isr, \ - dma2_stream2_isr, \ - dma2_stream3_isr, \ - dma2_stream4_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - dma2_stream5_isr, \ - dma2_stream6_isr, \ - dma2_stream7_isr, \ - usart6_isr, \ - i2c3_ev_isr, \ - i2c3_er_isr, \ - otg_hs_ep1_out_isr, \ - otg_hs_ep1_in_isr, \ - otg_hs_wkup_isr, \ - otg_hs_isr, \ - dcmi_isr, \ - cryp_isr, \ - hash_rng_isr, - -#endif diff --git a/include/libopencm3/stm32/f4/irq.yaml b/include/libopencm3/stm32/f4/irq.yaml new file mode 100644 index 0000000..2d4bae9 --- /dev/null +++ b/include/libopencm3/stm32/f4/irq.yaml @@ -0,0 +1,85 @@ +includeguard: LIBOPENCM3_STM32_F4_NVIC_H +partname_humanreadable: STM32 F4 series +partname_doxygen: STM32F4 +irqs: + - nvic_wwdg + - pvd + - tamp_stamp + - rtc_wkup + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_stream0 + - dma1_stream1 + - dma1_stream2 + - dma1_stream3 + - dma1_stream4 + - dma1_stream5 + - dma1_stream6 + - adc + - can1_tx + - can1_rx0 + - can1_rx1 + - can1_sce + - exti9_5 + - tim1_brk_tim9 + - tim1_up_tim10 + - tim1_trg_com_tim11 + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_fs_wkup + - tim8_brk_tim12 + - tim8_up_tim13 + - tim8_trg_com_tim14 + - tim8_cc + - dma1_stream7 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6_dac + - tim7 + - dma2_stream0 + - dma2_stream1 + - dma2_stream2 + - dma2_stream3 + - dma2_stream4 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs + - dma2_stream5 + - dma2_stream6 + - dma2_stream7 + - usart6 + - i2c3_ev + - i2c3_er + - otg_hs_ep1_out + - otg_hs_ep1_in + - otg_hs_wkup + - otg_hs + - dcmi + - cryp + - hash_rng diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h deleted file mode 100644 index 013e3b5..0000000 --- a/include/libopencm3/stm32/f4/nvic_f4.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F4_H -#define LIBOPENCM3_NVIC_F4_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F4 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -#define NVIC_NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMP_STAMP_IRQ 2 -#define NVIC_RTC_WKUP_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_STREAM0_IRQ 11 -#define NVIC_DMA1_STREAM1_IRQ 12 -#define NVIC_DMA1_STREAM2_IRQ 13 -#define NVIC_DMA1_STREAM3_IRQ 14 -#define NVIC_DMA1_STREAM4_IRQ 15 -#define NVIC_DMA1_STREAM5_IRQ 16 -#define NVIC_DMA1_STREAM6_IRQ 17 -#define NVIC_ADC_IRQ 18 -#define NVIC_CAN1_TX_IRQ 19 -#define NVIC_CAN1_RX0_IRQ 20 -#define NVIC_CAN1_RX1_IRQ 21 -#define NVIC_CAN1_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_TIM9_IRQ 24 -#define NVIC_TIM1_UP_TIM10_IRQ 25 -#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_FS_WKUP_IRQ 42 -#define NVIC_TIM8_BRK_TIM12_IRQ 43 -#define NVIC_TIM8_UP_TIM13_IRQ 44 -#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_DMA1_STREAM7_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_DAC_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_STREAM0_IRQ 56 -#define NVIC_DMA2_STREAM1_IRQ 57 -#define NVIC_DMA2_STREAM2_IRQ 58 -#define NVIC_DMA2_STREAM3_IRQ 59 -#define NVIC_DMA2_STREAM4_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 -#define NVIC_DMA2_STREAM5_IRQ 68 -#define NVIC_DMA2_STREAM6_IRQ 69 -#define NVIC_DMA2_STREAM7_IRQ 70 -#define NVIC_USART6_IRQ 71 -#define NVIC_I2C3_EV_IRQ 72 -#define NVIC_I2C3_ER_IRQ 73 -#define NVIC_OTG_HS_EP1_OUT_IRQ 74 -#define NVIC_OTG_HS_EP1_IN_IRQ 75 -#define NVIC_OTG_HS_WKUP_IRQ 76 -#define NVIC_OTG_HS_IRQ 77 -#define NVIC_DCMI_IRQ 78 -#define NVIC_CRYP_IRQ 79 -#define NVIC_HASH_RNG_IRQ 80 - -#define NVIC_IRQ_COUNT 81 - -#endif diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h new file mode 100755 index 0000000..9346e9b --- /dev/null +++ b/scripts/irq2nvic_h @@ -0,0 +1,105 @@ +#!/usr/bin/env python + +# This file is part of the libopencm3 project. +# +# Copyright (C) 2012 chrysn +# +# This library is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this library. If not, see . + +"""Generate an nvic.h header from a small YAML file describing the interrupt +numbers. + +Code generation is chosen here because the resulting C code needs to be very +repetetive (definition of the IRQ numbers, function prototypes, weak fallback +definition and vector table definition), all being very repetitive. No portable +method to achive the same thing with C preprocessor is known to the author. +(Neither is any non-portable method, for that matter.)""" + +import sys +import yaml + +template = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + */ + +#ifndef {includeguard} +#define {includeguard} + +/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} + @ingroup CM3_nvic_defines + + @{{*/ + +{irqdefinitions} + +#define NVIC_IRQ_COUNT {irqcount} + +/**@}}*/ + +#define WEAK __attribute__ ((weak)) + +/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} + @ingroup CM3_nvic_isrprototypes + + @{{*/ + +{isrprototypes} + +/**@}}*/ + +/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} + @ingroup CM3_nvic_isrpragmas + + @{{*/ + +{isrpragmas} + +/**@}}*/ + +/* Initialization template for the interrupt vector table. This definition is + * used by the startup code generator (vector.c) to set the initial values for + * the interrupt handling routines to the chip family specific _isr weak + * symbols. */ + +#define IRQ_HANDLERS \\ + {vectortableinitialization} + +#endif /* {includeguard} */ +''' + +def convert(infile, outfile): + data = yaml.load(infile) + + irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) + irqnames = [v for (k,v) in irq2name] + + if isinstance(data['irqs'], list): + data['irqcount'] = len(irq2name) + else: + data['irqcount'] = max(data['irqs'].keys()) + 1 + + data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) + data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) + data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) + data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) + + outfile.write(template.format(**data)) + +def main(): + convert(open('irq.yaml'), open('nvic.h', 'w')) + +if __name__ == "__main__": + main() -- cgit v1.2.3 From ae832b4ee87f2cf94b29f790bc04d7b570109919 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 17:30:18 +0200 Subject: split irq.yaml output in nvic.h and vector_nvic.h the weak pragmas need to be used in the very compilation unit where their target is defined, requiring another dispatch --- include/libopencm3/dispatch/nvic.h | 1 - lib/cm3/vector.c | 2 ++ scripts/irq2nvic_h | 29 +++++++++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 67ba544..d8e7889 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -15,6 +15,5 @@ # warning"no chipset defined; user interrupts are disabled" #define NVIC_IRQ_COUNT 0 -#define IRQ_HANDLERS #endif diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index 7b660f9..e0c2972 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -22,6 +22,8 @@ /* load optional platform dependent initialization routines */ #include "../dispatch/vector.c" +/* load the weak symbols for IRQ_HANDLERS */ +#include #define WEAK __attribute__ ((weak)) diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index 9346e9b..fc5e571 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -29,7 +29,7 @@ method to achive the same thing with C preprocessor is known to the author. import sys import yaml -template = '''\ +template_nvic_h = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. @@ -38,6 +38,8 @@ template = '''\ #ifndef {includeguard} #define {includeguard} +#include + /** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} @ingroup CM3_nvic_defines @@ -60,6 +62,19 @@ template = '''\ /**@}}*/ +#endif /* {includeguard} */ +''' + +template_vector_nvic_h = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + * + * This part needs to get included in the compilation unit where + * blocking_handler gets defined due to the way #pragma works. + */ + + /** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} @ingroup CM3_nvic_isrpragmas @@ -76,11 +91,9 @@ template = '''\ #define IRQ_HANDLERS \\ {vectortableinitialization} - -#endif /* {includeguard} */ ''' -def convert(infile, outfile): +def convert(infile, outfile_nvic, outfile_vectornvic): data = yaml.load(infile) irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) @@ -96,10 +109,14 @@ def convert(infile, outfile): data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) - outfile.write(template.format(**data)) + outfile_nvic.write(template_nvic_h.format(**data)) + # FIXME: the vector_nvic.h file could just as well be a vector_nvic.c file + # in lib/, but that'd spread this mechanism over the whole library; just + # needs some thingking over + outfile_vectornvic.write(template_vector_nvic_h.format(**data)) def main(): - convert(open('irq.yaml'), open('nvic.h', 'w')) + convert(open('irq.yaml'), open('nvic.h', 'w'), open('vector_nvic.h', 'w')) if __name__ == "__main__": main() -- cgit v1.2.3 From c69916ffb6d515b1dd644830ba27daef4fc75b58 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 17:57:59 +0200 Subject: integrate irq2nvic_h script in buildprocess --- Makefile | 8 +++++++- include/libopencm3/efm32/tinygecko/Makefile | 2 -- lib/cm3/vector.c | 2 +- lib/dispatch/vector_nvic.c | 19 +++++++++++++++++++ scripts/irq2nvic_h | 14 ++++++++------ 5 files changed, 35 insertions(+), 10 deletions(-) delete mode 100644 include/libopencm3/efm32/tinygecko/Makefile create mode 100644 lib/dispatch/vector_nvic.c (limited to 'include') diff --git a/Makefile b/Makefile index 492b618..76c302d 100644 --- a/Makefile +++ b/Makefile @@ -39,7 +39,13 @@ all: build build: lib examples -lib: +generatedheaders: + @printf " UPDATING HEADERS\n" + $(Q)for yamlfile in `find -name 'irq.yaml'`; do \ + ./scripts/irq2nvic_h $$yamlfile ; \ + done + +lib: generatedheaders $(Q)for i in $(addprefix $@/,$(TARGETS)); do \ if [ -d $$i ]; then \ printf " BUILD $$i\n"; \ diff --git a/include/libopencm3/efm32/tinygecko/Makefile b/include/libopencm3/efm32/tinygecko/Makefile deleted file mode 100644 index 4ac5347..0000000 --- a/include/libopencm3/efm32/tinygecko/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -nvic.h: irq.yaml - ./irq2nvic_h diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index e0c2972..a6d2e93 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -23,7 +23,7 @@ /* load optional platform dependent initialization routines */ #include "../dispatch/vector.c" /* load the weak symbols for IRQ_HANDLERS */ -#include +#include "../dispatch/vector_nvic.c" #define WEAK __attribute__ ((weak)) diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c new file mode 100644 index 0000000..fc5fdd2 --- /dev/null +++ b/lib/dispatch/vector_nvic.c @@ -0,0 +1,19 @@ +#if defined(STM32F1) +# include "../stm32/f1/vector_nvic.c" +#elif defined(STM32F2) +# include "../stm32/f2/vector_nvic.c" +#elif defined(STM32F4) +# include "../stm32/f4/vector_nvic.c" + +#elif defined(TINYGECKO) +# include "../efm32/tinygecko/vector_nvic.c" + +#elif defined(LPC43XX) +# include "../lpc43xx/vector_nvic.c" + +#else +# warning"no chipset defined; user interrupts are disabled" + +#define IRQ_HANDLERS + +#endif diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index fc5e571..92d63b8 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -65,7 +65,7 @@ template_nvic_h = '''\ #endif /* {includeguard} */ ''' -template_vector_nvic_h = '''\ +template_vector_nvic_c = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. @@ -110,13 +110,15 @@ def convert(infile, outfile_nvic, outfile_vectornvic): data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) outfile_nvic.write(template_nvic_h.format(**data)) - # FIXME: the vector_nvic.h file could just as well be a vector_nvic.c file - # in lib/, but that'd spread this mechanism over the whole library; just - # needs some thingking over - outfile_vectornvic.write(template_vector_nvic_h.format(**data)) + outfile_vectornvic.write(template_vector_nvic_c.format(**data)) def main(): - convert(open('irq.yaml'), open('nvic.h', 'w'), open('vector_nvic.h', 'w')) + infile = sys.argv[1] + if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.yaml'): + raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml") + nvic_h = infile.replace('irq.yaml', 'nvic.h') + vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c') + convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w')) if __name__ == "__main__": main() -- cgit v1.2.3 From 0e3fdc57d5880ed41269dd3ab3ed33f6e0dc3fd9 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 19:18:25 +0200 Subject: remove files not required in generalizations branch any more --- include/libopencm3/efm32/tinygecko/irq.h | 55 ----------- include/libopencm3/efm32/vector.h | 66 ------------- lib/efm32/tinygecko/vector.c | 159 ------------------------------- 3 files changed, 280 deletions(-) delete mode 100644 include/libopencm3/efm32/tinygecko/irq.h delete mode 100644 include/libopencm3/efm32/vector.h delete mode 100644 lib/efm32/tinygecko/vector.c (limited to 'include') diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h deleted file mode 100644 index 1b0a484..0000000 --- a/include/libopencm3/efm32/tinygecko/irq.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Definitions of interrupt names on EFM32 Tiny Gecko systems - * - * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H -#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H - -#define IRQ_DMA 0 -#define IRQ_GPIO_EVEN 1 -#define IRQ_TIMER0 2 -#define IRQ_USART0_RX 3 -#define IRQ_USART0_TX 4 -#define IRQ_ACMP01 5 -#define IRQ_ADC0 6 -#define IRQ_DAC0 7 -#define IRQ_I2C0 8 -#define IRQ_GPIO_ODD 9 -#define IRQ_TIMER1 10 -#define IRQ_USART1_RX 11 -#define IRQ_USART1_TX 12 -#define IRQ_LESENSE 13 -#define IRQ_LEUART0 14 -#define IRQ_LETIMER0 15 -#define IRQ_PCNT0 16 -#define IRQ_RTC 17 -#define IRQ_CMU 18 -#define IRQ_VCMP 19 -#define IRQ_LCD 20 -#define IRQ_MSC 21 -#define IRQ_AES 22 -#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ - -#endif diff --git a/include/libopencm3/efm32/vector.h b/include/libopencm3/efm32/vector.h deleted file mode 100644 index 2ae55af..0000000 --- a/include/libopencm3/efm32/vector.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Definitions for handling vector tables. - * - * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2. - * - * The structure of the vector table is implemented independently of the system - * vector table starting at memory position 0x0, as it can be relocated to - * other memory locations too. - * - * The exact size of a vector interrupt table depends on the number of - * interrupts IRQ_COUNT, which is defined per family. - */ - -#ifndef LIBOPENCM3_EFM32_VECTOR_H -#define LIBOPENCM3_EFM32_VECTOR_H - -#include - -#ifdef TINYGECKO -# include -#else -# error "efm32 family not defined." -#endif - -/** Type of an interrupt function. Only used to avoid hard-to-read function - * pointers in the efm32_vector_table_t struct. */ -typedef void (*efm32_vector_table_entry_t)(void); - -typedef struct { - unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ - efm32_vector_table_entry_t reset; - efm32_vector_table_entry_t nmi; - efm32_vector_table_entry_t hard_fault; - efm32_vector_table_entry_t memory_manage_fault; - efm32_vector_table_entry_t bus_fault; - efm32_vector_table_entry_t usage_fault; - efm32_vector_table_entry_t reserved_x001c[4]; - efm32_vector_table_entry_t sv_call; - efm32_vector_table_entry_t reserved_debug; - efm32_vector_table_entry_t reserved_x0034; - efm32_vector_table_entry_t pend_sv; - efm32_vector_table_entry_t systick; - efm32_vector_table_entry_t irq[IRQ_COUNT]; -} efm32_vector_table_t; - -#endif diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c deleted file mode 100644 index 81421e7..0000000 --- a/lib/efm32/tinygecko/vector.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski , - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void blocking_handler(void); - -void WEAK reset_handler(void); -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); - -void WEAK dma_isr(void); -void WEAK gpio_even_isr(void); -void WEAK timer0_isr(void); -void WEAK usart0_rx_isr(void); -void WEAK usart0_tx_isr(void); -void WEAK acmp01_isr(void); -void WEAK adc0_isr(void); -void WEAK dac0_isr(void); -void WEAK i2c0_isr(void); -void WEAK gpio_odd_isr(void); -void WEAK timer1_isr(void); -void WEAK usart1_rx_isr(void); -void WEAK usart1_tx_isr(void); -void WEAK lesense_isr(void); -void WEAK leuart0_isr(void); -void WEAK letimer0_isr(void); -void WEAK pcnt0_isr(void); -void WEAK rtc_isr(void); -void WEAK cmu_isr(void); -void WEAK vcmp_isr(void); -void WEAK lcd_isr(void); -void WEAK msc_isr(void); -void WEAK aes_isr(void); - -__attribute__ ((section(".vectors"))) -efm32_vector_table_t vector_table = { - .initial_sp_value = &_stack, - .reset = reset_handler, - .nmi = nmi_handler, - .hard_fault = hard_fault_handler, - .memory_manage_fault = mem_manage_handler, - .bus_fault = bus_fault_handler, - .usage_fault = usage_fault_handler, - .sv_call = sv_call_handler, - .pend_sv = pend_sv_handler, - .systick = sys_tick_handler, - .irq = { - [IRQ_DMA] = dma_isr, - [IRQ_GPIO_EVEN] = gpio_even_isr, - [IRQ_TIMER0] = timer0_isr, - [IRQ_USART0_RX] = usart0_rx_isr, - [IRQ_USART0_TX] = usart0_tx_isr, - [IRQ_ACMP01] = acmp01_isr, - [IRQ_ADC0] = adc0_isr, - [IRQ_DAC0] = dac0_isr, - [IRQ_I2C0] = i2c0_isr, - [IRQ_GPIO_ODD] = gpio_odd_isr, - [IRQ_TIMER1] = timer1_isr, - [IRQ_USART1_RX] = usart1_rx_isr, - [IRQ_USART1_TX] = usart1_tx_isr, - [IRQ_LESENSE] = lesense_isr, - [IRQ_LEUART0] = leuart0_isr, - [IRQ_LETIMER0] = letimer0_isr, - [IRQ_PCNT0] = pcnt0_isr, - [IRQ_RTC] = rtc_isr, - [IRQ_CMU] = cmu_isr, - [IRQ_VCMP] = vcmp_isr, - [IRQ_LCD] = lcd_isr, - [IRQ_MSC] = msc_isr, - [IRQ_AES] = aes_isr, - } -}; - -void WEAK reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -#pragma weak nmi_handler = blocking_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = blocking_handler -#pragma weak debug_monitor_handler = blocking_handler -#pragma weak pend_sv_handler = blocking_handler -#pragma weak sys_tick_handler = blocking_handler - -#pragma weak dma_isr = blocking_handler -#pragma weak gpio_even_isr = blocking_handler -#pragma weak timer0_isr = blocking_handler -#pragma weak usart0_rx_isr = blocking_handler -#pragma weak usart0_tx_isr = blocking_handler -#pragma weak acmp01_isr = blocking_handler -#pragma weak adc0_isr = blocking_handler -#pragma weak dac0_isr = blocking_handler -#pragma weak i2c0_isr = blocking_handler -#pragma weak gpio_odd_isr = blocking_handler -#pragma weak timer1_isr = blocking_handler -#pragma weak usart1_rx_isr = blocking_handler -#pragma weak usart1_tx_isr = blocking_handler -#pragma weak lesense_isr = blocking_handler -#pragma weak leuart0_isr = blocking_handler -#pragma weak letimer0_isr = blocking_handler -#pragma weak pcnt0_isr = blocking_handler -#pragma weak rtc_isr = blocking_handler -#pragma weak cmu_isr = blocking_handler -#pragma weak vcmp_isr = blocking_handler -#pragma weak lcd_isr = blocking_handler -#pragma weak msc_isr = blocking_handler -#pragma weak aes_isr = blocking_handler -- cgit v1.2.3 From e20f1c0d8fb6c75c434b93834a9d67262198d908 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 21:42:12 +0200 Subject: unify scb (system control block) these register definitions are common to all cortex mcus. some of the registers might not be implemented everywhere (especially the floating point registers), but defining them does no harm. this modification does not result in any changes in the example binaries. --- examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c | 2 +- examples/stm32/f1/other/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/other/usb_hid/usbhid.c | 2 +- examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/stm32-h103/usb_hid/usbhid.c | 2 +- examples/stm32/f1/stm32-h103/usb_iap/usbiap.c | 2 +- include/libopencm3/cm3/scb.h | 376 ++++++++++++++++++++++++++ include/libopencm3/stm32/f1/scb.h | 307 --------------------- include/libopencm3/stm32/f2/scb.h | 307 --------------------- include/libopencm3/stm32/f4/scb.h | 376 -------------------------- lib/cm3/scb.c | 35 +++ lib/stm32/f1/scb.c | 35 --- lib/stm32/f2/scb.c | 35 --- lib/stm32/f4/scb.c | 35 --- lib/stm32/f4/vector_chipset.c | 2 +- 16 files changed, 419 insertions(+), 1103 deletions(-) create mode 100644 include/libopencm3/cm3/scb.h delete mode 100644 include/libopencm3/stm32/f1/scb.h delete mode 100644 include/libopencm3/stm32/f2/scb.h delete mode 100644 include/libopencm3/stm32/f4/scb.h create mode 100644 lib/cm3/scb.c delete mode 100644 lib/stm32/f1/scb.c delete mode 100644 lib/stm32/f2/scb.c delete mode 100644 lib/stm32/f4/scb.c (limited to 'include') diff --git a/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c b/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c index 4ffc0a1..d8fcde4 100644 --- a/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c index 8d83896..a0a4d12 100644 --- a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c +++ b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c @@ -32,7 +32,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/other/usb_dfu/usbdfu.c b/examples/stm32/f1/other/usb_dfu/usbdfu.c index 0211a47..84e1b36 100644 --- a/examples/stm32/f1/other/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/other/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/other/usb_hid/usbhid.c b/examples/stm32/f1/other/usb_hid/usbhid.c index dd3c57a..6329f0e 100644 --- a/examples/stm32/f1/other/usb_hid/usbhid.c +++ b/examples/stm32/f1/other/usb_hid/usbhid.c @@ -28,7 +28,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c b/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c index 49f265b..9c0bab9 100644 --- a/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c index 9ed40d1..d0c2aff 100644 --- a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c +++ b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c @@ -28,7 +28,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c b/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c index c5cc8ba..9091f36 100644 --- a/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c +++ b/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/libopencm3/cm3/scb.h b/include/libopencm3/cm3/scb.h new file mode 100644 index 0000000..8e9c757 --- /dev/null +++ b/include/libopencm3/cm3/scb.h @@ -0,0 +1,376 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SCB_H +#define LIBOPENCM3_SCB_H + +#include +#include + +/* --- SCB: Registers ------------------------------------------------------ */ + +/* CPUID: CPUID base register */ +#define SCB_CPUID MMIO32(SCB_BASE + 0x00) + +/* ICSR: Interrupt Control State Register */ +#define SCB_ICSR MMIO32(SCB_BASE + 0x04) + +/* VTOR: Vector Table Offset Register */ +#define SCB_VTOR MMIO32(SCB_BASE + 0x08) + +/* AIRCR: Application Interrupt and Reset Control Register */ +#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) + +/* SCR: System Control Register */ +#define SCB_SCR MMIO32(SCB_BASE + 0x10) + +/* CCR: Configuration Control Register */ +#define SCB_CCR MMIO32(SCB_BASE + 0x14) + +/* SHP: System Handler Priority Registers */ +/* Note: 12 8bit registers */ +#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) +#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) +#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) +#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) + +/* SHCSR: System Handler Control and State Register */ +#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) + +/* CFSR: Configurable Fault Status Registers */ +#define SCB_CFSR MMIO32(SCB_BASE + 0x28) + +/* HFSR: Hard Fault Status Register */ +#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) + +/* DFSR: Debug Fault Status Register */ +#define SCB_DFSR MMIO32(SCB_BASE + 0x30) + +/* MMFAR: Memory Manage Fault Address Register */ +#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) + +/* BFAR: Bus Fault Address Register */ +#define SCB_BFAR MMIO32(SCB_BASE + 0x38) + +/* AFSR: Auxiliary Fault Status Register */ +#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) + +/* ID_PFR0: Processor Feature Register 0 */ +#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) + +/* ID_PFR1: Processor Feature Register 1 */ +#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) + +/* ID_DFR0: Debug Features Register 0 */ +#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) + +/* ID_AFR0: Auxiliary Features Register 0 */ +#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) + +/* ID_MMFR0: Memory Model Feature Register 0 */ +#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) + +/* ID_MMFR1: Memory Model Feature Register 1 */ +#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) + +/* ID_MMFR2: Memory Model Feature Register 2 */ +#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) + +/* ID_MMFR3: Memory Model Feature Register 3 */ +#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) + +/* ID_ISAR0: Instruction Set Attributes Register 0 */ +#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) + +/* ID_ISAR1: Instruction Set Attributes Register 1 */ +#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) + +/* ID_ISAR2: Instruction Set Attributes Register 2 */ +#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) + +/* ID_ISAR3: Instruction Set Attributes Register 3 */ +#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) + +/* ID_ISAR4: Instruction Set Attributes Register 4 */ +#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) + +/* CPACR: Coprocessor Access Control Register */ +#define SCB_CPACR MMIO32(SCB_BASE + 0x88) + +/* FPCCR: Floating-Point Context Control Register */ +#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) + +/* FPCAR: Floating-Point Context Address Register */ +#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) + +/* FPDSCR: Floating-Point Default Status Control Register */ +#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) + +/* MVFR0: Media and Floating-Point Feature Register 0 */ +#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) + +/* MVFR1: Media and Floating-Point Feature Register 1 */ +#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) + +/* --- SCB values ---------------------------------------------------------- */ + +/* --- SCB_CPUID values ---------------------------------------------------- */ + +/* Implementer[31:24]: Implementer code */ +#define SCP_CPUID_IMPLEMENTER_LSB 24 +/* Variant[23:20]: Variant number */ +#define SCP_CPUID_VARIANT_LSB 20 +/* Constant[19:16]: Reads as 0xF */ +#define SCP_CPUID_CONSTANT_LSB 16 +/* PartNo[15:4]: Part number of the processor */ +#define SCP_CPUID_PARTNO_LSB 4 +/* Revision[3:0]: Revision number */ +#define SCP_CPUID_REVISION_LSB 0 + +/* --- SCB_ICSR values ----------------------------------------------------- */ + +/* NMIPENDSET: NMI set-pending bit */ +#define SCB_ICSR_NMIPENDSET (1 << 31) +/* Bits [30:29]: reserved - must be kept cleared */ +/* PENDSVSET: PendSV set-pending bit */ +#define SCB_ICSR_PENDSVSET (1 << 28) +/* PENDSVCLR: PendSV clear-pending bit */ +#define SCB_ICSR_PENDSVCLR (1 << 27) +/* PENDSTSET: SysTick exception set-pending bit */ +#define SCB_ICSR_PENDSTSET (1 << 26) +/* PENDSTCLR: SysTick exception clear-pending bit */ +#define SCB_ICSR_PENDSTCLR (1 << 25) +/* Bit 24: reserved - must be kept cleared */ +/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ +/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ +#define SCB_ICSR_ISRPENDING (1 << 22) +/* VECTPENDING[21:12] Pending vector */ +#define SCB_ICSR_VECTPENDING_LSB 12 +/* RETOBASE: Return to base level */ +#define SCB_ICSR_RETOBASE (1 << 11) +/* Bits [10:9]: reserved - must be kept cleared */ +/* VECTACTIVE[8:0] Active vector */ +#define SCB_ICSR_VECTACTIVE_LSB 0 + +/* --- SCB_VTOR values ----------------------------------------------------- */ + +/* Bits [31:30]: reserved - must be kept cleared */ +/* TBLOFF[29:9]: Vector table base offset field */ +#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ + +/* --- SCB_AIRCR values ---------------------------------------------------- */ + +/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ +#define SCB_AIRCR_VECTKEYSTAT_LSB 16 +#define SCB_AIRCR_VECTKEY 0x05FA0000 +/* ENDIANESS Data endianness bit */ +#define SCB_AIRCR_ENDIANESS (1 << 15) +/* Bits [14:11]: reserved - must be kept cleared */ +/* PRIGROUP[10:8]: Interrupt priority grouping field */ +#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) +#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) +#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) +#define SCB_AIRCR_PRIGROUP_SHIFT 8 +/* Bits [7:3]: reserved - must be kept cleared */ +/* SYSRESETREQ System reset request */ +#define SCB_AIRCR_SYSRESETREQ (1 << 2) +/* VECTCLRACTIVE */ +#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) +/* VECTRESET */ +#define SCB_AIRCR_VECTRESET (1 << 0) + +/* --- SCB_SCR values ------------------------------------------------------ */ + +/* Bits [31:5]: reserved - must be kept cleared */ +/* SEVEONPEND Send Event on Pending bit */ +#define SCB_SCR_SEVEONPEND (1 << 4) +/* Bit 3: reserved - must be kept cleared */ +/* SLEEPDEEP */ +#define SCB_SCR_SLEEPDEEP (1 << 2) +/* SLEEPONEXIT */ +#define SCB_SCR_SLEEPONEXIT (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_CCR values ------------------------------------------------------ */ + +/* Bits [31:10]: reserved - must be kept cleared */ +/* STKALIGN */ +#define SCB_CCR_STKALIGN (1 << 9) +/* BFHFNMIGN */ +#define SCB_CCR_BFHFNMIGN (1 << 8) +/* Bits [7:5]: reserved - must be kept cleared */ +/* DIV_0_TRP */ +#define SCB_CCR_DIV_0_TRP (1 << 4) +/* UNALIGN_TRP */ +#define SCB_CCR_UNALIGN_TRP (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* USERSETMPEND */ +#define SCB_CCR_USERSETMPEND (1 << 1) +/* NONBASETHRDENA */ +#define SCB_CCR_NONBASETHRDENA (1 << 0) + +/* --- SCB_SHPR1 values ---------------------------------------------------- */ + +/* Bits [31:24]: reserved - must be kept cleared */ +/* PRI_6[23:16]: Priority of system handler 6, usage fault */ +#define SCB_SHPR1_PRI_6_LSB 16 +/* PRI_5[15:8]: Priority of system handler 5, bus fault */ +#define SCB_SHPR1_PRI_5_LSB 8 +/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ +#define SCB_SHPR1_PRI_4_LSB 0 + +/* --- SCB_SHPR2 values ---------------------------------------------------- */ + +/* PRI_11[31:24]: Priority of system handler 11, SVCall */ +#define SCB_SHPR2_PRI_11_LSB 24 +/* Bits [23:0]: reserved - must be kept cleared */ + +/* --- SCB_SHPR3 values ---------------------------------------------------- */ + +/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ +#define SCB_SHPR3_PRI_15_LSB 24 +/* PRI_14[23:16]: Priority of system handler 14, PendSV */ +#define SCB_SHPR3_PRI_14_LSB 16 +/* Bits [15:0]: reserved - must be kept cleared */ + +/* --- SCB_SHCSR values ---------------------------------------------------- */ + +/* Bits [31:19]: reserved - must be kept cleared */ +/* USGFAULTENA: Usage fault enable */ +#define SCB_SHCSR_USGFAULTENA (1 << 18) +/* BUSFAULTENA: Bus fault enable */ +#define SCB_SHCSR_BUSFAULTENA (1 << 17) +/* MEMFAULTENA: Memory management fault enable */ +#define SCB_SHCSR_MEMFAULTENA (1 << 16) +/* SVCALLPENDED: SVC call pending */ +#define SCB_SHCSR_SVCALLPENDED (1 << 15) +/* BUSFAULTPENDED: Bus fault exception pending */ +#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) +/* MEMFAULTPENDED: Memory management fault exception pending */ +#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) +/* USGFAULTPENDED: Usage fault exception pending */ +#define SCB_SHCSR_USGFAULTPENDED (1 << 12) +/* SYSTICKACT: SysTick exception active */ +#define SCB_SHCSR_SYSTICKACT (1 << 11) +/* PENDSVACT: PendSV exception active */ +#define SCB_SHCSR_PENDSVACT (1 << 10) +/* Bit 9: reserved - must be kept cleared */ +/* MONITORACT: Debug monitor active */ +#define SCB_SHCSR_MONITORACT (1 << 8) +/* SVCALLACT: SVC call active */ +#define SCB_SHCSR_SVCALLACT (1 << 7) +/* Bits [6:4]: reserved - must be kept cleared */ +/* USGFAULTACT: Usage fault exception active */ +#define SCB_SHCSR_USGFAULTACT (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* BUSFAULTACT: Bus fault exception active */ +#define SCB_SHCSR_BUSFAULTACT (1 << 1) +/* MEMFAULTACT: Memory management fault exception active */ +#define SCB_SHCSR_MEMFAULTACT (1 << 0) + +/* --- SCB_CFSR values ----------------------------------------------------- */ + +/* Bits [31:26]: reserved - must be kept cleared */ +/* DIVBYZERO: Divide by zero usage fault */ +#define SCB_CFSR_DIVBYZERO (1 << 25) +/* UNALIGNED: Unaligned access usage fault */ +#define SCB_CFSR_UNALIGNED (1 << 24) +/* Bits [23:20]: reserved - must be kept cleared */ +/* NOCP: No coprocessor usage fault */ +#define SCB_CFSR_NOCP (1 << 19) +/* INVPC: Invalid PC load usage fault */ +#define SCB_CFSR_INVPC (1 << 18) +/* INVSTATE: Invalid state usage fault */ +#define SCB_CFSR_INVSTATE (1 << 17) +/* UNDEFINSTR: Undefined instruction usage fault */ +#define SCB_CFSR_UNDEFINSTR (1 << 16) +/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ +#define SCB_CFSR_BFARVALID (1 << 15) +/* Bits [14:13]: reserved - must be kept cleared */ +/* STKERR: Bus fault on stacking for exception entry */ +#define SCB_CFSR_STKERR (1 << 12) +/* UNSTKERR: Bus fault on unstacking for a return from exception */ +#define SCB_CFSR_UNSTKERR (1 << 11) +/* IMPRECISERR: Imprecise data bus error */ +#define SCB_CFSR_IMPRECISERR (1 << 10) +/* PRECISERR: Precise data bus error */ +#define SCB_CFSR_PRECISERR (1 << 9) +/* IBUSERR: Instruction bus error */ +#define SCB_CFSR_IBUSERR (1 << 8) +/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ +#define SCB_CFSR_MMARVALID (1 << 7) +/* Bits [6:5]: reserved - must be kept cleared */ +/* MSTKERR: Memory manager fault on stacking for exception entry */ +#define SCB_CFSR_MSTKERR (1 << 4) +/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ +#define SCB_CFSR_MUNSTKERR (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* DACCVIOL: Data access violation flag */ +#define SCB_CFSR_DACCVIOL (1 << 1) +/* IACCVIOL: Instruction access violation flag */ +#define SCB_CFSR_IACCVIOL (1 << 0) + +/* --- SCB_HFSR values ----------------------------------------------------- */ + +/* DEBUG_VT: reserved for debug use */ +#define SCB_HFSR_DEBUG_VT (1 << 31) +/* FORCED: Forced hard fault */ +#define SCB_HFSR_FORCED (1 << 30) +/* Bits [29:2]: reserved - must be kept cleared */ +/* VECTTBL: Vector table hard fault */ +#define SCB_HFSR_VECTTBL (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_MMFAR values ---------------------------------------------------- */ + +/* MMFAR [31:0]: Memory management fault address */ + +/* --- SCB_BFAR values ----------------------------------------------------- */ + +/* BFAR [31:0]: Bus fault address */ + +/* --- SCB_CPACR values ---------------------------------------------------- */ + +/* CPACR CPn: Access privileges values */ +#define SCB_CPACR_NONE 0 /* Access denied */ +#define SCB_CPACR_PRIV 1 /* Privileged access only */ +#define SCB_CPACR_FULL 3 /* Full access */ + +/* CPACR [20:21]: Access privileges for coprocessor 10 */ +#define SCB_CPACR_CP10 (1 << 20) +/* CPACR [22:23]: Access privileges for coprocessor 11 */ +#define SCB_CPACR_CP11 (1 << 22) + +/* --- SCB functions ------------------------------------------------------- */ + +BEGIN_DECLS + +void scb_reset_core(void); +void scb_reset_system(void); +void scb_set_priority_grouping(u32 prigroup); + +/* TODO: */ + +END_DECLS + +#endif diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h deleted file mode 100644 index 181aa7a..0000000 --- a/include/libopencm3/stm32/f1/scb.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h deleted file mode 100644 index 181aa7a..0000000 --- a/include/libopencm3/stm32/f2/scb.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h deleted file mode 100644 index 7187ca9..0000000 --- a/include/libopencm3/stm32/f4/scb.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* ID_PFR0: Processor Feature Register 0 */ -#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) - -/* ID_PFR1: Processor Feature Register 1 */ -#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) - -/* ID_DFR0: Debug Features Register 0 */ -#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) - -/* ID_AFR0: Auxiliary Features Register 0 */ -#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) - -/* ID_MMFR0: Memory Model Feature Register 0 */ -#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) - -/* ID_MMFR1: Memory Model Feature Register 1 */ -#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) - -/* ID_MMFR2: Memory Model Feature Register 2 */ -#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) - -/* ID_MMFR3: Memory Model Feature Register 3 */ -#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) - -/* ID_ISAR0: Instruction Set Attributes Register 0 */ -#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) - -/* ID_ISAR1: Instruction Set Attributes Register 1 */ -#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) - -/* ID_ISAR2: Instruction Set Attributes Register 2 */ -#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) - -/* ID_ISAR3: Instruction Set Attributes Register 3 */ -#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) - -/* ID_ISAR4: Instruction Set Attributes Register 4 */ -#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) - -/* CPACR: Coprocessor Access Control Register */ -#define SCB_CPACR MMIO32(SCB_BASE + 0x88) - -/* FPCCR: Floating-Point Context Control Register */ -#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) - -/* FPCAR: Floating-Point Context Address Register */ -#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) - -/* FPDSCR: Floating-Point Default Status Control Register */ -#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) - -/* MVFR0: Media and Floating-Point Feature Register 0 */ -#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) - -/* MVFR1: Media and Floating-Point Feature Register 1 */ -#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB_CPACR values ---------------------------------------------------- */ - -/* CPACR CPn: Access privileges values */ -#define SCB_CPACR_NONE 0 /* Access denied */ -#define SCB_CPACR_PRIV 1 /* Privileged access only */ -#define SCB_CPACR_FULL 3 /* Full access */ - -/* CPACR [20:21]: Access privileges for coprocessor 10 */ -#define SCB_CPACR_CP10 (1 << 20) -/* CPACR [22:23]: Access privileges for coprocessor 11 */ -#define SCB_CPACR_CP11 (1 << 22) - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c new file mode 100644 index 0000000..904bd7c --- /dev/null +++ b/lib/cm3/scb.c @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void scb_reset_core(void) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; +} + +void scb_reset_system(void) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; +} + +void scb_set_priority_grouping(u32 prigroup) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; +} diff --git a/lib/stm32/f1/scb.c b/lib/stm32/f1/scb.c deleted file mode 100644 index e59134e..0000000 --- a/lib/stm32/f1/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f2/scb.c b/lib/stm32/f2/scb.c deleted file mode 100644 index abb7b44..0000000 --- a/lib/stm32/f2/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f4/scb.c b/lib/stm32/f4/scb.c deleted file mode 100644 index cbf4d53..0000000 --- a/lib/stm32/f4/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f4/vector_chipset.c b/lib/stm32/f4/vector_chipset.c index 5304299..145be05 100644 --- a/lib/stm32/f4/vector_chipset.c +++ b/lib/stm32/f4/vector_chipset.c @@ -18,7 +18,7 @@ * along with this library. If not, see . */ -#include +#include static void pre_main(void) { -- cgit v1.2.3 From bc5146b710c8be3dfa4a8601bd3ca29408ae6397 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 22:26:46 +0200 Subject: unified systick handling the only change this results in in the example binaries is in the hackrf-jellybean/systick example, where the the check in systick_set_clocksource for overflowing from the stm32 area gets used. --- .../lpc43xx/hackrf-jellybean/systick/systickdemo.c | 2 +- examples/stm32/f1/lisa-m-1/can/can.c | 2 +- examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c | 2 +- .../lisa-m-2/usart_irq_printf/usart_irq_printf.c | 2 +- examples/stm32/f1/obldc/can/can.c | 2 +- examples/stm32/f1/obldc/systick/systick.c | 2 +- examples/stm32/f1/other/systick/systick.c | 2 +- examples/stm32/f1/other/usb_hid/usbhid.c | 2 +- .../stm32-h103/usart_irq_printf/usart_irq_printf.c | 2 +- examples/stm32/f1/stm32-h103/usb_hid/usbhid.c | 2 +- include/libopencm3/cm3/systick.h | 113 ++++++++++++++++ include/libopencm3/lpc43xx/systick.h | 88 ------------ include/libopencm3/stm32/systick.h | 111 --------------- lib/cm3/systick.c | 149 +++++++++++++++++++++ lib/lpc43xx/systick.c | 69 ---------- lib/stm32/systick.c | 139 ------------------- 16 files changed, 272 insertions(+), 417 deletions(-) create mode 100644 include/libopencm3/cm3/systick.h delete mode 100644 include/libopencm3/lpc43xx/systick.h delete mode 100644 include/libopencm3/stm32/systick.h create mode 100644 lib/cm3/systick.c delete mode 100644 lib/lpc43xx/systick.c delete mode 100644 lib/stm32/systick.c (limited to 'include') diff --git a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c index 61792d1..d38b0bc 100644 --- a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include "../jellybean_conf.h" diff --git a/examples/stm32/f1/lisa-m-1/can/can.c b/examples/stm32/f1/lisa-m-1/can/can.c index 92ebd85..41432b6 100644 --- a/examples/stm32/f1/lisa-m-1/can/can.c +++ b/examples/stm32/f1/lisa-m-1/can/can.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include struct can_tx_msg { diff --git a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c index a0a4d12..f5f0146 100644 --- a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c +++ b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c b/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c index e4e0127..dd2e221 100644 --- a/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/obldc/can/can.c b/examples/stm32/f1/obldc/can/can.c index a29d8d7..281ab1d 100644 --- a/examples/stm32/f1/obldc/can/can.c +++ b/examples/stm32/f1/obldc/can/can.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include struct can_tx_msg { diff --git a/examples/stm32/f1/obldc/systick/systick.c b/examples/stm32/f1/obldc/systick/systick.c index 7abdd54..1426793 100644 --- a/examples/stm32/f1/obldc/systick/systick.c +++ b/examples/stm32/f1/obldc/systick/systick.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include u32 temp32; diff --git a/examples/stm32/f1/other/systick/systick.c b/examples/stm32/f1/other/systick/systick.c index 9aa2e94..c04704d 100644 --- a/examples/stm32/f1/other/systick/systick.c +++ b/examples/stm32/f1/other/systick/systick.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include u32 temp32; diff --git a/examples/stm32/f1/other/usb_hid/usbhid.c b/examples/stm32/f1/other/usb_hid/usbhid.c index 6329f0e..a61d9ea 100644 --- a/examples/stm32/f1/other/usb_hid/usbhid.c +++ b/examples/stm32/f1/other/usb_hid/usbhid.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c b/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c index 5effb28..b052dc3 100644 --- a/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c index d0c2aff..1c27c2f 100644 --- a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c +++ b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/libopencm3/cm3/systick.h b/include/libopencm3/cm3/systick.h new file mode 100644 index 0000000..5e7715b --- /dev/null +++ b/include/libopencm3/cm3/systick.h @@ -0,0 +1,113 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_systick_defines SysTick Defines + +@brief libopencm3 Defined Constants and Types for the Cortex SysTick + +@ingroup CM3_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 19 August 2012 + +LGPL License Terms @ref lgpl_license + */ + +/**@{*/ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +#define STK_CTRL_CLKSOURCE_LSB 2 +/** @defgroup systick_clksource Clock source selection +@ingroup CM3_systick_defines + +@{*/ +#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 +#define STK_CTRL_CLKSOURCE_AHB 1 +/**@}*/ + +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +u32 systick_get_calib(void); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h deleted file mode 100644 index 2ae52c2..0000000 --- a/include/libopencm3/lpc43xx/systick.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ -/* See also libopencm3\cm3\scs.h for details on SysTicks registers */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -u32 systick_get_calib(void); - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h deleted file mode 100644 index e42c4e6..0000000 --- a/include/libopencm3/stm32/systick.h +++ /dev/null @@ -1,111 +0,0 @@ -/** @defgroup STM32F_systick_defines SysTick Defines - -@brief libopencm3 Defined Constants and Types for the STM32F SysTick - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 19 August 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -#define STK_CTRL_CLKSOURCE_LSB 2 -/** @defgroup systick_clksource Clock source selection -@ingroup STM32F_systick_defines - -@{*/ -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 -/**@}*/ - -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -END_DECLS - -#endif -/**@}*/ - diff --git a/lib/cm3/systick.c b/lib/cm3/systick.c new file mode 100644 index 0000000..325ffff --- /dev/null +++ b/lib/cm3/systick.c @@ -0,0 +1,149 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_systick_file SysTick + +@ingroup CM3_files + +@brief libopencm3 Cortex System Tick Timer + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 19 August 2012 + +This library supports the System Tick timer in ARM Cortex Microcontrollers. + +The System Tick timer is part of the ARM Cortex core. It is a 24 bit +down counter that can be configured with an automatical reload value. + +LGPL License Terms @ref lgpl_license + */ + +/**@{*/ +#include + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Set the Automatic Reload Value. + +The counter is set to the reload value when the counter starts and after it +reaches zero. + +@param[in] value u32. 24 bit reload value. +*/ + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Read the Automatic Reload Value. + +@returns 24 bit reload value as u32. +*/ + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Set the SysTick Clock Source. + +The clock source can be either the AHB clock or the same clock divided by 8. + +@param[in] clocksource u8. Clock source from @ref systick_clksource. +*/ + +void systick_set_clocksource(u8 clocksource) +{ + if (clocksource < 2) + STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Enable SysTick Interrupt. + +*/ + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Disable SysTick Interrupt. + +*/ + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Enable SysTick Counter. + +*/ + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Disable SysTick Counter. + +*/ + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Read the Counter Flag. + +The count flag is set when the timer count becomes zero, and is cleared when the +flag is read. + +@returns Boolean if flag set. +*/ + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Get Calibration Value + +@returns Current calibration value +*/ +u32 systick_get_calib(void) +{ + return (STK_CALIB&0x00FFFFFF); +} +/**@}*/ + diff --git a/lib/lpc43xx/systick.c b/lib/lpc43xx/systick.c deleted file mode 100644 index 82345a9..0000000 --- a/lib/lpc43xx/systick.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -void systick_set_clocksource(u8 clocksource) -{ - STK_CTRL |= clocksource; -} - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} - -u32 systick_get_calib(void) -{ - return (STK_CALIB&0x00FFFFFF); -} diff --git a/lib/stm32/systick.c b/lib/stm32/systick.c deleted file mode 100644 index 36077cc..0000000 --- a/lib/stm32/systick.c +++ /dev/null @@ -1,139 +0,0 @@ -/** @defgroup STM32F_systick_file SysTick - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxx System Tick Timer - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 19 August 2012 - -This library supports the System Tick timer in the -STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. - -The System Tick timer is part of the ARM Cortex core. It is a 24 bit -down counter that can be configured with an automatical reload value. - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#include - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Set the Automatic Reload Value. - -The counter is set to the reload value when the counter starts and after it -reaches zero. - -@param[in] value u32. 24 bit reload value. -*/ - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Read the Automatic Reload Value. - -@returns 24 bit reload value as u32. -*/ - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Set the SysTick Clock Source. - -The clock source can be either the AHB clock or the same clock divided by 8. - -@param[in] clocksource u8. Clock source from @ref systick_clksource. -*/ - -void systick_set_clocksource(u8 clocksource) -{ - if (clocksource < 2) - STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Enable SysTick Interrupt. - -*/ - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Disable SysTick Interrupt. - -*/ - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Enable SysTick Counter. - -*/ - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Disable SysTick Counter. - -*/ - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Read the Counter Flag. - -The count flag is set when the timer count becomes zero, and is cleared when the -flag is read. - -@returns Boolean if flag set. -*/ - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} -/**@}*/ - -- cgit v1.2.3 From a818dbe7293b0f7235f866c43e60e54b2da9fb86 Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 19 Oct 2012 00:04:07 +0200 Subject: use generalized libopencm3 functions in cmsis --- include/libopencmsis/core_cm3.h | 69 +++++++++-------------------- include/libopencmsis/dispatch/irqhandlers.h | 17 +++++++ scripts/irq2nvic_h | 20 ++++++++- 3 files changed, 57 insertions(+), 49 deletions(-) create mode 100644 include/libopencmsis/dispatch/irqhandlers.h (limited to 'include') diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index 5ad1327..292a456 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -4,14 +4,15 @@ * particularly unimplemented features are FIXME'd extra * */ +/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant of the symbols efm32lib needs of CMSIS. */ + #ifndef OPENCMSIS_CORECM3_H #define OPENCMSIS_CORECM3_H -/* needed in various places where we rather should include libopencm3 functionality */ -#define MMIO32(addr) (*(volatile uint32_t *)(addr)) - -/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant of the symbols efm32lib needs of CMSIS. */ -#include +#include +#include +#include +#include /* needed by system_efm32.h:196, guessing */ #define __INLINE inline @@ -27,11 +28,12 @@ /* -> style access for what is defined in libopencm3/stm32/f1/scb.h / * cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */ -/* from stm32/f1/scb.h */ -#define SCB_SCR_SLEEPDEEP_Msk (1 << 2) +/* from cm3/scb.h */ +#define SCB_SCR_SLEEPDEEP_Msk SCB_SCR_SLEEPDEEP + /* structure as in, for example, * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from - * libopencm3/stm32/f1/scb.h. FIXME incomplete. */ + * libopencm3/cm3/scb.h. FIXME incomplete. */ typedef struct { __IO uint32_t CPUID; @@ -44,10 +46,6 @@ typedef struct __IO uint32_t SHCSR; } SCB_TypeDef; #define SCB ((SCB_TypeDef *) SCB_BASE) -/* from libopencm3/cm3/memorymap.h */ -#define PPBI_BASE 0xE0000000 -#define SCS_BASE (PPBI_BASE + 0xE000) -#define SCB_BASE (SCS_BASE + 0x0D00) /* needed by efm32_emu.h, guessing and taking the implementation used in * lightswitch-interrupt.c */ @@ -72,24 +70,17 @@ typedef struct /* stubs for efm32_dma */ -/* also used by the clock example. code taken from stm32's nvic.[hc], FIXME until - * the generic cm3 functionality is moved out from stm32 and can be used here - * easily (nvic_clear_pending_irq, nvic_enable_irq, nvic_disable_irq). */ -#define NVIC_BASE (SCS_BASE + 0x0100) -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) static inline void NVIC_ClearPendingIRQ(uint8_t irqn) { - NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); + nvic_clear_pending_irq(irqn); } static inline void NVIC_EnableIRQ(uint8_t irqn) { - NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); + nvic_enable_irq(irqn); } static inline void NVIC_DisableIRQ(uint8_t irqn) { - NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); + nvic_disable_irq(irqn); } /* stubs for efm32_int. FIXME: how do they do that? nvic documentation in the @@ -139,7 +130,6 @@ typedef struct * * modified for CMSIS style array as the powertest example needs it. * */ -#define SYS_TICK_BASE (SCS_BASE + 0x0010) /* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */ typedef struct @@ -151,21 +141,16 @@ typedef struct } SysTick_TypeDef; #define SysTick ((SysTick_TypeDef *) SYS_TICK_BASE) -#define STK_CTRL_TICKINT (1 << 1) -#define STK_CTRL_ENABLE (1 << 0) - -#define STK_CTRL_CLKSOURCE_LSB 2 -#define STK_CTRL_CLKSOURCE_AHB 1 static inline uint32_t SysTick_Config(uint32_t n_ticks) { + /* constant from systick_set_reload -- as this returns something that's + * not void, this is the only possible error condition */ if (n_ticks & ~0x00FFFFFF) return 1; - SysTick->LOAD = n_ticks; - SysTick->CTRL |= (STK_CTRL_CLKSOURCE_AHB << STK_CTRL_CLKSOURCE_LSB); - - SysTick->CTRL |= STK_CTRL_TICKINT; - - SysTick->CTRL |= STK_CTRL_ENABLE; + systick_set_reload(n_ticks); + systick_set_clocksource(true); + systick_interrupt_enable(); + systick_counter_enable(); return 0; } @@ -182,20 +167,10 @@ typedef struct /* blink.h expects the isr for systicks to be named SysTick_Handler. with this, * its Systick_Handler function gets renamed to the weak symbol exported by * vector.c */ -#define SysTick_Handler sys_tick_handler - -/* likewise, clock.c defines GPIO_ODD_IRQHandler and GPIO_EVEN_IRQHandler */ -#define GPIO_ODD_IRQHandler gpio_odd_isr -#define GPIO_EVEN_IRQHandler gpio_even_isr -#define RTC_IRQHandler rtc_isr -/* for inttemp (i should really get a list and convert them all) */ - -#define ADC0_IRQHandler adc0_isr - -/* for the lightsense example */ +#define SysTick_Handler sys_tick_handler +/* FIXME: this needs to be done for all of the 14 hard vectors */ -#define LESENSE_IRQHandler lesense_isr -#define PCNT0_IRQHandler pcnt0_isr +#include #endif diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h new file mode 100644 index 0000000..1f6b02a --- /dev/null +++ b/include/libopencmsis/dispatch/irqhandlers.h @@ -0,0 +1,17 @@ +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include + +#elif defined(TINYGECKO) +# include + +#elif defined(LPC43XX) +# include + +#else +# warning"no chipset defined; user interrupts are not redirected" + +#endif diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index f84c88e..6e45fa2 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -99,7 +99,19 @@ template_vector_nvic_c = '''\ {vectortableinitialization} ''' -def convert(infile, outfile_nvic, outfile_vectornvic): +template_cmsis_h = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + * + * These definitions bend every interrupt handler that is defined CMSIS style + * to the weak symbol exported by libopenmc3. + */ + +{cmsisbends} +''' + +def convert(infile, outfile_nvic, outfile_vectornvic, outfile_cmsis): data = yaml.load(infile) irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) @@ -114,9 +126,11 @@ def convert(infile, outfile_nvic, outfile_vectornvic): data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) + data['cmsisbends'] = "\n".join("#define %s_IRQHandler %s_isr"%(name.upper(), name.lower()) for name in irqnames) outfile_nvic.write(template_nvic_h.format(**data)) outfile_vectornvic.write(template_vector_nvic_c.format(**data)) + outfile_cmsis.write(template_cmsis_h.format(**data)) def makeparentdir(filename): try: @@ -131,11 +145,13 @@ def main(): raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml") nvic_h = infile.replace('irq.yaml', 'nvic.h') vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c') + cmsis = infile.replace('irq.yaml', 'irqhandlers.h').replace('/libopencm3/', '/libopencmsis/') makeparentdir(nvic_h) makeparentdir(vector_nvic_c) + makeparentdir(cmsis) - convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w')) + convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w'), open(cmsis, 'w')) if __name__ == "__main__": main() -- cgit v1.2.3 From d13043d787146f82ce70ba8b81a8660f7a04b697 Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 19 Oct 2012 00:31:10 +0200 Subject: change discriminator in efm32 series from TINYGECKO to EFM32TG --- include/libopencm3/dispatch/nvic.h | 2 +- include/libopencmsis/core_cm3.h | 1 + include/libopencmsis/dispatch/irqhandlers.h | 2 +- lib/dispatch/vector_nvic.c | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index d8e7889..2146c83 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -5,7 +5,7 @@ #elif defined(STM32F4) # include -#elif defined(TINYGECKO) +#elif defined(EFM32TG) # include #elif defined(LPC43XX) diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index 292a456..0a89381 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -12,6 +12,7 @@ #include #include #include +#include #include /* needed by system_efm32.h:196, guessing */ diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h index 1f6b02a..ad3f4a1 100644 --- a/include/libopencmsis/dispatch/irqhandlers.h +++ b/include/libopencmsis/dispatch/irqhandlers.h @@ -5,7 +5,7 @@ #elif defined(STM32F4) # include -#elif defined(TINYGECKO) +#elif defined(EFM32TG) # include #elif defined(LPC43XX) diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index fc5fdd2..9ac9517 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -5,7 +5,7 @@ #elif defined(STM32F4) # include "../stm32/f4/vector_nvic.c" -#elif defined(TINYGECKO) +#elif defined(EFM32TG) # include "../efm32/tinygecko/vector_nvic.c" #elif defined(LPC43XX) -- cgit v1.2.3 From d526dd3268500d397746b19d2ab6688abf524077 Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 19 Oct 2012 00:49:27 +0200 Subject: rename tinygecko->efm32tg everywhere --- Makefile | 2 +- include/libopencm3/dispatch/nvic.h | 2 +- include/libopencm3/efm32/efm32tg/irq.yaml | 28 +++++++++ include/libopencm3/efm32/efm32tg/memorymap.h | 76 +++++++++++++++++++++++ include/libopencm3/efm32/tinygecko/irq.yaml | 28 --------- include/libopencm3/efm32/tinygecko/memorymap.h | 76 ----------------------- include/libopencmsis/dispatch/irqhandlers.h | 2 +- lib/dispatch/vector_nvic.c | 2 +- lib/efm32/efm32tg/EFM32TG840F32.ld | 15 +++++ lib/efm32/efm32tg/Makefile | 38 ++++++++++++ lib/efm32/efm32tg/libopencm3_efm32tg.ld | 79 ++++++++++++++++++++++++ lib/efm32/tinygecko/EFM32TG840F32.ld | 15 ----- lib/efm32/tinygecko/Makefile | 38 ------------ lib/efm32/tinygecko/libopencm3_efm32tinygecko.ld | 79 ------------------------ 14 files changed, 240 insertions(+), 240 deletions(-) create mode 100644 include/libopencm3/efm32/efm32tg/irq.yaml create mode 100644 include/libopencm3/efm32/efm32tg/memorymap.h delete mode 100644 include/libopencm3/efm32/tinygecko/irq.yaml delete mode 100644 include/libopencm3/efm32/tinygecko/memorymap.h create mode 100644 lib/efm32/efm32tg/EFM32TG840F32.ld create mode 100644 lib/efm32/efm32tg/Makefile create mode 100644 lib/efm32/efm32tg/libopencm3_efm32tg.ld delete mode 100644 lib/efm32/tinygecko/EFM32TG840F32.ld delete mode 100644 lib/efm32/tinygecko/Makefile delete mode 100644 lib/efm32/tinygecko/libopencm3_efm32tinygecko.ld (limited to 'include') diff --git a/Makefile b/Makefile index 02d3c7a..80f0822 100644 --- a/Makefile +++ b/Makefile @@ -26,7 +26,7 @@ SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL = install SRCLIBDIR = $(shell pwd)/lib -TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lpc43xx lm3s efm32/tinygecko +TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lpc43xx lm3s efm32/efm32tg # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 2146c83..27c6161 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -6,7 +6,7 @@ # include #elif defined(EFM32TG) -# include +# include #elif defined(LPC43XX) # include diff --git a/include/libopencm3/efm32/efm32tg/irq.yaml b/include/libopencm3/efm32/efm32tg/irq.yaml new file mode 100644 index 0000000..f4aaba3 --- /dev/null +++ b/include/libopencm3/efm32/efm32tg/irq.yaml @@ -0,0 +1,28 @@ +includeguard: LIBOPENCM3_EFM32TG_NVIC_H +partname_humanreadable: EFM32 Tiny Gecko series +partname_doxygen: EFM32TG +# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. +irqs: + - dma + - gpio_even + - timer0 + - usart0_rx + - usart0_tx + - acmp01 + - adc0 + - dac0 + - i2c0 + - gpio_odd + - timer1 + - usart1_rx + - usart1_tx + - lesense + - leuart0 + - letimer0 + - pcnt0 + - rtc + - cmu + - vcmp + - lcd + - msc + - aes diff --git a/include/libopencm3/efm32/efm32tg/memorymap.h b/include/libopencm3/efm32/efm32tg/memorymap.h new file mode 100644 index 0000000..abf37ce --- /dev/null +++ b/include/libopencm3/efm32/efm32tg/memorymap.h @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Layout of the system address space of Tiny Gecko devices. + * + * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2. + */ + +/* The common cortex-m3 definitions were verified from + * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be + * missing there. The details (everything based on SCS_BASE) was verified from + * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but + * there are discrepancies. */ +#include + +#define CODE_BASE 0x00000000 + +#define SRAM_BASE 0x20000000 +#define SRAM_BASE_BITBAND 0x22000000 + +#define PERIPH_BASE 0x40000000 +#define PERIPH_BASE_BITBAND 0x42000000 + +/* Details of the "Code" section */ + +#define FLASH_BASE (CODE_BASE + 0x00000000) +#define USERDATA_BASE (CODE_BASE + 0x0fe00000) +#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000) +#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000) +#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000) + +/* Tiny Gecko peripherial definitions */ + +#define VCMP_BASE (PERIPH_BASE + 0x00000000) +#define ACMP0_BASE (PERIPH_BASE + 0x00001000) +#define ACMP1_BASE (PERIPH_BASE + 0x00001400) +#define ADC_BASE (PERIPH_BASE + 0x00002000) +#define DAC0_BASE (PERIPH_BASE + 0x00004000) +#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */ +#define I2C0_BASE (PERIPH_BASE + 0x0000a000) +#define USART0_BASE (PERIPH_BASE + 0x0000c000) +#define USART1_BASE (PERIPH_BASE + 0x0000c400) +#define TIMER0_BASE (PERIPH_BASE + 0x00010000) +#define TIMER1_BASE (PERIPH_BASE + 0x00010400) +#define RTC_BASE (PERIPH_BASE + 0x00080000) +#define LETIMER0_BASE (PERIPH_BASE + 0x00082000) +#define LEUART0_BASE (PERIPH_BASE + 0x00084000) +#define PCNT0_BASE (PERIPH_BASE + 0x00086000) +#define WDOG_BASE (PERIPH_BASE + 0x00088000) +#define LCD_BASE (PERIPH_BASE + 0x0008a000) +#define LESENSE_BASE (PERIPH_BASE + 0x0008c000) +#define MSC_BASE (PERIPH_BASE + 0x000c0000) +#define DMA_BASE (PERIPH_BASE + 0x000c2000) +#define EMU_BASE (PERIPH_BASE + 0x000c6000) +#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */ +#define RMU_BASE (PERIPH_BASE + 0x000ca000) +#define PRS_BASE (PERIPH_BASE + 0x000cc000) +#define AES_BASE (PERIPH_BASE + 0x000e0000) diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/tinygecko/irq.yaml deleted file mode 100644 index da954f6..0000000 --- a/include/libopencm3/efm32/tinygecko/irq.yaml +++ /dev/null @@ -1,28 +0,0 @@ -includeguard: LIBOPENCM3_EFM32_TINYGECKO_NVIC_H -partname_humanreadable: EFM32 Tiny Gecko series -partname_doxygen: EFM32TG -# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. -irqs: - - dma - - gpio_even - - timer0 - - usart0_rx - - usart0_tx - - acmp01 - - adc0 - - dac0 - - i2c0 - - gpio_odd - - timer1 - - usart1_rx - - usart1_tx - - lesense - - leuart0 - - letimer0 - - pcnt0 - - rtc - - cmu - - vcmp - - lcd - - msc - - aes diff --git a/include/libopencm3/efm32/tinygecko/memorymap.h b/include/libopencm3/efm32/tinygecko/memorymap.h deleted file mode 100644 index abf37ce..0000000 --- a/include/libopencm3/efm32/tinygecko/memorymap.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Layout of the system address space of Tiny Gecko devices. - * - * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2. - */ - -/* The common cortex-m3 definitions were verified from - * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be - * missing there. The details (everything based on SCS_BASE) was verified from - * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but - * there are discrepancies. */ -#include - -#define CODE_BASE 0x00000000 - -#define SRAM_BASE 0x20000000 -#define SRAM_BASE_BITBAND 0x22000000 - -#define PERIPH_BASE 0x40000000 -#define PERIPH_BASE_BITBAND 0x42000000 - -/* Details of the "Code" section */ - -#define FLASH_BASE (CODE_BASE + 0x00000000) -#define USERDATA_BASE (CODE_BASE + 0x0fe00000) -#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000) -#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000) -#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000) - -/* Tiny Gecko peripherial definitions */ - -#define VCMP_BASE (PERIPH_BASE + 0x00000000) -#define ACMP0_BASE (PERIPH_BASE + 0x00001000) -#define ACMP1_BASE (PERIPH_BASE + 0x00001400) -#define ADC_BASE (PERIPH_BASE + 0x00002000) -#define DAC0_BASE (PERIPH_BASE + 0x00004000) -#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */ -#define I2C0_BASE (PERIPH_BASE + 0x0000a000) -#define USART0_BASE (PERIPH_BASE + 0x0000c000) -#define USART1_BASE (PERIPH_BASE + 0x0000c400) -#define TIMER0_BASE (PERIPH_BASE + 0x00010000) -#define TIMER1_BASE (PERIPH_BASE + 0x00010400) -#define RTC_BASE (PERIPH_BASE + 0x00080000) -#define LETIMER0_BASE (PERIPH_BASE + 0x00082000) -#define LEUART0_BASE (PERIPH_BASE + 0x00084000) -#define PCNT0_BASE (PERIPH_BASE + 0x00086000) -#define WDOG_BASE (PERIPH_BASE + 0x00088000) -#define LCD_BASE (PERIPH_BASE + 0x0008a000) -#define LESENSE_BASE (PERIPH_BASE + 0x0008c000) -#define MSC_BASE (PERIPH_BASE + 0x000c0000) -#define DMA_BASE (PERIPH_BASE + 0x000c2000) -#define EMU_BASE (PERIPH_BASE + 0x000c6000) -#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */ -#define RMU_BASE (PERIPH_BASE + 0x000ca000) -#define PRS_BASE (PERIPH_BASE + 0x000cc000) -#define AES_BASE (PERIPH_BASE + 0x000e0000) diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h index ad3f4a1..41c4b28 100644 --- a/include/libopencmsis/dispatch/irqhandlers.h +++ b/include/libopencmsis/dispatch/irqhandlers.h @@ -6,7 +6,7 @@ # include #elif defined(EFM32TG) -# include +# include #elif defined(LPC43XX) # include diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 9ac9517..9373319 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -6,7 +6,7 @@ # include "../stm32/f4/vector_nvic.c" #elif defined(EFM32TG) -# include "../efm32/tinygecko/vector_nvic.c" +# include "../efm32/efm32tg/vector_nvic.c" #elif defined(LPC43XX) # include "../lpc43xx/vector_nvic.c" diff --git a/lib/efm32/efm32tg/EFM32TG840F32.ld b/lib/efm32/efm32tg/EFM32TG840F32.ld new file mode 100644 index 0000000..f7baa90 --- /dev/null +++ b/lib/efm32/efm32tg/EFM32TG840F32.ld @@ -0,0 +1,15 @@ +/* lengths from d011_efm32tg840_datasheet.pdf table 1.1, offset from + * d0034_efm32tg_reference_manual.pdf figure 5.2. + * + * the origins and memory structure are constant over all tinygeckos, but the + * MEMORY section requires the use of constants, and has thus to be duplicated + * over the chip variants. + * */ + +MEMORY +{ + rom (rx) : ORIGIN = 0, LENGTH = 32k + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4k +} + +INCLUDE tinygecko.ld; diff --git a/lib/efm32/efm32tg/Makefile b/lib/efm32/efm32tg/Makefile new file mode 100644 index 0000000..65f8d02 --- /dev/null +++ b/lib/efm32/efm32tg/Makefile @@ -0,0 +1,38 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2012 chrysn +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_efm32tg +FAMILY = EFM32TG + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ + -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -D$(FAMILY) +# ARFLAGS = rcsv +ARFLAGS = rcs +OBJS = vector.o + +VPATH += ../:../../cm3 + +include ../../Makefile.include + diff --git a/lib/efm32/efm32tg/libopencm3_efm32tg.ld b/lib/efm32/efm32tg/libopencm3_efm32tg.ld new file mode 100644 index 0000000..8ef5e42 --- /dev/null +++ b/lib/efm32/efm32tg/libopencm3_efm32tg.ld @@ -0,0 +1,79 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Generic linker script for EFM32 targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + _etext = .; + } >rom + + . = ORIGIN(ram); + + .data : AT(_etext) { + _data = .; + *(.data*) /* Read-write initialized data */ + . = ALIGN(4); + _edata = .; + } >ram + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram AT >rom + _data_loadaddr = LOADADDR(.data); + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support - discard it for now. + */ + /DISCARD/ : { *(.ARM.exidx) } + + . = ALIGN(4); + end = .; +} + +PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); + diff --git a/lib/efm32/tinygecko/EFM32TG840F32.ld b/lib/efm32/tinygecko/EFM32TG840F32.ld deleted file mode 100644 index f7baa90..0000000 --- a/lib/efm32/tinygecko/EFM32TG840F32.ld +++ /dev/null @@ -1,15 +0,0 @@ -/* lengths from d011_efm32tg840_datasheet.pdf table 1.1, offset from - * d0034_efm32tg_reference_manual.pdf figure 5.2. - * - * the origins and memory structure are constant over all tinygeckos, but the - * MEMORY section requires the use of constants, and has thus to be duplicated - * over the chip variants. - * */ - -MEMORY -{ - rom (rx) : ORIGIN = 0, LENGTH = 32k - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4k -} - -INCLUDE tinygecko.ld; diff --git a/lib/efm32/tinygecko/Makefile b/lib/efm32/tinygecko/Makefile deleted file mode 100644 index 550860c..0000000 --- a/lib/efm32/tinygecko/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## Copyright (C) 2012 chrysn -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -LIBNAME = libopencm3_efm32tinygecko -FAMILY = TINYGECKO - -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar -CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ - -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD -D$(FAMILY) -# ARFLAGS = rcsv -ARFLAGS = rcs -OBJS = vector.o - -VPATH += ../:../../cm3 - -include ../../Makefile.include - diff --git a/lib/efm32/tinygecko/libopencm3_efm32tinygecko.ld b/lib/efm32/tinygecko/libopencm3_efm32tinygecko.ld deleted file mode 100644 index 8ef5e42..0000000 --- a/lib/efm32/tinygecko/libopencm3_efm32tinygecko.ld +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann , - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* Generic linker script for EFM32 targets using libopencm3. */ - -/* Memory regions must be defined in the ld script which includes this one. */ - -/* Enforce emmition of the vector table. */ -EXTERN (vector_table) - -/* Define the entry point of the output file. */ -ENTRY(reset_handler) - -/* Define sections. */ -SECTIONS -{ - . = ORIGIN(rom); - - .text : { - *(.vectors) /* Vector table */ - *(.text*) /* Program code */ - . = ALIGN(4); - *(.rodata*) /* Read-only data */ - . = ALIGN(4); - _etext = .; - } >rom - - . = ORIGIN(ram); - - .data : AT(_etext) { - _data = .; - *(.data*) /* Read-write initialized data */ - . = ALIGN(4); - _edata = .; - } >ram - - .bss : { - *(.bss*) /* Read-write zero initialized data */ - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >ram AT >rom - _data_loadaddr = LOADADDR(.data); - - /* - * The .eh_frame section appears to be used for C++ exception handling. - * You may need to fix this if you're using C++. - */ - /DISCARD/ : { *(.eh_frame) } - - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - discard it for now. - */ - /DISCARD/ : { *(.ARM.exidx) } - - . = ALIGN(4); - end = .; -} - -PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); - -- cgit v1.2.3 From ab5a544d45dc3a6af3f976847d4dda81aa931892 Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 19 Oct 2012 01:09:51 +0200 Subject: added irqs for the rest of the efm32 devices --- include/libopencm3/dispatch/nvic.h | 6 ++++ include/libopencm3/efm32/efm32g/irq.yaml | 35 +++++++++++++++++++++++ include/libopencm3/efm32/efm32gg/irq.yaml | 43 +++++++++++++++++++++++++++++ include/libopencm3/efm32/efm32lg/irq.yaml | 43 +++++++++++++++++++++++++++++ include/libopencmsis/dispatch/irqhandlers.h | 6 ++++ lib/dispatch/vector_nvic.c | 6 ++++ 6 files changed, 139 insertions(+) create mode 100644 include/libopencm3/efm32/efm32g/irq.yaml create mode 100644 include/libopencm3/efm32/efm32gg/irq.yaml create mode 100644 include/libopencm3/efm32/efm32lg/irq.yaml (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 27c6161..a0db510 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -7,6 +7,12 @@ #elif defined(EFM32TG) # include +#elif defined(EFM32G) +# include +#elif defined(EFM32LG) +# include +#elif defined(EFM32GG) +# include #elif defined(LPC43XX) # include diff --git a/include/libopencm3/efm32/efm32g/irq.yaml b/include/libopencm3/efm32/efm32g/irq.yaml new file mode 100644 index 0000000..770f755 --- /dev/null +++ b/include/libopencm3/efm32/efm32g/irq.yaml @@ -0,0 +1,35 @@ +includeguard: LIBOPENCM3_EFM32G_NVIC_H +partname_humanreadable: EFM32 Gecko series +partname_doxygen: EFM32G +# The names and sequence are taken from d0001_efm32g_reference_manual.pdf table 4.1. +irqs: + - dma + - gpio_even + - timer0 + - usart0_rx + - usart0_tx + - acmp01 + - adc0 + - dac0 + - i2c0 + - gpio_odd + - timer1 + - timer2 + - usart1_rx + - usart1_tx + - usart2_rx + - usart2_tx + - uart0_rx + - uart0_tx + - leuart0 + - leuart1 + - letimer0 + - pcnt0 + - pcnt1 + - pcnt2 + - rtc + - cmu + - vcmp + - lcd + - msc + - aes diff --git a/include/libopencm3/efm32/efm32gg/irq.yaml b/include/libopencm3/efm32/efm32gg/irq.yaml new file mode 100644 index 0000000..1cb4601 --- /dev/null +++ b/include/libopencm3/efm32/efm32gg/irq.yaml @@ -0,0 +1,43 @@ +includeguard: LIBOPENCM3_EFM32GG_NVIC_H +partname_humanreadable: EFM32 Giant Gecko series +partname_doxygen: EFM32GG +# The names and sequence are taken from d0053_efm32gg_refreence_manual.pdf table 4.1. +irqs: + - dma + - gpio_even + - timer0 + - usart0_rx + - usart0_tx + - usb + - acmp01 + - adc0 + - dac0 + - i2c0 + - i2c1 + - gpio_odd + - timer1 + - timer2 + - timer3 + - usart1_rx + - usart1_tx + - lesense + - usart2_rx + - usart2_tx + - uart0_rx + - uart0_tx + - uart1_rx + - uart1_tx + - leuart0 + - leuart1 + - letimer0 + - pcnt0 + - pcnt1 + - pcnt2 + - rtc + - burtc + - cmu + - vcmp + - lcd + - msc + - aes + - ebi diff --git a/include/libopencm3/efm32/efm32lg/irq.yaml b/include/libopencm3/efm32/efm32lg/irq.yaml new file mode 100644 index 0000000..ec38bc1 --- /dev/null +++ b/include/libopencm3/efm32/efm32lg/irq.yaml @@ -0,0 +1,43 @@ +includeguard: LIBOPENCM3_EFM32LG_NVIC_H +partname_humanreadable: EFM32 Leopard Gecko series +partname_doxygen: EFM32LG +# The names and sequence are taken from d0183_efm32lg_reference_manual.pdf table 4.1. +irqs: + - dma + - gpio_even + - timer0 + - usart0_rx + - usart0_tx + - usb + - acmp01 + - adc0 + - dac0 + - i2c0 + - i2c1 + - gpio_odd + - timer1 + - timer2 + - timer3 + - usart1_rx + - usart1_tx + - lesense + - usart2_rx + - usart2_tx + - uart0_rx + - uart0_tx + - uart1_rx + - uart1_tx + - leuart0 + - leuart1 + - letimer0 + - pcnt0 + - pcnt1 + - pcnt2 + - rtc + - burtc + - cmu + - vcmp + - lcd + - msc + - aes + - ebi diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h index 41c4b28..65e071d 100644 --- a/include/libopencmsis/dispatch/irqhandlers.h +++ b/include/libopencmsis/dispatch/irqhandlers.h @@ -7,6 +7,12 @@ #elif defined(EFM32TG) # include +#elif defined(EFM32G) +# include +#elif defined(EFM32LG) +# include +#elif defined(EFM32GG) +# include #elif defined(LPC43XX) # include diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 9373319..d710d31 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -7,6 +7,12 @@ #elif defined(EFM32TG) # include "../efm32/efm32tg/vector_nvic.c" +#elif defined(EFM32G) +# include "../efm32/efm32g/vector_nvic.c" +#elif defined(EFM32LG) +# include "../efm32/efm32lg/vector_nvic.c" +#elif defined(EFM32GG) +# include "../efm32/efm32gg/vector_nvic.c" #elif defined(LPC43XX) # include "../lpc43xx/vector_nvic.c" -- cgit v1.2.3 From 14a5fc78cf5e50364d6268aaeb1871966ee89b32 Mon Sep 17 00:00:00 2001 From: chrysn Date: Fri, 19 Oct 2012 19:07:30 +0200 Subject: completing dispatch the LM3S irq list was previously unused as it was missing in the dispatch files; now it got added. (before HEAD^, it wouldn't have made any difference because the discriminating constant wasn't defined anyway) also, this enhances the warning messages --- include/libopencm3/dispatch/nvic.h | 5 ++++- lib/dispatch/vector_nvic.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index d8e7889..441fd28 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -11,8 +11,11 @@ #elif defined(LPC43XX) # include +#elif defined(LM3S) +# include + #else -# warning"no chipset defined; user interrupts are disabled" +# warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0" #define NVIC_IRQ_COUNT 0 diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index fc5fdd2..d5e4a60 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -11,8 +11,11 @@ #elif defined(LPC43XX) # include "../lpc43xx/vector_nvic.c" +#elif defined(LM3S) +# include "../lm3s/vector_nvic.c" + #else -# warning"no chipset defined; user interrupts are disabled" +# warning"no interrupts defined for chipset; not allocating space in the vector table" #define IRQ_HANDLERS -- cgit v1.2.3 From 0a1cf977eb2003dd55cee8f5f840f3a2f6e9c0ce Mon Sep 17 00:00:00 2001 From: Silvio Gissi Date: Fri, 19 Oct 2012 23:09:45 +0200 Subject: Added irq.yaml to lpc_13xx and lpc_17xx families --- include/libopencm3/dispatch/nvic.h | 4 +++ include/libopencm3/lpc13xx/irq.yaml | 62 +++++++++++++++++++++++++++++++++++++ include/libopencm3/lpc17xx/irq.yaml | 39 +++++++++++++++++++++++ lib/dispatch/vector_nvic.c | 4 +++ 4 files changed, 109 insertions(+) create mode 100644 include/libopencm3/lpc13xx/irq.yaml create mode 100644 include/libopencm3/lpc17xx/irq.yaml (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 441fd28..ff08269 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -8,6 +8,10 @@ #elif defined(TINYGECKO) # include +#elif defined(LPC13XX) +# include +#elif defined(LPC17XX) +# include #elif defined(LPC43XX) # include diff --git a/include/libopencm3/lpc13xx/irq.yaml b/include/libopencm3/lpc13xx/irq.yaml new file mode 100644 index 0000000..5a372db --- /dev/null +++ b/include/libopencm3/lpc13xx/irq.yaml @@ -0,0 +1,62 @@ +includeguard: LIBOPENCM3_LPC13xx_NVIC_H +partname_humanreadable: LPC 13xx series +partname_doxygen: LPC13xx +irqs: + 0: pio0_0 + 1: pio0_1 + 2: pio0_2 + 3: pio0_3 + 4: pio0_4 + 5: pio0_5 + 6: pio0_6 + 7: pio0_7 + 8: pio0_8 + 9: pio0_9 + 10: pio0_10 + 11: pio0_11 + 12: pio1_0 + 13: pio1_1 + 14: pio1_2 + 15: pio1_3 + 16: pio1_4 + 17: pio1_5 + 18: pio1_6 + 19: pio1_7 + 20: pio1_8 + 21: pio1_9 + 22: pio1_10 + 23: pio1_11 + 24: pio2_0 + 25: pio2_1 + 26: pio2_2 + 27: pio2_3 + 28: pio2_4 + 29: pio2_5 + 30: pio2_6 + 31: pio2_7 + 32: pio2_8 + 33: pio2_9 + 34: pio2_10 + 35: pio2_11 + 36: pio3_0 + 37: pio3_1 + 38: pio3_2 + 39: pio3_3 + 40: i2c0 + 41: ct16b0 + 42: ct16b1 + 43: ct32b0 + 44: ct32b1 + 45: ssp0 + 46: uart + 47: usb + 48: usb_fiq + 49: adc + 50: wdt + 51: bod +# 52: reserved + 53: pio3 + 54: pio2 + 55: pio1 + 56: pio0 + 56: ssp1 diff --git a/include/libopencm3/lpc17xx/irq.yaml b/include/libopencm3/lpc17xx/irq.yaml new file mode 100644 index 0000000..faa140f --- /dev/null +++ b/include/libopencm3/lpc17xx/irq.yaml @@ -0,0 +1,39 @@ +includeguard: LIBOPENCM3_LPC17xx_NVIC_H +partname_humanreadable: LPC 17xx series +partname_doxygen: LPC17xx +irqs: + 0: wdt + 1: timer0 + 2: timer1 + 3: timer2 + 4: timer3 + 5: uart0 + 6: uart1 + 7: uart2 + 8: uart3 + 9: pwm + 10: i2c0 + 11: i2c1 + 12: i2c2 + 13: spi + 14: ssp0 + 15: ssp1 + 16: pll0 + 17: rtc + 18: eint0 + 19: eint1 + 20: eint2 + 21: eint3 + 22: adc + 23: bod + 24: usb + 25: can + 26: gpdma + 27: i2s + 28: ethernet + 29: rit + 30: motor_pwm + 31: qei + 32: pll1 + 33: usb_act + 34: can_act diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index d5e4a60..1f4753d 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -8,6 +8,10 @@ #elif defined(TINYGECKO) # include "../efm32/tinygecko/vector_nvic.c" +#elif defined(LPC13XX) +# include "../lpc13xx/vector_nvic.c" +#elif defined(LPC17XX) +# include "../lpc17xx/vector_nvic.c" #elif defined(LPC43XX) # include "../lpc43xx/vector_nvic.c" -- cgit v1.2.3 From e55a9e387560924a157d60b29a3aa49300b9b456 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 22 Oct 2012 22:37:44 +0000 Subject: Missing EXTI ports and flag numbers for F4 (Also missing for forthcoming L1) --- include/libopencm3/stm32/exti.h | 3 +++ lib/stm32/f4/exti.c | 6 ++++++ 2 files changed, 9 insertions(+) (limited to 'include') diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h index 7645825..48065b9 100644 --- a/include/libopencm3/stm32/exti.h +++ b/include/libopencm3/stm32/exti.h @@ -53,6 +53,9 @@ #define EXTI17 (1 << 17) #define EXTI18 (1 << 18) #define EXTI19 (1 << 19) +#define EXTI20 (1 << 20) +#define EXTI21 (1 << 21) +#define EXTI22 (1 << 22) /* Trigger types */ typedef enum trigger_e { diff --git a/lib/stm32/f4/exti.c b/lib/stm32/f4/exti.c index 155c21f..f69e99e 100644 --- a/lib/stm32/f4/exti.c +++ b/lib/stm32/f4/exti.c @@ -127,6 +127,12 @@ void exti_select_source(u32 exti, u32 gpioport) case GPIOG: bits = 0x9; break; + case GPIOH: + bits = 0x8; + break; + case GPIOI: + bits = 0x7; + break; } /* Ensure that only valid EXTI lines are used. */ -- cgit v1.2.3 From f80bf1ccb107e2ad54d7d8ac586e9ffd09e8730e Mon Sep 17 00:00:00 2001 From: Jeff Ciesielski Date: Mon, 22 Oct 2012 15:48:22 -0700 Subject: stm32/i2c: Add DOXYGEN strings for i2c helper functions. Also: Define i2c_dutycycle group in i2c header --- include/libopencm3/stm32/i2c.h | 6 +++++ lib/stm32/i2c.c | 51 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) (limited to 'include') diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h index 05a4d16..1b2dc0e 100644 --- a/include/libopencm3/stm32/i2c.h +++ b/include/libopencm3/stm32/i2c.h @@ -321,9 +321,15 @@ LGPL License Terms @ref lgpl_license #define I2C_CCR_FS (1 << 15) /* DUTY: Fast Mode Duty Cycle */ +/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles +@ingroup i2c_defines + +@{*/ #define I2C_CCR_DUTY (1 << 14) #define I2C_CCR_DUTY_DIV2 0 #define I2C_CCR_DUTY_16_DIV_9 1 +/**@}*/ + /* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ /* diff --git a/lib/stm32/i2c.c b/lib/stm32/i2c.c index e6869f6..a67bece 100644 --- a/lib/stm32/i2c.c +++ b/lib/stm32/i2c.c @@ -313,26 +313,57 @@ void i2c_disable_interrupt(u32 i2c, u32 interrupt) I2C_CR2(i2c) &= ~interrupt; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Enable ACK + +Enables acking of own 7/10 bit address +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ void i2c_enable_ack(u32 i2c) { I2C_CR1(i2c) |= I2C_CR1_ACK; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Disable ACK + +Disables acking of own 7/10 bit address +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ void i2c_disable_ack(u32 i2c) { I2C_CR1(i2c) &= ~I2C_CR1_ACK; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C NACK Next Byte + +Causes the I2C controller to NACK the reception of the next byte +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ void i2c_nack_next(u32 i2c) { I2C_CR1(i2c) |= I2C_CR1_POS; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C NACK Next Byte + +Causes the I2C controller to NACK the reception of the current byte + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ void i2c_nack_current(u32 i2c) { I2C_CR1(i2c) &= ~I2C_CR1_POS; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set clock duty cycle + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle. +*/ void i2c_set_dutycycle(u32 i2c, u32 dutycycle) { if (dutycycle == I2C_CCR_DUTY_DIV2) @@ -341,21 +372,41 @@ void i2c_set_dutycycle(u32 i2c, u32 dutycycle) I2C_CCR(i2c) |= I2C_CCR_DUTY; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Enable DMA + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ void i2c_enable_dma(u32 i2c) { I2C_CR2(i2c) |= I2C_CR2_DMAEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Disable DMA + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ void i2c_disable_dma(u32 i2c) { I2C_CR2(i2c) &= ~I2C_CR2_DMAEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set DMA last transfer + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ void i2c_set_dma_last_transfer(u32 i2c) { I2C_CR2(i2c) |= I2C_CR2_LAST; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Clear DMA last transfer + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ void i2c_clear_dma_last_transfer(u32 i2c) { I2C_CR2(i2c) &= ~I2C_CR2_LAST; -- cgit v1.2.3 From 0fd7cc3559eb3c180de97898edbfd77f827a83b1 Mon Sep 17 00:00:00 2001 From: Thomas Daede Date: Sun, 28 Oct 2012 02:56:22 -0500 Subject: Fix CAN standard ID mask to be 11 bits. --- include/libopencm3/stm32/can.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h index d6636d5..cdb5df1 100644 --- a/include/libopencm3/stm32/can.h +++ b/include/libopencm3/stm32/can.h @@ -458,7 +458,7 @@ /* --- CAN_TIxR values ------------------------------------------------------ */ /* STID[10:0]: Standard identifier */ -#define CAN_TIxR_STID_MASK (0x3FF << 21) +#define CAN_TIxR_STID_MASK (0x7FF << 21) #define CAN_TIxR_STID_SHIFT 21 /* EXID[15:0]: Extended identifier */ -- cgit v1.2.3 From 0bd415365d4fee0df9d51959803f86ccfa5ecad8 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Tue, 30 Oct 2012 10:22:52 +1030 Subject: STM32F4: New adc module Note adc.h was provided by Matthew Lai but was never merged. adc.c is new. --- include/libopencm3/stm32/f4/adc.h | 873 +++++++++++++++++++++++++++++++ lib/stm32/f4/adc.c | 1027 +++++++++++++++++++++++++++++++++++++ 2 files changed, 1900 insertions(+) create mode 100644 include/libopencm3/stm32/f4/adc.h create mode 100644 lib/stm32/f4/adc.c (limited to 'include') diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h new file mode 100644 index 0000000..272c4c2 --- /dev/null +++ b/include/libopencm3/stm32/f4/adc.h @@ -0,0 +1,873 @@ +/** @defgroup STM32F4xx_adc_defines ADC Defines + +@brief Defined Constants and Types for the STM32F4xx Analog to Digital Converters + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Matthew Lai +@author @htmlonly © @endhtmlonly 2009 Edward Cheeseman + +@date 31 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Matthew Lai + * Copyright (C) 2009 Edward Cheeseman + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC port base addresses (for convenience) */ +/****************************************************************************/ +/** @defgroup adc_reg_base ADC register base addresses +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC1 ADC1_BASE +#define ADC2 ADC2_BASE +#define ADC3 ADC3_BASE +/**@}*/ + +/* --- ADC registers ------------------------------------------------------- */ + +/* ADC status register (ADC_SR) */ +#define ADC_SR(block) MMIO32(block + 0x00) +#define ADC1_SR ADC_SR(ADC1) +#define ADC2_SR ADC_SR(ADC2) +#define ADC3_SR ADC_SR(ADC3) + +/* ADC control register 1 (ADC_CR1) */ +#define ADC_CR1(block) MMIO32(block + 0x04) +#define ADC1_CR1 ADC_CR1(ADC1) +#define ADC2_CR1 ADC_CR1(ADC2) +#define ADC3_CR1 ADC_CR1(ADC3) + +/* ADC control register 2 (ADC_CR2) */ +#define ADC_CR2(block) MMIO32(block + 0x08) +#define ADC1_CR2 ADC_CR2(ADC1) +#define ADC2_CR2 ADC_CR2(ADC2) +#define ADC3_CR2 ADC_CR2(ADC3) + +/* ADC sample time register 1 (ADC_SMPR1) */ +#define ADC_SMPR1(block) MMIO32(block + 0x0c) +#define ADC1_SMPR1 ADC_SMPR1(ADC1) +#define ADC2_SMPR1 ADC_SMPR1(ADC2) +#define ADC3_SMPR1 ADC_SMPR1(ADC3) + +/* ADC sample time register 2 (ADC_SMPR2) */ +#define ADC_SMPR2(block) MMIO32(block + 0x10) +#define ADC1_SMPR2 ADC_SMPR2(ADC1) +#define ADC2_SMPR2 ADC_SMPR2(ADC2) +#define ADC3_SMPR2 ADC_SMPR2(ADC3) + +/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ +#define ADC_JOFR1(block) MMIO32(block + 0x14) +#define ADC_JOFR2(block) MMIO32(block + 0x18) +#define ADC_JOFR3(block) MMIO32(block + 0x1c) +#define ADC_JOFR4(block) MMIO32(block + 0x20) +#define ADC1_JOFR1 ADC_JOFR1(ADC1) +#define ADC2_JOFR1 ADC_JOFR1(ADC2) +#define ADC3_JOFR1 ADC_JOFR1(ADC3) +#define ADC1_JOFR2 ADC_JOFR2(ADC1) +#define ADC2_JOFR2 ADC_JOFR2(ADC2) +#define ADC3_JOFR2 ADC_JOFR2(ADC3) +#define ADC1_JOFR3 ADC_JOFR3(ADC1) +#define ADC2_JOFR3 ADC_JOFR3(ADC2) +#define ADC3_JOFR3 ADC_JOFR3(ADC3) +#define ADC1_JOFR4 ADC_JOFR4(ADC1) +#define ADC2_JOFR4 ADC_JOFR4(ADC2) +#define ADC3_JOFR4 ADC_JOFR4(ADC3) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC_HTR(block) MMIO32(block + 0x24) +#define ADC1_HTR ADC_HTR(ADC1) +#define ADC2_HTR ADC_HTR(ADC2) +#define ADC3_HTR ADC_HTR(ADC3) + +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC_LTR(block) MMIO32(block + 0x28) +#define ADC1_LTR ADC_LTR(ADC1_BASE) +#define ADC2_LTR ADC_LTR(ADC2_BASE) +#define ADC3_LTR ADC_LTR(ADC3_BASE) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC_SQR1(block) MMIO32(block + 0x2c) +#define ADC1_SQR1 ADC_SQR1(ADC1) +#define ADC2_SQR1 ADC_SQR1(ADC2) +#define ADC3_SQR1 ADC_SQR1(ADC3) + +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC_SQR2(block) MMIO32(block + 0x30) +#define ADC1_SQR2 ADC_SQR2(ADC1) +#define ADC2_SQR2 ADC_SQR2(ADC2) +#define ADC3_SQR2 ADC_SQR2(ADC3) + +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC_SQR3(block) MMIO32(block + 0x34) +#define ADC1_SQR3 ADC_SQR3(ADC1) +#define ADC2_SQR3 ADC_SQR3(ADC2) +#define ADC3_SQR3 ADC_SQR3(ADC3) + +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC_JSQR(block) MMIO32(block + 0x38) +#define ADC1_JSQR ADC_JSQR(ADC1_BASE) +#define ADC2_JSQR ADC_JSQR(ADC2_BASE) +#define ADC3_JSQR ADC_JSQR(ADC3_BASE) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC_JDR1(block) MMIO32(block + 0x3c) +#define ADC_JDR2(block) MMIO32(block + 0x40) +#define ADC_JDR3(block) MMIO32(block + 0x44) +#define ADC_JDR4(block) MMIO32(block + 0x48) +#define ADC1_JDR1 ADC_JDR1(ADC1) +#define ADC2_JDR1 ADC_JDR1(ADC2) +#define ADC3_JDR1 ADC_JDR1(ADC3) +#define ADC1_JDR2 ADC_JDR2(ADC1) +#define ADC2_JDR2 ADC_JDR2(ADC2) +#define ADC3_JDR2 ADC_JDR2(ADC3) +#define ADC1_JDR3 ADC_JDR3(ADC1) +#define ADC2_JDR3 ADC_JDR3(ADC2) +#define ADC3_JDR3 ADC_JDR3(ADC3) +#define ADC1_JDR4 ADC_JDR4(ADC1) +#define ADC2_JDR4 ADC_JDR4(ADC2) +#define ADC3_JDR4 ADC_JDR4(ADC3) + +/* ADC regular data register (ADC_DR) */ +#define ADC_DR(block) MMIO32(block + 0x4c) +#define ADC1_DR ADC_DR(ADC1) +#define ADC2_DR ADC_DR(ADC2) +#define ADC3_DR ADC_DR(ADC3) + +/* ADC common (shared) registers */ +#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) +#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) +#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) +#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) + +/* --- ADC Channels ------------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup adc_channel ADC Channel Numbers +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CHANNEL0 0x00 +#define ADC_CHANNEL1 0x01 +#define ADC_CHANNEL2 0x02 +#define ADC_CHANNEL3 0x03 +#define ADC_CHANNEL4 0x04 +#define ADC_CHANNEL5 0x05 +#define ADC_CHANNEL6 0x06 +#define ADC_CHANNEL7 0x07 +#define ADC_CHANNEL8 0x08 +#define ADC_CHANNEL9 0x09 +#define ADC_CHANNEL10 0x0A +#define ADC_CHANNEL11 0x0B +#define ADC_CHANNEL12 0x0C +#define ADC_CHANNEL13 0x0D +#define ADC_CHANNEL14 0x0E +#define ADC_CHANNEL15 0x0F +#define ADC_CHANNEL16 0x10 +#define ADC_CHANNEL17 0x11 +#define ADC_CHANNEL18 0x12 +/**@}*/ +#define ADC_MASK 0x1F +#define ADC_SHIFT 0 + +/* --- ADC_SR values ------------------------------------------------------- */ + +#define ADC_SR_OVR (1 << 5) +#define ADC_SR_STRT (1 << 4) +#define ADC_SR_JSTRT (1 << 3) +#define ADC_SR_JEOC (1 << 2) +#define ADC_SR_EOC (1 << 1) +#define ADC_SR_AWD (1 << 0) + +/* --- ADC_CR1 values specific to STM32F2,4------------------------------------ */ + +/* OVRIE: Overrun interrupt enable */ +#define ADC_CR1_OVRIE (1 << 26) + +/* RES[1:0]: Resolution */ +/****************************************************************************/ +/** @defgroup adc_cr1_res ADC Resolution. +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CR1_RES_12BIT (0x0 << 24) +#define ADC_CR1_RES_10BIT (0x1 << 24) +#define ADC_CR1_RES_8BIT (0x2 << 24) +#define ADC_CR1_RES_6BIT (0x3 << 24) +/**@}*/ +#define ADC_CR1_RES_MASK (0x3 << 24) +#define ADC_CR1_RES_SHIFT 24 + +/* Note: Bits [21:16] are reserved, and must be kept at reset value. */ + +/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */ + +/* AWDEN: Analog watchdog enable on regular channels */ +#define ADC_CR1_AWDEN (1 << 23) + +/* JAWDEN: Analog watchdog enable on injected channels */ +#define ADC_CR1_JAWDEN (1 << 22) + +/* DISCNUM[2:0]: Discontinuous mode channel count. */ +/****************************************************************************/ +/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13) +#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13) +#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13) +#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13) +#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13) +#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13) +#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13) +#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) +/**@}*/ +#define ADC_CR1_DISCNUM_MASK (0x7 << 13) +#define ADC_CR1_DISCNUM_SHIFT 13 + +/* JDISCEN: */ /** Discontinuous mode on injected channels. */ +#define ADC_CR1_JDISCEN (1 << 12) + +/* DISCEN: */ /** Discontinuous mode on regular channels. */ +#define ADC_CR1_DISCEN (1 << 11) + +/* JAUTO: */ /** Automatic Injection Group conversion. */ +#define ADC_CR1_JAUTO (1 << 10) + +/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */ +#define ADC_CR1_AWDSGL (1 << 9) + +/* SCAN: */ /** Scan mode. */ +#define ADC_CR1_SCAN (1 << 8) + +/* JEOCIE: */ /** Interrupt enable for injected channels. */ +#define ADC_CR1_JEOCIE (1 << 7) + +/* AWDIE: */ /** Analog watchdog interrupt enable. */ +#define ADC_CR1_AWDIE (1 << 6) + +/* EOCIE: */ /** Interrupt enable EOC. */ +#define ADC_CR1_EOCIE (1 << 5) + +/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ +/* Notes: + * ADC1: Analog channel 16 and 17 are internally connected to the temperature + * sensor and V_REFINT, respectively. + * ADC2: Analog channel 16 and 17 are internally connected to V_SS. + * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS. + */ +/****************************************************************************/ +/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */ +/** @defgroup adc_watchdog_channel ADC watchdog channel +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0) +#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0) +#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0) +#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0) +#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0) +#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0) +#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0) +#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0) +#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0) +#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0) +#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0) +#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0) +#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0) +#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0) +#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0) +#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0) +#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0) +#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) +/**@}*/ +#define ADC_CR1_AWDCH_MASK (0x1F << 0) +#define ADC_CR1_AWDCH_SHIFT 0 + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +/* SWSTART: Start conversion of regular channels. */ +#define ADC_CR2_SWSTART (1 << 30) + +/* EXTEN[1:0]: External trigger enable for regular channels. */ +/****************************************************************************/ +/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CR2_EXTEN_DISABLED (0x0 << 28) +#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28) +#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28) +#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28) +/**@}*/ +#define ADC_CR2_EXTEN_MASK (0x3 << 28) +#define ADC_CR2_EXTEN_SHIFT 28 + +/* EXTSEL[3:0]: External event selection for regular group. */ +/****************************************************************************/ +/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group +@ingroup STM32F4xx_adc_defines + +@{*/ +/** Timer 1 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) +/** Timer 1 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) +/** Timer 1 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) +/** Timer 2 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) +/** Timer 2 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24) +/** Timer 2 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24) +/** Timer 2 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24) +/** Timer 3 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24) +/** Timer 3 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24) +/** Timer 4 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24) +/** Timer 5 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24) +/** Timer 5 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24) +/** Timer 5 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24) +/** Timer 8 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24) +/** Timer 8 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24) +/** EXTI Line 11 Event */ +#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24) +/**@}*/ +#define ADC_CR2_EXTSEL_MASK (0xF << 24) +#define ADC_CR2_EXTSEL_SHIFT 24 + +/* Bit 23 is reserved */ + +/* JSWSTART: Start conversion of injected channels. */ +#define ADC_CR2_JSWSTART (1 << 22) + +/* JEXTEN[1:0]: External trigger enable for injected channels. */ +/****************************************************************************/ +/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20) +#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20) +#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20) +#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20) +/**@}*/ +#define ADC_CR2_JEXTEN_MASK (0x3 << 20) +#define ADC_CR2_JEXTEN_SHIFT 20 + +/* JEXTSEL[3:0]: External event selection for injected group. */ +/****************************************************************************/ +/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16) +#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16) +#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16) +#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16) +#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16) +#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16) +#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16) +#define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16) +/**@}*/ +#define ADC_CR2_JEXTSEL_MASK (0xF << 16) +#define ADC_CR2_JEXTSEL_SHIFT 16 + +/* ALIGN: Data alignement. */ +#define ADC_CR2_ALIGN_RIGHT (0 << 11) +#define ADC_CR2_ALIGN_LEFT (1 << 11) +#define ADC_CR2_ALIGN (1 << 11) + +/* EOCS: End of conversion selection. */ +#define ADC_CR2_EOCS (1 << 10) + +/* DDS: DMA disable selection */ +#define ADC_CR2_DDS (1 << 9) + +/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ +#define ADC_CR2_DMA (1 << 8) + +/* Note: Bits [7:2] are reserved and must be kept at reset value. */ + +/* CONT: Continous conversion. */ +#define ADC_CR2_CONT (1 << 1) + +/* ADON: A/D converter On/Off. */ +/* Note: If any other bit in this register apart from ADON is changed at the + * same time, then conversion is not triggered. This is to prevent triggering + * an erroneous conversion. + * Conclusion: Must be separately written. + */ +#define ADC_CR2_ADON (1 << 0) + +/* --- ADC_SMPR1 values ---------------------------------------------------- */ + +#define ADC_SMPR1_SMP17_LSB 21 +#define ADC_SMPR1_SMP16_LSB 18 +#define ADC_SMPR1_SMP15_LSB 15 +#define ADC_SMPR1_SMP14_LSB 12 +#define ADC_SMPR1_SMP13_LSB 9 +#define ADC_SMPR1_SMP12_LSB 6 +#define ADC_SMPR1_SMP11_LSB 3 +#define ADC_SMPR1_SMP10_LSB 0 +#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) +#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) +#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) +#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) +#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) +#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) +#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) +#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) +/****************************************************************************/ +/* ADC_SMPR1 ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1 +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_SMPR1_SMP_1DOT5CYC 0x0 +#define ADC_SMPR1_SMP_7DOT5CYC 0x1 +#define ADC_SMPR1_SMP_13DOT5CYC 0x2 +#define ADC_SMPR1_SMP_28DOT5CYC 0x3 +#define ADC_SMPR1_SMP_41DOT5CYC 0x4 +#define ADC_SMPR1_SMP_55DOT5CYC 0x5 +#define ADC_SMPR1_SMP_71DOT5CYC 0x6 +#define ADC_SMPR1_SMP_239DOT5CYC 0x7 +/**@}*/ + +/* --- ADC_SMPR2 values ---------------------------------------------------- */ + +#define ADC_SMPR2_SMP9_LSB 27 +#define ADC_SMPR2_SMP8_LSB 24 +#define ADC_SMPR2_SMP7_LSB 21 +#define ADC_SMPR2_SMP6_LSB 18 +#define ADC_SMPR2_SMP5_LSB 15 +#define ADC_SMPR2_SMP4_LSB 12 +#define ADC_SMPR2_SMP3_LSB 9 +#define ADC_SMPR2_SMP2_LSB 6 +#define ADC_SMPR2_SMP1_LSB 3 +#define ADC_SMPR2_SMP0_LSB 0 +#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) +#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) +#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) +#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) +#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) +#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) +#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) +#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) +#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) +#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) +/****************************************************************************/ +/* ADC_SMPR2 ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2 +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_SMPR2_SMP_1DOT5CYC 0x0 +#define ADC_SMPR2_SMP_7DOT5CYC 0x1 +#define ADC_SMPR2_SMP_13DOT5CYC 0x2 +#define ADC_SMPR2_SMP_28DOT5CYC 0x3 +#define ADC_SMPR2_SMP_41DOT5CYC 0x4 +#define ADC_SMPR2_SMP_55DOT5CYC 0x5 +#define ADC_SMPR2_SMP_71DOT5CYC 0x6 +#define ADC_SMPR2_SMP_239DOT5CYC 0x7 +/**@}*/ + +/* --- ADC_SMPRx generic values -------------------------------------------- */ +/****************************************************************************/ +/* ADC_SMPRG ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_SMPR_SMP_1DOT5CYC 0x0 +#define ADC_SMPR_SMP_7DOT5CYC 0x1 +#define ADC_SMPR_SMP_13DOT5CYC 0x2 +#define ADC_SMPR_SMP_28DOT5CYC 0x3 +#define ADC_SMPR_SMP_41DOT5CYC 0x4 +#define ADC_SMPR_SMP_55DOT5CYC 0x5 +#define ADC_SMPR_SMP_71DOT5CYC 0x6 +#define ADC_SMPR_SMP_239DOT5CYC 0x7 +/**@}*/ + +/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ + +#define ADC_JOFFSET_LSB 0 +#define ADC_JOFFSET_MSK (0x7ff << 0) +#define ADC_HT_LSB 0 +#define ADC_HT_MSK (0x7ff << 0) +#define ADC_LT_LSB 0 +#define ADC_LT_MSK (0x7ff << 0) + +/* --- ADC_SQR1 values ----------------------------------------------------- */ + +#define ADC_SQR1_L_LSB 20 +#define ADC_SQR1_SQ16_LSB 15 +#define ADC_SQR1_SQ15_LSB 10 +#define ADC_SQR1_SQ14_LSB 5 +#define ADC_SQR1_SQ13_LSB 0 +#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) +#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) +#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) +#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) +#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) + +/* --- ADC_SQR2 values ----------------------------------------------------- */ + +#define ADC_SQR2_SQ12_LSB 25 +#define ADC_SQR2_SQ11_LSB 20 +#define ADC_SQR2_SQ10_LSB 15 +#define ADC_SQR2_SQ9_LSB 10 +#define ADC_SQR2_SQ8_LSB 5 +#define ADC_SQR2_SQ7_LSB 0 +#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) +#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) +#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) +#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) +#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) +#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) + +/* --- ADC_SQR3 values ----------------------------------------------------- */ + +#define ADC_SQR3_SQ6_LSB 25 +#define ADC_SQR3_SQ5_LSB 20 +#define ADC_SQR3_SQ4_LSB 15 +#define ADC_SQR3_SQ3_LSB 10 +#define ADC_SQR3_SQ2_LSB 5 +#define ADC_SQR3_SQ1_LSB 0 +#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) +#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) +#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) +#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) +#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) +#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) + +/* --- ADC_JSQR values ----------------------------------------------------- */ + +#define ADC_JSQR_JL_LSB 20 +#define ADC_JSQR_JSQ4_LSB 15 +#define ADC_JSQR_JSQ3_LSB 10 +#define ADC_JSQR_JSQ2_LSB 5 +#define ADC_JSQR_JSQ1_LSB 0 + +/* JL[2:0]: Discontinous mode channel count injected channels. */ +/****************************************************************************/ +/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels. +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB) +/**@}*/ +#define ADC_JSQR_JL_SHIFT 13 +#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) +#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) +#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) +#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) + +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) + +/* --- Common Registers ---------------------------------------------------- */ + +/* --- ADC_CSR values (read only images) ------------------------------------ */ + +/* OVR3: Overrun ADC3. */ +#define ADC_CSR_OVR3 (1 << 21) + +/* STRT3: Regular channel start ADC3. */ +#define ADC_CSR_STRT3 (1 << 20) + +/* JSTRT3: Injected channel start ADC3. */ +#define ADC_CSR_JSTRT3 (1 << 19) + +/* JEOC3: Injected channel end of conversion ADC3. */ +#define ADC_CSR_JEOC3 (1 << 18) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_EOC3 (1 << 17) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_AWD3 (1 << 16) + +/* Bits 15:14 Reserved, must be kept at reset value */ + +/* OVR2: Overrun ADC2. */ +#define ADC_CSR_OVR2 (1 << 13) + +/* STRT2: Regular channel start ADC2. */ +#define ADC_CSR_STRT2 (1 << 12) + +/* JSTRT2: Injected channel start ADC2. */ +#define ADC_CSR_JSTRT2 (1 << 11) + +/* JEOC2: Injected channel end of conversion ADC2. */ +#define ADC_CSR_JEOC2 (1 << 10) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_EOC2 (1 << 9) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_AWD2 (1 << 8) + +/* Bits 7:6 Reserved, must be kept at reset value */ + +/* OVR1: Overrun ADC1. */ +#define ADC_CSR_OVR1 (1 << 5) + +/* STRT1: Regular channel start ADC1. */ +#define ADC_CSR_STRT1 (1 << 4) + +/* JSTRT1: Injected channel start ADC1. */ +#define ADC_CSR_JSTRT1 (1 << 3) + +/* JEOC1: Injected channel end of conversion ADC1. */ +#define ADC_CSR_JEOC1 (1 << 2) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_EOC1 (1 << 1) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_AWD1 (1 << 0) + +/* --- ADC_CCR values ------------------------------------------------------ */ + +/* TSVREFE: Temperature sensor and Vrefint enable. */ +#define ADC_CCR_TSVREFE (1 << 23) + +/* VBATE: VBat enable. */ +#define ADC_CCR_VBATE (1 << 22) + +/* Bit 18:21 reserved, must be kept at reset value. */ + +/* ADCPRE: ADC prescaler. */ +/****************************************************************************/ +/** @defgroup adc_ccr_adcpre ADC Prescale +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CCR_ADCPRE_BY2 (0x0 << 16) +#define ADC_CCR_ADCPRE_BY4 (0x1 << 16) +#define ADC_CCR_ADCPRE_BY6 (0x2 << 16) +#define ADC_CCR_ADCPRE_BY8 (0x3 << 16) +/**@}*/ +#define ADC_CCR_ADCPRE_MASK (0x3 << 16) +#define ADC_CCR_ADCPRE_SHIFT 16 + +/* DMA: Direct memory access mode for multi ADC mode. */ +/****************************************************************************/ +/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CCR_DMA_DISABLE (0x0 << 14) +#define ADC_CCR_DMA_MODE_1 (0x1 << 14) +#define ADC_CCR_DMA_MODE_2 (0x2 << 14) +#define ADC_CCR_DMA_MODE_3 (0x3 << 14) +/**@}*/ +#define ADC_CCR_DMA_MASK (0x3 << 14) +#define ADC_CCR_DMA_SHIFT 14 + +/* DDS: DMA disable selection (for multi-ADC mode). */ +#define ADC_CCR_DDS (1 << 13) + +/* Bit 12 reserved, must be kept at reset value */ + +/* DELAY: Delay between 2 sampling phases. */ +/****************************************************************************/ +/** @defgroup adc_delay ADC Delay between 2 sampling phases +@ingroup STM32F4xx_adc_defines + +@{*/ +#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8) +#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8) +#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8) +#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8) +#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8) +#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8) +#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8) +#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8) +#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8) +#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8) +#define ADC_CCR_DELAY_15ADCCLK (0xa << 8) +#define ADC_CCR_DELAY_16ADCCLK (0xb << 8) +#define ADC_CCR_DELAY_17ADCCLK (0xc << 8) +#define ADC_CCR_DELAY_18ADCCLK (0xd << 8) +#define ADC_CCR_DELAY_19ADCCLK (0xe << 8) +#define ADC_CCR_DELAY_20ADCCLK (0xf << 8) +/**@}*/ +#define ADC_CCR_DELAY_MASK (0xf << 8) +#define ADC_CCR_DELAY_SHIFT 8 + +/* Bit 7:5 reserved, must be kept at reset value */ + +/* MULTI: Multi ADC mode selection. */ +/****************************************************************************/ +/** @defgroup adc_multi_mode ADC Multi mode selection +@ingroup STM32F4xx_adc_defines + +@{*/ + +/** All ADCs independent */ +#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) + +/* dual modes (ADC1 + ADC2) */ +/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) +/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) +/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) +/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) +/** Dual modes (ADC1 + ADC2) Interleaved mode only. */ +#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) +/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) + +/* Triple modes (ADC1 + ADC2 + ADC3) */ +/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) +/**@}*/ + +#define ADC_CCR_MULTI_MASK (0x1f << 0) +#define ADC_CCR_MULTI_SHIFT 0 + +/* --- ADC_CDR values ------------------------------------------------------ */ + +#define ADC_CDR_DATA2_MASK (0xffff << 16) +#define ADC_CDR_DATA2_SHIFT 16 + +#define ADC_CDR_DATA1_MASK (0xffff << 0) +#define ADC_CDR_DATA1_SHIFT 0 + +BEGIN_DECLS + +void adc_power_on(u32 adc); +void adc_off(u32 adc); +void adc_enable_analog_watchdog_regular(u32 adc); +void adc_disable_analog_watchdog_regular(u32 adc); +void adc_enable_analog_watchdog_injected(u32 adc); +void adc_disable_analog_watchdog_injected(u32 adc); +void adc_enable_discontinuous_mode_regular(u32 adc, u8 length); +void adc_disable_discontinuous_mode_regular(u32 adc); +void adc_enable_discontinuous_mode_injected(u32 adc); +void adc_disable_discontinuous_mode_injected(u32 adc); +void adc_enable_automatic_injected_group_conversion(u32 adc); +void adc_disable_automatic_injected_group_conversion(u32 adc); +void adc_enable_analog_watchdog_on_all_channels(u32 adc); +void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel); +void adc_enable_scan_mode(u32 adc); +void adc_disable_scan_mode(u32 adc); +void adc_enable_eoc_interrupt_injected(u32 adc); +void adc_disable_eoc_interrupt_injected(u32 adc); +void adc_enable_awd_interrupt(u32 adc); +void adc_disable_awd_interrupt(u32 adc); +void adc_enable_eoc_interrupt(u32 adc); +void adc_disable_eoc_interrupt(u32 adc); +void adc_start_conversion_regular(u32 adc); +void adc_start_conversion_injected(u32 adc); +void adc_disable_external_trigger_regular(u32 adc); +void adc_disable_external_trigger_injected(u32 adc); +void adc_set_left_aligned(u32 adc); +void adc_set_right_aligned(u32 adc); +void adc_enable_dma(u32 adc); +void adc_disable_dma(u32 adc); +void adc_set_continuous_conversion_mode(u32 adc); +void adc_set_single_conversion_mode(u32 adc); +void adc_set_sample_time(u32 adc, u8 channel, u8 time); +void adc_set_sample_time_on_all_channels(u32 adc, u8 time); +void adc_set_watchdog_high_threshold(u32 adc, u16 threshold); +void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); +void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); +void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); +bool adc_eoc(u32 adc); +bool adc_eoc_injected(u32 adc); +u32 adc_read_regular(u32 adc); +u32 adc_read_injected(u32 adc, u8 reg); +void adc_set_injected_offset(u32 adc, u8 reg, u32 offset); + +void adc_set_clk_prescale(u32 prescaler); +void adc_set_multi_mode(u32 mode); +void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity); +void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity); +void adc_set_resolution(u32 adc, u16 resolution); +void adc_enable_overrun_interrupt(u32 adc); +void adc_disable_overrun_interrupt(u32 adc); +bool adc_get_overrun_flag(u32 adc); +void adc_clear_overrun_flag(u32 adc); +bool adc_awd(u32 adc); +void adc_eoc_after_each(u32 adc); +void adc_eoc_after_group(u32 adc); +void adc_set_dma_continue(u32 adc); +void adc_set_dma_terminate(u32 adc); +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); + +END_DECLS + +/**@}*/ + +#endif diff --git a/lib/stm32/f4/adc.c b/lib/stm32/f4/adc.c new file mode 100644 index 0000000..7475fac --- /dev/null +++ b/lib/stm32/f4/adc.c @@ -0,0 +1,1027 @@ +/** @defgroup STM32F4xx_adc_file ADC + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx Analog to Digital Converters + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 30 August 2012 + +This library supports the A/D Converter Control System in the STM32 series +of ARM Cortex Microcontrollers by ST Microelectronics. + +Devices can have up to three A/D converters each with their own set of registers. +However all the A/D converters share a common clock which is prescaled from the APB2 +clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution +can be set to 12, 10, 8 or 6 bits. + +Each A/D converter has up to 19 channels: +@li On ADC1 the analog channels 16 is internally connected to the temperature +sensor, channel 17 to VREFINT, and channel 18 to VBATT. +@li On ADC2 and ADC3 the analog channels 16 - 18 are not used. + +The conversions can occur as a one-off conversion whereby the process stops once +conversion is complete. The conversions can also be continuous wherein a new +conversion starts immediately the previous conversion has ended. + +Conversion can occur as a single channel conversion or a scan of a group of +channels in either continuous or one-off mode. If more than one channel is converted +in a scan group, DMA must be used to transfer the data as there is only one +result register available. An interrupt can be set to occur at the end of +conversion, which occurs after all channels have been scanned. + +A discontinuous mode allows a subgroup of group of a channels to be converted in +bursts of a given length. + +Injected conversions allow a second group of channels to be converted separately +from the regular group. An interrupt can be set to occur at the end of +conversion, which occurs after all channels have been scanned. + +@section adc_f4_api_ex Basic ADC Handling API. + +Example 1: Simple single channel conversion polled. Enable the peripheral clock +and ADC, reset ADC and set the prescaler divider. Set multiple mode to independent. + +@code +gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); +rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); +adc_set_clk_prescale(RCC_CFGR_ADCPRE_BY2); +adc_disable_scan_mode(ADC1); +adc_set_single_conversion_mode(ADC1); +adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); +u8 channels[] = ADC_CHANNEL0; +adc_set_regular_sequence(ADC1, 1, channels); +adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); +adc_power_on(ADC1); +adc_start_conversion_regular(ADC1); +while (! adc_eoc(ADC1)); +reg16 = adc_read_regular(ADC1); +@endcode + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Off + +Turn off the ADC to reduce power consumption to a few microamps. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_off(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_ADON; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Analog Watchdog for Regular Conversions + +The analog watchdog allows the monitoring of an analog signal between two threshold +levels. The thresholds must be preset. Comparison is done before data alignment +takes place, so the thresholds are left-aligned. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_analog_watchdog_regular(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_AWDEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Analog Watchdog for Regular Conversions + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_analog_watchdog_regular(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_AWDEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Analog Watchdog for Injected Conversions + +The analog watchdog allows the monitoring of an analog signal between two threshold +levels. The thresholds must be preset. Comparison is done before data alignment +takes place, so the thresholds are left-aligned. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_analog_watchdog_injected(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_JAWDEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Analog Watchdog for Injected Conversions + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_analog_watchdog_injected(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_JAWDEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Discontinuous Mode for Regular Conversions + +In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the +defined regular channel group. The subgroup is defined by the number of +consecutive channels to be converted. After a subgroup has been converted +the next trigger will start conversion of the immediately following subgroup +of the same length or until the whole group has all been converted. When the +the whole group has been converted, the next trigger will restart conversion +of the subgroup at the beginning of the whole group. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum +*/ + +void adc_enable_discontinuous_mode_regular(u32 adc, u8 length) +{ + if ( (length-1) > 7 ) return; + ADC_CR1(adc) |= ADC_CR1_DISCEN; + ADC_CR2(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Discontinuous Mode for Regular Conversions + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_discontinuous_mode_regular(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_DISCEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Discontinuous Mode for Injected Conversions + +In this mode the ADC converts sequentially one channel of the defined group of +injected channels, cycling back to the first channel in the group once the +entire group has been converted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_discontinuous_mode_injected(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_JDISCEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Discontinuous Mode for Injected Conversions + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_discontinuous_mode_injected(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Automatic Injected Conversions + +The ADC converts a defined injected group of channels immediately after the +regular channels have been converted. The external trigger on the injected +channels is disabled as required. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_automatic_injected_group_conversion(u32 adc) +{ + adc_disable_external_trigger_injected(adc); + ADC_CR1(adc) |= ADC_CR1_JAUTO; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Automatic Injected Conversions + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_automatic_injected_group_conversion(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_JAUTO; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels + +The analog watchdog allows the monitoring of an analog signal between two threshold +levels. The thresholds must be preset. Comparison is done before data alignment +takes place, so the thresholds are left-aligned. + +@note The analog watchdog must be enabled for either or both of the regular or +injected channels. If neither are enabled, the analog watchdog feature will be +disabled. +@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_analog_watchdog_on_all_channels(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Analog Watchdog for a Selected Channel + +The analog watchdog allows the monitoring of an analog signal between two threshold +levels. The thresholds must be preset. Comparison is done before data alignment +takes place, so the thresholds are left-aligned. + +@note The analog watchdog must be enabled for either or both of the regular or +injected channels. If neither are enabled, the analog watchdog feature will be +disabled. If both are enabled, the same channel number is monitored. +@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel +*/ + +void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel) +{ + u32 reg32; + + reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */ + if (channel < 18) + reg32 |= channel; + ADC_CR1(adc) = reg32; + ADC_CR1(adc) |= ADC_CR1_AWDSGL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set Scan Mode + +In this mode a conversion consists of a scan of the predefined set of channels, +regular and injected, each channel conversion immediately following the +previous one. It can use single, continuous or discontinuous mode. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_scan_mode(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_SCAN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Scan Mode + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_scan_mode(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_SCAN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Injected End-Of-Conversion Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_eoc_interrupt_injected(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_JEOCIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Injected End-Of-Conversion Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_eoc_interrupt_injected(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Analog Watchdog Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_awd_interrupt(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_AWDIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Analog Watchdog Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_awd_interrupt(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_AWDIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Regular End-Of-Conversion Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_eoc_interrupt(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_EOCIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable Regular End-Of-Conversion Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_eoc_interrupt(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_EOCIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Software Triggered Conversion on Regular Channels + +This starts conversion on a set of defined regular channels. It is cleared by +hardware once conversion starts. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_start_conversion_regular(u32 adc) +{ + /* Start conversion on regular channels. */ + ADC_CR2(adc) |= ADC_CR2_SWSTART; + + /* Wait until the ADC starts the conversion. */ + while (ADC_CR2(adc) & ADC_CR2_SWSTART); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Software Triggered Conversion on Injected Channels + +This starts conversion on a set of defined injected channels. It is cleared by +hardware once conversion starts. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_start_conversion_injected(u32 adc) +{ + /* Start conversion on injected channels. */ + ADC_CR2(adc) |= ADC_CR2_JSWSTART; + + /* Wait until the ADC starts the conversion. */ + while (ADC_CR2(adc) & ADC_CR2_JSWSTART); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set the Data as Left Aligned + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_left_aligned(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_ALIGN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set the Data as Right Aligned + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_right_aligned(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_ALIGN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable DMA Transfers + +Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5. +ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer +mode. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_dma(u32 adc) +{ + if ((adc == ADC1) | (adc == ADC3)) + ADC_CR2(adc) |= ADC_CR2_DMA; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable DMA Transfers + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_dma(u32 adc) +{ + if ((adc == ADC1) | (adc == ADC3)) + ADC_CR2(adc) &= ~ADC_CR2_DMA; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Continuous Conversion Mode + +In this mode the ADC starts a new conversion of a single channel or a channel +group immediately following completion of the previous channel group conversion. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_continuous_conversion_mode(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_CONT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable Single Conversion Mode + +In this mode the ADC performs a conversion of one channel or a channel group +and stops. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_single_conversion_mode(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_CONT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for a Single Channel + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg +*/ + +void adc_set_sample_time(u32 adc, u8 channel, u8 time) +{ + u32 reg32; + + if (channel < 10) { + reg32 = ADC_SMPR2(adc); + reg32 &= ~(0x7 << (channel * 3)); + reg32 |= (time << (channel * 3)); + ADC_SMPR2(adc) = reg32; + } else { + reg32 = ADC_SMPR1(adc); + reg32 &= ~(0x7 << ((channel - 10) * 3)); + reg32 |= (time << ((channel - 10) * 3)); + ADC_SMPR1(adc) = reg32; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for All Channels + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for +all channels. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg +*/ + +void adc_set_sample_time_on_all_channels(u32 adc, u8 time) +{ + u8 i; + u32 reg32 = 0; + + for (i = 0; i <= 9; i++) + reg32 |= (time << (i * 3)); + ADC_SMPR2(adc) = reg32; + + for (i = 10; i <= 17; i++) + reg32 |= (time << ((i - 10) * 3)); + ADC_SMPR1(adc) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set Analog Watchdog Upper Threshold + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] threshold Unsigned int8. Upper threshold value +*/ + +void adc_set_watchdog_high_threshold(u32 adc, u16 threshold) +{ + u32 reg32 = 0; + + reg32 = (u32)threshold; + reg32 &= ~0xfffff000; /* Clear all bits above 11. */ + ADC_HTR(adc) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set Analog Watchdog Lower Threshold + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] threshold Unsigned int8. Lower threshold value +*/ + +void adc_set_watchdog_low_threshold(u32 adc, u16 threshold) +{ + u32 reg32 = 0; + + reg32 = (u32)threshold; + reg32 &= ~0xfffff000; /* Clear all bits above 11. */ + ADC_LTR(adc) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set a Regular Channel Conversion Sequence + +Define a sequence of channels to be converted as a regular group with a length +from 1 to 16 channels. If this is called during conversion, the current conversion +is reset and conversion begins again with the newly defined group. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] length Unsigned int8. Number of channels in the group. +@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18. +*/ + +void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) +{ + u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0; + u8 i = 0; + + /* Maximum sequence length is 16 channels. */ + if (length > 16) + return; + + for (i = 1; i <= length; i++) { + if (i <= 6) + reg32_3 |= (channel[i - 1] << ((i - 1) * 5)); + if ((i > 6) & (i <= 12)) + reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5)); + if ((i > 12) & (i <= 16)) + reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5)); + } + reg32_1 |= ((length -1) << ADC_SQR1_L_LSB); + + ADC_SQR1(adc) = reg32_1; + ADC_SQR2(adc) = reg32_2; + ADC_SQR3(adc) = reg32_3; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set an Injected Channel Conversion Sequence + +Defines a sequence of channels to be converted as an injected group with a length +from 1 to 4 channels. If this is called during conversion, the current conversion +is reset and conversion begins again with the newly defined group. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] length Unsigned int8. Number of channels in the group. +@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18 +*/ + +void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) +{ + u32 reg32 = 0; + u8 i = 0; + + /* Maximum sequence length is 4 channels. */ + if ((length-1) > 3) + return; + + for (i = 1; i <= length; i++) + reg32 |= (channel[4 - i] << ((4 - i) * 5)); + + reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); + + ADC_JSQR(adc) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read the End-of-Conversion Flag + +This flag is set after all channels of a regular or injected group have been +converted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. End of conversion flag. +*/ + +bool adc_eoc(u32 adc) +{ + return ((ADC_SR(adc) & ADC_SR_EOC) != 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion + +This flag is set after all channels of an injected group have been converted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. End of conversion flag. +*/ + +bool adc_eoc_injected(u32 adc) +{ + return ((ADC_SR(adc) & ADC_SR_JEOC) != 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read from the Regular Conversion Result Register + +The result read back is 12 bits, right or left aligned within the first 16 bits. +For ADC1 only, the higher 16 bits will hold the result from ADC2 if +an appropriate dual mode has been set @see adc_set_dual_mode. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +u32 adc_read_regular(u32 adc) +{ + return ADC_DR(adc); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read from an Injected Conversion Result Register + +The result read back from the selected injected result register (one of four) is +12 bits, right or left aligned within the first 16 bits. The result can have a +negative value if the injected channel offset has been set @see adc_set_injected_offset. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] reg Unsigned int8. Register number (1 ... 4). +@returns Unsigned int32 conversion result. +*/ + +u32 adc_read_injected(u32 adc, u8 reg) +{ + switch (reg) { + case 1: + return ADC_JDR1(adc); + case 2: + return ADC_JDR2(adc); + case 3: + return ADC_JDR3(adc); + case 4: + return ADC_JDR4(adc); + } + return 0; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set the Injected Channel Data Offset + +This value is subtracted from the injected channel results after conversion +is complete, and can result in negative results. A separate value can be specified +for each injected data register. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] reg Unsigned int8. Register number (1 ... 4). +@param[in] offset Unsigned int32. +*/ + +void adc_set_injected_offset(u32 adc, u8 reg, u32 offset) +{ + switch (reg) { + case 1: + ADC_JOFR1(adc) = offset; + break; + case 2: + ADC_JOFR2(adc) = offset; + break; + case 3: + ADC_JOFR3(adc) = offset; + break; + case 4: + ADC_JOFR4(adc) = offset; + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Power On + +If the ADC is in power-down mode then it is powered up. The application needs +to wait a time of about 3 microseconds for stabilization before using the ADC. +If the ADC is already on this function call will have no effect. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_power_on(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_ADON; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set Clock Prescale + +The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. + +@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref adc_ccr_adcpre +*/ + +void adc_set_clk_prescale(u32 prescale) +{ + u32 reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale); + ADC_CCR = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set Dual/Triple Mode + +The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave +arrangement. This setting is applied to ADC1 only. + +The various modes possible are described in the reference manual. + +@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode +*/ + +void adc_set_multi_mode(u32 mode) +{ + ADC_CCR |= mode; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable an External Trigger for Regular Channels + +This enables an external trigger for set of defined regular channels, and sets the +polarity of the trigger event: rising or falling edge or both. Note that if the +trigger polarity is zero, triggering is disabled. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular +@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_regular +*/ + +void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity) +{ + u32 reg32 = ADC_CR2(adc); + + reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK); + reg32 |= (trigger | polarity); + ADC_CR2(adc) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable an External Trigger for Regular Channels + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_external_trigger_regular(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable an External Trigger for Injected Channels + +This enables an external trigger for set of defined injected channels, and sets the +polarity of the trigger event: rising or falling edge or both. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected +@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_injected +*/ + +void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity) +{ + u32 reg32 = ADC_CR2(adc); + + reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK); + reg32 |= (trigger | polarity); + ADC_CR2(adc) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable an External Trigger for Injected Channels + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_external_trigger_injected(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set Resolution + +ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a corresponding +reduction in conversion time (resolution + 3 ADC clock cycles). + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res +*/ + +void adc_set_resolution(u32 adc, u16 resolution) +{ + u32 reg32 = ADC_CR1(adc); + + reg32 &= ~ADC_CR1_RES_MASK; + reg32 |= resolution; + ADC_CR1(adc) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable the Overrun Interrupt + +The overrun interrupt is generated when data is not read from a result register +before the next conversion is written. If DMA is enabled, all transfers are +terminated and any conversion sequence is aborted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_overrun_interrupt(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_OVRIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable the Overrun Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_overrun_interrupt(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_OVRIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read the Overrun Flag + +The overrun flag is set when data is not read from a result register before the next +conversion is written. If DMA is enabled, all transfers are terminated and any +conversion sequence is aborted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +bool adc_get_overrun_flag(u32 adc) +{ + return (ADC_SR(adc) & ADC_SR_OVR); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Clear Overrun Flags + +The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. +The flag must be cleared and the DMA stream and ADC reinitialised to resume +conversions (see the reference manual). + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +void adc_clear_overrun_flag(u32 adc) +{ +/* need to write zero to clear this */ + ADC_SR(adc) &= ~ADC_SR_OVR; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable an EOC for Each Conversion + +The EOC is set after each conversion in a sequence rather than at the end of the +sequence. Overrun detection is enabled only if DMA is enabled. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_eoc_after_each(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_EOCS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable the EOC for Each Conversion + +The EOC is set at the end of each sequence rather than after each conversion in the +sequence. Overrun detection is enabled always. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_eoc_after_group(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_EOCS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set DMA to Continue + +This must be set to allow DMA to continue to operate after the last conversion in +the DMA sequence. This allows DMA to be used in continuous circular mode. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_dma_continue(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_DDS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set DMA to Terminate + +This must be set to allow DMA to terminate after the last conversion in the DMA +sequence. This can avoid overrun errors. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_dma_terminate(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_DDS; +} +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read the Analog Watchdog Flag + +This flag is set when the converted voltage crosses the high or low thresholds. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. AWD flag. +*/ + +bool adc_awd(u32 adc) +{ + return (ADC_SR(adc) & ADC_SR_AWD); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Enable The Temperature Sensor + +This enables both the sensor and the reference voltage measurements on channels +16 and 17. These are only available on ADC1 channel 16 and 17 respectively. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_temperature_sensor() +{ + ADC_CCR |= ADC_CCR_TSVREFE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Disable The Temperature Sensor + +Disabling this will reduce power consumption from the sensor and the reference +voltage measurements. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_temperature_sensor() +{ + ADC_CCR &= ~ADC_CCR_TSVREFE; +} + +/*-----------------------------------------------------------------------------*/ + +/**@}*/ + -- cgit v1.2.3 From 5a6b1a19344fe03aa84164ea97e4dadcc5a9709b Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 26 Oct 2012 23:50:44 +1030 Subject: STM32F1 Addition to DMA to add interrupt flag read and clear. Additional macros and defines added to header for the purpose. Also disable of increment modes (seem to have been omitted originally). --- include/libopencm3/stm32/f1/dma.h | 59 ++++++++++++++++++++-------- lib/stm32/f1/dma.c | 82 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 118 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h index b08803f..6e5cc20 100644 --- a/include/libopencm3/stm32/f1/dma.h +++ b/include/libopencm3/stm32/f1/dma.h @@ -141,9 +141,30 @@ LGPL License Terms @ref lgpl_license /* --- DMA_ISR values ------------------------------------------------------ */ +/* --- DMA Interrupt Flag offset values ------------------------------------- */ +/* These are based on every interrupt flag and flag clear being at the same relative location */ +/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group. +@ingroup STM32F1xx_dma_defines + +@{*/ +/** Transfer Error Interrupt Flag */ +#define DMA_TEIF (1 << 3) +/** Half Transfer Interrupt Flag */ +#define DMA_HTIF (1 << 2) +/** Transfer Complete Interrupt Flag */ +#define DMA_TCIF (1 << 1) +/** Global Interrupt Flag */ +#define DMA_GIF (1 << 0) +/**@}*/ + +/* Offset within interrupt status register to start of stream interrupt flag field */ +#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) +#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF) +#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel) + /* TEIF: Transfer error interrupt flag */ -#define DMA_ISR_TEIF_BIT (1 << 3) -#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (4 * ((channel) -1))) +#define DMA_ISR_TEIF_BIT DMA_ISR_TEIF +#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << DMA_FLAG_OFFSET(channel))) #define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) #define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) @@ -154,8 +175,8 @@ LGPL License Terms @ref lgpl_license #define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) /* HTIF: Half transfer interrupt flag */ -#define DMA_ISR_HTIF_BIT (1 << 2) -#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (4 * ((channel) -1))) +#define DMA_ISR_HTIF_BIT DMA_HTIF +#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << DMA_FLAG_OFFSET(channel))) #define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) #define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) @@ -166,8 +187,8 @@ LGPL License Terms @ref lgpl_license #define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) /* TCIF: Transfer complete interrupt flag */ -#define DMA_ISR_TCIF_BIT (1 << 1) -#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (4 * ((channel) -1))) +#define DMA_ISR_TCIF_BIT DMA_TCIF +#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) #define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) @@ -178,8 +199,8 @@ LGPL License Terms @ref lgpl_license #define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7) /* GIF: Global interrupt flag */ -#define DMA_ISR_GIF_BIT (1 << 0) -#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (4 * ((channel) -1))) +#define DMA_ISR_GIF_BIT DMA_GIF +#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) #define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) @@ -192,8 +213,8 @@ LGPL License Terms @ref lgpl_license /* --- DMA_IFCR values ----------------------------------------------------- */ /* CTEIF: Transfer error clear */ -#define DMA_IFCR_CTEIF_BIT (1 << 3) -#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * ((channel) -1))) +#define DMA_IFCR_CTEIF_BIT DMA_TEIF +#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) @@ -204,8 +225,8 @@ LGPL License Terms @ref lgpl_license #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) /* CHTIF: Half transfer clear */ -#define DMA_IFCR_CHTIF_BIT (1 << 2) -#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * ((channel) -1))) +#define DMA_IFCR_CHTIF_BIT DMA_HTIF +#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) @@ -216,8 +237,8 @@ LGPL License Terms @ref lgpl_license #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) /* CTCIF: Transfer complete clear */ -#define DMA_IFCR_CTCIF_BIT (1 << 1) -#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * ((channel) -1))) +#define DMA_IFCR_CTCIF_BIT DMA_TCIF +#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) @@ -228,8 +249,8 @@ LGPL License Terms @ref lgpl_license #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) /* CGIF: Global interrupt clear */ -#define DMA_IFCR_CGIF_BIT (1 << 0) -#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * ((channel) -1))) +#define DMA_IFCR_CGIF_BIT DMA_GIF +#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) @@ -241,7 +262,7 @@ LGPL License Terms @ref lgpl_license /* Clear interrupts mask */ #define DMA_IFCR_CIF_BIT 0xF -#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (4 * ((channel) - 1))) +#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) #define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) @@ -349,12 +370,16 @@ LGPL License Terms @ref lgpl_license BEGIN_DECLS void dma_channel_reset(u32 dma, u8 channel); +void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts); +bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupts); void dma_enable_mem2mem_mode(u32 dma, u8 channel); void dma_set_priority(u32 dma, u8 channel, u32 prio); void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size); void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size); void dma_enable_memory_increment_mode(u32 dma, u8 channel); +void dma_disable_memory_increment_mode(u32 dma, u8 channel); void dma_enable_peripheral_increment_mode(u32 dma, u8 channel); +void dma_disable_peripheral_increment_mode(u32 dma, u8 channel); void dma_enable_circular_mode(u32 dma, u8 channel); void dma_set_read_from_peripheral(u32 dma, u8 channel); void dma_set_read_from_memory(u32 dma, u8 channel); diff --git a/lib/stm32/f1/dma.c b/lib/stm32/f1/dma.c index 04cb8a1..c26020a 100644 --- a/lib/stm32/f1/dma.c +++ b/lib/stm32/f1/dma.c @@ -10,12 +10,18 @@ @date 18 August 2012 -This library supports the DMA -Control System in the STM32F1xx series of ARM Cortex Microcontrollers -by ST Microelectronics. It can provide for two DMA controllers, -one with 7 channels and one with 5. Channels are hardware dedicated -and each is shared with a number of different sources (only one can be -used at a time, under the responsibility of the programmer). +This library supports the DMA Control System in the STM32 series of ARM Cortex +Microcontrollers by ST Microelectronics. + +Up to two DMA controllers are supported. 12 DMA channels are allocated 7 to +the first DMA controller and 5 to the second. Each channel is connected to +between 3 and 6 hardware peripheral DMA signals in a logical OR arrangement. + +DMA transfers can be configured to occur between peripheral and memory in +any combination including memory to memory. Circular mode transfers are +also supported in transfers involving a peripheral. An arbiter is provided +to resolve priority DMA requests. Transfers can be made with 8, 16 or 32 bit +words. LGPL License Terms @ref lgpl_license */ @@ -67,6 +73,42 @@ void dma_channel_reset(u32 dma, u8 channel) DMA_IFCR(dma) |= DMA_IFCR_CIF(channel); } +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Clear Interrupt Flag + +The interrupt flag for the channel is cleared. More than one interrupt for the +same channel may be cleared by using the logical OR of the interrupt flags. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: @ref dma_st_number +@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset +*/ + +void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts) +{ +/* Get offset to interrupt flag location in channel field */ + u32 flags = (interrupts << DMA_FLAG_OFFSET(channel)); + DMA_IFCR(dma) = flags; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Read Interrupt Flag + +The interrupt flag for the channel is returned. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: @ref dma_st_number +@param[in] interrupt unsigned int32. Interrupt number: @ref dma_st_number +@returns bool interrupt flag is set. +*/ + +bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt) +{ +/* get offset to interrupt flag location in channel field. */ + u32 flag = (interrupt << DMA_FLAG_OFFSET(channel)); + return ((DMA_ISR(dma) & flag) > 0); +} + /*-----------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Memory to Memory Transfers @@ -160,11 +202,39 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel) @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ +void dma_disable_memory_increment_mode(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_MINC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Peripheral Increment after Transfer + +Following each transfer the current peripheral address is incremented by +1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The +value held by the base peripheral address register is unchanged. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + void dma_enable_peripheral_increment_mode(u32 dma, u8 channel) { DMA_CCR(dma, channel) |= DMA_CCR_PINC; } +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable Peripheral Increment after Transfer + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_disable_peripheral_increment_mode(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_PINC; +} + /*-----------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Memory Circular Mode -- cgit v1.2.3 From 68e68187616c535622ccd5180806935dee0e0d38 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 26 Oct 2012 23:57:11 +1030 Subject: STM32F4 New: headers and source code for DMA This has been tested with some dac, timer and (as yet uncommitted) adc examples. --- include/libopencm3/stm32/f4/dma.h | 693 ++++++++++++++++++++++++++++++++++ lib/stm32/f4/dma.c | 772 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 1465 insertions(+) create mode 100644 include/libopencm3/stm32/f4/dma.h create mode 100644 lib/stm32/f4/dma.c (limited to 'include') diff --git a/include/libopencm3/stm32/f4/dma.h b/include/libopencm3/stm32/f4/dma.h new file mode 100644 index 0000000..1f034fa --- /dev/null +++ b/include/libopencm3/stm32/f4/dma.h @@ -0,0 +1,693 @@ +/** @defgroup STM32F4xx_dma_defines DMA Defines + +@ingroup STM32F4xx_defines + +@brief Defined Constants and Types for the STM32F4xx DMA Controller + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 18 October 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* DMA register base adresses (for convenience) */ +#define DMA1 DMA1_BASE +#define DMA2 DMA2_BASE + +/* --- DMA registers ------------------------------------------------------- */ + +/* DMA low interrupt status register (DMAx_ISR) */ +#define DMA_LISR(dma_base) MMIO32(dma_base + 0x00) +#define DMA1_LISR DMA_ISR(DMA1) +#define DMA2_LISR DMA_ISR(DMA2) + +/* DMA high interrupt status register (DMAx_ISR) */ +#define DMA_HISR(dma_base) MMIO32(dma_base + 0x04) +#define DMA1_HISR DMA_ISR(DMA1) +#define DMA2_HISR DMA_ISR(DMA2) + +/* DMA low interrupt flag clear register (DMAx_IFCR) */ +#define DMA_LIFCR(dma_base) MMIO32(dma_base + 0x08) +#define DMA1_LIFCR DMA_IFCR(DMA1) +#define DMA2_LIFCR DMA_IFCR(DMA2) + +/* DMA high interrupt flag clear register (DMAx_IFCR) */ +#define DMA_HIFCR(dma_base) MMIO32(dma_base + 0x0C) +#define DMA1_HIFCR DMA_IFCR(DMA1) +#define DMA2_HIFCR DMA_IFCR(DMA2) + +/* DMA stream configuration register (DMAx_SyCR) */ +#define DMA_SCR(dma_base, stream) MMIO32(dma_base + 0x10 + \ + (0x18 * (stream))) + +#define DMA1_SCR(stream) DMA_SCR(DMA1, stream) +#define DMA1_S0CR DMA1_SCR(DMA_STREAM0) +#define DMA1_S1CR DMA1_SCR(DMA_STREAM1) +#define DMA1_S2CR DMA1_SCR(DMA_STREAM2) +#define DMA1_S3CR DMA1_SCR(DMA_STREAM3) +#define DMA1_S4CR DMA1_SCR(DMA_STREAM4) +#define DMA1_S5CR DMA1_SCR(DMA_STREAM5) +#define DMA1_S6CR DMA1_SCR(DMA_STREAM6) +#define DMA1_S7CR DMA1_SCR(DMA_STREAM7) + +#define DMA2_SCR(stream) DMA_SCR(DMA2, stream) +#define DMA2_S0CR DMA2_SCR(DMA_STREAM0) +#define DMA2_S1CR DMA2_SCR(DMA_STREAM1) +#define DMA2_S2CR DMA2_SCR(DMA_STREAM2) +#define DMA2_S3CR DMA2_SCR(DMA_STREAM3) +#define DMA2_S4CR DMA2_SCR(DMA_STREAM4) +#define DMA2_S5CR DMA2_SCR(DMA_STREAM5) +#define DMA2_S6CR DMA2_SCR(DMA_STREAM6) +#define DMA2_S7CR DMA2_SCR(DMA_STREAM7) + +/* DMA number of data register (DMAx_SyNDTR) */ +#define DMA_SNDTR(dma_base, stream) MMIO32(dma_base + 0x14 + \ + (0x18 * (stream))) + +#define DMA1_SNDTR(stream) DMA_SNDTR(DMA1, stream) +#define DMA1_S0NDTR DMA1_SNDTR(DMA_STREAM0) +#define DMA1_S1NDTR DMA1_SNDTR(DMA_STREAM1) +#define DMA1_S2NDTR DMA1_SNDTR(DMA_STREAM2) +#define DMA1_S3NDTR DMA1_SNDTR(DMA_STREAM3) +#define DMA1_S4NDTR DMA1_SNDTR(DMA_STREAM4) +#define DMA1_S5NDTR DMA1_SNDTR(DMA_STREAM5) +#define DMA1_S6NDTR DMA1_SNDTR(DMA_STREAM6) +#define DMA1_S7NDTR DMA1_SNDTR(DMA_STREAM7) + +#define DMA2_SNDTR(stream) DMA_CNDTR(DMA2, stream) +#define DMA2_S0NDTR DMA2_SNDTR(DMA_STREAM0) +#define DMA2_S1NDTR DMA2_SNDTR(DMA_STREAM1) +#define DMA2_S2NDTR DMA2_SNDTR(DMA_STREAM2) +#define DMA2_S3NDTR DMA2_SNDTR(DMA_STREAM3) +#define DMA2_S4NDTR DMA2_SNDTR(DMA_STREAM4) +#define DMA2_S5NDTR DMA2_SNDTR(DMA_STREAM5) +#define DMA2_S6NDTR DMA2_SNDTR(DMA_STREAM6) +#define DMA2_S7NDTR DMA2_SNDTR(DMA_STREAM7) + +/* DMA peripheral address register (DMAx_SyPAR) */ +#define DMA_SPAR(dma_base, stream) MMIO32(dma_base + 0x18 + \ + (0x18 * (stream))) + +#define DMA1_SPAR(stream) DMA_SPAR(DMA1, stream) +#define DMA1_S0PAR DMA1_SPAR(DMA_STREAM0) +#define DMA1_S1PAR DMA1_SPAR(DMA_STREAM1) +#define DMA1_S2PAR DMA1_SPAR(DMA_STREAM2) +#define DMA1_S3PAR DMA1_SPAR(DMA_STREAM3) +#define DMA1_S4PAR DMA1_SPAR(DMA_STREAM4) +#define DMA1_S5PAR DMA1_SPAR(DMA_STREAM5) +#define DMA1_S6PAR DMA1_SPAR(DMA_STREAM6) +#define DMA1_S7PAR DMA1_SPAR(DMA_STREAM7) + +#define DMA2_SPAR(stream) DMA_SPAR(DMA2, stream) +#define DMA2_S0PAR DMA2_SPAR(DMA_STREAM0) +#define DMA2_S1PAR DMA2_SPAR(DMA_STREAM1) +#define DMA2_S2PAR DMA2_SPAR(DMA_STREAM2) +#define DMA2_S3PAR DMA2_SPAR(DMA_STREAM3) +#define DMA2_S4PAR DMA2_SPAR(DMA_STREAM4) +#define DMA2_S5PAR DMA2_SPAR(DMA_STREAM5) +#define DMA2_S6PAR DMA2_SPAR(DMA_STREAM6) +#define DMA2_S7PAR DMA2_SPAR(DMA_STREAM7) + +/* DMA memory 0 address register (DMAx_SyM0AR) */ + +#define DMA_SM0AR(dma_base, stream) MMIO32(dma_base + 0x1C + \ + (0x18 * (stream))) + +#define DMA1_SM0AR(stream) DMA_SM0AR(DMA1, stream) +#define DMA1_S0M0AR DMA1_SM0AR(DMA_STREAM0) +#define DMA1_S1M0AR DMA1_SM0AR(DMA_STREAM1) +#define DMA1_S2M0AR DMA1_SM0AR(DMA_STREAM2) +#define DMA1_S3M0AR DMA1_SM0AR(DMA_STREAM3) +#define DMA1_S4M0AR DMA1_SM0AR(DMA_STREAM4) +#define DMA1_S5M0AR DMA1_SM0AR(DMA_STREAM5) +#define DMA1_S6M0AR DMA1_SM0AR(DMA_STREAM6) +#define DMA1_S7M0AR DMA1_SM0AR(DMA_STREAM7) + +#define DMA2_SM0AR(stream) DMA_CM0AR(DMA2, stream) +#define DMA2_S0M0AR DMA2_SM0AR(DMA_STREAM0) +#define DMA2_S1M0AR DMA2_SM0AR(DMA_STREAM1) +#define DMA2_S2M0AR DMA2_SM0AR(DMA_STREAM2) +#define DMA2_S3M0AR DMA2_SM0AR(DMA_STREAM3) +#define DMA2_S4M0AR DMA2_SM0AR(DMA_STREAM4) +#define DMA2_S5M0AR DMA2_SM0AR(DMA_STREAM5) +#define DMA2_S6M0AR DMA2_SM0AR(DMA_STREAM6) +#define DMA2_S7M0AR DMA2_SM0AR(DMA_STREAM7) + +/* DMA memory 1 address register (DMAx_SyM1AR) */ + +#define DMA_SM1AR(dma_base, stream) MMIO32(dma_base + 0x20 + \ + (0x18 * (stream))) + +#define DMA1_SM1AR(stream) DMA_SM1AR(DMA1, stream) +#define DMA1_S0M1AR DMA1_SM1AR(DMA_STREAM0) +#define DMA1_S1M1AR DMA1_SM1AR(DMA_STREAM1) +#define DMA1_S2M1AR DMA1_SM1AR(DMA_STREAM2) +#define DMA1_S3M1AR DMA1_SM1AR(DMA_STREAM3) +#define DMA1_S4M1AR DMA1_SM1AR(DMA_STREAM4) +#define DMA1_S5M1AR DMA1_SM1AR(DMA_STREAM5) +#define DMA1_S6M1AR DMA1_SM1AR(DMA_STREAM6) +#define DMA1_S7M1AR DMA1_SM1AR(DMA_STREAM7) + +#define DMA2_SM1AR(stream) DMA_CM1AR(DMA2, stream) +#define DMA2_S0M1AR DMA2_SM1AR(DMA_STREAM0) +#define DMA2_S1M1AR DMA2_SM1AR(DMA_STREAM1) +#define DMA2_S2M1AR DMA2_SM1AR(DMA_STREAM2) +#define DMA2_S3M1AR DMA2_SM1AR(DMA_STREAM3) +#define DMA2_S4M1AR DMA2_SM1AR(DMA_STREAM4) +#define DMA2_S5M1AR DMA2_SM1AR(DMA_STREAM5) +#define DMA2_S6M1AR DMA2_SM1AR(DMA_STREAM6) +#define DMA2_S7M1AR DMA2_SM1AR(DMA_STREAM7) + +/* DMA FIFO Control Register register (DMAx_SyFCR) */ + +#define DMA_SFCR(dma_base, stream) MMIO32(dma_base + 0x24 + \ + (0x18 * (stream))) + +#define DMA1_SFCR(stream) DMA_SFCR(DMA1, stream) +#define DMA1_S0FCR DMA1_SFCR(DMA_STREAM0) +#define DMA1_S1FCR DMA1_SFCR(DMA_STREAM1) +#define DMA1_S2FCR DMA1_SFCR(DMA_STREAM2) +#define DMA1_S3FCR DMA1_SFCR(DMA_STREAM3) +#define DMA1_S4FCR DMA1_SFCR(DMA_STREAM4) +#define DMA1_S5FCR DMA1_SFCR(DMA_STREAM5) +#define DMA1_S6FCR DMA1_SFCR(DMA_STREAM6) +#define DMA1_S7FCR DMA1_SFCR(DMA_STREAM7) + +#define DMA2_SFCR(stream) DMA_CFCR(DMA2, stream) +#define DMA2_S0FCR DMA2_SFCR(DMA_STREAM0) +#define DMA2_S1FCR DMA2_SFCR(DMA_STREAM1) +#define DMA2_S2FCR DMA2_SFCR(DMA_STREAM2) +#define DMA2_S3FCR DMA2_SFCR(DMA_STREAM3) +#define DMA2_S4FCR DMA2_SFCR(DMA_STREAM4) +#define DMA2_S5FCR DMA2_SFCR(DMA_STREAM5) +#define DMA2_S6FCR DMA2_SFCR(DMA_STREAM6) +#define DMA2_S7FCR DMA2_SFCR(DMA_STREAM7) + +/* --- DMA Interrupt Flag offset values ------------------------------------- */ +/* These are based on every interrupt flag and flag clear being at the same relative location */ +/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group. +@ingroup STM32F4xx_dma_defines + +@{*/ +/** Transfer Complete Interrupt Flag */ +#define DMA_ISR_TCIF (1 << 5) +/** Half Transfer Interrupt Flag */ +#define DMA_ISR_HTIF (1 << 4) +/** Transfer Error Interrupt Flag */ +#define DMA_ISR_TEIF (1 << 3) +/** Direct Mode Error Interrupt Flag */ +#define DMA_ISR_DMEIF (1 << 2) +/** FIFO Error Interrupt Flag */ +#define DMA_ISR_FEIF (1 << 0) +/**@}*/ + +/* Offset within interrupt status register to start of stream interrupt flag field */ +#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*(stream & 0x02)) +#define DMA_ISR_FLAGS (DMA_ISR_TCIF | DMA_ISR_HTIF | DMA_ISR_TEIF | DMA_ISR_DMEIF | DMA_ISR_FEIF) +#define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream) + +/* --- DMA_LISR values ------------------------------------------------------ */ + +/* TCIF: Transfer complete interrupt flag, streams 0-3 only */ +#define DMA_LISR_TCIF_BIT DMA_ISR_TCIF +#define DMA_LISR_TCIF(stream) (DMA_LISR_TCIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LISR_TCIF0 DMA_LISR_TCIF(DMA_STREAM0) +#define DMA_LISR_TCIF1 DMA_LISR_TCIF(DMA_STREAM1) +#define DMA_LISR_TCIF2 DMA_LISR_TCIF(DMA_STREAM2) +#define DMA_LISR_TCIF3 DMA_LISR_TCIF(DMA_STREAM3) + +/* HTIF: Half transfer interrupt flag, streams 0-3 only */ +#define DMA_LISR_HTIF_BIT DMA_ISR_HTIF +#define DMA_LISR_HTIF(stream) (DMA_LISR_HTIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LISR_HTIF0 DMA_LISR_HTIF(DMA_STREAM0) +#define DMA_LISR_HTIF1 DMA_LISR_HTIF(DMA_STREAM1) +#define DMA_LISR_HTIF2 DMA_LISR_HTIF(DMA_STREAM2) +#define DMA_LISR_HTIF3 DMA_LISR_HTIF(DMA_STREAM3) + +/* TEIF: Transfer error interrupt flag, streams 0-3 only */ +#define DMA_LISR_TEIF_BIT DMA_ISR_TEIF +#define DMA_LISR_TEIF(stream) (DMA_LISR_TEIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LISR_TEIF0 DMA_LISR_TEIF(DMA_STREAM0) +#define DMA_LISR_TEIF1 DMA_LISR_TEIF(DMA_STREAM1) +#define DMA_LISR_TEIF2 DMA_LISR_TEIF(DMA_STREAM2) +#define DMA_LISR_TEIF3 DMA_LISR_TEIF(DMA_STREAM3) + +/* DMEIF: Direct Mode Error interrupt flag, streams 0-3 only */ +#define DMA_LISR_DMEIF_BIT DMA_ISR_DMEIF +#define DMA_LISR_DMEIF(stream) (DMA_LISR_DMEIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF(DMA_STREAM0) +#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF(DMA_STREAM1) +#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF(DMA_STREAM2) +#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF(DMA_STREAM3) + +/* Interrupt #1 is reserved */ + +/* FEIF: FIFO Error interrupt flag, streams 0-3 only */ +#define DMA_LISR_FEIF_BIT DMA_ISR_FEIF +#define DMA_LISR_FEIF(stream) (DMA_LISR_FEIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LISR_FEIF0 DMA_LISR_FEIF(DMA_STREAM0) +#define DMA_LISR_FEIF1 DMA_LISR_FEIF(DMA_STREAM1) +#define DMA_LISR_FEIF2 DMA_LISR_FEIF(DMA_STREAM2) +#define DMA_LISR_FEIF3 DMA_LISR_FEIF(DMA_STREAM3) + +/* --- DMA_HISR values ------------------------------------------------------ */ + +/* TCIF: Transfer complete interrupt flag, streams 4-7 only */ +#define DMA_HISR_TCIF_BIT DMA_ISR_TCIF +#define DMA_HISR_TCIF(stream) (DMA_HISR_TCIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HISR_TCIF4 DMA_HISR_TCIF(DMA_STREAM4) +#define DMA_HISR_TCIF5 DMA_HISR_TCIF(DMA_STREAM5) +#define DMA_HISR_TCIF6 DMA_HISR_TCIF(DMA_STREAM6) +#define DMA_HISR_TCIF7 DMA_HISR_TCIF(DMA_STREAM7) + +/* HTIF: Half transfer interrupt flag, streams 4-7 only */ +#define DMA_HISR_HTIF_BIT DMA_ISR_HTIF +#define DMA_HISR_HTIF(stream) (DMA_HISR_HTIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HISR_HTIF4 DMA_HISR_HTIF(DMA_STREAM4) +#define DMA_HISR_HTIF5 DMA_HISR_HTIF(DMA_STREAM5) +#define DMA_HISR_HTIF6 DMA_HISR_HTIF(DMA_STREAM6) +#define DMA_HISR_HTIF7 DMA_HISR_HTIF(DMA_STREAM7) + +/* TEIF: Transfer error interrupt flag, streams 4-7 only */ +#define DMA_HISR_TEIF_BIT DMA_ISR_TEIF +#define DMA_HISR_TEIF(stream) (DMA_HISR_TEIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HISR_TEIF4 DMA_HISR_TEIF(DMA_STREAM4) +#define DMA_HISR_TEIF5 DMA_HISR_TEIF(DMA_STREAM5) +#define DMA_HISR_TEIF6 DMA_HISR_TEIF(DMA_STREAM6) +#define DMA_HISR_TEIF7 DMA_HISR_TEIF(DMA_STREAM7) + +/* DMEIF: Direct Mode Error interrupt flag, streams 4-7 only */ +#define DMA_HISR_DMEIF_BIT DMA_ISR_DMEIF +#define DMA_HISR_DMEIF(stream) (DMA_HISR_DMEIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF(DMA_STREAM4) +#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF(DMA_STREAM5) +#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF(DMA_STREAM6) +#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF(DMA_STREAM7) + +/* Interrupt #1 is reserved */ + +/* FEIF: FIFO Error interrupt flag, streams 4-7 only */ +#define DMA_HISR_FEIF_BIT DMA_ISR_FEIF +#define DMA_HISR_FEIF(stream) (DMA_HISR_FEIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HISR_FEIF4 DMA_HISR_FEIF(DMA_STREAM4) +#define DMA_HISR_FEIF5 DMA_HISR_FEIF(DMA_STREAM5) +#define DMA_HISR_FEIF6 DMA_HISR_FEIF(DMA_STREAM6) +#define DMA_HISR_FEIF7 DMA_HISR_FEIF(DMA_STREAM7) + +/* --- DMA_LIFCR values ------------------------------------------------------ */ + +/* TCIF: Transfer complete interrupt flag, streams 0-3 only */ +#define DMA_LIFCR_CTCIF_BIT DMA_ISR_TCIF +#define DMA_LIFCR_CTCIF(stream) (DMA_LIFCR_CTCIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF(DMA_STREAM0) +#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF(DMA_STREAM1) +#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF(DMA_STREAM2) +#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF(DMA_STREAM3) + +/* HTIF: Half transfer interrupt flag, streams 0-3 only */ +#define DMA_LIFCR_CHTIF_BIT DMA_ISR_HTIF +#define DMA_LIFCR_CHTIF(stream) (DMA_LIFCR_CHTIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF(DMA_STREAM0) +#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF(DMA_STREAM1) +#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF(DMA_STREAM2) +#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF(DMA_STREAM3) + +/* TEIF: Transfer error interrupt flag, streams 0-3 only */ +#define DMA_LIFCR_CTEIF_BIT DMA_ISR_TEIF +#define DMA_LIFCR_CTEIF(stream) (DMA_LIFCR_CTEIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF(DMA_STREAM0) +#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF(DMA_STREAM1) +#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF(DMA_STREAM2) +#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF(DMA_STREAM3) + +/* DMEIF: Direct Mode Error interrupt flag, streams 0-3 only */ +#define DMA_LIFCR_CDMEIF_BIT DMA_ISR_DMEIF +#define DMA_LIFCR_CDMEIF(stream) (DMA_LIFCR_CDMEIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF(DMA_STREAM0) +#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF(DMA_STREAM1) +#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF(DMA_STREAM2) +#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF(DMA_STREAM3) + +/* Interrupt #1 is reserved */ + +/* FEIF: FIFO Error interrupt flag, streams 0-3 only */ +#define DMA_LIFCR_CFEIF_BIT DMA_ISR_FEIF +#define DMA_LIFCR_CFEIF(stream) (DMA_LIFCR_CFEIF_BIT << DMA_ISR_OFFSET(stream)) + +#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF(DMA_STREAM0) +#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF(DMA_STREAM1) +#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF(DMA_STREAM2) +#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF(DMA_STREAM3) + +/* --- DMA_HIFCR values ------------------------------------------------------ */ + +/* TCIF: Transfer complete interrupt flag, streams 4-7 only */ +#define DMA_HIFCR_CTCIF_BIT DMA_ISR_TCIF +#define DMA_HIFCR_CTCIF(stream) (DMA_HIFCR_CTCIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF(DMA_STREAM4) +#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF(DMA_STREAM5) +#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF(DMA_STREAM6) +#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF(DMA_STREAM7) + +/* HTIF: Half transfer interrupt flag, streams 4-7 only */ +#define DMA_HIFCR_CHTIF_BIT DMA_ISR_HTIF +#define DMA_HIFCR_CHTIF(stream) (DMA_HIFCR_CHTIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF(DMA_STREAM4) +#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF(DMA_STREAM5) +#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF(DMA_STREAM6) +#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF(DMA_STREAM7) + +/* TEIF: Transfer error interrupt flag, streams 4-7 only */ +#define DMA_HIFCR_CTEIF_BIT DMA_ISR_TEIF +#define DMA_HIFCR_CTEIF(stream) (DMA_HIFCR_CTEIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF(DMA_STREAM4) +#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF(DMA_STREAM5) +#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF(DMA_STREAM6) +#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF(DMA_STREAM7) + +/* DMEIF: Direct Mode Error interrupt flag, streams 4-7 only */ +#define DMA_HIFCR_CDMEIF_BIT DMA_ISR_DMEIF +#define DMA_HIFCR_CDMEIF(stream) (DMA_HIFCR_CDMEIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF(DMA_STREAM4) +#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF(DMA_STREAM5) +#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF(DMA_STREAM6) +#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF(DMA_STREAM7) + +/* Interrupt #1 is reserved */ + +/* FEIF: FIFO Error interrupt flag, streams 4-7 only */ +#define DMA_HIFCR_CFEIF_BIT DMA_ISR_FEIF +#define DMA_HIFCR_CFEIF(stream) (DMA_HIFCR_CFEIF_BIT << (DMA_ISR_OFFSET(stream - 4)) + +#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF(DMA_STREAM4) +#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF(DMA_STREAM5) +#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF(DMA_STREAM6) +#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF(DMA_STREAM7) + +/* --- DMA_SxCR generic values --------------------------------------------- */ + +/* Reserved [31:28] */ + +/* CHSEL[13:12]: Channel Select */ +/** @defgroup dma_ch_sel DMA Channel Select +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SCR_CHSEL_0 (0x0 << 25) +#define DMA_SCR_CHSEL_1 (0x1 << 25) +#define DMA_SCR_CHSEL_2 (0x2 << 25) +#define DMA_SCR_CHSEL_3 (0x3 << 25) +#define DMA_SCR_CHSEL_4 (0x4 << 25) +#define DMA_SCR_CHSEL_5 (0x5 << 25) +#define DMA_SCR_CHSEL_6 (0x6 << 25) +#define DMA_SCR_CHSEL_7 (0x7 << 25) +/**@}*/ +#define DMA_SCR_CHSEL_MASK (0x7 << 25) +#define DMA_SCR_CHSEL_SHIFT 25 + +/* MBURST[13:12]: Memory Burst Configuration */ +/** @defgroup dma_mburst DMA Memory Burst Length +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SCR_MBURST_INCR0 (0x0 << 23) +#define DMA_SCR_MBURST_INCR4 (0x1 << 23) +#define DMA_SCR_MBURST_INCR8 (0x2 << 23) +#define DMA_SCR_MBURST_INCR16 (0x3 << 23) +/**@}*/ +#define DMA_SCR_MBURST_MASK (0x3 << 23) +#define DMA_SCR_MBURST_SHIFT 23 + +/* PBURST[13:12]: Peripheral Burst Configuration */ +/** @defgroup dma_pburst DMA Peripheral Burst Length +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SCR_PBURST_INCR0 (0x0 << 21) +#define DMA_SCR_PBURST_INCR4 (0x1 << 21) +#define DMA_SCR_PBURST_INCR8 (0x2 << 21) +#define DMA_SCR_PBURST_INCR16 (0x3 << 21) +/**@}*/ +#define DMA_SCR_PBURST_MASK (0x3 << 21) +#define DMA_SCR_PBURST_SHIFT 21 + +/* Bit 20 reserved */ + +/* CT: Current target (in double buffered mode) */ +#define DMA_SCR_CT (1 << 19) + +/* DBM: Double buffered mode */ +#define DMA_SCR_DBM (1 << 18) + +/* PL[17:16]: Stream priority level */ +/** @defgroup dma_st_pri DMA Stream Priority Levels +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SCR_PL_LOW (0x0 << 16) +#define DMA_SCR_PL_MEDIUM (0x1 << 16) +#define DMA_SCR_PL_HIGH (0x2 << 16) +#define DMA_SCR_PL_VERY_HIGH (0x3 << 16) +/**@}*/ +#define DMA_SCR_PL_MASK (0x3 << 16) +#define DMA_SCR_PL_SHIFT 16 + +/* PINCOS: Peripheral increment offset size */ +#define DMA_SCR_PINCOS (1 << 15) + +/* MSIZE[14:13]: Memory size */ +/** @defgroup dma_st_memwidth DMA Stream Memory Word Width +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SCR_MSIZE_8BIT (0x0 << 13) +#define DMA_SCR_MSIZE_16BIT (0x1 << 13) +#define DMA_SCR_MSIZE_32BIT (0x2 << 13) +/**@}*/ +#define DMA_SCR_MSIZE_MASK (0x3 << 13) +#define DMA_SCR_MSIZE_SHIFT 13 + +/* PSIZE[12:11]: Peripheral size */ +/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SCR_PSIZE_8BIT (0x0 << 11) +#define DMA_SCR_PSIZE_16BIT (0x1 << 11) +#define DMA_SCR_PSIZE_32BIT (0x2 << 11) +/**@}*/ +#define DMA_SCR_PSIZE_MASK (0x3 << 11) +#define DMA_SCR_PSIZE_SHIFT 11 + +/* MINC: Memory increment mode */ +#define DMA_SCR_MINC (1 << 10) + +/* PINC: Peripheral increment mode */ +#define DMA_SCR_PINC (1 << 9) + +/* CIRC: Circular mode */ +#define DMA_SCR_CIRC (1 << 8) + +/* DIR[7:6]: Data transfer direction */ +/** @defgroup dma_st_dir DMA Stream Data transfer direction +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SCR_DIR_PER2MEM (0x0 << 6) +#define DMA_SCR_DIR_MEM2PER (0x1 << 6) +#define DMA_SCR_DIR_MEM2MEM (0x2 << 6) +/**@}*/ +#define DMA_SCR_DIR_MASK (0x3 << 6) +#define DMA_SCR_DIR_SHIFT 6 + +/* PFCTRL: Peripheral Flow Controller */ +#define DMA_SCR_PFCTRL (1 << 5) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_SCR_TCIE (1 << 4) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_SCR_HTIE (1 << 3) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_SCR_TEIE (1 << 2) + +/* DMEIE: Direct Mode error interrupt enable */ +#define DMA_SCR_DMEIE (1 << 1) + +/* EN: Stream enable */ +#define DMA_SCR_EN (1 << 0) + +/* --- DMA_SxNDTR values --------------------------------------------------- */ + +/* NDT[15:0]: Number of data to transfer */ + +/* --- DMA_SxPAR values ---------------------------------------------------- */ + +/* PA[31:0]: Peripheral address */ + +/* --- DMA_SxM0AR values ---------------------------------------------------- */ + +/* M0A[31:0]: Memory address */ + +/* --- DMA_SxM1AR values ---------------------------------------------------- */ + +/* M1A[31:0]: Memory address */ + +/* --- DMA_SxFCR generic values --------------------------------------------- */ + +/* Reserved [31:8] */ + +/* FEIE: FIFO error interrupt enable */ +#define DMA_FCR_FEIE (1 << 7) + +/* Bit 6 reserved */ + +/* FS[5:3]: FIFO Status */ +/** @defgroup dma_fifo_status FIFO Status +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_FCR_FS_LOW (0x0 << 3) +#define DMA_FCR_FS_UNDER_HALF (0x1 << 3) +#define DMA_FCR_FS_MEDIUM (0x2 << 3) +#define DMA_FCR_FS_HIGH (0x3 << 3) +#define DMA_FCR_FS_EMPTY (0x4 << 3) +#define DMA_FCR_FS_FULL (0x5 << 3) +/**@}*/ +#define DMA_FCR_FS_MASK (0x7 << 3) +#define DMA_FCR_FS_SHIFT 3 + +/* DMDIS: Direct Mode disable */ +#define DMA_FCR_DMDIS (1 << 2) + +/* FTH[1:0]: FIFO Threshold selection */ +/** @defgroup dma_fifo_thresh FIFO Threshold selection +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_FCR_FTH_LOW (0x0 << 0) +#define DMA_FCR_FTH_HALF (0x1 << 0) +#define DMA_FCR_FTH_MEDIUM (0x2 << 0) +#define DMA_FCR_FTH_FULL (0x3 << 0) +/**@}*/ +#define DMA_FCR_FTH_MASK (0x3 << 0) +#define DMA_FCR_FTH_SHIFT 3 + +/* --- Generic values ------------------------------------------------------ */ + +/** @defgroup dma_st_number DMA Stream Number +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_STREAM0 0 +#define DMA_STREAM1 1 +#define DMA_STREAM2 2 +#define DMA_STREAM3 3 +#define DMA_STREAM4 4 +#define DMA_STREAM5 5 +#define DMA_STREAM6 6 +#define DMA_STREAM7 7 +/**@}*/ + +/* --- function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dma_stream_reset(u32 dma, u8 stream); +void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts); +bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt); +void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction); +void dma_set_priority(u32 dma, u8 stream, u32 prio); +void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size); +void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size); +void dma_enable_memory_increment_mode(u32 dma, u8 stream); +void dma_disable_memory_increment_mode(u32 dma, u8 channel); +void dma_enable_peripheral_increment_mode(u32 dma, u8 stream); +void dma_disable_peripheral_increment_mode(u32 dma, u8 channel); +void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream); +void dma_enable_circular_mode(u32 dma, u8 stream); +void dma_channel_select(u32 dma, u8 stream, u32 channel); +void dma_channel_select(u32 dma, u8 stream, u32 channel); +void dma_set_memory_burst(u32 dma, u8 stream, u32 burst); +void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst); +void dma_set_initial_target(u32 dma, u8 stream, u8 memory); +u8 dma_get_target(u32 dma, u8 stream); +void dma_enable_double_buffer_mode(u32 dma, u8 stream); +void dma_set_peripheral_flow_control(u32 dma, u8 stream); +void dma_set_dma_flow_control(u32 dma, u8 stream); +void dma_enable_transfer_error_interrupt(u32 dma, u8 stream); +void dma_disable_transfer_error_interrupt(u32 dma, u8 stream); +void dma_enable_half_transfer_interrupt(u32 dma, u8 stream); +void dma_disable_half_transfer_interrupt(u32 dma, u8 stream); +void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream); +void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream); +u32 dma_fifo_status(u32 dma, u8 stream); +void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream); +void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream); +void dma_enable_fifo_error_interrupt(u32 dma, u8 stream); +void dma_disable_fifo_error_interrupt(u32 dma, u8 stream); +void dma_enable_direct_mode(u32 dma, u8 stream); +void dma_enable_fifo_mode(u32 dma, u8 stream); +void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold); +void dma_enable_stream(u32 dma, u8 stream); +void dma_disable_stream(u32 dma, u8 stream); +void dma_set_peripheral_address(u32 dma, u8 stream, u32 address); +void dma_set_memory_address(u32 dma, u8 stream, u32 address); +void dma_set_memory_address_1(u32 dma, u8 stream, u32 address); +void dma_set_number_of_data(u32 dma, u8 stream, u16 number); + +END_DECLS + +#endif +/**@}*/ + diff --git a/lib/stm32/f4/dma.c b/lib/stm32/f4/dma.c new file mode 100644 index 0000000..80eb963 --- /dev/null +++ b/lib/stm32/f4/dma.c @@ -0,0 +1,772 @@ +/** @defgroup STM32F4xx-dma-file DMA + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx DMA Controller + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 18 October 2012 + +This library supports the DMA Control System in the STM32F2 and STM32F4 +series of ARM Cortex Microcontrollers by ST Microelectronics. + +Up to two DMA controllers are supported each with 8 streams, and each stream +having up to 8 channels hardware dedicated to various peripheral DMA signals. + +DMA transfers can be configured to occur between peripheral and memory in +either direction, and memory to memory. Peripheral to peripheral transfer +is not supported. Circular mode transfers are also supported in transfers +involving a peripheral. An arbiter is provided to resolve priority DMA +requests. Transfers can be made with 8, 16 or 32 bit words. + +Each stream has access to a 4 word deep FIFO and can use double buffering +by means of two memory pointers. When using the FIFO it is possible to +configure transfers to occur in indivisible bursts. + +It is also possible to select a peripheral to control the flow of data rather +than the DMA controller. This limits the functionality but is udeful when the +number of transfers is unknown. + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Reset + +The specified stream is disabled and configuration registers are cleared. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_stream_reset(u32 dma, u8 stream) +{ +/* Disable stream (must be done before register is otherwise changed). */ + DMA_SCR(dma, stream) &= ~DMA_SCR_EN; +/* Reset all config bits. */ + DMA_SCR(dma, stream) = 0; +/* Reset data transfer number. */ + DMA_SNDTR(dma, stream) = 0; +/* Reset peripheral and memory addresses. */ + DMA_SPAR(dma, stream) = 0; + DMA_SM0AR(dma, stream) = 0; + DMA_SM1AR(dma, stream) = 0; +/* This is the default setting */ + DMA_SFCR(dma, stream) = 0x21; +/* Reset all stream interrupt flags using the interrupt flag clear register. */ + u32 mask = DMA_ISR_MASK(stream); + if (stream < 4) + { + DMA_LIFCR(dma) |= mask; + } + else + { + DMA_HIFCR(dma) |= mask; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Clear Interrupt Flag + +The interrupt flag for the stream is cleared. More than one interrupt for the +same stream may be cleared by using the logical OR of the interrupt flags. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset +*/ + +void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts) +{ +/* Get offset to interrupt flag location in stream field */ + u32 flags = (interrupts << DMA_ISR_OFFSET(stream)); +/* First four streams are in low register. Flag clear must be set then reset. */ + if (stream < 4) + { + DMA_LIFCR(dma) = flags; + } + else + { + DMA_HIFCR(dma) = flags; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Read Interrupt Flag + +The interrupt flag for the stream is returned. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] interrupt unsigned int32. Interrupt number: @ref dma_st_number +@returns bool interrupt flag is set. +*/ + +bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt) +{ +/* get offset to interrupt flag location in stream field. +Assumes stream and interrupt parameters are integers */ + u32 flag = (interrupt << DMA_ISR_OFFSET(stream)); +/* First four streams are in low register */ + if (stream < 4) return ((DMA_LISR(dma) & flag) > 0); + else return ((DMA_HISR(dma) & flag) > 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable Transfer Direction + +Set peripheral to memory, memory to peripheral or memory to memory. If memory +to memory mode is selected, circular mode and double buffer modes are disabled. +Ensure that these modes are not enabled at a later time. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] direction unsigned int32. Data transfer direction @ref dma_st_dir +*/ + +void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction) +{ + u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SCR_DIR_MASK); +/* Disable circular and double buffer modes if memory to memory transfers +are in effect (Direct Mode is automatically disabled by hardware) */ + if (direction == DMA_SCR_DIR_MEM2MEM) + { + reg32 &= ~(DMA_SCR_CIRC | DMA_SCR_DBM); + } + DMA_SCR(dma, stream) = (reg32 | direction); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set Priority + +Stream Priority has four levels: low to very high. This has precedence over the +hardware priority. In the event of equal software priority the lower numbered +stream has priority. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] prio unsigned int32. Priority level @ref dma_st_pri. +*/ + +void dma_set_priority(u32 dma, u8 stream, u32 prio) +{ + DMA_SCR(dma, stream) &= ~(DMA_SCR_PL_MASK); + DMA_SCR(dma, stream) |= prio; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set Memory Word Width + +Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for +alignment information if the source and destination widths do not match. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] mem_size unsigned int32. Memory word width @ref dma_st_memwidth. +*/ + +void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size) +{ + + DMA_SCR(dma, stream) &= ~(DMA_SCR_MSIZE_MASK); + DMA_SCR(dma, stream) |= mem_size; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set Peripheral Word Width + +Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for +alignment information if the source and destination widths do not match, or +if the peripheral does not support byte or half-word writes. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_st_perwidth. +*/ + +void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size) +{ + DMA_SCR(dma, stream) &= ~(DMA_SCR_PSIZE_MASK); + DMA_SCR(dma, stream) |= peripheral_size; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable Memory Increment after Transfer + +Following each transfer the current memory address is incremented by +1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The +value held by the base memory address register is unchanged. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_memory_increment_mode(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) |= DMA_SCR_MINC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable Memory Increment after Transfer + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_disable_memory_increment_mode(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) &= ~DMA_SCR_MINC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer + +Following each transfer the current peripheral address is incremented by +1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The +value held by the base peripheral address register is unchanged. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_peripheral_increment_mode(u32 dma, u8 stream) +{ + u32 reg32 = (DMA_SCR(dma, stream) | DMA_SCR_PINC); + DMA_SCR(dma, stream) = (reg32 & ~DMA_SCR_PINCOS); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable Peripheral Increment after Transfer + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_disable_peripheral_increment_mode(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) &= ~DMA_SCR_PINC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer + +Following each transfer the current peripheral address is incremented by +4 regardless of the data size. The value held by the base peripheral address +register is unchanged. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) |= (DMA_SCR_PINC | DMA_SCR_PINCOS); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable Memory Circular Mode + +After the number of bytes/words to be transferred has been completed, the +original transfer block size, memory and peripheral base addresses are +reloaded and the process repeats. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@note This cannot be used with memory to memory mode. It is disabled +automatically if the peripheral is selected as the flow controller. +It is enabled automatically if double buffered mode is selected. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_circular_mode(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) |= DMA_SCR_CIRC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Channel Select + +Associate an input channel to the stream. Not every channel is allocated to a +hardware DMA request signal. The allocations for each stream are given in the +STM32F4 Reference Manual. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] channel unsigned int8. Channel selection @ref dma_ch_sel +*/ + +void dma_channel_select(u32 dma, u8 stream, u32 channel) +{ + DMA_SCR(dma, stream) |= channel; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set Memory Burst Configuration + +Set the memory burst type to none, 4 8 or 16 word length. This is forced to none +if direct mode is used. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] burst unsigned int8. Memory Burst selection @ref dma_mburst +*/ + +void dma_set_memory_burst(u32 dma, u8 stream, u32 burst) +{ + u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SCR_MBURST_MASK); + DMA_SCR(dma, stream) = (reg32 | burst); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set Peripheral Burst Configuration + +Set the memory burst type to none, 4 8 or 16 word length. This is forced to none +if direct mode is used. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] burst unsigned int8. Peripheral Burst selection @ref dma_pburst +*/ + +void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst) +{ + u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SCR_PBURST_MASK); + DMA_SCR(dma, stream) = (reg32 | burst); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set Initial Target Memory + +In double buffered mode, set the target memory (M0 or M1) to be used for the first +transfer. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] memory unsigned int8. Initial memory pointer to use: 0 or 1 +*/ + +void dma_set_initial_target(u32 dma, u8 stream, u8 memory) +{ + u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SCR_CT); + if (memory == 1) reg32 |= DMA_SCR_CT; + DMA_SCR(dma, stream) = reg32; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Read Current Memory Target + +In double buffer mode, return the current memory target (M0 or M1). It is possible +to update the memory pointer in the register that is not currently in +use. An attempt to change the register currently in use will cause the stream +to be disabled and the transfer error flag to be set. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@returns unsigned int8. Memory buffer in use: 0 or 1 +*/ + +u8 dma_get_target(u32 dma, u8 stream) +{ + if (DMA_SCR(dma, stream) & DMA_SCR_CT) return 1; + return 0; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable Double Buffer Mode + +Double buffer mode is used for memory to/from peripheral transfers only, and in +circular mode which is automatically enabled. Two memory buffers must be +established with pointers stored in the memory pointer registers. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@note This cannot be used with memory to memory mode. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_double_buffer_mode(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) |= DMA_SCR_DBM; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set Peripheral Flow Control + +Set the peripheral to control DMA flow. Useful when the number of transfers is +unknown. This is forced off when memory to memory mode is selected. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_set_peripheral_flow_control(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) |= DMA_SCR_PFCTRL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set DMA Flow Control + +Set the DMA controller to control DMA flow. This is the default. + +Ensure that the stream is disabled otherwise the setting will not be changed. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_set_dma_flow_control(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) &= ~DMA_SCR_PFCTRL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable Interrupt on Transfer Error + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_transfer_error_interrupt(u32 dma, u8 stream) +{ + dma_clear_interrupt_flags(dma, stream, DMA_ISR_TEIF); + DMA_SCR(dma, stream) |= DMA_SCR_TEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Disable Interrupt on Transfer Error + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_disable_transfer_error_interrupt(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) &= ~DMA_SCR_TEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable Interrupt on Transfer Half Complete + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_half_transfer_interrupt(u32 dma, u8 stream) +{ + dma_clear_interrupt_flags(dma, stream, DMA_ISR_HTIF); + DMA_SCR(dma, stream) |= DMA_SCR_HTIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Disable Interrupt on Transfer Half Complete + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_disable_half_transfer_interrupt(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) &= ~DMA_SCR_HTIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable Interrupt on Transfer Complete + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream) +{ + dma_clear_interrupt_flags(dma, stream, DMA_ISR_TCIF); + DMA_SCR(dma, stream) |= DMA_SCR_TCIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Disable Interrupt on Transfer Complete + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) &= ~DMA_SCR_TCIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable Interrupt on Direct Mode Error + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream) +{ + dma_clear_interrupt_flags(dma, stream, DMA_ISR_DMEIF); + DMA_SCR(dma, stream) |= DMA_SCR_DMEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Disable Interrupt on Direct Mode Error + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) &= ~DMA_SCR_DMEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Enable Interrupt on FIFO Error + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_fifo_error_interrupt(u32 dma, u8 stream) +{ + dma_clear_interrupt_flags(dma, stream, DMA_ISR_FEIF); + DMA_SFCR(dma, stream) |= DMA_FCR_FEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Disable Interrupt on FIFO Error + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_disable_fifo_error_interrupt(u32 dma, u8 stream) +{ + DMA_SFCR(dma, stream) &= ~DMA_FCR_FEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Get FIFO Status + +Status of FIFO (empty. full or partial filled states) is returned. This has no +meaning if direct mode is enabled (as the FIFO is not used). + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@returns u32 FIFO Status @ref dma_fifo_status +*/ + +u32 dma_fifo_status(u32 dma, u8 stream) +{ + return (DMA_SFCR(dma, stream) & DMA_FCR_FS_MASK); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Enable Direct Mode + +Direct mode is the default. Data is transferred as soon as a DMA request is +received. The FIFO is not used. This must not be set when memory to memory +mode is selected. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_direct_mode(u32 dma, u8 stream) +{ + DMA_SFCR(dma, stream) &= ~DMA_FCR_DMDIS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Enable FIFO Mode + +Data is transferred via a FIFO. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_fifo_mode(u32 dma, u8 stream) +{ + DMA_SFCR(dma, stream) |= DMA_FCR_DMDIS; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Set FIFO Threshold + +This is the filled level at which data is transferred out of the FIFO to the +destination. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] threshold unsigned int8. Threshold setting @ref dma_fifo_thresh +*/ + +void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold) +{ + u32 reg32 = (DMA_SFCR(dma, stream) & ~DMA_FCR_FTH_MASK); + DMA_SFCR(dma, stream) = (reg32 | threshold); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Enable + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_enable_stream(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) |= DMA_SCR_EN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Disable + +@note The DMA stream registers retain their values when the stream is disabled. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +*/ + +void dma_disable_stream(u32 dma, u8 stream) +{ + DMA_SCR(dma, stream) &= ~DMA_SCR_EN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set the Peripheral Address + +Set the address of the peripheral register to or from which data is to be transferred. +Refer to the documentation for the specific peripheral. + +@note The DMA stream must be disabled before setting this address. This function +has no effect if the stream is enabled. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] address unsigned int32. Peripheral Address. +*/ + +void dma_set_peripheral_address(u32 dma, u8 stream, u32 address) +{ + if (!(DMA_SCR(dma, stream) & DMA_SCR_EN)) + DMA_SPAR(dma, stream) = (u32) address; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set the Base Memory Address 0 + +Set the address pointer to the memory location for DMA transfers. The DMA stream +must normally be disabled before setting this address, however it is possible +to change this in double buffer mode when the current target is memory area 1 +(see @ref dma_get_target). + +This is the default base memory address used in direct mode. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] address unsigned int32. Memory Initial Address. +*/ + +void dma_set_memory_address(u32 dma, u8 stream, u32 address) +{ + u32 reg32 = DMA_SCR(dma, stream); + if ( !(reg32 & DMA_SCR_EN) || ((reg32 & DMA_SCR_CT) && (reg32 & DMA_SCR_DBM)) ) + DMA_SM0AR(dma, stream) = (u32) address; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set the Base Memory Address 1 + +Set the address pointer to the memory location for DMA transfers. The DMA stream +must normally be disabled before setting this address, however it is possible +to change this in double buffer mode when the current target is memory area 0 +(see @ref dma_get_target). + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] address unsigned int32. Memory Initial Address. +*/ + +void dma_set_memory_address_1(u32 dma, u8 stream, u32 address) +{ + u32 reg32 = DMA_SCR(dma, stream); + if ( !(reg32 & DMA_SCR_EN) || (!(reg32 & DMA_SCR_CT) && (reg32 & DMA_SCR_DBM)) ) + DMA_SM1AR(dma, stream) = (u32) address; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Stream Set the Transfer Block Size + +@note The DMA stream must be disabled before setting this count value. The count +is not changed if the stream is enabled. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] stream unsigned int8. Stream number: @ref dma_st_number +@param[in] number unsigned int16. Number of data words to transfer (65535 maximum). +*/ + +void dma_set_number_of_data(u32 dma, u8 stream, u16 number) +{ + DMA_SNDTR(dma, stream) = number; +} +/**@}*/ + -- cgit v1.2.3 From 7e9b79aa55875b636e690ddf6f9ec2ac7aebf786 Mon Sep 17 00:00:00 2001 From: Jeff Ciesielski Date: Wed, 31 Oct 2012 17:01:56 -0700 Subject: stm32/can: add 'shift' defines for can timing bits Useful whe you want to return min/max values of timing parameters --- include/libopencm3/stm32/can.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h index f787df7..1919da4 100644 --- a/include/libopencm3/stm32/can.h +++ b/include/libopencm3/stm32/can.h @@ -417,6 +417,7 @@ #define CAN_BTR_SJW_3TQ (0x2 << 24) #define CAN_BTR_SJW_4TQ (0x3 << 24) #define CAN_BTR_SJW_MASK (0x3 << 24) +#define CAN_BTR_SJW_SHIFT 24 /* 23 Reserved, forced by hardware to 0 */ @@ -430,6 +431,7 @@ #define CAN_BTR_TS2_7TQ (0x6 << 20) #define CAN_BTR_TS2_8TQ (0x7 << 20) #define CAN_BTR_TS2_MASK (0x7 << 20) +#define CAN_BTR_TS2_SHIFT 20 /* TS1[3:0]: Time segment 1 */ #define CAN_BTR_TS1_1TQ (0x0 << 16) @@ -449,6 +451,7 @@ #define CAN_BTR_TS1_15TQ (0xE << 16) #define CAN_BTR_TS1_16TQ (0xF << 16) #define CAN_BTR_TS1_MASK (0xF << 16) +#define CAN_BTR_TS1_SHIFT 16 /* 15:10 Reserved, forced by hardware to 0 */ -- cgit v1.2.3 From e5cf92b9aee4ce70f000961309d4fb9a9222a7b5 Mon Sep 17 00:00:00 2001 From: Jeff Ciesielski Date: Fri, 2 Nov 2012 10:52:25 -0700 Subject: stm32/f1/rcc: expose method for selecting MCO source --- include/libopencm3/stm32/f1/rcc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h index 52b3469..868ad9c 100644 --- a/include/libopencm3/stm32/f1/rcc.h +++ b/include/libopencm3/stm32/f1/rcc.h @@ -507,6 +507,7 @@ void rcc_osc_on(osc_t osc); void rcc_osc_off(osc_t osc); void rcc_css_enable(void); void rcc_css_disable(void); +void rcc_set_mco(u32 mcosrc); void rcc_osc_bypass_enable(osc_t osc); void rcc_osc_bypass_disable(osc_t osc); void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en); -- cgit v1.2.3 From 7a5da60e2669c57d7b615aabe16ab851606f8bf1 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 6 Nov 2012 16:46:55 -0800 Subject: Change USB strings handling code This commit add an extra field to the _usbd_device, that allows to keep track of the number of USB strings which allows simplify boundaries checking code in usb_standard_get_descriptor. This commit also changes the index base for strings in usb_standard_get_descriptor which allows to get rid of necessity to have a dummy one-character string in a strings array. --- include/libopencm3/usb/usbd.h | 2 +- lib/usb/usb.c | 4 +++- lib/usb/usb_private.h | 1 + lib/usb/usb_standard.c | 22 +++++++++++----------- 4 files changed, 16 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h index e4b3578..9da8379 100644 --- a/include/libopencm3/usb/usbd.h +++ b/include/libopencm3/usb/usbd.h @@ -38,7 +38,7 @@ extern u8 usbd_control_buffer[]; extern int usbd_init(const usbd_driver *driver, const struct usb_device_descriptor *dev, const struct usb_config_descriptor *conf, - const char **strings); + const char **strings, int num_strings); extern void usbd_set_control_buffer_size(u16 size); extern void usbd_register_reset_callback(void (*callback)(void)); diff --git a/lib/usb/usb.c b/lib/usb/usb.c index 1ebb6ec..d5ec980 100644 --- a/lib/usb/usb.c +++ b/lib/usb/usb.c @@ -45,12 +45,14 @@ u8 usbd_control_buffer[128] __attribute__((weak)); */ int usbd_init(const usbd_driver *driver, const struct usb_device_descriptor *dev, - const struct usb_config_descriptor *conf, const char **strings) + const struct usb_config_descriptor *conf, + const char **strings, int num_strings) { _usbd_device.driver = driver; _usbd_device.desc = dev; _usbd_device.config = conf; _usbd_device.strings = strings; + _usbd_device.num_strings = num_strings; _usbd_device.ctrl_buf = usbd_control_buffer; _usbd_device.ctrl_buf_len = sizeof(usbd_control_buffer); diff --git a/lib/usb/usb_private.h b/lib/usb/usb_private.h index a1e5e4c..238f14f 100644 --- a/lib/usb/usb_private.h +++ b/lib/usb/usb_private.h @@ -29,6 +29,7 @@ extern struct _usbd_device { const struct usb_device_descriptor *desc; const struct usb_config_descriptor *config; const char **strings; + int num_strings; u8 *ctrl_buf; /**< Internal buffer used for control transfers */ u16 ctrl_buf_len; diff --git a/lib/usb/usb_standard.c b/lib/usb/usb_standard.c index 2d7c619..1c8b952 100644 --- a/lib/usb/usb_standard.c +++ b/lib/usb/usb_standard.c @@ -90,7 +90,7 @@ static u16 build_config_descriptor(u8 index, u8 *buf, u16 len) static int usb_standard_get_descriptor(struct usb_setup_data *req, u8 **buf, u16 *len) { - int i; + int i, index; struct usb_string_descriptor *sd; switch (req->wValue >> 8) { @@ -105,16 +105,20 @@ static int usb_standard_get_descriptor(struct usb_setup_data *req, case USB_DT_STRING: sd = (struct usb_string_descriptor *)_usbd_device.ctrl_buf; + /* Send sane Language ID descriptor... */ + if ((req->wValue & 0xff) == 0) + sd->wData[0] = 0x409; + + index = (req->wValue & 0xff) - 1; + if (!_usbd_device.strings) return 0; /* Device doesn't support strings. */ /* Check that string index is in range. */ - for (i = 0; i <= (req->wValue & 0xff); i++) - if (_usbd_device.strings[i] == NULL) - return 0; + if (index >= _usbd_device.num_strings) + return 0; - sd->bLength = strlen(_usbd_device.strings[req->wValue & 0xff]) - * 2 + 2; + sd->bLength = strlen(_usbd_device.strings[index]) * 2 + 2; sd->bDescriptorType = USB_DT_STRING; *buf = (u8 *)sd; @@ -122,11 +126,7 @@ static int usb_standard_get_descriptor(struct usb_setup_data *req, for (i = 0; i < (*len / 2) - 1; i++) sd->wData[i] = - _usbd_device.strings[req->wValue & 0xff][i]; - - /* Send sane Language ID descriptor... */ - if ((req->wValue & 0xff) == 0) - sd->wData[0] = 0x409; + _usbd_device.strings[index][i]; return 1; } -- cgit v1.2.3 From 12e178686331fd0a8e3564a9f0e77fece4a04617 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 6 Nov 2012 16:48:40 -0800 Subject: Add a desig_get_unique_id_as_string This commit adds desig_get_unique_id_as_string which is useful if one wants to use device ID as USB serial number(iSerialNumber), for example. --- include/libopencm3/stm32/f1/desig.h | 9 +++++++++ lib/stm32/f1/desig.c | 22 ++++++++++++++++++++++ 2 files changed, 31 insertions(+) (limited to 'include') diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/f1/desig.h index 74cfb35..6ceb665 100644 --- a/include/libopencm3/stm32/f1/desig.h +++ b/include/libopencm3/stm32/f1/desig.h @@ -51,6 +51,15 @@ u16 desig_get_flash_size(void); */ void desig_get_unique_id(u32 result[]); +/** + * Read the full 96 bit unique identifier and return it as a + * zero-terminated string + * @param string memory region to write the result to + 8 @param string_len the size of string in bytes + */ +void desig_get_unique_id_as_string(char *string, + unsigned int string_len); + END_DECLS #endif diff --git a/lib/stm32/f1/desig.c b/lib/stm32/f1/desig.c index 7ae968e..7f213fa 100644 --- a/lib/stm32/f1/desig.c +++ b/lib/stm32/f1/desig.c @@ -35,3 +35,25 @@ void desig_get_unique_id(u32 result[]) result[1] = bits63_32; result[2] = bits31_16 << 16 | bits15_0; } + +void desig_get_unique_id_as_string(char *string, + unsigned int string_len) +{ + int i, len; + u8 device_id[12]; + static const char chars[] = "0123456789ABCDEF"; + + desig_get_unique_id((u32 *)device_id); + + /* Each byte produces two characters */ + len = (2 * sizeof(device_id) < string_len) ? + 2 * sizeof(device_id) : string_len - 1; + + for (i = 0; i < len; i += 2) { + string[i] = chars[(device_id[i / 2] >> 0) & 0x0F]; + string[i + 1] = chars[(device_id[i / 2] >> 4) & 0x0F]; + } + + string[len] = '\0'; +} + -- cgit v1.2.3 From c5c4db01969608ac19bba290b9f6ec965ef01e5c Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 7 Nov 2012 10:33:51 -0800 Subject: Extend control hook framework This commits adds a new error code that can be return from a registered control callback: USBD_REQ_NEXT_CALLBACK. This return code signifies that the callback is done processing the data successfully, but user would like to have all matching callbacks down the callback chain to be executed too. This change allows for example to intercept standard requests like GET_DESCRIPTOR, do some small action upon receiving of one, but still have the standard callback executed and do it's job. This way user doesn't have to re-implement standard GET_DESCRIPTOR functionality if they want to intercept that request to do some small thing. --- include/libopencm3/usb/usbd.h | 7 +++++++ lib/usb/usb_control.c | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h index 9da8379..8f68555 100644 --- a/include/libopencm3/usb/usbd.h +++ b/include/libopencm3/usb/usbd.h @@ -24,6 +24,13 @@ BEGIN_DECLS + +enum usbd_request_return_codes { + USBD_REQ_NOTSUPP = 0, + USBD_REQ_HANDLED = 1, + USBD_REQ_NEXT_CALLBACK = 2, +}; + typedef struct _usbd_driver usbd_driver; extern const usbd_driver stm32f103_usb_driver; extern const usbd_driver stm32f107_usb_driver; diff --git a/lib/usb/usb_control.c b/lib/usb/usb_control.c index 3dd0857..b4ac57e 100644 --- a/lib/usb/usb_control.c +++ b/lib/usb/usb_control.c @@ -102,7 +102,8 @@ static int usb_control_request_dispatch(struct usb_setup_data *req) result = cb[i].cb(req, &control_state.ctrl_buf, &control_state.ctrl_len, &control_state.complete); - if (result) + if (result == USBD_REQ_HANDLED || + result == USBD_REQ_NOTSUPP) return result; } } -- cgit v1.2.3 From 720e85f850064ad6ab3e79101b972e43d4e31ef6 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 7 Nov 2012 11:30:44 -0800 Subject: Further re-factor USB string handling code This commit refactors USB string code, making it, hopefully, less buggy and more easier to understand. It also removes "magic" bit manipulation and "magic" numbers; --- include/libopencm3/usb/usbstd.h | 3 ++ lib/usb/usb_standard.c | 70 +++++++++++++++++++++++++++-------------- 2 files changed, 50 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/libopencm3/usb/usbstd.h b/include/libopencm3/usb/usbstd.h index 8610fdb..01fc7e3 100644 --- a/include/libopencm3/usb/usbstd.h +++ b/include/libopencm3/usb/usbstd.h @@ -220,4 +220,7 @@ struct usb_iface_assoc_descriptor { #define USB_DT_INTERFACE_ASSOCIATION_SIZE \ sizeof(struct usb_iface_assoc_descriptor) +enum usb_language_id { + USB_LANGID_ENGLISH_US = 0x409, +}; #endif diff --git a/lib/usb/usb_standard.c b/lib/usb/usb_standard.c index 1c8b952..08923d8 100644 --- a/lib/usb/usb_standard.c +++ b/lib/usb/usb_standard.c @@ -87,50 +87,74 @@ static u16 build_config_descriptor(u8 index, u8 *buf, u16 len) return total; } +static int usb_descriptor_type(u16 wValue) +{ + return wValue >> 8; +} + +static int usb_descriptor_index(u16 wValue) +{ + return wValue & 0xFF; +} + static int usb_standard_get_descriptor(struct usb_setup_data *req, u8 **buf, u16 *len) { - int i, index; + int i, array_idx, descr_idx; struct usb_string_descriptor *sd; - switch (req->wValue >> 8) { + descr_idx = usb_descriptor_index(req->wValue); + + switch (usb_descriptor_type(req->wValue)) { case USB_DT_DEVICE: *buf = (u8 *) _usbd_device.desc; *len = MIN(*len, _usbd_device.desc->bLength); - return 1; + return USBD_REQ_HANDLED; case USB_DT_CONFIGURATION: *buf = _usbd_device.ctrl_buf; - *len = build_config_descriptor(req->wValue & 0xff, *buf, *len); - return 1; + *len = build_config_descriptor(descr_idx, *buf, *len); + return USBD_REQ_HANDLED; case USB_DT_STRING: sd = (struct usb_string_descriptor *)_usbd_device.ctrl_buf; - /* Send sane Language ID descriptor... */ - if ((req->wValue & 0xff) == 0) - sd->wData[0] = 0x409; + if (descr_idx == 0) { + /* Send sane Language ID descriptor... */ + sd->wData[0] = USB_LANGID_ENGLISH_US; + sd->bLength = sizeof(sd->bLength) + sizeof(sd->bDescriptorType) + + sizeof(sd->wData[0]); - index = (req->wValue & 0xff) - 1; + *len = MIN(*len, sd->bLength); + } else { + array_idx = descr_idx - 1; - if (!_usbd_device.strings) - return 0; /* Device doesn't support strings. */ + if (!_usbd_device.strings) + return USBD_REQ_NOTSUPP; /* Device doesn't support strings. */ + /* Check that string index is in range. */ + if (array_idx >= _usbd_device.num_strings) + return USBD_REQ_NOTSUPP; - /* Check that string index is in range. */ - if (index >= _usbd_device.num_strings) - return 0; + /* Strings with Language ID differnet from + * USB_LANGID_ENGLISH_US are not supported */ + if (req->wIndex != USB_LANGID_ENGLISH_US) + return USBD_REQ_NOTSUPP; - sd->bLength = strlen(_usbd_device.strings[index]) * 2 + 2; - sd->bDescriptorType = USB_DT_STRING; + /* Ths string is returned as UTF16, hence the multiplication */ + sd->bLength = strlen(_usbd_device.strings[array_idx]) * 2 + + sizeof(sd->bLength) + sizeof(sd->bDescriptorType); - *buf = (u8 *)sd; - *len = MIN(*len, sd->bLength); + *len = MIN(*len, sd->bLength); + + for (i = 0; i < (*len / 2) - 1; i++) + sd->wData[i] = + _usbd_device.strings[array_idx][i]; + } - for (i = 0; i < (*len / 2) - 1; i++) - sd->wData[i] = - _usbd_device.strings[index][i]; + sd->bDescriptorType = USB_DT_STRING; + *buf = (u8 *)sd; - return 1; + return USBD_REQ_HANDLED; } - return 0; + return USBD_REQ_NOTSUPP; } static int usb_standard_set_address(struct usb_setup_data *req, u8 **buf, -- cgit v1.2.3 From 2011941b55302ee269b440c32ad83a3fff326944 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 12 Jul 2012 20:01:54 +0000 Subject: Vectors and Memory Map for STM32L1 series --- include/libopencm3/stm32/desig.h | 56 ++++++++ include/libopencm3/stm32/f1/desig.h | 56 -------- include/libopencm3/stm32/l1/memorymap.h | 108 +++++++++++++++ include/libopencm3/stm32/memorymap.h | 2 + lib/stm32/desig.c | 37 ++++++ lib/stm32/f1/desig.c | 37 ------ lib/stm32/l1/Makefile | 58 ++++++++ lib/stm32/l1/vector.c | 228 ++++++++++++++++++++++++++++++++ 8 files changed, 489 insertions(+), 93 deletions(-) create mode 100644 include/libopencm3/stm32/desig.h delete mode 100644 include/libopencm3/stm32/f1/desig.h create mode 100644 include/libopencm3/stm32/l1/memorymap.h create mode 100644 lib/stm32/desig.c delete mode 100644 lib/stm32/f1/desig.c create mode 100644 lib/stm32/l1/Makefile create mode 100644 lib/stm32/l1/vector.c (limited to 'include') diff --git a/include/libopencm3/stm32/desig.h b/include/libopencm3/stm32/desig.h new file mode 100644 index 0000000..74cfb35 --- /dev/null +++ b/include/libopencm3/stm32/desig.h @@ -0,0 +1,56 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DESIG_H +#define LIBOPENCM3_DESIG_H + +#include +#include + +/* --- Device Electronic Signature -------------------------------- */ + +/* Flash size register */ +#define DESIG_FLASH_SIZE MMIO16(DESIG_FLASH_SIZE_BASE + 0x00) + +/* Unique ID register (96 bits) */ +/* Note: ST says these may be accessed in any width if you choose */ +#define DESIG_UID_15_0 MMIO16(DESIG_UNIQUE_ID_BASE + 0x00) +/* Listed as "This field value is also reserved for a future feature" WTH?! */ +#define DESIG_UID_31_16 MMIO16(DESIG_UNIQUE_ID_BASE + 0x02) +#define DESIG_UID_63_32 MMIO32(DESIG_UNIQUE_ID_BASE + 0x04) +#define DESIG_UID_95_64 MMIO32(DESIG_UNIQUE_ID_BASE + 0x08) + +BEGIN_DECLS + +/** + * Read the onboard flash size + * @return flash size in KB + */ +u16 desig_get_flash_size(void); + +/** + * Read the full 96 bit unique identifier + * Note: ST specifies that bits 31..16 are _also_ reserved for future use + * @param result pointer to at least 3xu32s (96 bits) + */ +void desig_get_unique_id(u32 result[]); + +END_DECLS + +#endif diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/f1/desig.h deleted file mode 100644 index 74cfb35..0000000 --- a/include/libopencm3/stm32/f1/desig.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DESIG_H -#define LIBOPENCM3_DESIG_H - -#include -#include - -/* --- Device Electronic Signature -------------------------------- */ - -/* Flash size register */ -#define DESIG_FLASH_SIZE MMIO16(DESIG_FLASH_SIZE_BASE + 0x00) - -/* Unique ID register (96 bits) */ -/* Note: ST says these may be accessed in any width if you choose */ -#define DESIG_UID_15_0 MMIO16(DESIG_UNIQUE_ID_BASE + 0x00) -/* Listed as "This field value is also reserved for a future feature" WTH?! */ -#define DESIG_UID_31_16 MMIO16(DESIG_UNIQUE_ID_BASE + 0x02) -#define DESIG_UID_63_32 MMIO32(DESIG_UNIQUE_ID_BASE + 0x04) -#define DESIG_UID_95_64 MMIO32(DESIG_UNIQUE_ID_BASE + 0x08) - -BEGIN_DECLS - -/** - * Read the onboard flash size - * @return flash size in KB - */ -u16 desig_get_flash_size(void); - -/** - * Read the full 96 bit unique identifier - * Note: ST specifies that bits 31..16 are _also_ reserved for future use - * @param result pointer to at least 3xu32s (96 bits) - */ -void desig_get_unique_id(u32 result[]); - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h new file mode 100644 index 0000000..950dd18 --- /dev/null +++ b/include/libopencm3/stm32/l1/memorymap.h @@ -0,0 +1,108 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE ((u32)0x40000000) +#define INFO_BASE ((u32)0x1ff00000) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) +// datasheet has an error? here +#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) +#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) +/* gap */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00) +#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04) + +/* APB2 */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000) +/* gap */ +#define ADC_BASE (PERIPH_BASE_APB2 + 0x2400) +/* gap */ +#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +/* gap */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) + +/* AHB */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400) +/* gap */ +#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) +/* gap */ +#define RCC_BASE (PERIPH_BASE_AHB + 0x03800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00) +/* gap */ +#define DMA_BASE (PERIPH_BASE_AHB + 0x06000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* FSMC */ +#define FSMC_BASE (PERIPH_BASE + 0x60000000) +/* AES */ +#define AES_BASE (PERIPH_BASE + 0x10000000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C) +#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050) + +#endif diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h index 6f213da..9b757ce 100644 --- a/include/libopencm3/stm32/memorymap.h +++ b/include/libopencm3/stm32/memorymap.h @@ -26,6 +26,8 @@ # include #elif defined(STM32F4) # include +#elif defined(STM32L1) +# include #else # error "stm32 family not defined." #endif diff --git a/lib/stm32/desig.c b/lib/stm32/desig.c new file mode 100644 index 0000000..0743dc8 --- /dev/null +++ b/lib/stm32/desig.c @@ -0,0 +1,37 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +u16 desig_get_flash_size(void) +{ + return DESIG_FLASH_SIZE; +} + +void desig_get_unique_id(u32 result[]) +{ + // Could also just return a pointer to the start? read it as they wish? + u16 bits15_0 = DESIG_UID_15_0; + u32 bits31_16 = DESIG_UID_31_16; + u32 bits63_32 = DESIG_UID_63_32; + u32 bits95_64 = DESIG_UID_95_64; + result[0] = bits95_64; + result[1] = bits63_32; + result[2] = bits31_16 << 16 | bits15_0; +} diff --git a/lib/stm32/f1/desig.c b/lib/stm32/f1/desig.c deleted file mode 100644 index 7ae968e..0000000 --- a/lib/stm32/f1/desig.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -u16 desig_get_flash_size(void) -{ - return DESIG_FLASH_SIZE; -} - -void desig_get_unique_id(u32 result[]) -{ - // Could also just return a pointer to the start? read it as they wish? - u16 bits15_0 = DESIG_UID_15_0; - u32 bits31_16 = DESIG_UID_31_16; - u32 bits63_32 = DESIG_UID_63_32; - u32 bits95_64 = DESIG_UID_95_64; - result[0] = bits95_64; - result[1] = bits63_32; - result[2] = bits31_16 << 16 | bits15_0; -} diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile new file mode 100644 index 0000000..d2cc1be --- /dev/null +++ b/lib/stm32/l1/Makefile @@ -0,0 +1,58 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_stm32l1 + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ + -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSTM32L1 +# ARFLAGS = rcsv +ARFLAGS = rcs +OBJS = vector.o desig.o crc.o + +VPATH += ../../usb:../ + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +endif + +all: $(LIBNAME).a + +$(LIBNAME).a: $(OBJS) + @printf " AR $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(AR) $(ARFLAGS) $@ $^ + +%.o: %.c + @printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + @printf " CLEAN lib/stm32/f1\n" + $(Q)rm -f *.o *.d + $(Q)rm -f $(LIBNAME).a + +.PHONY: clean + +-include $(OBJS:.o=.d) + diff --git a/lib/stm32/l1/vector.c b/lib/stm32/l1/vector.c new file mode 100644 index 0000000..d8e0ea5 --- /dev/null +++ b/lib/stm32/l1/vector.c @@ -0,0 +1,228 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by the linker script(s). */ +extern unsigned __exidx_end, _data, _edata, _ebss, _stack; + +void main(void); +void reset_handler(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamper_isr(void); +void WEAK rtc_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_channel1_isr(void); +void WEAK dma1_channel2_isr(void); +void WEAK dma1_channel3_isr(void); +void WEAK dma1_channel4_isr(void); +void WEAK dma1_channel5_isr(void); +void WEAK dma1_channel6_isr(void); +void WEAK dma1_channel7_isr(void); +void WEAK adc1_isr(void); +void WEAK usb_hp_isr(void); +void WEAK usb_lp_isr(void); +void WEAK dac_isr(void); +void WEAK comp_isr(void); +void WEAK exti9_5_isr(void); +void WEAK lcd_isr(void); +void WEAK tim9_isr(void); +void WEAK tim10_isr(void); +void WEAK tim11_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_wakeup_isr(void); +void WEAK tim6_isr(void); +void WEAK tim7_isr(void); + + +__attribute__ ((section(".vectors"))) +void (*const vector_table[]) (void) = { + (void*)&_stack, /* Addr: 0x0000_0000 */ + reset_handler, /* Addr: 0x0000_0004 */ + nmi_handler, /* Addr: 0x0000_0008 */ + hard_fault_handler, /* Addr: 0x0000_000C */ + mem_manage_handler, /* Addr: 0x0000_0010 */ + bus_fault_handler, /* Addr: 0x0000_0014 */ + usage_fault_handler, /* Addr: 0x0000_0018 */ + 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ + sv_call_handler, /* Addr: 0x0000_002C */ + debug_monitor_handler, /* Addr: 0x0000_0030*/ + 0, /* Reserved Addr: 0x0000_00034 */ + pend_sv_handler, /* Addr: 0x0000_0038 */ + sys_tick_handler, /* Addr: 0x0000_003C */ + wwdg_isr, /* Addr: 0x0000_0040 */ + pvd_isr, /* Addr: 0x0000_0044 */ + tamper_isr, /* Addr: 0x0000_0048 */ + rtc_isr, /* Addr: 0x0000_004C */ + flash_isr, /* Addr: 0x0000_0050 */ + rcc_isr, /* Addr: 0x0000_0054 */ + exti0_isr, /* Addr: 0x0000_0058 */ + exti1_isr, /* Addr: 0x0000_005C */ + exti2_isr, /* Addr: 0x0000_0060 */ + exti3_isr, /* Addr: 0x0000_0064 */ + exti4_isr, /* Addr: 0x0000_0068 */ + dma1_channel1_isr, /* Addr: 0x0000_006C */ + dma1_channel2_isr, /* Addr: 0x0000_0070 */ + dma1_channel3_isr, /* Addr: 0x0000_0074 */ + dma1_channel4_isr, /* Addr: 0x0000_0078 */ + dma1_channel5_isr, /* Addr: 0x0000_007C */ + dma1_channel6_isr, /* Addr: 0x0000_0080 */ + dma1_channel7_isr, /* Addr: 0x0000_0084 */ + adc1_isr, /* Addr: 0x0000_0088 */ + usb_hp_isr, /* Addr: 0x0000_008C */ + usb_lp_isr, /* Addr: 0x0000_0090 */ + dac_isr, /* Addr: 0x0000_0094 */ + comp_isr, /* Addr: 0x0000_0098 */ + exti9_5_isr, /* Addr: 0x0000_009C */ + lcd_isr, /* Addr: 0x0000_00A0 */ + tim9_isr, /* Addr: 0x0000_00A4 */ + tim10_isr, /* Addr: 0x0000_00A8 */ + tim11_isr, /* Addr: 0x0000_00AC */ + tim2_isr, /* Addr: 0x0000_00B0 */ + tim3_isr, /* Addr: 0x0000_00B4 */ + tim4_isr, /* Addr: 0x0000_00B8 */ + i2c1_ev_isr, /* Addr: 0x0000_00BC */ + i2c1_er_isr, /* Addr: 0x0000_00C0 */ + i2c2_ev_isr, /* Addr: 0x0000_00C4 */ + i2c2_er_isr, /* Addr: 0x0000_00C8 */ + spi1_isr, /* Addr: 0x0000_00CC */ + spi2_isr, /* Addr: 0x0000_00D0 */ + usart1_isr, /* Addr: 0x0000_00D4 */ + usart2_isr, /* Addr: 0x0000_00D8 */ + usart3_isr, /* Addr: 0x0000_00DC */ + exti15_10_isr, /* Addr: 0x0000_00E0 */ + rtc_alarm_isr, /* Addr: 0x0000_00E4 */ + usb_wakeup_isr, /* Addr: 0x0000_00E8 */ + tim6_isr, /* Addr: 0x0000_00EC */ + tim7_isr, /* Addr: 0x0000_00F0 */ +}; + +void reset_handler(void) +{ + volatile unsigned *src, *dest; + + __asm__("MSR msp, %0" : : "r"(&_stack)); + + for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamper_isr = null_handler +#pragma weak rtc_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_channel1_isr = null_handler +#pragma weak dma1_channel2_isr = null_handler +#pragma weak dma1_channel3_isr = null_handler +#pragma weak dma1_channel4_isr = null_handler +#pragma weak dma1_channel5_isr = null_handler +#pragma weak dma1_channel6_isr = null_handler +#pragma weak dma1_channel7_isr = null_handler +#pragma weak adc1_isr = null_handler +#pragma weak usb_hp_isr = null_handler +#pragma weak usb_lp_isr = null_handler +#pragma weak dac_isr = null_handler +#pragma weak comp_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak lcd_isr = null_handler +#pragma weak tim9_isr = null_handler +#pragma weak tim10_isr = null_handler +#pragma weak tim11_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_wakeup_isr = null_handler +#pragma weak tim6_isr = null_handler +#pragma weak tim7_isr = null_handler -- cgit v1.2.3 From 8318384cf1fec4d0b336e5d4deb1f126526584be Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 19 Jul 2012 22:41:52 +0000 Subject: More progress towards L1 support. Believe gpio is complete, but untested without finishing at least the RCC defines. RCC defines are a work in progress --- Makefile | 2 +- examples/stm32/l1/Makefile.include | 165 ++++++++ .../stm32/l1/stm32l-discovery/miniblink/Makefile | 25 ++ .../stm32/l1/stm32l-discovery/miniblink/README | 9 + .../l1/stm32l-discovery/miniblink/miniblink.c | 72 ++++ include/libopencm3/stm32/l1/gpio.h | 241 +++++++++++ include/libopencm3/stm32/l1/rcc.h | 453 +++++++++++++++++++++ lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/libopencm3_stm32l1.ld | 84 ++++ lib/stm32/l1/stm32l15xx8.ld | 31 ++ lib/stm32/l1/stm32l15xxB.ld | 31 ++ 11 files changed, 1113 insertions(+), 2 deletions(-) create mode 100644 examples/stm32/l1/Makefile.include create mode 100644 examples/stm32/l1/stm32l-discovery/miniblink/Makefile create mode 100644 examples/stm32/l1/stm32l-discovery/miniblink/README create mode 100644 examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c create mode 100644 include/libopencm3/stm32/l1/gpio.h create mode 100644 include/libopencm3/stm32/l1/rcc.h create mode 100644 lib/stm32/l1/libopencm3_stm32l1.ld create mode 100644 lib/stm32/l1/stm32l15xx8.ld create mode 100644 lib/stm32/l1/stm32l15xxB.ld (limited to 'include') diff --git a/Makefile b/Makefile index 83332e9..6c060bf 100644 --- a/Makefile +++ b/Makefile @@ -32,7 +32,7 @@ SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL = install SRCLIBDIR = $(shell pwd)/lib -TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lpc43xx lm3s efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg +TARGETS = stm32/f1 stm32/f2 stm32/f4 stm32/l1 lpc13xx lpc17xx lpc43xx lm3s efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) diff --git a/examples/stm32/l1/Makefile.include b/examples/stm32/l1/Makefile.include new file mode 100644 index 0000000..f152b2a --- /dev/null +++ b/examples/stm32/l1/Makefile.include @@ -0,0 +1,165 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2010 Piotr Esden-Tempski +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +LD = $(PREFIX)-gcc +OBJCOPY = $(PREFIX)-objcopy +OBJDUMP = $(PREFIX)-objdump +GDB = $(PREFIX)-gdb +# If you are copying this file to use in your own project, +# You will need to change this... (Leave unset to assume installed +# in the toolchain itself) +#OPENCM3_DIR ?= /opt/libopencm3/$(PREFIX) +OPENCM3_DIR ?= ../../../../.. + +ARCH_FLAGS = -mcpu=cortex-m3 -mthumb -msoft-float +CFLAGS += -g -Os -Wall -Wextra \ + -fno-common $(ARCH_FLAGS) -MD -DSTM32L1 +LDSCRIPT ?= $(BINARY).ld +LDFLAGS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \ + -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ + $(ARCH_FLAGS) -mfix-cortex-m3-ldrd + +ifneq ($(OPENCM3_DIR),) +CFLAGS += -I$(OPENCM3_DIR)/include +LDFLAGS += -L$(OPENCM3_DIR)/lib -L$(OPENCM3_DIR)/lib/stm32/l1 +SCRIPT_DIR = $(OPENCM3_DIR)/share +else +SCRIPT_DIR = $(shell dirname $(shell readlink -f $(shell which $(PREFIX)-gcc)))/../$(PREFIX)/share +endif + +OBJS += $(BINARY).o + +OOCD ?= openocd +OOCD_INTERFACE ?= flossjtag +OOCD_BOARD ?= olimex_stm32_h103 +# Black magic probe specific variables +# Set the BMP_PORT to a serial port and then BMP is used for flashing +BMP_PORT ?= +# texane/stlink can be used by uncommenting this... +# or defining it in your own makefiles +#STLINK_PORT ?= :4242 + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +NULL := 2>/dev/null +else +LDFLAGS += -Wl,--print-gc-sections +endif + +.SUFFIXES: .elf .bin .hex .srec .list .images +.SECONDEXPANSION: +.SECONDARY: + +all: images + +images: $(BINARY).images +flash: $(BINARY).flash + +%.images: %.bin %.hex %.srec %.list + @#echo "*** $* images generated ***" + +%.bin: %.elf + @#printf " OBJCOPY $(*).bin\n" + $(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin + +%.hex: %.elf + @#printf " OBJCOPY $(*).hex\n" + $(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex + +%.srec: %.elf + @#printf " OBJCOPY $(*).srec\n" + $(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec + +%.list: %.elf + @#printf " OBJDUMP $(*).list\n" + $(Q)$(OBJDUMP) -S $(*).elf > $(*).list + +ifeq ($(OPENCM3_DIR),) +%.elf: $(OBJS) $(LDSCRIPT) +else +%.elf: $(OBJS) $(LDSCRIPT) $(OPENCM3_DIR)/lib/stm32/l1/libopencm3_stm32l1.a +endif + @#printf " LD $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32l1 $(LDFLAGS) + +%.o: %.c Makefile + @#printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + $(Q)rm -f *.o + $(Q)rm -f *.d + $(Q)rm -f *.elf + $(Q)rm -f *.bin + $(Q)rm -f *.hex + $(Q)rm -f *.srec + $(Q)rm -f *.list + +ifeq ($(STLINK_PORT),) +ifeq ($(BMP_PORT),) +ifeq ($(OOCD_SERIAL),) +%.flash: %.hex + @printf " FLASH $<\n" + @# IMPORTANT: Don't use "resume", only "reset" will work correctly! + $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ + -f board/$(OOCD_BOARD).cfg \ + -c "init" -c "reset init" \ + -c "stm32l1x mass_erase 0" \ + -c "flash write_image $(*).hex" \ + -c "reset" \ + -c "shutdown" $(NULL) +else +%.flash: %.hex + @printf " FLASH $<\n" + @# IMPORTANT: Don't use "resume", only "reset" will work correctly! + $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ + -f board/$(OOCD_BOARD).cfg \ + -c "ft2232_serial $(OOCD_SERIAL)" \ + -c "init" -c "reset init" \ + -c "stm32l1x mass_erase 0" \ + -c "flash write_image $(*).hex" \ + -c "reset" \ + -c "shutdown" $(NULL) +endif +else +%.flash: %.elf + @echo " GDB $(*).elf (flash)" + $(Q)$(GDB) --batch \ + -ex 'target extended-remote $(BMP_PORT)' \ + -x $(TOOLCHAIN_DIR)/scripts/black_magic_probe_flash.scr \ + $(*).elf +endif +else +%.flash: %.elf + @echo " GDB $(*).elf (flash)" + $(Q)$(GDB) --batch \ + -ex 'target extended-remote $(STLINK_PORT)' \ + -x $(SCRIPT_DIR)/libopencm3/scripts/stlink_flash.scr \ + $(*).elf +endif + +.PHONY: images clean + +-include $(OBJS:.o=.d) + diff --git a/examples/stm32/l1/stm32l-discovery/miniblink/Makefile b/examples/stm32/l1/stm32l-discovery/miniblink/Makefile new file mode 100644 index 0000000..8c88be0 --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/miniblink/Makefile @@ -0,0 +1,25 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = miniblink + +LDSCRIPT = ../stm32l15xxB.ld + +include ../../Makefile.include + diff --git a/examples/stm32/l1/stm32l-discovery/miniblink/README b/examples/stm32/l1/stm32l-discovery/miniblink/README new file mode 100644 index 0000000..8bdd314 --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/miniblink/README @@ -0,0 +1,9 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + +It's intended for the ST STM32L-DISCOVERY eval board. It should blink +the blue LED on the board. + diff --git a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c new file mode 100644 index 0000000..a9d7c3d --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c @@ -0,0 +1,72 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2011 Stephen Caudle + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#define PORT_LED GPIOB +#define PIN_LED GPIO6 + +void gpio_setup(void) +{ + /* Enable GPIOB clock. */ + /* Manually: */ + RCC_AHBENR |= RCC_AHBENR_IOPBEN; + /* Using API functions: */ + //rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPBEN); + + /* Set GPIO6 (in GPIO port B) to 'output push-pull'. */ + /* Using API functions: */ + gpio_mode_setup(PORT_LED, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, PIN_LED); +} + +int main(void) +{ + int i; + + gpio_setup(); + + /* Blink the LED (PC8) on the board. */ + while (1) { + /* Manually: */ + // GPIOD_BSRR = GPIO12; /* LED off */ + // for (i = 0; i < 1000000; i++) /* Wait a bit. */ + // __asm__("nop"); + // GPIOD_BRR = GPIO12; /* LED on */ + // for (i = 0; i < 1000000; i++) /* Wait a bit. */ + // __asm__("nop"); + + /* Using API functions gpio_set()/gpio_clear(): */ + // gpio_set(GPIOD, GPIO12); /* LED off */ + // for (i = 0; i < 1000000; i++) /* Wait a bit. */ + // __asm__("nop"); + // gpio_clear(GPIOD, GPIO12); /* LED on */ + // for (i = 0; i < 1000000; i++) /* Wait a bit. */ + // __asm__("nop"); + + /* Using API function gpio_toggle(): */ + gpio_toggle(PORT_LED, PORT_LED); /* LED on/off */ + for (i = 0; i < 1000000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h new file mode 100644 index 0000000..76325a9 --- /dev/null +++ b/include/libopencm3/stm32/l1/gpio.h @@ -0,0 +1,241 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOH GPIO_PORT_H_BASE + +/* GPIO number definitions (for convenience) */ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff + +/* --- GPIO registers ------------------------------------------------------ */ + +/* Port mode register (GPIOx_MODER) */ +#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIOA_MODER GPIO_MODER(GPIOA) +#define GPIOB_MODER GPIO_MODER(GPIOB) +#define GPIOC_MODER GPIO_MODER(GPIOC) +#define GPIOD_MODER GPIO_MODER(GPIOD) +#define GPIOE_MODER GPIO_MODER(GPIOE) +#define GPIOH_MODER GPIO_MODER(GPIOH) + +/* Port output type register (GPIOx_OTYPER) */ +#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) +#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) +#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) +#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) +#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) +#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) + +/* Port output speed register (GPIOx_OSPEEDR) */ +#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) +#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) +#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) +#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) +#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) +#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) + +/* Port pull-up/pull-down register (GPIOx_PUPDR) */ +#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) +#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) +#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) +#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) +#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) +#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOH_IDR GPIO_IDR(GPIOH) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOH_ODR GPIO_ODR(GPIOH) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOH_BSRR GPIO_BSRR(GPIOH) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x1C) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOH_LCKR GPIO_LCKR(GPIOH) + +/* Alternate function low register (GPIOx_AFRL) */ +#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIOA_AFRL GPIO_AFRL(GPIOA) +#define GPIOB_AFRL GPIO_AFRL(GPIOB) +#define GPIOC_AFRL GPIO_AFRL(GPIOC) +#define GPIOD_AFRL GPIO_AFRL(GPIOD) +#define GPIOE_AFRL GPIO_AFRL(GPIOE) +#define GPIOH_AFRL GPIO_AFRL(GPIOH) + +/* Alternate function high register (GPIOx_AFRH) */ +#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIOA_AFRH GPIO_AFRH(GPIOA) +#define GPIOB_AFRH GPIO_AFRH(GPIOB) +#define GPIOC_AFRH GPIO_AFRH(GPIOC) +#define GPIOD_AFRH GPIO_AFRH(GPIOD) +#define GPIOE_AFRH GPIO_AFRH(GPIOE) +#define GPIOH_AFRH GPIO_AFRH(GPIOH) + +/* --- GPIOx_MODER values-------------------------------------------- */ + +#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) +#define GPIO_MODE_INPUT 0x00 /* Default */ +#define GPIO_MODE_OUTPUT 0x01 +#define GPIO_MODE_ALTFN 0x02 +#define GPIO_MODE_ANALOG 0x03 + +/* --- GPIOx_OTYPER values -------------------------------------------- */ +/* Output type (OTx values) */ +#define GPIO_OTYPE_PP 0x0 +#define GPIO_OTYPE_OD 0x1 + +/* Output speed values */ +#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) +#define GPIO_OSPEED_400KHZ 0x0 +#define GPIO_OSPEED_2MHZ 0x1 +#define GPIO_OSPEED_10MHZ 0x2 +#define GPIO_OSPEED_40MHZ 0x3 + +/* --- GPIOx_PUPDR values ------------------------------------------- */ + +#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) +#define GPIO_PUPD_NONE 0x0 +#define GPIO_PUPD_PULLUP 0x1 +#define GPIO_PUPD_PULLDOWN 0x2 + +/* --- GPIO_IDR values ----------------------------------------------------- */ + +/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIO_ODR values ----------------------------------------------------- */ + +/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIO_BSRR values ---------------------------------------------------- */ + +/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIO_LCKR values ---------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- GPIOx_AFRL/H values ------------------------------------------------- */ + +/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ +/* See datasheet table 5, page 35 for the definitions */ + +#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) +#define GPIO_AF0 0x0 +#define GPIO_AF1 0x1 +#define GPIO_AF2 0x2 +#define GPIO_AF3 0x3 +#define GPIO_AF4 0x4 +#define GPIO_AF5 0x5 +#define GPIO_AF6 0x6 +#define GPIO_AF7 0x7 +#define GPIO_AF8 0x8 +#define GPIO_AF9 0x9 +#define GPIO_AF10 0xa +#define GPIO_AF11 0xb +#define GPIO_AF12 0xc +#define GPIO_AF13 0xd +#define GPIO_AF14 0xe +#define GPIO_AF15 0xf + +/* --- Function prototypes ------------------------------------------------- */ + +/* + * L1, like F2 and F4, has the "new" GPIO peripheral, so use that style + * TODO: this should all really be moved to a "common" gpio header + */ + +void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios); +void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios); +void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios); + +/* F1 compatible api */ +void gpio_set(u32 gpioport, u16 gpios); +void gpio_clear(u32 gpioport, u16 gpios); +u16 gpio_get(u32 gpioport, u16 gpios); +void gpio_toggle(u32 gpioport, u16 gpios); +u16 gpio_port_read(u32 gpioport); +void gpio_port_write(u32 gpioport, u16 data); +void gpio_port_config_lock(u32 gpioport, u16 gpios); + +#endif diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h new file mode 100644 index 0000000..ebcca86 --- /dev/null +++ b/include/libopencm3/stm32/l1/rcc.h @@ -0,0 +1,453 @@ +/** @file + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx Reset and Clock Control + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \ +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 Karl Palsson + +@date 18 May 2012 + +LGPL License Terms @ref lgpl_license + */ +/** @defgroup STM32L1xx_rcc_defines + +@brief Defined Constants and Types for the STM32L1xx Reset and Clock Control + +@ingroup STM32L1xx_defines + +LGPL License Terms @ref lgpl_license + + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + * + * Originally based on the F1 code, as it seemed most similar to the L1 + * TODO: very incomplete still! + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +#include +#include + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) +#define RCC_CFGR MMIO32(RCC_BASE + 0x08) +#define RCC_CIR MMIO32(RCC_BASE + 0x0c) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28) +#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c) +#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30) +#define RCC_CSR MMIO32(RCC_BASE + 0x34) + +/* --- RCC_CR values ------------------------------------------------------- */ + +/* RTCPRE[1:0] at 30:29 */ +#define RCC_CR_CSSON (1 << 28) +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +#define RCC_CR_MSIRDY (1 << 9) +#define RCC_CR_MSION (1 << 8) +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_ICSCR values ---------------------------------------------------- */ + +// TODO + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +/* MCOPRE */ +#define RCC_CFGR_MCOPRE_DIV1 0 +#define RCC_CFGR_MCOPRE_DIV2 1 +#define RCC_CFGR_MCOPRE_DIV4 2 +#define RCC_CFGR_MCOPRE_DIV8 3 +#define RCC_CFGR_MCOPRE_DIV16 4 + +/* MCO: Microcontroller clock output */ +#define RCC_CFGR_MCO_NOCLK 0x0 +#define RCC_CFGR_MCO_SYSCLK 0x1 +#define RCC_CFGR_MCO_HSICLK 0x2 +#define RCC_CFGR_MCO_MSICLK 0x3 +#define RCC_CFGR_MCO_HSECLK 0x4 +#define RCC_CFGR_MCO_PLLCLK 0x5 +#define RCC_CFGR_MCO_LSICLK 0x6 +#define RCC_CFGR_MCO_LSECLK 0x7 + +/* PLL Output division selection */ +#define RCC_CFGR_PLLDIV_DIV2 0x1 +#define RCC_CFGR_PLLDIV_DIV3 0x2 +#define RCC_CFGR_PLLDIV_DIV4 0x3 + +/* PLLMUL: PLL multiplication factor */ +#define RCC_CFGR_PLLMUL_MUL3 0x0 +#define RCC_CFGR_PLLMUL_MUL4 0x1 +#define RCC_CFGR_PLLMUL_MUL6 0x2 +#define RCC_CFGR_PLLMUL_MUL8 0x3 +#define RCC_CFGR_PLLMUL_MUL12 0x4 +#define RCC_CFGR_PLLMUL_MUL16 0x5 +#define RCC_CFGR_PLLMUL_MUL24 0x6 +#define RCC_CFGR_PLLMUL_MUL32 0x7 +#define RCC_CFGR_PLLMUL_MUL48 0x8 + +/* PLLSRC: PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI_CLK 0x0 +#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 + +/* PPRE2: APB high-speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 + +/* PPRE1: APB low-speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 + +/* HPRE: AHB prescaler */ +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0 +#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1 +#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2 +#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0 +#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1 +#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2 +#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_MSIRDYC (1 << 21) +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_MSIRDYIE (1 << 13) +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */ +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_AHBRSTR values ------------------------------------------------- */ +#define RCC_AHBRSTR_DMA1RST (1 << 24) +#define RCC_AHBRSTR_FLITFRST (1 << 15) +#define RCC_AHBRSTR_CRCRST (1 << 12) +#define RCC_AHBRSTR_GPIOHRST (1 << 5) +#define RCC_AHBRSTR_GPIOERST (1 << 4) +#define RCC_AHBRSTR_GPIODRST (1 << 3) +#define RCC_AHBRSTR_GPIOCRST (1 << 2) +#define RCC_AHBRSTR_GPIOBRST (1 << 1) +#define RCC_AHBRSTR_GPIOARST (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_ADC1RST (1 << 9) +#define RCC_APB2RSTR_TIM11RST (1 << 4) +#define RCC_APB2RSTR_TIM10RST (1 << 3) +#define RCC_APB2RSTR_TIM9RST (1 << 2) +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +TODO : up to here + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_BKPRST (1 << 27) +#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ +#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ +#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_UART5RST (1 << 20) +#define RCC_APB1RSTR_UART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_AHBENR values --------------------------------------------------- */ + +/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values +@ingroup STM32L1xx_rcc_defines + +@{*/ +#define RCC_AHBENR_ETHMACENRX (1 << 16) +#define RCC_AHBENR_ETHMACENTX (1 << 15) +#define RCC_AHBENR_ETHMACEN (1 << 14) +#define RCC_AHBENR_OTGFSEN (1 << 12) +#define RCC_AHBENR_SDIOEN (1 << 10) +#define RCC_AHBENR_FSMCEN (1 << 8) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLITFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMA2EN (1 << 1) +#define RCC_AHBENR_DMA1EN (1 << 0) +/*@}*/ + +/* --- RCC_APB2ENR values -------------------------------------------------- */ + +/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values +@ingroup STM32L1xx_rcc_defines + +@{*/ +#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_ADC2EN (1 << 10) +#define RCC_APB2ENR_ADC1EN (1 << 9) +#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ +#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ +#define RCC_APB2ENR_IOPEEN (1 << 6) +#define RCC_APB2ENR_IOPDEN (1 << 5) +#define RCC_APB2ENR_IOPCEN (1 << 4) +#define RCC_APB2ENR_IOPBEN (1 << 3) +#define RCC_APB2ENR_IOPAEN (1 << 2) +#define RCC_APB2ENR_AFIOEN (1 << 0) +/*@}*/ + +/* --- RCC_APB1ENR values -------------------------------------------------- */ + +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@ingroup STM32L1xx_rcc_defines + +@{*/ +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_BKPEN (1 << 27) +#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ +#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ +#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_UART5EN (1 << 20) +#define RCC_APB1ENR_UART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) +/*@}*/ + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_AHBRSTR values -------------------------------------------------- */ + +#define RCC_AHBRSTR_ETHMACRST (1 << 14) +#define RCC_AHBRSTR_OTGFSRST (1 << 12) + +/* --- RCC_CFGR2 values ---------------------------------------------------- */ + +/* I2S3SRC: I2S3 clock source */ +#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 + +/* I2S2SRC: I2S2 clock source */ +#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 + +/* PREDIV1SRC: PREDIV1 entry clock source */ +#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 +#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 + +#define RCC_CFGR2_PLL2MUL (1 << 0) +#define RCC_CFGR2_PREDIV2 (1 << 0) +#define RCC_CFGR2_PREDIV1 (1 << 0) + +/* PLL3MUL: PLL3 multiplication factor */ +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf + +/* PLL2MUL: PLL2 multiplication factor */ +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf + +/* PREDIV2: PREDIV2 division factor */ +#define RCC_CFGR2_PREDIV2_NODIV 0x0 +#define RCC_CFGR2_PREDIV2_DIV2 0x1 +#define RCC_CFGR2_PREDIV2_DIV3 0x2 +#define RCC_CFGR2_PREDIV2_DIV4 0x3 +#define RCC_CFGR2_PREDIV2_DIV5 0x4 +#define RCC_CFGR2_PREDIV2_DIV6 0x5 +#define RCC_CFGR2_PREDIV2_DIV7 0x6 +#define RCC_CFGR2_PREDIV2_DIV8 0x7 +#define RCC_CFGR2_PREDIV2_DIV9 0x8 +#define RCC_CFGR2_PREDIV2_DIV10 0x9 +#define RCC_CFGR2_PREDIV2_DIV11 0xa +#define RCC_CFGR2_PREDIV2_DIV12 0xb +#define RCC_CFGR2_PREDIV2_DIV13 0xc +#define RCC_CFGR2_PREDIV2_DIV14 0xd +#define RCC_CFGR2_PREDIV2_DIV15 0xe +#define RCC_CFGR2_PREDIV2_DIV16 0xf + +/* --- Variable definitions ------------------------------------------------ */ +extern u32 rcc_ppre1_frequency; +extern u32 rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + PLL, HSE, HSI, LSE, LSI +} osc_t; + +void rcc_osc_ready_int_clear(osc_t osc); +void rcc_osc_ready_int_enable(osc_t osc); +void rcc_osc_ready_int_disable(osc_t osc); +int rcc_osc_ready_int_flag(osc_t osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(osc_t osc); +void rcc_osc_on(osc_t osc); +void rcc_osc_off(osc_t osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(osc_t osc); +void rcc_osc_bypass_disable(osc_t osc); +void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en); +void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en); +void rcc_peripheral_reset(volatile u32 *reg, u32 reset); +void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset); +void rcc_set_sysclk_source(u32 clk); +void rcc_set_pll_multiplication_factor(u32 mul); +void rcc_set_pll_source(u32 pllsrc); +void rcc_set_pllxtpre(u32 pllxtpre); +void rcc_set_adcpre(u32 adcpre); +void rcc_set_ppre2(u32 ppre2); +void rcc_set_ppre1(u32 ppre1); +void rcc_set_hpre(u32 hpre); +void rcc_set_usbpre(u32 usbpre); +u32 rcc_get_system_clock_source(int i); +void rcc_clock_setup_in_hsi_out_64mhz(void); +void rcc_clock_setup_in_hsi_out_48mhz(void); + +/** + * Maximum speed possible for F100 (Value Line) on HSI + */ +void rcc_clock_setup_in_hsi_out_24mhz(void); +void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); +void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); +void rcc_backupdomain_reset(void); + +#endif diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index d2cc1be..543c416 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o desig.o crc.o +OBJS = vector.o desig.o crc.o gpio.o VPATH += ../../usb:../ diff --git a/lib/stm32/l1/libopencm3_stm32l1.ld b/lib/stm32/l1/libopencm3_stm32l1.ld new file mode 100644 index 0000000..a64a1f7 --- /dev/null +++ b/lib/stm32/l1/libopencm3_stm32l1.ld @@ -0,0 +1,84 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Generic linker script for STM32 targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + _etext = .; + } >rom + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >rom + + . = ORIGIN(ram); + + .data : AT (__exidx_end) { + _data = .; + *(.data*) /* Read-write initialized data */ + . = ALIGN(4); + _edata = .; + } >ram + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram AT >rom + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + . = ALIGN(4); + end = .; +} + +PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); + diff --git a/lib/stm32/l1/stm32l15xx8.ld b/lib/stm32/l1/stm32l15xx8.ld new file mode 100644 index 0000000..1f20f57 --- /dev/null +++ b/lib/stm32/l1/stm32l15xx8.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson . + */ + +/* Linker script for STM32L15xx8, 64K flash, 10K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 10K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32l1.ld + diff --git a/lib/stm32/l1/stm32l15xxB.ld b/lib/stm32/l1/stm32l15xxB.ld new file mode 100644 index 0000000..4c14b71 --- /dev/null +++ b/lib/stm32/l1/stm32l15xxB.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson . + */ + +/* Linker script for STM32L15xxB, 128K flash, 16K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32l1.ld + -- cgit v1.2.3 From 9aed64a19db77ad55f46cc9eea979b48c920d13e Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sun, 22 Jul 2012 19:04:06 +0000 Subject: Finish RCC definitions => Working example! --- .../l1/stm32l-discovery/miniblink/miniblink.c | 4 +- include/libopencm3/stm32/l1/rcc.h | 178 ++++++++------------- 2 files changed, 67 insertions(+), 115 deletions(-) (limited to 'include') diff --git a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c index a9d7c3d..fbace3c 100644 --- a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c +++ b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c @@ -29,7 +29,7 @@ void gpio_setup(void) { /* Enable GPIOB clock. */ /* Manually: */ - RCC_AHBENR |= RCC_AHBENR_IOPBEN; + RCC_AHBENR |= RCC_AHBENR_GPIOBEN; /* Using API functions: */ //rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPBEN); @@ -63,7 +63,7 @@ int main(void) // __asm__("nop"); /* Using API function gpio_toggle(): */ - gpio_toggle(PORT_LED, PORT_LED); /* LED on/off */ + gpio_toggle(PORT_LED, PIN_LED); /* LED on/off */ for (i = 0; i < 1000000; i++) /* Wait a bit. */ __asm__("nop"); } diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index ebcca86..07d3692 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -219,27 +219,19 @@ LGPL License Terms @ref lgpl_license /* --- RCC_APB1RSTR values ------------------------------------------------- */ -TODO : up to here - +#define RCC_APB1RSTR_COMPRST (1 << 31) #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_BKPRST (1 << 27) -#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ -#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ -#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ -#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ +#define RCC_APB1RSTR_USBRST (1 << 23) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_UART5RST (1 << 20) -#define RCC_APB1RSTR_UART4RST (1 << 19) #define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_LCDRST (1 << 9) #define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) @@ -250,17 +242,15 @@ TODO : up to here @ingroup STM32L1xx_rcc_defines @{*/ -#define RCC_AHBENR_ETHMACENRX (1 << 16) -#define RCC_AHBENR_ETHMACENTX (1 << 15) -#define RCC_AHBENR_ETHMACEN (1 << 14) -#define RCC_AHBENR_OTGFSEN (1 << 12) -#define RCC_AHBENR_SDIOEN (1 << 10) -#define RCC_AHBENR_FSMCEN (1 << 8) -#define RCC_AHBENR_CRCEN (1 << 6) -#define RCC_AHBENR_FLITFEN (1 << 4) -#define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMA2EN (1 << 1) -#define RCC_AHBENR_DMA1EN (1 << 0) +#define RCC_AHBENR_DMA1EN (1 << 24) +#define RCC_AHBENR_FLITFEN (1 << 15) +#define RCC_AHBENR_CRCEN (1 << 12) +#define RCC_AHBENR_GPIOHEN (1 << 5) +#define RCC_AHBENR_GPIOEEN (1 << 4) +#define RCC_AHBENR_GPIODEN (1 << 3) +#define RCC_AHBENR_GPIOCEN (1 << 2) +#define RCC_AHBENR_GPIOBEN (1 << 1) +#define RCC_AHBENR_GPIOAEN (1 << 0) /*@}*/ /* --- RCC_APB2ENR values -------------------------------------------------- */ @@ -269,21 +259,13 @@ TODO : up to here @ingroup STM32L1xx_rcc_defines @{*/ -#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ #define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ #define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_ADC2EN (1 << 10) #define RCC_APB2ENR_ADC1EN (1 << 9) -#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ -#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ -#define RCC_APB2ENR_IOPEEN (1 << 6) -#define RCC_APB2ENR_IOPDEN (1 << 5) -#define RCC_APB2ENR_IOPCEN (1 << 4) -#define RCC_APB2ENR_IOPBEN (1 << 3) -#define RCC_APB2ENR_IOPAEN (1 << 2) -#define RCC_APB2ENR_AFIOEN (1 << 0) +#define RCC_APB2ENR_TIM11EN (1 << 4) +#define RCC_APB2ENR_TIM10EN (1 << 3) +#define RCC_APB2ENR_TIM9EN (1 << 2) +#define RCC_APB2ENR_SYSCFGEN (1 << 0) /*@}*/ /* --- RCC_APB1ENR values -------------------------------------------------- */ @@ -292,38 +274,61 @@ TODO : up to here @ingroup STM32L1xx_rcc_defines @{*/ +#define RCC_APB1ENR_COMPEN (1 << 31) #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_BKPEN (1 << 27) -#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ -#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ -#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ -#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ +#define RCC_APB1ENR_USBEN (1 << 23) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_UART5EN (1 << 20) -#define RCC_APB1ENR_UART4EN (1 << 19) #define RCC_APB1ENR_USART3EN (1 << 18) #define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_LCDEN (1 << 9) #define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM5EN (1 << 3) #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /*@}*/ -/* --- RCC_BDCR values ----------------------------------------------------- */ +/* --- RCC_AHBLPENR -------------------------------------------------------- */ +#define RCC_AHBLPENR_DMA1LPEN (1 << 24) +#define RCC_AHBLPENR_SRAMLPEN (1 << 16) +#define RCC_AHBLPENR_FLITFLPEN (1 << 15) +#define RCC_AHBLPENR_CRCLPEN (1 << 12) +#define RCC_AHBLPENR_GPIOHLPEN (1 << 5) +#define RCC_AHBLPENR_GPIOELPEN (1 << 4) +#define RCC_AHBLPENR_GPIODLPEN (1 << 3) +#define RCC_AHBLPENR_GPIOCLPEN (1 << 2) +#define RCC_AHBLPENR_GPIOBLPEN (1 << 1) +#define RCC_AHBLPENR_GPIOALPEN (1 << 0) + +#define RCC_APB2LPENR_USART1LPEN (1 << 14) +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) +#define RCC_APB2LPENR_ADC1LPEN (1 << 9) +#define RCC_APB2LPENR_TIM11LPEN (1 << 4) +#define RCC_APB2LPENR_TIM10LPEN (1 << 3) +#define RCC_APB2LPENR_TIM9LPEN (1 << 2) +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0) + +#define RCC_APB1LPENR_COMPLPEN (1 << 31) +#define RCC_APB1LPENR_DACLPEN (1 << 29) +#define RCC_APB1LPENR_PWRLPEN (1 << 28) +#define RCC_APB1LPENR_USBLPEN (1 << 23) +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) +#define RCC_APB1LPENR_USART3LPEN (1 << 18) +#define RCC_APB1LPENR_USART2LPEN (1 << 17) +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) +#define RCC_APB1LPENR_LCDLPEN (1 << 9) +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ @@ -333,72 +338,17 @@ TODO : up to here #define RCC_CSR_SFTRSTF (1 << 28) #define RCC_CSR_PORRSTF (1 << 27) #define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_OBLRSTF (1 << 25) #define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_RTCRST (1 << 23) +#define RCC_CSR_RTCEN (1 << 22) +/* RTCSEL[1:0] */ +#define RCC_CSR_LSEBYP (1 << 10) +#define RCC_CSR_LSERDY (1 << 9) +#define RCC_CSR_LSEON (1 << 8) #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) -/* --- RCC_AHBRSTR values -------------------------------------------------- */ - -#define RCC_AHBRSTR_ETHMACRST (1 << 14) -#define RCC_AHBRSTR_OTGFSRST (1 << 12) - -/* --- RCC_CFGR2 values ---------------------------------------------------- */ - -/* I2S3SRC: I2S3 clock source */ -#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 - -/* I2S2SRC: I2S2 clock source */ -#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 - -/* PREDIV1SRC: PREDIV1 entry clock source */ -#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 -#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 - -#define RCC_CFGR2_PLL2MUL (1 << 0) -#define RCC_CFGR2_PREDIV2 (1 << 0) -#define RCC_CFGR2_PREDIV1 (1 << 0) - -/* PLL3MUL: PLL3 multiplication factor */ -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf - -/* PLL2MUL: PLL2 multiplication factor */ -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf - -/* PREDIV2: PREDIV2 division factor */ -#define RCC_CFGR2_PREDIV2_NODIV 0x0 -#define RCC_CFGR2_PREDIV2_DIV2 0x1 -#define RCC_CFGR2_PREDIV2_DIV3 0x2 -#define RCC_CFGR2_PREDIV2_DIV4 0x3 -#define RCC_CFGR2_PREDIV2_DIV5 0x4 -#define RCC_CFGR2_PREDIV2_DIV6 0x5 -#define RCC_CFGR2_PREDIV2_DIV7 0x6 -#define RCC_CFGR2_PREDIV2_DIV8 0x7 -#define RCC_CFGR2_PREDIV2_DIV9 0x8 -#define RCC_CFGR2_PREDIV2_DIV10 0x9 -#define RCC_CFGR2_PREDIV2_DIV11 0xa -#define RCC_CFGR2_PREDIV2_DIV12 0xb -#define RCC_CFGR2_PREDIV2_DIV13 0xc -#define RCC_CFGR2_PREDIV2_DIV14 0xd -#define RCC_CFGR2_PREDIV2_DIV15 0xe -#define RCC_CFGR2_PREDIV2_DIV16 0xf /* --- Variable definitions ------------------------------------------------ */ extern u32 rcc_ppre1_frequency; @@ -407,9 +357,10 @@ extern u32 rcc_ppre2_frequency; /* --- Function prototypes ------------------------------------------------- */ typedef enum { - PLL, HSE, HSI, LSE, LSI + PLL, HSE, HSI, MSI, LSE, LSI } osc_t; +#if FINISHED == 0 void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); @@ -449,5 +400,6 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); void rcc_backupdomain_reset(void); +#endif #endif -- cgit v1.2.3 From e4f84278f2b62dee7b4e0ac718c7c6ce998240ba Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sun, 22 Jul 2012 21:58:09 +0000 Subject: Add most of the rcc functions. (Add the forgotten gpio.c file from before) --- .../l1/stm32l-discovery/miniblink/miniblink.c | 4 +- include/libopencm3/stm32/l1/rcc.h | 7 +- lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/gpio.c | 146 +++++++++ lib/stm32/l1/rcc.c | 357 +++++++++++++++++++++ 5 files changed, 511 insertions(+), 5 deletions(-) create mode 100644 lib/stm32/l1/gpio.c create mode 100644 lib/stm32/l1/rcc.c (limited to 'include') diff --git a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c index fbace3c..2f5c70f 100644 --- a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c +++ b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c @@ -29,9 +29,9 @@ void gpio_setup(void) { /* Enable GPIOB clock. */ /* Manually: */ - RCC_AHBENR |= RCC_AHBENR_GPIOBEN; + //RCC_AHBENR |= RCC_AHBENR_GPIOBEN; /* Using API functions: */ - //rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPBEN); + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN); /* Set GPIO6 (in GPIO port B) to 'output push-pull'. */ /* Using API functions: */ diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index 07d3692..209d24f 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -84,6 +84,11 @@ LGPL License Terms @ref lgpl_license #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) +#define RCC_CR_RTCPRE_DIV2 0 +#define RCC_CR_RTCPRE_DIV4 1 +#define RCC_CR_RTCPRE_DIV8 2 +#define RCC_CR_RTCPRE_DIV18 3 + /* --- RCC_ICSCR values ---------------------------------------------------- */ // TODO @@ -360,7 +365,6 @@ typedef enum { PLL, HSE, HSI, MSI, LSE, LSI } osc_t; -#if FINISHED == 0 void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); @@ -400,6 +404,5 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); void rcc_backupdomain_reset(void); -#endif #endif diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index 543c416..9bd942d 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o desig.o crc.o gpio.o +OBJS = vector.o desig.o crc.o gpio.o rcc.o VPATH += ../../usb:../ diff --git a/lib/stm32/l1/gpio.c b/lib/stm32/l1/gpio.c new file mode 100644 index 0000000..2314bd4 --- /dev/null +++ b/lib/stm32/l1/gpio.c @@ -0,0 +1,146 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + * + * This is virtually a carbon copy of the F4 code... + * TODO: make this code shared by f2, f4, l1 + */ + +#include + +void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) +{ + u16 i; + u32 moder, pupd; + + /* + * We want to set the config only for the pins mentioned in gpios, + * but keeping the others, so read out the actual config first. + */ + moder = GPIO_MODER(gpioport); + pupd = GPIO_PUPDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + + moder &= ~GPIO_MODE_MASK(i); + moder |= GPIO_MODE(i, mode); + pupd &= ~GPIO_PUPD_MASK(i); + pupd |= GPIO_PUPD(i, pull_up_down); + } + + /* Set mode and pull up/down control registers. */ + GPIO_MODER(gpioport) = moder; + GPIO_PUPDR(gpioport) = pupd; +} + +void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) +{ + u16 i; + u32 ospeedr; + + if (otype == GPIO_OTYPE_OD) + GPIO_OTYPER(gpioport) |= gpios; + else + GPIO_OTYPER(gpioport) &= ~gpios; + + ospeedr = GPIO_OSPEEDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + ospeedr &= ~GPIO_OSPEED_MASK(i); + ospeedr |= GPIO_OSPEED(i, speed); + } + + GPIO_OSPEEDR(gpioport) = ospeedr; +} + +void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) +{ + u16 i; + u32 afrl, afrh; + + afrl = GPIO_AFRL(gpioport); + afrh = GPIO_AFRH(gpioport); + + for (i = 0; i < 8; i++) { + if (!((1 << i) & gpios)) + continue; + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR(i, alt_func_num); + } + + for (i = 8; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + afrl &= ~GPIO_AFR_MASK(i - 8); + afrh |= GPIO_AFR(i - 8, alt_func_num); + } + + GPIO_AFRL(gpioport) = afrl; + GPIO_AFRH(gpioport) = afrh; +} + +void gpio_set(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios; +} + +void gpio_clear(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios << 16; +} + +u16 gpio_get(u32 gpioport, u16 gpios) +{ + return gpio_port_read(gpioport) & gpios; +} + +void gpio_toggle(u32 gpioport, u16 gpios) +{ + GPIO_ODR(gpioport) ^= gpios; +} + +u16 gpio_port_read(u32 gpioport) +{ + return (u16)GPIO_IDR(gpioport); +} + +void gpio_port_write(u32 gpioport, u16 data) +{ + GPIO_ODR(gpioport) = data; +} + +void gpio_port_config_lock(u32 gpioport, u16 gpios) +{ + u32 reg32; + + /* Special "Lock Key Writing Sequence", see datasheet. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ + + /* Tell the compiler the variable is actually used. It will get optimized out anyways. */ + reg32 = reg32; + + /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ +} diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c new file mode 100644 index 0000000..a023622 --- /dev/null +++ b/lib/stm32/l1/rcc.c @@ -0,0 +1,357 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + * Based on the F4 code... + */ + +#include + +/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ +u32 rcc_ppre1_frequency = 2097000; +u32 rcc_ppre2_frequency = 2097000; + +void rcc_osc_ready_int_clear(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYC; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYC; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYC; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYC; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYC; + break; + case MSI: + RCC_CIR |= RCC_CIR_MSIRDYC; + break; + } +} + +void rcc_osc_ready_int_enable(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYIE; + break; + case MSI: + RCC_CIR |= RCC_CIR_MSIRDYIE; + break; + } +} + +void rcc_osc_ready_int_disable(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR &= ~RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR &= ~RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR &= ~RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR &= ~RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR &= ~RCC_CIR_LSIRDYIE; + break; + case MSI: + RCC_CIR &= ~RCC_CIR_MSIRDYIE; + break; + } +} + +int rcc_osc_ready_int_flag(osc_t osc) +{ + switch (osc) { + case PLL: + return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); + break; + case HSE: + return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); + break; + case HSI: + return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); + break; + case LSE: + return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); + break; + case LSI: + return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); + break; + case MSI: + return ((RCC_CIR & RCC_CIR_MSIRDYF) != 0); + break; + } + + /* Shouldn't be reached. */ + return -1; +} + +void rcc_css_int_clear(void) +{ + RCC_CIR |= RCC_CIR_CSSC; +} + +int rcc_css_int_flag(void) +{ + return ((RCC_CIR & RCC_CIR_CSSF) != 0); +} + +void rcc_wait_for_osc_ready(osc_t osc) +{ + switch (osc) { + case PLL: + while ((RCC_CR & RCC_CR_PLLRDY) == 0); + break; + case HSE: + while ((RCC_CR & RCC_CR_HSERDY) == 0); + break; + case HSI: + while ((RCC_CR & RCC_CR_HSIRDY) == 0); + break; + case MSI: + while ((RCC_CR & RCC_CR_MSIRDY) == 0); + break; + case LSE: + while ((RCC_CSR & RCC_CSR_LSERDY) == 0); + break; + case LSI: + while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); + break; + } +} + +void rcc_wait_for_sysclk_status(osc_t osc) +{ + switch (osc) { + case PLL: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_PLLCLK); + break; + case HSE: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSECLK); + break; + case HSI: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSICLK); + break; + case MSI: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_MSICLK); + break; + default: + /* Shouldn't be reached. */ + break; + } +} + +void rcc_osc_on(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case MSI: + RCC_CR |= RCC_CR_MSION; + break; + case HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case HSI: + RCC_CR |= RCC_CR_HSION; + break; + case LSE: + RCC_CSR |= RCC_CSR_LSEON; + break; + case LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + } +} + +void rcc_osc_off(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case MSI: + RCC_CR &= ~RCC_CR_MSION; + break; + case HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case LSE: + RCC_CSR &= ~RCC_CSR_LSEON; + break; + case LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + } +} + +void rcc_css_enable(void) +{ + RCC_CR |= RCC_CR_CSSON; +} + +void rcc_css_disable(void) +{ + RCC_CR &= ~RCC_CR_CSSON; +} + +void rcc_osc_bypass_enable(osc_t osc) +{ + switch (osc) { + case HSE: + RCC_CR |= RCC_CR_HSEBYP; + break; + case LSE: + RCC_CSR |= RCC_CSR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + case MSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } +} + +void rcc_osc_bypass_disable(osc_t osc) +{ + switch (osc) { + case HSE: + RCC_CR &= ~RCC_CR_HSEBYP; + break; + case LSE: + RCC_CSR &= ~RCC_CSR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + case MSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } +} + +void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) +{ + *reg |= en; +} + +void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en) +{ + *reg &= ~en; +} + +void rcc_peripheral_reset(volatile u32 *reg, u32 reset) +{ + *reg |= reset; +} + +void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset) +{ + *reg &= ~clear_reset; +} + +void rcc_set_sysclk_source(u32 clk) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR = (reg32 | clk); +} + +void rcc_set_pll_source(u32 pllsrc) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(1 << 16); + RCC_CFGR = (reg32 | (pllsrc << 16)); +} + +void rcc_set_ppre2(u32 ppre2) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 13) | (1 << 12) | (1 << 11)); + RCC_CFGR = (reg32 | (ppre2 << 11)); +} + +void rcc_set_ppre1(u32 ppre1) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8)); + RCC_CFGR = (reg32 | (ppre1 << 8)); +} + +void rcc_set_hpre(u32 hpre) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); + RCC_CFGR = (reg32 | (hpre << 4)); +} + +void rcc_set_rtcpre(u32 rtcpre) +{ + u32 reg32; + + reg32 = RCC_CR; + reg32 &= ~((1 << 30) | (1 << 29)); + RCC_CR = (reg32 | (rtcpre << 29)); +} + +u32 rcc_system_clock_source(void) +{ + /* Return the clock source which is used as system clock. */ + return ((RCC_CFGR & 0x000c) >> 2); +} + -- cgit v1.2.3 From 49412864544c3b7c5ab321098c419b61dfc05b3b Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 20 Oct 2012 19:37:46 +0000 Subject: STM32L1 support, rebased onto upstream generalizations branch. Working example again. --- examples/stm32/l1/Makefile.include | 43 ++-- .../stm32/l1/stm32l-discovery/miniblink/Makefile | 2 +- include/libopencm3/stm32/l1/irq.yaml | 49 +++++ lib/stm32/l1/Makefile | 30 +-- lib/stm32/l1/libopencm3_stm32l1.ld | 19 +- lib/stm32/l1/stm32l15xxB.ld | 31 --- lib/stm32/l1/stm32l15xxb.ld | 31 +++ lib/stm32/l1/vector.c | 228 --------------------- 8 files changed, 116 insertions(+), 317 deletions(-) create mode 100644 include/libopencm3/stm32/l1/irq.yaml delete mode 100644 lib/stm32/l1/stm32l15xxB.ld create mode 100644 lib/stm32/l1/stm32l15xxb.ld delete mode 100644 lib/stm32/l1/vector.c (limited to 'include') diff --git a/examples/stm32/l1/Makefile.include b/examples/stm32/l1/Makefile.include index f152b2a..32c3cee 100644 --- a/examples/stm32/l1/Makefile.include +++ b/examples/stm32/l1/Makefile.include @@ -25,27 +25,32 @@ LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump GDB = $(PREFIX)-gdb -# If you are copying this file to use in your own project, -# You will need to change this... (Leave unset to assume installed -# in the toolchain itself) -#OPENCM3_DIR ?= /opt/libopencm3/$(PREFIX) -OPENCM3_DIR ?= ../../../../.. - -ARCH_FLAGS = -mcpu=cortex-m3 -mthumb -msoft-float -CFLAGS += -g -Os -Wall -Wextra \ + +TOOLCHAIN_DIR ?= ../../../../.. +ifeq ($(wildcard ../../../../../lib/libopencm3_stm32l1.a),) +ifneq ($(strip $(shell which $(CC))),) +TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +endif +else +ifeq ($(V),1) +$(info We seem to be building the example in the source directory. Using local library!) +endif +endif + +$(info GAHHHH toolchain: $(TOOLCHAIN_DIR)) + +ARCH_FLAGS = -mthumb -mcpu=cortex-m3 -msoft-float +CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common $(ARCH_FLAGS) -MD -DSTM32L1 LDSCRIPT ?= $(BINARY).ld -LDFLAGS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \ +LDFLAGS += --static -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \ + -L$(TOOLCHAIN_DIR)/lib \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ $(ARCH_FLAGS) -mfix-cortex-m3-ldrd -ifneq ($(OPENCM3_DIR),) -CFLAGS += -I$(OPENCM3_DIR)/include -LDFLAGS += -L$(OPENCM3_DIR)/lib -L$(OPENCM3_DIR)/lib/stm32/l1 -SCRIPT_DIR = $(OPENCM3_DIR)/share -else -SCRIPT_DIR = $(shell dirname $(shell readlink -f $(shell which $(PREFIX)-gcc)))/../$(PREFIX)/share -endif +CFLAGS += -I$(TOOLCHAIN_DIR)/include +LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/l1 +SCRIPT_DIR = $(TOOLCHAIN_DIR)/share OBJS += $(BINARY).o @@ -95,11 +100,7 @@ flash: $(BINARY).flash @#printf " OBJDUMP $(*).list\n" $(Q)$(OBJDUMP) -S $(*).elf > $(*).list -ifeq ($(OPENCM3_DIR),) -%.elf: $(OBJS) $(LDSCRIPT) -else -%.elf: $(OBJS) $(LDSCRIPT) $(OPENCM3_DIR)/lib/stm32/l1/libopencm3_stm32l1.a -endif +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32l1.a @#printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32l1 $(LDFLAGS) diff --git a/examples/stm32/l1/stm32l-discovery/miniblink/Makefile b/examples/stm32/l1/stm32l-discovery/miniblink/Makefile index 8c88be0..b0586e5 100644 --- a/examples/stm32/l1/stm32l-discovery/miniblink/Makefile +++ b/examples/stm32/l1/stm32l-discovery/miniblink/Makefile @@ -19,7 +19,7 @@ BINARY = miniblink -LDSCRIPT = ../stm32l15xxB.ld +LDSCRIPT = ../../../../../lib/stm32/l1/stm32l15xxb.ld include ../../Makefile.include diff --git a/include/libopencm3/stm32/l1/irq.yaml b/include/libopencm3/stm32/l1/irq.yaml new file mode 100644 index 0000000..c2f118f --- /dev/null +++ b/include/libopencm3/stm32/l1/irq.yaml @@ -0,0 +1,49 @@ +includeguard: LIBOPENCM3_STM32_L1_NVIC_H +partname_humanreadable: STM32 L1 series +partname_doxygen: STM32L1 +irqs: + - wwdg + - pvd + - tamper + - rtc + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_channel1 + - dma1_channel2 + - dma1_channel3 + - dma1_channel4 + - dma1_channel5 + - dma1_channel6 + - dma1_channel7 + - adc1 + - usb_hp + - usb_lp + - dac + - comp + - exti9_5 + - lcd + - tim9 + - tim10 + - tim11 + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_wakeup + - tim6 + - tim7 diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index 9bd942d..a009857 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -25,34 +25,12 @@ CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD -DSTM32L1 + -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o desig.o crc.o gpio.o rcc.o +OBJS = rcc.o gpio.o desig.o crc.o -VPATH += ../../usb:../ +VPATH += ../../usb:../:../../cm3 -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/stm32/f1\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) +include ../../Makefile.include diff --git a/lib/stm32/l1/libopencm3_stm32l1.ld b/lib/stm32/l1/libopencm3_stm32l1.ld index a64a1f7..9d165f6 100644 --- a/lib/stm32/l1/libopencm3_stm32l1.ld +++ b/lib/stm32/l1/libopencm3_stm32l1.ld @@ -30,21 +30,18 @@ ENTRY(reset_handler) /* Define sections. */ SECTIONS { - . = ORIGIN(rom); - .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); - _etext = .; } >rom /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - */ + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ .ARM.extab : { *(.ARM.extab*) } >rom @@ -54,21 +51,23 @@ SECTIONS __exidx_end = .; } >rom - . = ORIGIN(ram); + . = ALIGN(4); + _etext = .; - .data : AT (__exidx_end) { + .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; - } >ram + } >ram AT >rom + _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; - } >ram AT >rom + } >ram /* * The .eh_frame section appears to be used for C++ exception handling. diff --git a/lib/stm32/l1/stm32l15xxB.ld b/lib/stm32/l1/stm32l15xxB.ld deleted file mode 100644 index 4c14b71..0000000 --- a/lib/stm32/l1/stm32l15xxB.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Karl Palsson . - */ - -/* Linker script for STM32L15xxB, 128K flash, 16K RAM. */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32l1.ld - diff --git a/lib/stm32/l1/stm32l15xxb.ld b/lib/stm32/l1/stm32l15xxb.ld new file mode 100644 index 0000000..4c14b71 --- /dev/null +++ b/lib/stm32/l1/stm32l15xxb.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson . + */ + +/* Linker script for STM32L15xxB, 128K flash, 16K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32l1.ld + diff --git a/lib/stm32/l1/vector.c b/lib/stm32/l1/vector.c deleted file mode 100644 index d8e0ea5..0000000 --- a/lib/stm32/l1/vector.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s). */ -extern unsigned __exidx_end, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamper_isr(void); -void WEAK rtc_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_channel1_isr(void); -void WEAK dma1_channel2_isr(void); -void WEAK dma1_channel3_isr(void); -void WEAK dma1_channel4_isr(void); -void WEAK dma1_channel5_isr(void); -void WEAK dma1_channel6_isr(void); -void WEAK dma1_channel7_isr(void); -void WEAK adc1_isr(void); -void WEAK usb_hp_isr(void); -void WEAK usb_lp_isr(void); -void WEAK dac_isr(void); -void WEAK comp_isr(void); -void WEAK exti9_5_isr(void); -void WEAK lcd_isr(void); -void WEAK tim9_isr(void); -void WEAK tim10_isr(void); -void WEAK tim11_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_wakeup_isr(void); -void WEAK tim6_isr(void); -void WEAK tim7_isr(void); - - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void*)&_stack, /* Addr: 0x0000_0000 */ - reset_handler, /* Addr: 0x0000_0004 */ - nmi_handler, /* Addr: 0x0000_0008 */ - hard_fault_handler, /* Addr: 0x0000_000C */ - mem_manage_handler, /* Addr: 0x0000_0010 */ - bus_fault_handler, /* Addr: 0x0000_0014 */ - usage_fault_handler, /* Addr: 0x0000_0018 */ - 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ - sv_call_handler, /* Addr: 0x0000_002C */ - debug_monitor_handler, /* Addr: 0x0000_0030*/ - 0, /* Reserved Addr: 0x0000_00034 */ - pend_sv_handler, /* Addr: 0x0000_0038 */ - sys_tick_handler, /* Addr: 0x0000_003C */ - wwdg_isr, /* Addr: 0x0000_0040 */ - pvd_isr, /* Addr: 0x0000_0044 */ - tamper_isr, /* Addr: 0x0000_0048 */ - rtc_isr, /* Addr: 0x0000_004C */ - flash_isr, /* Addr: 0x0000_0050 */ - rcc_isr, /* Addr: 0x0000_0054 */ - exti0_isr, /* Addr: 0x0000_0058 */ - exti1_isr, /* Addr: 0x0000_005C */ - exti2_isr, /* Addr: 0x0000_0060 */ - exti3_isr, /* Addr: 0x0000_0064 */ - exti4_isr, /* Addr: 0x0000_0068 */ - dma1_channel1_isr, /* Addr: 0x0000_006C */ - dma1_channel2_isr, /* Addr: 0x0000_0070 */ - dma1_channel3_isr, /* Addr: 0x0000_0074 */ - dma1_channel4_isr, /* Addr: 0x0000_0078 */ - dma1_channel5_isr, /* Addr: 0x0000_007C */ - dma1_channel6_isr, /* Addr: 0x0000_0080 */ - dma1_channel7_isr, /* Addr: 0x0000_0084 */ - adc1_isr, /* Addr: 0x0000_0088 */ - usb_hp_isr, /* Addr: 0x0000_008C */ - usb_lp_isr, /* Addr: 0x0000_0090 */ - dac_isr, /* Addr: 0x0000_0094 */ - comp_isr, /* Addr: 0x0000_0098 */ - exti9_5_isr, /* Addr: 0x0000_009C */ - lcd_isr, /* Addr: 0x0000_00A0 */ - tim9_isr, /* Addr: 0x0000_00A4 */ - tim10_isr, /* Addr: 0x0000_00A8 */ - tim11_isr, /* Addr: 0x0000_00AC */ - tim2_isr, /* Addr: 0x0000_00B0 */ - tim3_isr, /* Addr: 0x0000_00B4 */ - tim4_isr, /* Addr: 0x0000_00B8 */ - i2c1_ev_isr, /* Addr: 0x0000_00BC */ - i2c1_er_isr, /* Addr: 0x0000_00C0 */ - i2c2_ev_isr, /* Addr: 0x0000_00C4 */ - i2c2_er_isr, /* Addr: 0x0000_00C8 */ - spi1_isr, /* Addr: 0x0000_00CC */ - spi2_isr, /* Addr: 0x0000_00D0 */ - usart1_isr, /* Addr: 0x0000_00D4 */ - usart2_isr, /* Addr: 0x0000_00D8 */ - usart3_isr, /* Addr: 0x0000_00DC */ - exti15_10_isr, /* Addr: 0x0000_00E0 */ - rtc_alarm_isr, /* Addr: 0x0000_00E4 */ - usb_wakeup_isr, /* Addr: 0x0000_00E8 */ - tim6_isr, /* Addr: 0x0000_00EC */ - tim7_isr, /* Addr: 0x0000_00F0 */ -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamper_isr = null_handler -#pragma weak rtc_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_channel1_isr = null_handler -#pragma weak dma1_channel2_isr = null_handler -#pragma weak dma1_channel3_isr = null_handler -#pragma weak dma1_channel4_isr = null_handler -#pragma weak dma1_channel5_isr = null_handler -#pragma weak dma1_channel6_isr = null_handler -#pragma weak dma1_channel7_isr = null_handler -#pragma weak adc1_isr = null_handler -#pragma weak usb_hp_isr = null_handler -#pragma weak usb_lp_isr = null_handler -#pragma weak dac_isr = null_handler -#pragma weak comp_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak lcd_isr = null_handler -#pragma weak tim9_isr = null_handler -#pragma weak tim10_isr = null_handler -#pragma weak tim11_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_wakeup_isr = null_handler -#pragma weak tim6_isr = null_handler -#pragma weak tim7_isr = null_handler -- cgit v1.2.3 From 25acaa58783b4d046acbe961cb62efe0b39ec981 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 22 Oct 2012 21:29:42 +0000 Subject: Add usart support for L1. Only tested with basic tx blocking, ie, the same example code as on F2/F4, but the description of the block is almost identical. --- examples/stm32/l1/stm32l-discovery/usart/Makefile | 25 +++++++ examples/stm32/l1/stm32l-discovery/usart/README | 12 ++++ examples/stm32/l1/stm32l-discovery/usart/usart.c | 80 +++++++++++++++++++++++ include/libopencm3/stm32/l1/gpio.h | 2 +- lib/stm32/l1/Makefile | 2 +- lib/stm32/usart.c | 2 + 6 files changed, 121 insertions(+), 2 deletions(-) create mode 100644 examples/stm32/l1/stm32l-discovery/usart/Makefile create mode 100644 examples/stm32/l1/stm32l-discovery/usart/README create mode 100644 examples/stm32/l1/stm32l-discovery/usart/usart.c (limited to 'include') diff --git a/examples/stm32/l1/stm32l-discovery/usart/Makefile b/examples/stm32/l1/stm32l-discovery/usart/Makefile new file mode 100644 index 0000000..ac088fe --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/usart/Makefile @@ -0,0 +1,25 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = usart + +LDSCRIPT = ../../../../../lib/stm32/l1/stm32l15xxb.ld + +include ../../Makefile.include + diff --git a/examples/stm32/l1/stm32l-discovery/usart/README b/examples/stm32/l1/stm32l-discovery/usart/README new file mode 100644 index 0000000..dcbc5d9 --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/usart/README @@ -0,0 +1,12 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program sends some characters on USART2 on the +ST STM32L DISCOVERY eval board. (USART2 TX on PA2) + +The terminal settings for the receiving device/PC are 38400 8n1. + +The sending is done in a blocking way in the code, see the usart_irq example +for a more elaborate USART example. + diff --git a/examples/stm32/l1/stm32l-discovery/usart/usart.c b/examples/stm32/l1/stm32l-discovery/usart/usart.c new file mode 100644 index 0000000..3335ca8 --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/usart/usart.c @@ -0,0 +1,80 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include + +void clock_setup(void) { + /* We are running on MSI after boot. */ + /* Enable GPIOD clock for LED & USARTs. */ + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOAEN); + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN); + + /* Enable clocks for USART2. */ + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN); +} + +void usart_setup(void) { + /* Setup USART2 parameters. */ + usart_set_baudrate(USART2, 38400); + usart_set_databits(USART2, 8); + usart_set_stopbits(USART2, USART_STOPBITS_1); + usart_set_mode(USART2, USART_MODE_TX); + usart_set_parity(USART2, USART_PARITY_NONE); + usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART2); +} + +void gpio_setup(void) { + /* Setup GPIO pin GPIO7 on GPIO port B for Green LED. */ + gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO7); + + /* Setup GPIO pins for USART2 transmit. */ + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2); + + /* Setup USART2 TX pin as alternate function. */ + gpio_set_af(GPIOA, GPIO_AF7, GPIO2); +} + +int main(void) { + int i, j = 0, c = 0; + + clock_setup(); + gpio_setup(); + usart_setup(); + + /* Blink the LED (PD12) on the board with every transmitted byte. */ + while (1) { + gpio_toggle(GPIOB, GPIO7); /* LED on/off */ + usart_send_blocking(USART2, c + '0'); /* USART2: Send byte. */ + c = (c == 9) ? 0 : c + 1; /* Increment c. */ + if ((j++ % 80) == 0) { /* Newline after line full. */ + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + } + for (i = 0; i < 100000; i++) /* Wait a bit. */ + __asm__("NOP"); + } + + return 0; +} diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h index 76325a9..a39c9f6 100644 --- a/include/libopencm3/stm32/l1/gpio.h +++ b/include/libopencm3/stm32/l1/gpio.h @@ -152,7 +152,7 @@ #define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) #define GPIO_MODE_INPUT 0x00 /* Default */ #define GPIO_MODE_OUTPUT 0x01 -#define GPIO_MODE_ALTFN 0x02 +#define GPIO_MODE_AF 0x02 #define GPIO_MODE_ANALOG 0x03 /* --- GPIOx_OTYPER values -------------------------------------------- */ diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index a009857..f852239 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o desig.o crc.o +OBJS = rcc.o gpio.o desig.o crc.o usart.o VPATH += ../../usb:../:../../cm3 diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c index 5cf861b..1faf486 100644 --- a/lib/stm32/usart.c +++ b/lib/stm32/usart.c @@ -46,6 +46,8 @@ LGPL License Terms @ref lgpl_license # include #elif defined(STM32F4) # include +#elif defined(STM32L1) +# include #else # error "stm32 family not defined." #endif -- cgit v1.2.3 From b860504fed3244f96d9a7ab6d400fb0c133fc3bb Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 22 Oct 2012 22:35:19 +0000 Subject: Add L1 to nvic, now that it's all generated --- include/libopencm3/dispatch/nvic.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index c797d40..08074e3 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -4,6 +4,8 @@ # include #elif defined(STM32F4) # include +#elif defined(STM32L1) +# include #elif defined(EFM32TG) # include -- cgit v1.2.3 From ce8f47e7df8e0bc8abaaec79058cc08bc297f0c9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 22 Oct 2012 23:32:42 +0000 Subject: Enable nvic and exti support for L1 And include an example that uses it. --- .../l1/stm32l-discovery/button-irq-printf/Makefile | 24 +++ .../l1/stm32l-discovery/button-irq-printf/README | 4 + .../l1/stm32l-discovery/button-irq-printf/main.c | 117 ++++++++++++++ .../l1/stm32l-discovery/button-irq-printf/syscfg.h | 45 ++++++ include/libopencm3/stm32/f2/syscfg.h | 46 ------ include/libopencm3/stm32/f4/syscfg.h | 46 ------ include/libopencm3/stm32/syscfg.h | 46 ++++++ lib/dispatch/vector_nvic.c | 2 + lib/stm32/exti2.c | 170 +++++++++++++++++++++ lib/stm32/f2/Makefile | 2 +- lib/stm32/f2/exti.c | 146 ------------------ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/exti.c | 152 ------------------ lib/stm32/l1/Makefile | 4 +- 14 files changed, 412 insertions(+), 394 deletions(-) create mode 100644 examples/stm32/l1/stm32l-discovery/button-irq-printf/Makefile create mode 100644 examples/stm32/l1/stm32l-discovery/button-irq-printf/README create mode 100644 examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c create mode 100644 examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h delete mode 100644 include/libopencm3/stm32/f2/syscfg.h delete mode 100644 include/libopencm3/stm32/f4/syscfg.h create mode 100644 include/libopencm3/stm32/syscfg.h create mode 100644 lib/stm32/exti2.c delete mode 100644 lib/stm32/f2/exti.c delete mode 100644 lib/stm32/f4/exti.c (limited to 'include') diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf/Makefile b/examples/stm32/l1/stm32l-discovery/button-irq-printf/Makefile new file mode 100644 index 0000000..d57ea7a --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = main +LDSCRIPT = ../../../../../lib/stm32/l1/stm32l15xxb.ld + +include ../../Makefile.include + diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf/README b/examples/stm32/l1/stm32l-discovery/button-irq-printf/README new file mode 100644 index 0000000..09e52bc --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf/README @@ -0,0 +1,4 @@ +* Counts how long the user button was held down (in ms) +* Uses one free running counter plus EXTI as an ugly input capture +115200@8n1 console on PA2 (tx only) + diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c b/examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c new file mode 100644 index 0000000..1830c4d --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c @@ -0,0 +1,117 @@ +/* + * Karl Palsson, 2012 +#include +#include +#include +#include +#include +#include +#include + +#include "syscfg.h" + +static struct state_t state; + +void clock_setup(void) { + /* Lots of things on all ports... */ + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOAEN); + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN); + + /* Enable clocks for USART2. */ + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN); +} + +void gpio_setup(void) { + gpio_mode_setup(LED_DISCO_GREEN_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_DISCO_GREEN_PIN); + + /* Setup GPIO pins for USART2 transmit. */ + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2); + + /* Setup USART2 TX pin as alternate function. */ + gpio_set_af(GPIOA, GPIO_AF7, GPIO2); +} + +void usart_setup(void) { + usart_set_baudrate(USART_CONSOLE, 115200); + usart_set_databits(USART_CONSOLE, 8); + usart_set_stopbits(USART_CONSOLE, USART_STOPBITS_1); + usart_set_mode(USART_CONSOLE, USART_MODE_TX); + usart_set_parity(USART_CONSOLE, USART_PARITY_NONE); + usart_set_flow_control(USART_CONSOLE, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART_CONSOLE); +} + +/** + * Use USART_CONSOLE as a console. + * @param file + * @param ptr + * @param len + * @return + */ +int _write(int file, char *ptr, int len) { + int i; + + if (file == STDOUT_FILENO || file == STDERR_FILENO) { + for (i = 0; i < len; i++) { + if (ptr[i] == '\n') { + usart_send_blocking(USART_CONSOLE, '\r'); + } + usart_send_blocking(USART_CONSOLE, ptr[i]); + } + return i; + } + errno = EIO; + return -1; +} + +void BUTTON_DISCO_USER_isr(void) { + exti_reset_request(BUTTON_DISCO_USER_EXTI); + if (state.falling) { + state.falling = false; + exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_RISING); + // ILOG("fell: %d\n", TIM_CNT(TIM7)); + puts("fell!\n"); + } else { + puts("Rose!\n"); + // TIM_CNT(TIM7) = 0; + state.falling = true; + exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_FALLING); + } +} + +void setup_buttons(void) { + /* Enable EXTI0 interrupt. */ + nvic_enable_irq(BUTTON_DISCO_USER_NVIC); + + gpio_mode_setup(BUTTON_DISCO_USER_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, BUTTON_DISCO_USER_PIN); + + /* Configure the EXTI subsystem. */ + exti_select_source(BUTTON_DISCO_USER_EXTI, BUTTON_DISCO_USER_PORT); + state.falling = false; + exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_RISING); + exti_enable_request(BUTTON_DISCO_USER_EXTI); +} + +int main(void) { + int i; + int j = 0; + clock_setup(); + gpio_setup(); + usart_setup(); + puts("hi guys!\n"); + setup_buttons(); + while (1) { + puts("tick:"); + putchar('a' + (j++ % 26)); + gpio_toggle(GPIOB, GPIO7); /* LED on/off */ + for (i = 0; i < 100000; i++) /* Wait a bit. */ + __asm__("NOP"); + } + + return 0; +} diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h b/examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h new file mode 100644 index 0000000..17eb3f1 --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h @@ -0,0 +1,45 @@ +/* + * General configuration of the device + * + * Karl Palsson 2012 + */ + +#ifndef SYSCFG_H +#define SYSCFG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + + +#define USART_CONSOLE USART2 +#define USE_NASTYLOG 1 + +#define LED_DISCO_GREEN_PORT GPIOB +#define LED_DISCO_GREEN_PIN GPIO7 +#define LED_DISCO_BLUE_PORT GPIOB +#define LED_DISCO_BLUE_PIN GPIO6 + +#define BUTTON_DISCO_USER_PORT GPIOA +#define BUTTON_DISCO_USER_PIN GPIO0 +#define BUTTON_DISCO_USER_EXTI EXTI0 +#define BUTTON_DISCO_USER_isr exti0_isr +#define BUTTON_DISCO_USER_NVIC NVIC_EXTI0_IRQ + + + struct state_t { + bool falling; + }; + + +#ifdef __cplusplus +} +#endif + +#endif /* SYSCFG_H */ + diff --git a/include/libopencm3/stm32/f2/syscfg.h b/include/libopencm3/stm32/f2/syscfg.h deleted file mode 100644 index 7426f16..0000000 --- a/include/libopencm3/stm32/f2/syscfg.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -#include - -/* --- SYSCFG registers ------------------------------------------------------ */ - -#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00) - -#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) - -/* External interrupt configuration register 1 (SYSCFG_EXTICR1) */ -#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08) - -/* External interrupt configuration register 2 (SYSCFG_EXTICR2) */ -#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0c) - -/* External interrupt configuration register 3 (SYSCFG_EXTICR3) */ -#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10) - -/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */ -#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14) - -#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) - -#endif - diff --git a/include/libopencm3/stm32/f4/syscfg.h b/include/libopencm3/stm32/f4/syscfg.h deleted file mode 100644 index 7426f16..0000000 --- a/include/libopencm3/stm32/f4/syscfg.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -#include - -/* --- SYSCFG registers ------------------------------------------------------ */ - -#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00) - -#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) - -/* External interrupt configuration register 1 (SYSCFG_EXTICR1) */ -#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08) - -/* External interrupt configuration register 2 (SYSCFG_EXTICR2) */ -#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0c) - -/* External interrupt configuration register 3 (SYSCFG_EXTICR3) */ -#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10) - -/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */ -#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14) - -#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) - -#endif - diff --git a/include/libopencm3/stm32/syscfg.h b/include/libopencm3/stm32/syscfg.h new file mode 100644 index 0000000..7426f16 --- /dev/null +++ b/include/libopencm3/stm32/syscfg.h @@ -0,0 +1,46 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H + +#include + +/* --- SYSCFG registers ------------------------------------------------------ */ + +#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00) + +#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) + +/* External interrupt configuration register 1 (SYSCFG_EXTICR1) */ +#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08) + +/* External interrupt configuration register 2 (SYSCFG_EXTICR2) */ +#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0c) + +/* External interrupt configuration register 3 (SYSCFG_EXTICR3) */ +#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10) + +/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */ +#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14) + +#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) + +#endif + diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index b8e9b7f..33104eb 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -4,6 +4,8 @@ # include "../stm32/f2/vector_nvic.c" #elif defined(STM32F4) # include "../stm32/f4/vector_nvic.c" +#elif defined(STM32L1) +# include "../stm32/l1/vector_nvic.c" #elif defined(EFM32TG) # include "../efm32/efm32tg/vector_nvic.c" diff --git a/lib/stm32/exti2.c b/lib/stm32/exti2.c new file mode 100644 index 0000000..bea2f4d --- /dev/null +++ b/lib/stm32/exti2.c @@ -0,0 +1,170 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + * + * This provides the code for the "next gen" EXTI block provided in F2/F4/L1 + * devices. (differences only in the source selection) + */ + +#include +#include +#if defined(STM32F2) +#include +#elif defined(STM32F4) +#include +#elif defined(STM32L1) +#include +#else +#error "invalid/unknown stm32 family for this code" +#endif + +void exti_set_trigger(u32 extis, exti_trigger_type trig) +{ + switch (trig) { + case EXTI_TRIGGER_RISING: + EXTI_RTSR |= extis; + EXTI_FTSR &= ~extis; + break; + case EXTI_TRIGGER_FALLING: + EXTI_RTSR &= ~extis; + EXTI_FTSR |= extis; + break; + case EXTI_TRIGGER_BOTH: + EXTI_RTSR |= extis; + EXTI_FTSR |= extis; + break; + } +} + +void exti_enable_request(u32 extis) +{ + /* Enable interrupts. */ + EXTI_IMR |= extis; + + /* Enable events. */ + EXTI_EMR |= extis; +} + +void exti_disable_request(u32 extis) +{ + /* Disable interrupts. */ + EXTI_IMR &= ~extis; + + /* Disable events. */ + EXTI_EMR &= ~extis; +} + +/* + * Reset the interrupt request by writing a 1 to the corresponding + * pending bit register. + */ +void exti_reset_request(u32 extis) +{ + EXTI_PR = extis; +} + +/* + * Remap an external interrupt line to the corresponding pin on the + * specified GPIO port. + * + * TODO: This could be rewritten in fewer lines of code. + */ +void exti_select_source(u32 exti, u32 gpioport) +{ + u8 shift, bits; + + shift = bits = 0; + + switch (exti) { + case EXTI0: + case EXTI4: + case EXTI8: + case EXTI12: + shift = 0; + break; + case EXTI1: + case EXTI5: + case EXTI9: + case EXTI13: + shift = 4; + break; + case EXTI2: + case EXTI6: + case EXTI10: + case EXTI14: + shift = 8; + break; + case EXTI3: + case EXTI7: + case EXTI11: + case EXTI15: + shift = 12; + break; + } + + switch (gpioport) { + case GPIOA: + bits = 0xf; + break; + case GPIOB: + bits = 0xe; + break; + case GPIOC: + bits = 0xd; + break; + case GPIOD: + bits = 0xc; + break; + case GPIOE: + bits = 0xb; + break; +#if defined(STM32L1) +#else + case GPIOF: + bits = 0xa; + break; + case GPIOG: + bits = 0x9; + break; +#endif + case GPIOH: + bits = 0x8; + break; +#if defined(STM32L1) +#else + case GPIOI: + bits = 0x7; + break; +#endif + } + + /* Ensure that only valid EXTI lines are used. */ + if (exti < EXTI4) { + SYSCFG_EXTICR1 &= ~(0x000F << shift); + SYSCFG_EXTICR1 |= (~bits << shift); + } else if (exti < EXTI8) { + SYSCFG_EXTICR2 &= ~(0x000F << shift); + SYSCFG_EXTICR2 |= (~bits << shift); + } else if (exti < EXTI12) { + SYSCFG_EXTICR3 &= ~(0x000F << shift); + SYSCFG_EXTICR3 |= (~bits << shift); + } else if (exti < EXTI16) { + SYSCFG_EXTICR4 &= ~(0x000F << shift); + SYSCFG_EXTICR4 |= (~bits << shift); + } +} diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 5cbb977..e3d73fe 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -29,7 +29,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o spi.o flash.o \ - i2c.o exti.o timer.o + i2c.o exti2.o timer.o VPATH += ../../usb:../:../../cm3 diff --git a/lib/stm32/f2/exti.c b/lib/stm32/f2/exti.c deleted file mode 100644 index 5280914..0000000 --- a/lib/stm32/f2/exti.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Mark Butler - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include - -void exti_set_trigger(u32 extis, exti_trigger_type trig) -{ - switch (trig) { - case EXTI_TRIGGER_RISING: - EXTI_RTSR |= extis; - EXTI_FTSR &= ~extis; - break; - case EXTI_TRIGGER_FALLING: - EXTI_RTSR &= ~extis; - EXTI_FTSR |= extis; - break; - case EXTI_TRIGGER_BOTH: - EXTI_RTSR |= extis; - EXTI_FTSR |= extis; - break; - } -} - -void exti_enable_request(u32 extis) -{ - /* Enable interrupts. */ - EXTI_IMR |= extis; - - /* Enable events. */ - EXTI_EMR |= extis; -} - -void exti_disable_request(u32 extis) -{ - /* Disable interrupts. */ - EXTI_IMR &= ~extis; - - /* Disable events. */ - EXTI_EMR &= ~extis; -} - -/* - * Reset the interrupt request by writing a 1 to the corresponding - * pending bit register. - */ -void exti_reset_request(u32 extis) -{ - EXTI_PR = extis; -} - -/* - * Remap an external interrupt line to the corresponding pin on the - * specified GPIO port. - * - * TODO: This could be rewritten in fewer lines of code. - */ -void exti_select_source(u32 exti, u32 gpioport) -{ - u8 shift, bits; - - shift = bits = 0; - - switch (exti) { - case EXTI0: - case EXTI4: - case EXTI8: - case EXTI12: - shift = 0; - break; - case EXTI1: - case EXTI5: - case EXTI9: - case EXTI13: - shift = 4; - break; - case EXTI2: - case EXTI6: - case EXTI10: - case EXTI14: - shift = 8; - break; - case EXTI3: - case EXTI7: - case EXTI11: - case EXTI15: - shift = 12; - break; - } - - switch (gpioport) { - case GPIOA: - bits = 0xf; - break; - case GPIOB: - bits = 0xe; - break; - case GPIOC: - bits = 0xd; - break; - case GPIOD: - bits = 0xc; - break; - case GPIOE: - bits = 0xb; - break; - case GPIOF: - bits = 0xa; - break; - case GPIOG: - bits = 0x9; - break; - } - - /* Ensure that only valid EXTI lines are used. */ - if (exti < EXTI4) { - SYSCFG_EXTICR1 &= ~(0x000F << shift); - SYSCFG_EXTICR1 |= (~bits << shift); - } else if (exti < EXTI8) { - SYSCFG_EXTICR2 &= ~(0x000F << shift); - SYSCFG_EXTICR2 |= (~bits << shift); - } else if (exti < EXTI12) { - SYSCFG_EXTICR3 &= ~(0x000F << shift); - SYSCFG_EXTICR3 |= (~bits << shift); - } else if (exti < EXTI16) { - SYSCFG_EXTICR4 &= ~(0x000F << shift); - SYSCFG_EXTICR4 |= (~bits << shift); - } -} diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 19ea8ef..1e3192b 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o spi.o flash.o \ - i2c.o exti.o pwr.o timer.o \ + i2c.o exti2.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o diff --git a/lib/stm32/f4/exti.c b/lib/stm32/f4/exti.c deleted file mode 100644 index f69e99e..0000000 --- a/lib/stm32/f4/exti.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Mark Butler - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include - -void exti_set_trigger(u32 extis, exti_trigger_type trig) -{ - switch (trig) { - case EXTI_TRIGGER_RISING: - EXTI_RTSR |= extis; - EXTI_FTSR &= ~extis; - break; - case EXTI_TRIGGER_FALLING: - EXTI_RTSR &= ~extis; - EXTI_FTSR |= extis; - break; - case EXTI_TRIGGER_BOTH: - EXTI_RTSR |= extis; - EXTI_FTSR |= extis; - break; - } -} - -void exti_enable_request(u32 extis) -{ - /* Enable interrupts. */ - EXTI_IMR |= extis; - - /* Enable events. */ - EXTI_EMR |= extis; -} - -void exti_disable_request(u32 extis) -{ - /* Disable interrupts. */ - EXTI_IMR &= ~extis; - - /* Disable events. */ - EXTI_EMR &= ~extis; -} - -/* - * Reset the interrupt request by writing a 1 to the corresponding - * pending bit register. - */ -void exti_reset_request(u32 extis) -{ - EXTI_PR = extis; -} - -/* - * Remap an external interrupt line to the corresponding pin on the - * specified GPIO port. - * - * TODO: This could be rewritten in fewer lines of code. - */ -void exti_select_source(u32 exti, u32 gpioport) -{ - u8 shift, bits; - - shift = bits = 0; - - switch (exti) { - case EXTI0: - case EXTI4: - case EXTI8: - case EXTI12: - shift = 0; - break; - case EXTI1: - case EXTI5: - case EXTI9: - case EXTI13: - shift = 4; - break; - case EXTI2: - case EXTI6: - case EXTI10: - case EXTI14: - shift = 8; - break; - case EXTI3: - case EXTI7: - case EXTI11: - case EXTI15: - shift = 12; - break; - } - - switch (gpioport) { - case GPIOA: - bits = 0xf; - break; - case GPIOB: - bits = 0xe; - break; - case GPIOC: - bits = 0xd; - break; - case GPIOD: - bits = 0xc; - break; - case GPIOE: - bits = 0xb; - break; - case GPIOF: - bits = 0xa; - break; - case GPIOG: - bits = 0x9; - break; - case GPIOH: - bits = 0x8; - break; - case GPIOI: - bits = 0x7; - break; - } - - /* Ensure that only valid EXTI lines are used. */ - if (exti < EXTI4) { - SYSCFG_EXTICR1 &= ~(0x000F << shift); - SYSCFG_EXTICR1 |= (~bits << shift); - } else if (exti < EXTI8) { - SYSCFG_EXTICR2 &= ~(0x000F << shift); - SYSCFG_EXTICR2 |= (~bits << shift); - } else if (exti < EXTI12) { - SYSCFG_EXTICR3 &= ~(0x000F << shift); - SYSCFG_EXTICR3 |= (~bits << shift); - } else if (exti < EXTI16) { - SYSCFG_EXTICR4 &= ~(0x000F << shift); - SYSCFG_EXTICR4 |= (~bits << shift); - } -} diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index f852239..71a6505 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -25,10 +25,10 @@ CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD -DSTM32F1 + -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o desig.o crc.o usart.o +OBJS = rcc.o gpio.o desig.o crc.o usart.o exti2.o VPATH += ../../usb:../:../../cm3 -- cgit v1.2.3 From f3557b8d6087d6e041c781419cda694431916fc4 Mon Sep 17 00:00:00 2001 From: Ben Gamari Date: Thu, 8 Nov 2012 12:13:16 -0500 Subject: stm32f4/dma: Fix DMA_ISR_OFFSET definition --- include/libopencm3/stm32/f4/dma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/libopencm3/stm32/f4/dma.h b/include/libopencm3/stm32/f4/dma.h index 1f034fa..c765a79 100644 --- a/include/libopencm3/stm32/f4/dma.h +++ b/include/libopencm3/stm32/f4/dma.h @@ -233,7 +233,7 @@ LGPL License Terms @ref lgpl_license /**@}*/ /* Offset within interrupt status register to start of stream interrupt flag field */ -#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*(stream & 0x02)) +#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) #define DMA_ISR_FLAGS (DMA_ISR_TCIF | DMA_ISR_HTIF | DMA_ISR_TEIF | DMA_ISR_DMEIF | DMA_ISR_FEIF) #define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream) -- cgit v1.2.3 From 020ec859df2c55fcb7c23ebaed821228d9b2c737 Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Thu, 8 Nov 2012 14:29:11 -0800 Subject: Fixed cut and paste typo for CAN banks. --- include/libopencm3/stm32/f1/gpio.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h index a1e74cc..f342504 100644 --- a/include/libopencm3/stm32/f1/gpio.h +++ b/include/libopencm3/stm32/f1/gpio.h @@ -103,18 +103,18 @@ LGPL License Terms @ref lgpl_license /* CAN1 / CAN BANK */ #define GPIO_BANK_CAN1_RX GPIOA /* PA11 */ #define GPIO_BANK_CAN1_TX GPIOA /* PA12 */ -#define GPIO_BANK_CAN_RX GPIO_CAN1_RX /* Alias */ -#define GPIO_BANK_CAN_TX GPIO_CAN1_TX /* Alias */ +#define GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */ +#define GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */ #define GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */ #define GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */ -#define GPIO_BANK_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ -#define GPIO_BANK_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ +#define GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */ +#define GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */ #define GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */ #define GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */ -#define GPIO_BANK_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ -#define GPIO_BANK_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ +#define GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */ +#define GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */ /* CAN2 GPIO */ #define GPIO_CAN2_RX GPIO12 /* PB12 */ -- cgit v1.2.3