From 48eed286b98c6f5389c91be4a82e4e2bef6fc99d Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 22 Jan 2013 21:51:24 +0000 Subject: [l1] fix whitespace and missing license info Earlier additions to the L1 support were not correctly using linux coding guidelines as specified in /HACKING. Some examples were also missing license information. --- include/libopencm3/stm32/l1/flash.h | 54 ++++++++++++++++++------------------- include/libopencm3/stm32/l1/pwr.h | 28 +++++++++---------- 2 files changed, 40 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/include/libopencm3/stm32/l1/flash.h b/include/libopencm3/stm32/l1/flash.h index ed0a696..a2831b4 100644 --- a/include/libopencm3/stm32/l1/flash.h +++ b/include/libopencm3/stm32/l1/flash.h @@ -33,10 +33,10 @@ #define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) #define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) #define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) #define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c) #define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) @@ -46,9 +46,9 @@ /* --- FLASH_ACR values ---------------------------------------------------- */ #define FLASH_RUNPD (1 << 4) -#define FLASH_SLEEPPD (1 << 3) +#define FLASH_SLEEPPD (1 << 3) #define FLASH_ACC64 (1 << 2) -#define FLASH_PRFTEN (1 << 1) +#define FLASH_PRFTEN (1 << 1) #define FLASH_LATENCY_0WS 0x00 #define FLASH_LATENCY_1WS 0x01 @@ -85,30 +85,30 @@ /* --- FLASH_SR values ----------------------------------------------------- */ -#define FLASH_OPTVERRUSR (1 << 12) -#define FLASH_OPTVERR (1 << 11) -#define FLASH_SIZEERR (1 << 10) -#define FLASH_PGAERR (1 << 9) -#define FLASH_WRPERR (1 << 8) -#define FLASH_READY (1 << 3) -#define FLASH_ENDHV (1 << 2) -#define FLASH_EOP (1 << 1) -#define FLASH_BSY (1 << 0) +#define FLASH_OPTVERRUSR (1 << 12) +#define FLASH_OPTVERR (1 << 11) +#define FLASH_SIZEERR (1 << 10) +#define FLASH_PGAERR (1 << 9) +#define FLASH_WRPERR (1 << 8) +#define FLASH_READY (1 << 3) +#define FLASH_ENDHV (1 << 2) +#define FLASH_EOP (1 << 1) +#define FLASH_BSY (1 << 0) /* --- FLASH_OBR values ----------------------------------------------------- */ -#define FLASH_BFB2 (1 << 23) +#define FLASH_BFB2 (1 << 23) #define FLASH_NRST_STDBY (1 << 22) -#define FLASH_NRST_STOP (1 << 21) -#define FLASH_IWDG_SW (1 << 20) -#define FLASH_BOR_OFF (0x0 << 16) -#define FLASH_BOR_LEVEL_1 (0x8 << 16) -#define FLASH_BOR_LEVEL_2 (0x9 << 16) -#define FLASH_BOR_LEVEL_3 (0xa << 16) -#define FLASH_BOR_LEVEL_4 (0xb << 16) -#define FLASH_BOR_LEVEL_5 (0xc << 16) -#define FLASH_RDPRT_LEVEL_0 (0xaa) -#define FLASH_RDPRT_LEVEL_1 (0x00) -#define FLASH_RDPRT_LEVEL_2 (0xcc) +#define FLASH_NRST_STOP (1 << 21) +#define FLASH_IWDG_SW (1 << 20) +#define FLASH_BOR_OFF (0x0 << 16) +#define FLASH_BOR_LEVEL_1 (0x8 << 16) +#define FLASH_BOR_LEVEL_2 (0x9 << 16) +#define FLASH_BOR_LEVEL_3 (0xa << 16) +#define FLASH_BOR_LEVEL_4 (0xb << 16) +#define FLASH_BOR_LEVEL_5 (0xc << 16) +#define FLASH_RDPRT_LEVEL_0 (0xaa) +#define FLASH_RDPRT_LEVEL_1 (0x00) +#define FLASH_RDPRT_LEVEL_2 (0xcc) /* --- Function prototypes ------------------------------------------------- */ diff --git a/include/libopencm3/stm32/l1/pwr.h b/include/libopencm3/stm32/l1/pwr.h index 309b464..41992d7 100644 --- a/include/libopencm3/stm32/l1/pwr.h +++ b/include/libopencm3/stm32/l1/pwr.h @@ -33,49 +33,47 @@ /* Bits [31:15]: Reserved */ /* LPRUN: Low power run mode */ -#define PWR_CR_LPRUN (1 << 14) +#define PWR_CR_LPRUN (1 << 14) /* VOS[12:11]: Regulator voltage scaling output selection */ -#define PWR_CR_VOS_LSB 11 +#define PWR_CR_VOS_LSB 11 /** @defgroup pwr_vos Voltage Scaling Output level selection @ingroup STM32F_pwr_defines @{*/ -#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) -#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) -#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) /**@}*/ -#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) /* FWU: Fast wakeup */ -#define PWR_CR_FWU (1 << 10) +#define PWR_CR_FWU (1 << 10) /* ULP: Ultralow power mode */ -#define PWR_CR_ULP (1 << 9) +#define PWR_CR_ULP (1 << 9) /* --- PWR_CSR values ------------------------------------------------------- */ /* Bits [31:11]: Reserved */ /* EWUP3: Enable WKUP3 pin */ -#define PWR_CSR_EWUP3 (1 << 10) +#define PWR_CSR_EWUP3 (1 << 10) /* EWUP2: Enable WKUP2 pin */ -#define PWR_CSR_EWUP2 (1 << 9) +#define PWR_CSR_EWUP2 (1 << 9) /* EWUP1: Enable WKUP1 pin */ -#define PWR_CSR_EWUP1 PWR_CSR_EWUP +#define PWR_CSR_EWUP1 PWR_CSR_EWUP /* REGLPF : Regulator LP flag */ -#define PWR_CSR_REGLPF (1 << 5) +#define PWR_CSR_REGLPF (1 << 5) /* VOSF: Voltage Scaling select flag */ -#define PWR_CSR_VOSF (1 << 4) +#define PWR_CSR_VOSF (1 << 4) /* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */ #define PWR_CSR_VREFINTRDYF (1 << 3) - - /* --- Function prototypes ------------------------------------------------- */ typedef enum { -- cgit v1.2.3