From 72666a5b936368275423f0735af7939473616d68 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 9 Nov 2012 21:38:06 +0000 Subject: [l1] Add Flash Memory Controller Register defns for L1. Also, some of the most basic essential helper functions. --- include/libopencm3/stm32/l1/flash.h | 125 ++++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 include/libopencm3/stm32/l1/flash.h (limited to 'include') diff --git a/include/libopencm3/stm32/l1/flash.h b/include/libopencm3/stm32/l1/flash.h new file mode 100644 index 0000000..ed0a696 --- /dev/null +++ b/include/libopencm3/stm32/l1/flash.h @@ -0,0 +1,125 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming manual + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include +#include + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c) +#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) +#define FLASH_WRPR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) +#define FLASH_WRPR3 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x84) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_RUNPD (1 << 4) +#define FLASH_SLEEPPD (1 << 3) +#define FLASH_ACC64 (1 << 2) +#define FLASH_PRFTEN (1 << 1) +#define FLASH_LATENCY_0WS 0x00 +#define FLASH_LATENCY_1WS 0x01 + +/* --- FLASH_PECR values. Program/erase control register */ +#define FLASH_OBL_LAUNCH (1 << 18) +#define FLASH_ERRIE (1 << 17) +#define FLASH_EOPIE (1 << 16) +#define FLASH_PARALLBANK (1 << 15) +#define FLASH_FPRG (1 << 10) +#define FLASH_ERASE (1 << 9) +#define FLASH_FTDW (1 << 8) +#define FLASH_FTDW (1 << 8) +#define FLASH_DATA (1 << 4) +#define FLASH_PROG (1 << 3) +#define FLASH_OPTLOCK (1 << 2) +#define FLASH_PRGLOCK (1 << 1) +#define FLASH_PELOCK (1 << 0) + +/* Power down key register (FLASH_PDKEYR) */ +#define FLASH_PDKEY1 ((u32)0x04152637) +#define FLASH_PDKEY2 ((u32)0xFAFBFCFD) + +/* Program/erase key register (FLASH_PEKEYR) */ +#define FLASH_PEKEY1 ((u32)0x89ABCDEF) +#define FLASH_PEKEY2 ((u32)0x02030405) + +/* Program memory key register (FLASH_PRGKEYR) */ +#define FLASH_PRGKEY1 ((u32)0x8C9DAEBF) +#define FLASH_PRGKEY2 ((u32)0x13141516) + +/* Option byte key register (FLASH_OPTKEYR) */ +#define FLASH_OPTKEY1 ((u32)0xFBEAD9C8) +#define FLASH_OPTKEY2 ((u32)0x24252627) + + +/* --- FLASH_SR values ----------------------------------------------------- */ +#define FLASH_OPTVERRUSR (1 << 12) +#define FLASH_OPTVERR (1 << 11) +#define FLASH_SIZEERR (1 << 10) +#define FLASH_PGAERR (1 << 9) +#define FLASH_WRPERR (1 << 8) +#define FLASH_READY (1 << 3) +#define FLASH_ENDHV (1 << 2) +#define FLASH_EOP (1 << 1) +#define FLASH_BSY (1 << 0) + +/* --- FLASH_OBR values ----------------------------------------------------- */ +#define FLASH_BFB2 (1 << 23) +#define FLASH_NRST_STDBY (1 << 22) +#define FLASH_NRST_STOP (1 << 21) +#define FLASH_IWDG_SW (1 << 20) +#define FLASH_BOR_OFF (0x0 << 16) +#define FLASH_BOR_LEVEL_1 (0x8 << 16) +#define FLASH_BOR_LEVEL_2 (0x9 << 16) +#define FLASH_BOR_LEVEL_3 (0xa << 16) +#define FLASH_BOR_LEVEL_4 (0xb << 16) +#define FLASH_BOR_LEVEL_5 (0xc << 16) +#define FLASH_RDPRT_LEVEL_0 (0xaa) +#define FLASH_RDPRT_LEVEL_1 (0x00) +#define FLASH_RDPRT_LEVEL_2 (0xcc) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_64bit_enable(void); +void flash_64bit_disable(void); +void flash_prefetch_enable(void); +void flash_prefetch_disable(void); +void flash_set_ws(u32 ws); + +END_DECLS + +#endif -- cgit v1.2.3 From 259d4e5171e2fd9b612809f752f28b071526ca19 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 10 Nov 2012 20:50:25 +0000 Subject: [l1] Add missing TIM5 bit from newer ref manual --- include/libopencm3/stm32/l1/rcc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index d888d7c..6c7dc95 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -231,6 +231,7 @@ LGPL License Terms @ref lgpl_license #define RCC_APB1RSTR_LCDRST (1 << 9) #define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) -- cgit v1.2.3 From 40f3ac58fb00ef4899638b6a42c4d7d1eaa643ce Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 14 Nov 2012 00:09:17 +0000 Subject: [l1] Add PWR register definitions Just the include file. --- include/libopencm3/stm32/l1/pwr.h | 93 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 include/libopencm3/stm32/l1/pwr.h (limited to 'include') diff --git a/include/libopencm3/stm32/l1/pwr.h b/include/libopencm3/stm32/l1/pwr.h new file mode 100644 index 0000000..309b464 --- /dev/null +++ b/include/libopencm3/stm32/l1/pwr.h @@ -0,0 +1,93 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Stephen Caudle + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_L1_H +#define LIBOPENCM3_PWR_L1_H + +#include + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32L1 series of devices. + */ + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:15]: Reserved */ + +/* LPRUN: Low power run mode */ +#define PWR_CR_LPRUN (1 << 14) + +/* VOS[12:11]: Regulator voltage scaling output selection */ +#define PWR_CR_VOS_LSB 11 +/** @defgroup pwr_vos Voltage Scaling Output level selection +@ingroup STM32F_pwr_defines + +@{*/ +#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) +/**@}*/ +#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) + +/* FWU: Fast wakeup */ +#define PWR_CR_FWU (1 << 10) + +/* ULP: Ultralow power mode */ +#define PWR_CR_ULP (1 << 9) + +/* --- PWR_CSR values ------------------------------------------------------- */ + +/* Bits [31:11]: Reserved */ +/* EWUP3: Enable WKUP3 pin */ +#define PWR_CSR_EWUP3 (1 << 10) + +/* EWUP2: Enable WKUP2 pin */ +#define PWR_CSR_EWUP2 (1 << 9) + +/* EWUP1: Enable WKUP1 pin */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP + +/* REGLPF : Regulator LP flag */ +#define PWR_CSR_REGLPF (1 << 5) + +/* VOSF: Voltage Scaling select flag */ +#define PWR_CSR_VOSF (1 << 4) + +/* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_VREFINTRDYF (1 << 3) + + + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + RANGE1, + RANGE2, + RANGE3, +} vos_scale_t; + +BEGIN_DECLS + +void pwr_set_vos_scale(vos_scale_t scale); + +END_DECLS + +#endif -- cgit v1.2.3 From df1808e2dca719a18067e8f4d9ef7b74fd7e84da Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 14 Nov 2012 00:10:03 +0000 Subject: [l1] Add rcc clock setup helper routines Despite the L1 being a low power device, my initial focus is on making it basically compatible with existing devices. To that end, provide clock setup helper routines that configure it for maximum performance, allowing some similar clock speeds to F1 devices to help with testing. This requires adding the power chipset routines to set the voltage range. Clock setup style is similar to the F4 code, which seems nicer than the overflow of different routines used on the F1 code. NOTE: Both the F4 existing pwr code, and this code don't actually include the f1 core power code, even though it should be compatible --- include/libopencm3/stm32/l1/rcc.h | 43 ++++++++++---- lib/stm32/l1/Makefile | 6 +- lib/stm32/l1/pwr_chipset.c | 37 ++++++++++++ lib/stm32/l1/rcc.c | 121 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 192 insertions(+), 15 deletions(-) create mode 100644 lib/stm32/l1/pwr_chipset.c (limited to 'include') diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index 6c7dc95..21b073b 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -46,6 +46,7 @@ LGPL License Terms @ref lgpl_license #include #include +#include /* --- RCC registers ------------------------------------------------------- */ @@ -110,6 +111,8 @@ LGPL License Terms @ref lgpl_license #define RCC_CFGR_PLLDIV_DIV2 0x1 #define RCC_CFGR_PLLDIV_DIV3 0x2 #define RCC_CFGR_PLLDIV_DIV4 0x3 +#define RCC_CFGR_PLLDIV_SHIFT 22 +#define RCC_CFGR_PLLDIV_MASK 0x3 /* PLLMUL: PLL multiplication factor */ #define RCC_CFGR_PLLMUL_MUL3 0x0 @@ -121,6 +124,8 @@ LGPL License Terms @ref lgpl_license #define RCC_CFGR_PLLMUL_MUL24 0x6 #define RCC_CFGR_PLLMUL_MUL32 0x7 #define RCC_CFGR_PLLMUL_MUL48 0x8 +#define RCC_CFGR_PLLMUL_SHIFT 18 +#define RCC_CFGR_PLLMUL_MASK 0xf /* PLLSRC: PLL entry clock source */ #define RCC_CFGR_PLLSRC_HSI_CLK 0x0 @@ -349,6 +354,28 @@ LGPL License Terms @ref lgpl_license #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) +typedef struct { + uint8_t pll_mul; + uint16_t pll_div; + uint8_t pll_source; + uint32_t flash_config; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + vos_scale_t voltage_scale; + uint32_t apb1_frequency; + uint32_t apb2_frequency; +} clock_scale_t; + +typedef enum { + CLOCK_VRANGE1_HSI_PLL_24MHZ, + CLOCK_VRANGE1_HSI_PLL_32MHZ, + CLOCK_VRANGE1_HSI_RAW_16MHZ, + CLOCK_VRANGE1_END +} clock_volt_range1_t; + +extern const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END]; + /* --- Variable definitions ------------------------------------------------ */ extern u32 rcc_ppre1_frequency; @@ -378,26 +405,16 @@ void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en); void rcc_peripheral_reset(volatile u32 *reg, u32 reset); void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset); void rcc_set_sysclk_source(u32 clk); -void rcc_set_pll_multiplication_factor(u32 mul); +void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor); void rcc_set_pll_source(u32 pllsrc); -void rcc_set_pllxtpre(u32 pllxtpre); void rcc_set_adcpre(u32 adcpre); void rcc_set_ppre2(u32 ppre2); void rcc_set_ppre1(u32 ppre1); void rcc_set_hpre(u32 hpre); void rcc_set_usbpre(u32 usbpre); u32 rcc_get_system_clock_source(int i); -void rcc_clock_setup_in_hsi_out_64mhz(void); -void rcc_clock_setup_in_hsi_out_48mhz(void); - -/** - * Maximum speed possible for F100 (Value Line) on HSI - */ -void rcc_clock_setup_in_hsi_out_24mhz(void); -void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); -void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); +void rcc_clock_setup_hsi(const clock_scale_t *clock); +void rcc_clock_setup_pll(const clock_scale_t *clock); void rcc_backupdomain_reset(void); /**@}*/ diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index dc587c2..cecc95c 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,8 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o desig.o crc.o usart.o exti2.o \ - flash.o gpio_common_all.o gpio_common_f24.o +OBJS = rcc.o gpio.o desig.o crc.o usart.o exti2.o +OBJS += flash.o gpio_common_all.o gpio_common_f24.o +OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o +#OBJS += timer.o # WORK IN PROGRESS VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/pwr_chipset.c b/lib/stm32/l1/pwr_chipset.c new file mode 100644 index 0000000..9f4f599 --- /dev/null +++ b/lib/stm32/l1/pwr_chipset.c @@ -0,0 +1,37 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void pwr_set_vos_scale(vos_scale_t scale) +{ + PWR_CR &= ~(PWR_CR_VOS_MASK); + switch (scale) { + case RANGE1: + PWR_CR |= PWR_CR_VOS_RANGE1; + break; + case RANGE2: + PWR_CR |= PWR_CR_VOS_RANGE2; + break; + case RANGE3: + PWR_CR |= PWR_CR_VOS_RANGE3; + break; + } +} + diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c index a023622..bbba9a9 100644 --- a/lib/stm32/l1/rcc.c +++ b/lib/stm32/l1/rcc.c @@ -22,11 +22,50 @@ */ #include +#include +#include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ u32 rcc_ppre1_frequency = 2097000; u32 rcc_ppre2_frequency = 2097000; +const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] = +{ + { /* 24MHz PLL from HSI */ + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .pll_mul = RCC_CFGR_PLLMUL_MUL3, + .pll_div = RCC_CFGR_PLLDIV_DIV2, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .voltage_scale = RANGE1, + .flash_config = FLASH_LATENCY_1WS, + .apb1_frequency = 24000000, + .apb2_frequency = 24000000, + }, + { /* 32MHz PLL from HSI */ + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .pll_mul = RCC_CFGR_PLLMUL_MUL6, + .pll_div = RCC_CFGR_PLLDIV_DIV3, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .voltage_scale = RANGE1, + .flash_config = FLASH_LATENCY_1WS, + .apb1_frequency = 32000000, + .apb2_frequency = 32000000, + }, + { /* 16MHz HSI raw */ + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .voltage_scale = RANGE1, + .flash_config = FLASH_LATENCY_0WS, + .apb1_frequency = 16000000, + .apb2_frequency = 16000000, + }, +}; + void rcc_osc_ready_int_clear(osc_t osc) { switch (osc) { @@ -304,6 +343,20 @@ void rcc_set_sysclk_source(u32 clk) RCC_CFGR = (reg32 | clk); } +void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT); + reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT); + reg32 &= ~(1 << 16); + reg32 |= (source << 16); + reg32 |= (multiplier << RCC_CFGR_PLLMUL_SHIFT); + reg32 |= (divisor << RCC_CFGR_PLLDIV_SHIFT); + RCC_CFGR = reg32; +} + void rcc_set_pll_source(u32 pllsrc) { u32 reg32; @@ -355,3 +408,71 @@ u32 rcc_system_clock_source(void) return ((RCC_CFGR & 0x000c) >> 2); } +void rcc_clock_setup_hsi(const clock_scale_t *clock) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(clock->hpre); + rcc_set_ppre1(clock->ppre1); + rcc_set_ppre2(clock->ppre2); + + pwr_set_vos_scale(clock->voltage_scale); + + // I guess this should be in the settings? + flash_64bit_enable(); + flash_prefetch_enable(); + /* Configure flash settings. */ + flash_set_ws(clock->flash_config); + + /* Set the peripheral clock frequencies used. */ + rcc_ppre1_frequency = clock->apb1_frequency; + rcc_ppre2_frequency = clock->apb2_frequency; +} + +void rcc_clock_setup_pll(const clock_scale_t *clock) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(clock->hpre); + rcc_set_ppre1(clock->ppre1); + rcc_set_ppre2(clock->ppre2); + + pwr_set_vos_scale(clock->voltage_scale); + + // I guess this should be in the settings? + flash_64bit_enable(); + flash_prefetch_enable(); + /* Configure flash settings. */ + flash_set_ws(clock->flash_config); + + rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, clock->pll_div); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used. */ + rcc_ppre1_frequency = clock->apb1_frequency; + rcc_ppre2_frequency = clock->apb2_frequency; +} -- cgit v1.2.3