From dd5553f122eb388186f3822c113e652119951bc4 Mon Sep 17 00:00:00 2001 From: Thomas Otto Date: Tue, 11 May 2010 13:46:10 +0200 Subject: Changed rcc.h defs to rcc_registername_ prefix. --- include/libopenstm32/rcc.h | 501 ++++++++++++++++++++++----------------------- 1 file changed, 250 insertions(+), 251 deletions(-) (limited to 'include/libopenstm32') diff --git a/include/libopenstm32/rcc.h b/include/libopenstm32/rcc.h index 950f29a..00ec0ef 100644 --- a/include/libopenstm32/rcc.h +++ b/include/libopenstm32/rcc.h @@ -29,342 +29,341 @@ /* --- RCC registers ------------------------------------------------------- */ -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_CFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CIR MMIO32(RCC_BASE + 0x08) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) -#define RCC_BDCR MMIO32(RCC_BASE + 0x20) -#define RCC_CSR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */ -#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */ +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CIR MMIO32(RCC_BASE + 0x08) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) +#define RCC_BDCR MMIO32(RCC_BASE + 0x20) +#define RCC_CSR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */ +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */ /* --- RCC_CR values ------------------------------------------------------- */ -#define PLL3RDY (1 << 29) /* (**) */ -#define PLL3ON (1 << 28) /* (**) */ -#define PLL2RDY (1 << 27) /* (**) */ -#define PLL2ON (1 << 26) /* (**) */ -#define PLLRDY (1 << 25) -#define PLLON (1 << 24) -#define CSSON (1 << 19) -#define HSEBYP (1 << 18) -#define HSERDY (1 << 17) -#define HSEON (1 << 16) +#define RCC_CR_PLL3RDY (1 << 29) /* (**) */ +#define RCC_CR_PLL3ON (1 << 28) /* (**) */ +#define RCC_CR_PLL2RDY (1 << 27) /* (**) */ +#define RCC_CR_PLL2ON (1 << 26) /* (**) */ +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) /* HSICAL: [15:8] */ /* HSITRIM: [7:3] */ -#define HSIRDY (1 << 1) -#define HSION (1 << 0) +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) /* --- RCC_CFGR values ----------------------------------------------------- */ /* MCO: Microcontroller clock output */ -#define MCO_NOCLK 0x0 -#define MCO_SYSCLK 0x4 -#define MCO_HSICLK 0x5 -#define MCO_HSECLK 0x6 -#define MCO_PLLCLK_DIV2 0x7 -#define MCO_PLL2CLK 0x8 /* (**) */ -#define MCO_PLL3CLK_DIV2 0x9 /* (**) */ -#define MCO_XT1 0xa /* (**) */ -#define MCO_PLL3 0xb /* (**) */ +#define RCC_CFGR_MCO_NOCLK 0x0 +#define RCC_CFGR_MCO_SYSCLK 0x4 +#define RCC_CFGR_MCO_HSICLK 0x5 +#define RCC_CFGR_MCO_HSECLK 0x6 +#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7 +#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */ +#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */ +#define RCC_CFGR_MCO_XT1 0xa /* (**) */ +#define RCC_CFGR_MCO_PLL3 0xb /* (**) */ /* USBPRE: USB prescaler (RCC_CFGR[22]) */ -#define USBPRE_PLL_CLK_DIV1_5 0x0 -#define USBPRE_PLL_CLK_NODIV 0x1 +#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 +#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 /* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */ -#define USBPRE_PLL_VCO_CLK_DIV3 0x0 -#define USBPRE_PLL_VCO_CLK_DIV2 0x1 +#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 +#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 /* PLLMUL: PLL multiplication factor */ -#define PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ -#define PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ -#define PLLMUL_PLL_CLK_MUL4 0x2 -#define PLLMUL_PLL_CLK_MUL5 0x3 -#define PLLMUL_PLL_CLK_MUL6 0x4 -#define PLLMUL_PLL_CLK_MUL7 0x5 -#define PLLMUL_PLL_CLK_MUL8 0x6 -#define PLLMUL_PLL_CLK_MUL9 0x7 -#define PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ -#define PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ -#define PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ -#define PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ -#define PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ -#define PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ -#define PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */ -#define PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ // #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */ /* TODO: conn. line differs. */ /* PLLXTPRE: HSE divider for PLL entry */ -#define PLLXTPRE_HSE_CLK 0x0 -#define PLLXTPRE_HSE_CLK_DIV2 0x1 +#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 +#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 /* PLLSRC: PLL entry clock source */ -#define PLLSRC_HSI_CLK_DIV2 0x0 -#define PLLSRC_HSE_CLK 0x1 -#define PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ +#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 +#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 +#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ /* ADCPRE: ADC prescaler */ -/* TODO: Datasheet says "PLCK2". Typo? Should be "PCLK2"? */ -#define ADCPRE_PLCK2_DIV2 0x0 -#define ADCPRE_PLCK2_DIV4 0x1 -#define ADCPRE_PLCK2_DIV6 0x2 -#define ADCPRE_PLCK2_DIV8 0x3 +#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 +#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 +#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 +#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 /* PPRE2: APB high-speed prescaler (APB2) */ -#define PPRE2_HCLK_NODIV 0x0 -#define PPRE2_HCLK_DIV2 0x4 -#define PPRE2_HCLK_DIV4 0x5 -#define PPRE2_HCLK_DIV8 0x6 -#define PPRE2_HCLK_DIV16 0x7 +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 /* PPRE1: APB low-speed prescaler (APB1) */ -#define PPRE1_HCLK_NODIV 0x0 -#define PPRE1_HCLK_DIV2 0x4 -#define PPRE1_HCLK_DIV4 0x5 -#define PPRE1_HCLK_DIV8 0x6 -#define PPRE1_HCLK_DIV16 0x7 +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 /* HPRE: AHB prescaler */ -#define HPRE_SYSCLK_NODIV 0x0 -#define HPRE_SYSCLK_DIV2 0x8 -#define HPRE_SYSCLK_DIV4 0x9 -#define HPRE_SYSCLK_DIV8 0xa -#define HPRE_SYSCLK_DIV16 0xb -#define HPRE_SYSCLK_DIV64 0xc -#define HPRE_SYSCLK_DIV128 0xd -#define HPRE_SYSCLK_DIV256 0xe -#define HPRE_SYSCLK_DIV512 0xf +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf /* SWS: System clock switch status */ -#define SWS_SYSCLKSEL_HSICLK 0x0 -#define SWS_SYSCLKSEL_HSECLK 0x1 -#define SWS_SYSCLKSEL_PLLCLK 0x2 +#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 /* SW: System clock switch */ -#define SW_SYSCLKSEL_HSICLK 0x0 -#define SW_SYSCLKSEL_HSECLK 0x1 -#define SW_SYSCLKSEL_PLLCLK 0x2 +#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ -#define CSSC (1 << 23) +#define RCC_CIR_CSSC (1 << 23) /* OSC ready interrupt clear bits */ -#define PLL3RDYC (1 << 22) /* (**) */ -#define PLL2RDYC (1 << 21) /* (**) */ -#define PLLRDYC (1 << 20) -#define HSERDYC (1 << 19) -#define HSIRDYC (1 << 18) -#define LSERDYC (1 << 17) -#define LSIRDYC (1 << 16) +#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ +#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) /* OSC ready interrupt enable bits */ -#define PLL3RDYIE (1 << 14) /* (**) */ -#define PLL2RDYIE (1 << 13) /* (**) */ -#define PLLRDYIE (1 << 12) -#define HSERDYIE (1 << 11) -#define HSIRDYIE (1 << 10) -#define LSERDYIE (1 << 9) -#define LSIRDYIE (1 << 8) +#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ +#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) /* Clock security system interrupt flag bit */ -#define CSSF (1 << 7) +#define RCC_CIR_CSSF (1 << 7) /* OSC ready interrupt flag bits */ -#define PLL3RDYF (1 << 6) /* (**) */ -#define PLL2RDYF (1 << 5) /* (**) */ -#define PLLRDYF (1 << 4) -#define HSERDYF (1 << 3) -#define HSIRDYF (1 << 2) -#define LSERDYF (1 << 1) -#define LSIRDYF (1 << 0) +#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ +#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) /* --- RCC_APB2RSTR values ------------------------------------------------- */ -#define ADC3RST (1 << 15) /* (XX) */ -#define USART1RST (1 << 14) -#define TIM8RST (1 << 13) /* (XX) */ -#define SPI1RST (1 << 12) -#define TIM1RST (1 << 11) -#define ADC2RST (1 << 10) -#define ADC1RST (1 << 9) -#define IOPGRST (1 << 8) /* (XX) */ -#define IOPFRST (1 << 7) /* (XX) */ -#define IOPERST (1 << 6) -#define IOPDRST (1 << 5) -#define IOPCRST (1 << 4) -#define IOPBRST (1 << 3) -#define IOPARST (1 << 2) -#define AFIORST (1 << 0) +#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_TIM1RST (1 << 11) +#define RCC_APB2RSTR_ADC2RST (1 << 10) +#define RCC_APB2RSTR_ADC1RST (1 << 9) +#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ +#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ +#define RCC_APB2RSTR_IOPERST (1 << 6) +#define RCC_APB2RSTR_IOPDRST (1 << 5) +#define RCC_APB2RSTR_IOPCRST (1 << 4) +#define RCC_APB2RSTR_IOPBRST (1 << 3) +#define RCC_APB2RSTR_IOPARST (1 << 2) +#define RCC_APB2RSTR_AFIORST (1 << 0) /* --- RCC_APB1RSTR values ------------------------------------------------- */ -#define DACRST (1 << 29) -#define PWRRST (1 << 28) -#define BKPRST (1 << 27) -#define CAN2RST (1 << 26) /* (**) */ -#define CAN1RST (1 << 25) /* (**) */ -#define CANRST (1 << 25) /* (XX) Alias for CAN1RST */ -#define USBRST (1 << 23) /* (XX) */ -#define I2C2RST (1 << 22) -#define I2C1RST (1 << 21) -#define USART5RST (1 << 20) -#define USART4RST (1 << 19) -#define USART3RST (1 << 18) -#define USART2RST (1 << 17) -#define SPI3RST (1 << 15) -#define SPI2RST (1 << 14) -#define WWDGRST (1 << 11) -#define TIM7RST (1 << 5) -#define TIM6RST (1 << 4) -#define TIM5RST (1 << 3) -#define TIM4RST (1 << 2) -#define TIM3RST (1 << 1) -#define TIM2RST (1 << 0) +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_BKPRST (1 << 27) +#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ +#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ +#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART5RST (1 << 20) +#define RCC_APB1RSTR_USART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) /* --- RCC_AHBENR values --------------------------------------------------- */ -#define SDIOEN (1 << 10) -#define FSMCEN (1 << 8) -#define CRCEN (1 << 6) -#define FLITFEN (1 << 4) -#define SRAMEN (1 << 2) -#define DMA2EN (1 << 1) -#define DMA1EN (1 << 0) +#define RCC_AHBENR_SDIOEN (1 << 10) +#define RCC_AHBENR_FSMCEN (1 << 8) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLITFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMA2EN (1 << 1) +#define RCC_AHBENR_DMA1EN (1 << 0) /* --- RCC_APB2ENR values -------------------------------------------------- */ -#define ADC3EN (1 << 15) /* (XX) */ -#define USART1EN (1 << 14) -#define TIM8EN (1 << 13) /* (XX) */ -#define SPI1EN (1 << 12) -#define TIM1EN (1 << 11) -#define ADC2EN (1 << 10) -#define ADC1EN (1 << 9) -#define IOPGEN (1 << 8) /* (XX) */ -#define IOPFEN (1 << 7) /* (XX) */ -#define IOPEEN (1 << 6) -#define IOPDEN (1 << 5) -#define IOPCEN (1 << 4) -#define IOPBEN (1 << 3) -#define IOPAEN (1 << 2) -#define AFIOEN (1 << 0) +#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_ADC2EN (1 << 10) +#define RCC_APB2ENR_ADC1EN (1 << 9) +#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ +#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ +#define RCC_APB2ENR_IOPEEN (1 << 6) +#define RCC_APB2ENR_IOPDEN (1 << 5) +#define RCC_APB2ENR_IOPCEN (1 << 4) +#define RCC_APB2ENR_IOPBEN (1 << 3) +#define RCC_APB2ENR_IOPAEN (1 << 2) +#define RCC_APB2ENR_AFIOEN (1 << 0) /* --- RCC_APB1ENR values -------------------------------------------------- */ -#define DACEN (1 << 29) -#define PWREN (1 << 28) -#define BKPEN (1 << 27) -#define CAN2EN (1 << 26) /* (**) */ -#define CAN1EN (1 << 25) /* (**) */ -#define CANEN (1 << 25) /* (XX) Alias for CAN1EN */ -#define USBEN (1 << 23) /* (XX) */ -#define I2C2EN (1 << 22) -#define I2C1EN (1 << 21) -#define USART5EN (1 << 20) -#define USART4EN (1 << 19) -#define USART3EN (1 << 18) -#define USART2EN (1 << 17) -#define SPI3EN (1 << 15) -#define SPI2EN (1 << 14) -#define WWDGEN (1 << 11) -#define TIM7EN (1 << 5) -#define TIM6EN (1 << 4) -#define TIM5EN (1 << 3) -#define TIM4EN (1 << 2) -#define TIM3EN (1 << 1) -#define TIM2EN (1 << 0) +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_BKPEN (1 << 27) +#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ +#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ +#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART5EN (1 << 20) +#define RCC_APB1ENR_USART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) /* --- RCC_BDCR values ----------------------------------------------------- */ -#define BDRST (1 << 16) -#define RTCEN (1 << 15) +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) /* RCC_BDCR[9:8]: RTCSEL */ -#define LSEBYP (1 << 2) -#define LSERDY (1 << 1) -#define LSEON (1 << 0) +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ -#define LPWRRSTF (1 << 31) -#define WWDGRSTF (1 << 30) -#define IWDGRSTF (1 << 29) -#define SFTRSTF (1 << 28) -#define PORRSTF (1 << 27) -#define PINRSTF (1 << 26) -#define RMVF (1 << 24) -#define LSIRDY (1 << 1) -#define LSION (1 << 0) +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) /* --- RCC_AHBRSTR values -------------------------------------------------- */ -#define ETHMACRST (1 << 14) -#define OTGFSRST (1 << 12) +#define RCC_AHBRSTR_ETHMACRST (1 << 14) +#define RCC_AHBRSTR_OTGFSRST (1 << 12) /* --- RCC_CFGR2 values ---------------------------------------------------- */ /* I2S3SRC: I2S3 clock source */ -#define I2S3SRC_SYSCLK 0x0 -#define I2S3SRC_PLL3_VCO_CLK 0x1 +#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 /* I2S2SRC: I2S2 clock source */ -#define I2S2SRC_SYSCLK 0x0 -#define I2S2SRC_PLL3_VCO_CLK 0x1 +#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 /* PREDIV1SRC: PREDIV1 entry clock source */ -#define PREDIV1SRC_HSE_CLK 0x0 -#define PREDIV1SRC_PLL2_CLK 0x1 +#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 +#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 -#define PLL2MUL (1 << 0) -#define PREDIV2 (1 << 0) -#define PREDIV1 (1 << 0) +#define RCC_CFGR2_PLL2MUL (1 << 0) +#define RCC_CFGR2_PREDIV2 (1 << 0) +#define RCC_CFGR2_PREDIV1 (1 << 0) /* PLL3MUL: PLL3 multiplication factor */ -#define PLL3MUL_PLL3_CLK_MUL8 0x6 -#define PLL3MUL_PLL3_CLK_MUL9 0x7 -#define PLL3MUL_PLL3_CLK_MUL10 0x8 -#define PLL3MUL_PLL3_CLK_MUL11 0x9 -#define PLL3MUL_PLL3_CLK_MUL12 0xa -#define PLL3MUL_PLL3_CLK_MUL13 0xb -#define PLL3MUL_PLL3_CLK_MUL14 0xc -#define PLL3MUL_PLL3_CLK_MUL16 0xe -#define PLL3MUL_PLL3_CLK_MUL20 0xf +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf /* PLL2MUL: PLL2 multiplication factor */ -#define PLL2MUL_PLL2_CLK_MUL8 0x6 -#define PLL2MUL_PLL2_CLK_MUL9 0x7 -#define PLL2MUL_PLL2_CLK_MUL10 0x8 -#define PLL2MUL_PLL2_CLK_MUL11 0x9 -#define PLL2MUL_PLL2_CLK_MUL12 0xa -#define PLL2MUL_PLL2_CLK_MUL13 0xb -#define PLL2MUL_PLL2_CLK_MUL14 0xc -#define PLL2MUL_PLL2_CLK_MUL16 0xe -#define PLL2MUL_PLL2_CLK_MUL20 0xf +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf /* PREDIV2: PREDIV2 division factor */ -#define PREDIV2_NODIV 0x0 -#define PREDIV2_DIV2 0x1 -#define PREDIV2_DIV3 0x2 -#define PREDIV2_DIV4 0x3 -#define PREDIV2_DIV5 0x4 -#define PREDIV2_DIV6 0x5 -#define PREDIV2_DIV7 0x6 -#define PREDIV2_DIV8 0x7 -#define PREDIV2_DIV9 0x8 -#define PREDIV2_DIV10 0x9 -#define PREDIV2_DIV11 0xa -#define PREDIV2_DIV12 0xb -#define PREDIV2_DIV13 0xc -#define PREDIV2_DIV14 0xd -#define PREDIV2_DIV15 0xe -#define PREDIV2_DIV16 0xf +#define RCC_CFGR2_PREDIV2_NODIV 0x0 +#define RCC_CFGR2_PREDIV2_DIV2 0x1 +#define RCC_CFGR2_PREDIV2_DIV3 0x2 +#define RCC_CFGR2_PREDIV2_DIV4 0x3 +#define RCC_CFGR2_PREDIV2_DIV5 0x4 +#define RCC_CFGR2_PREDIV2_DIV6 0x5 +#define RCC_CFGR2_PREDIV2_DIV7 0x6 +#define RCC_CFGR2_PREDIV2_DIV8 0x7 +#define RCC_CFGR2_PREDIV2_DIV9 0x8 +#define RCC_CFGR2_PREDIV2_DIV10 0x9 +#define RCC_CFGR2_PREDIV2_DIV11 0xa +#define RCC_CFGR2_PREDIV2_DIV12 0xb +#define RCC_CFGR2_PREDIV2_DIV13 0xc +#define RCC_CFGR2_PREDIV2_DIV14 0xd +#define RCC_CFGR2_PREDIV2_DIV15 0xe +#define RCC_CFGR2_PREDIV2_DIV16 0xf /* --- Function prototypes ------------------------------------------------- */ -- cgit v1.2.3