From c26541c4c5e2766f4f20a70867cb46d043b9273c Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sat, 25 Jul 2009 02:35:46 +0200 Subject: Some random cosmetic changes and additional comments. --- include/libopenstm32/gpio.h | 76 ++++++++++++++++++++++++++++++-------------- include/libopenstm32/rcc.h | 2 ++ include/libopenstm32/usart.h | 10 +++--- 3 files changed, 60 insertions(+), 28 deletions(-) (limited to 'include/libopenstm32') diff --git a/include/libopenstm32/gpio.h b/include/libopenstm32/gpio.h index f2e9667..23d633d 100644 --- a/include/libopenstm32/gpio.h +++ b/include/libopenstm32/gpio.h @@ -22,6 +22,8 @@ #include +/* --- Convenience macros -------------------------------------------------- */ + /* GPIO port base addresses (for convenience) */ #define GPIOA GPIO_PORT_A_BASE #define GPIOB GPIO_PORT_B_BASE @@ -31,6 +33,27 @@ #define GPIOF GPIO_PORT_F_BASE #define GPIOG GPIO_PORT_G_BASE +/* GPIO number definitions (for convenience) */ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff + +/* --- GPIO registers ------------------------------------------------------ */ + /* Port configuration register low (GPIOx_CRL) */ #define GPIO_CRL(port) MMIO32(port + 0x00) #define GPIOA_CRL GPIO_CRL(GPIOA) @@ -101,41 +124,48 @@ #define GPIOF_LCKR GPIO_LCKR(GPIOF) #define GPIOG_LCKR GPIO_LCKR(GPIOG) -/* Output mode (MODE[1:0]) values */ -#define GPIO_MODE_INPUT 0x00 /* Default */ -#define GPIO_MODE_OUTPUT_10_MHZ 0x01 -#define GPIO_MODE_OUTPUT_2_MHZ 0x02 -#define GPIO_MODE_OUTPUT_50_MHZ 0x03 +/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */ /* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ #define GPIO_CNF_INPUT_ANALOG 0x00 #define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ #define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 +/* Output mode (MODE[1:0]) values */ +#define GPIO_MODE_INPUT 0x00 /* Default */ +#define GPIO_MODE_OUTPUT_10_MHZ 0x01 +#define GPIO_MODE_OUTPUT_2_MHZ 0x02 +#define GPIO_MODE_OUTPUT_50_MHZ 0x03 + /* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ #define GPIO_CNF_OUTPUT_PUSHPULL 0x00 #define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 #define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 #define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 -/* GPIO number definitions (just for convenience) */ -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO10 (1 << 10) -#define GPIO11 (1 << 11) -#define GPIO12 (1 << 12) -#define GPIO13 (1 << 13) -#define GPIO14 (1 << 14) -#define GPIO15 (1 << 15) -#define GPIO_ALL 0xffff +/* --- GPIO_IDR values ----------------------------------------------------- */ + +/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIO_ODR values ----------------------------------------------------- */ + +/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIO_BSRR values ---------------------------------------------------- */ + +/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIO_BRR values ----------------------------------------------------- */ + +/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */ + +/* --- GPIO_LCKR values ---------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- Function prototypes ------------------------------------------------- */ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios); void gpio_set(u32 gpioport, u16 gpios); diff --git a/include/libopenstm32/rcc.h b/include/libopenstm32/rcc.h index 0c544c6..649e03d 100644 --- a/include/libopenstm32/rcc.h +++ b/include/libopenstm32/rcc.h @@ -359,6 +359,8 @@ #define PREDIV2_DIV15 0xe #define PREDIV2_DIV16 0xf +/* --- Function prototypes ------------------------------------------------- */ + typedef enum { PLL, HSE, HSI, LSE, LSI } osc_t; diff --git a/include/libopenstm32/usart.h b/include/libopenstm32/usart.h index 1408611..31ea1ad 100644 --- a/include/libopenstm32/usart.h +++ b/include/libopenstm32/usart.h @@ -24,11 +24,11 @@ /* --- Convenience macros -------------------------------------------------- */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +#define UART4 UART4_BASE +#define UART5 UART5_BASE /* --- USART registers ----------------------------------------------------- */ -- cgit v1.2.3