From 17b2e87ba3ba3cc029a92f275f110e17249d59f7 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Thu, 30 Dec 2010 00:53:52 +0100 Subject: Factor out cm3/common.h and cm3/memorymap.h. --- include/libopenstm32/memorymap.h | 35 +---------------------------------- 1 file changed, 1 insertion(+), 34 deletions(-) (limited to 'include/libopenstm32/memorymap.h') diff --git a/include/libopenstm32/memorymap.h b/include/libopenstm32/memorymap.h index a9c7fef..9aa1e97 100644 --- a/include/libopenstm32/memorymap.h +++ b/include/libopenstm32/memorymap.h @@ -20,40 +20,7 @@ #ifndef LIBOPENSTM32_MEMORYMAP_H #define LIBOPENSTM32_MEMORYMAP_H -/* --- ARM Cortex-M3 specific definitions ---------------------------------- */ - -/* Private peripheral bus - Internal */ -#define PPBI_BASE 0xE0000000 -#define ITM_BASE (PPBI_BASE + 0x0000) -#define DWT_BASE (PPBI_BASE + 0x1000) -#define FPB_BASE (PPBI_BASE + 0x2000) -/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */ -#define SCS_BASE (PPBI_BASE + 0xE000) -/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */ - -/* --- ITM: Instrumentation Trace Macrocell --- */ -/* TODO */ - -/* --- DWT: Data Watchpoint and Trace unit --- */ -/* TODO */ - -/* --- FPB: Flash Patch and Breakpoint unit --- */ -/* TODO */ - -/* --- SCS: System Control Space --- */ - -/* ITR: Interrupt Type Register */ -#define ITR_BASE (SCS_BASE + 0x0000) -/* SYS_TICK: System Timer */ -#define SYS_TICK_BASE (SCS_BASE + 0x0010) -/* NVIC: Nested Vector Interrupt Controller */ -#define NVIC_BASE (SCS_BASE + 0x0100) -/* SCB: System Control Block */ -#define SCB_BASE (SCS_BASE + 0x0D00) -/* STE: Software Trigger Interrupt Register */ -#define STIR_BASE (SCS_BASE + 0x0F00) -/* ID: ID space */ -#define ID_BASE (SCS_BASE + 0x0FD0) +#include /* --- STM32 specific peripheral definitions ------------------------------- */ -- cgit v1.2.3