From 0834f41383df854c30f4db973c3632439d7d9cca Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Tue, 9 Oct 2012 11:50:57 +1030 Subject: stm32f1: Add object files to Makefile to include new modules into lib. Correct typo in pwr.c Add two new functions to timer.c to preset the counter (for use with deadman style timeouts) and to identify an interrupt source. Also noticed lib/makefile.include didn't clean lib/stm32, which isn't a target. Added a fix. --- include/libopencm3/stm32/timer.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/libopencm3/stm32/timer.h') diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index b6f8949..61d40e9 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -1028,6 +1028,7 @@ BEGIN_DECLS void timer_reset(u32 timer_peripheral); void timer_enable_irq(u32 timer_peripheral, u32 irq); void timer_disable_irq(u32 timer_peripheral, u32 irq); +bool timer_return_interrupt_source(u32 timer_peripheral, u32 flag); bool timer_get_flag(u32 timer_peripheral, u32 flag); void timer_clear_flag(u32 timer_peripheral, u32 flag); void timer_set_mode(u32 timer_peripheral, u32 clock_div, @@ -1090,6 +1091,7 @@ void timer_set_break_lock(u32 timer_peripheral, u32 lock); void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); void timer_generate_event(u32 timer_peripheral, u32 event); u32 timer_get_counter(u32 timer_peripheral); +void timer_set_counter(u32 timer_peripheral, u32 count); void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt); void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc); -- cgit v1.2.3 From 6ee8e44bd7743806eeb1ba0983fd1113c519f71c Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 10 Oct 2012 21:31:31 +1030 Subject: Initial documentation for stm32/usart.c, usart.h Some minor documentation corrections to timer.h --- doc/stm32f1/DoxygenLayout_stm32f1.xml | 2 +- include/libopencm3/stm32/timer.h | 26 ++--- include/libopencm3/stm32/usart.h | 77 ++++++++++++-- lib/stm32/usart.c | 187 ++++++++++++++++++++++++++++++++++ 4 files changed, 267 insertions(+), 25 deletions(-) (limited to 'include/libopencm3/stm32/timer.h') diff --git a/doc/stm32f1/DoxygenLayout_stm32f1.xml b/doc/stm32f1/DoxygenLayout_stm32f1.xml index 912f2c4..6ed9bba 100644 --- a/doc/stm32f1/DoxygenLayout_stm32f1.xml +++ b/doc/stm32f1/DoxygenLayout_stm32f1.xml @@ -6,7 +6,7 @@ - + diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index 61d40e9..4977674 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -1,6 +1,6 @@ /** @defgroup STM32F_tim_defines Timers Defines -@brief libopencm3 Defined Constants and Types for the STM32F1xx Timers +@brief libopencm3 Defined Constants and Types for the STM32 Timers @ingroup STM32F_defines @@ -44,7 +44,7 @@ LGPL License Terms @ref lgpl_license /* Timer register base adresses (for convenience) */ /****************************************************************************/ /** @defgroup tim_reg_base Timer register base addresses -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM1 TIM1_BASE @@ -251,7 +251,7 @@ LGPL License Terms @ref lgpl_license /****************************************************************************/ /** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* CKD[1:0]: Clock division */ @@ -267,7 +267,7 @@ LGPL License Terms @ref lgpl_license /* CMS[1:0]: Center-aligned mode selection */ /****************************************************************************/ /** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR1_CMS_EDGE (0x0 << 5) @@ -280,7 +280,7 @@ LGPL License Terms @ref lgpl_license /* DIR: Direction */ /****************************************************************************/ /** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR1_DIR_UP (0 << 4) @@ -303,7 +303,7 @@ LGPL License Terms @ref lgpl_license /****************************************************************************/ /** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* OIS4:*//** Output idle state 4 (OC4 output) */ @@ -335,7 +335,7 @@ LGPL License Terms @ref lgpl_license /* MMS[2:0]: Master mode selection */ /****************************************************************************/ /** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR2_MMS_RESET (0x0 << 4) @@ -397,7 +397,7 @@ LGPL License Terms @ref lgpl_license /* TS[2:0]: Trigger selection */ /** @defgroup tim_ts TS Trigger selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /** Internal Trigger 0 (ITR0) */ @@ -421,7 +421,7 @@ LGPL License Terms @ref lgpl_license /* SMS[2:0]: Slave mode selection */ /** @defgroup tim_sms SMS Slave mode selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /** Slave mode disabled */ @@ -451,7 +451,7 @@ and generates an update of the registers. */ /****************************************************************************/ /** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* TDE:*//** Trigger DMA request enable */ @@ -503,7 +503,7 @@ and generates an update of the registers. */ /* --- TIMx_SR values ------------------------------------------------------ */ /****************************************************************************/ /** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ @@ -548,7 +548,7 @@ and generates an update of the registers. */ /****************************************************************************/ /** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ @@ -908,7 +908,7 @@ and generates an update of the registers. */ /* LOCK[1:0]: Lock configuration */ /****************************************************************************/ /** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_BDTR_LOCK_OFF (0x0 << 8) diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 9ec6c3d..911781b 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -1,3 +1,18 @@ +/** @defgroup STM32F_usart_defines USART Defines + +@brief libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter + +@ingroup STM32F_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 1 September 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * @@ -17,6 +32,8 @@ * along with this library. If not, see . */ +/**@{*/ + #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H @@ -25,9 +42,15 @@ /* --- Convenience macros -------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_reg_base USART register base addresses +@ingroup STM32F_usart_defines + +@{*/ #define USART1 USART1_BASE #define USART2 USART2_BASE #define USART3 USART3_BASE +/**@}*/ #define UART4 UART4_BASE #define UART5 UART5_BASE @@ -90,37 +113,43 @@ #define UART5_GTPR USART_GTPR(UART5_BASE) /* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines -/* CTS: CTS flag */ -/* Note: N/A on UART4/5 */ +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ #define USART_SR_CTS (1 << 9) -/* LBD: LIN break detection flag */ +/** LBD: LIN break detection flag */ #define USART_SR_LBD (1 << 8) -/* TXE: Transmit data buffer empty */ +/** TXE: Transmit data buffer empty */ #define USART_SR_TXE (1 << 7) -/* TC: Transmission complete */ +/** TC: Transmission complete */ #define USART_SR_TC (1 << 6) -/* RXNE: Read data register not empty */ +/** RXNE: Read data register not empty */ #define USART_SR_RXNE (1 << 5) -/* IDLE: Idle line detected */ +/** IDLE: Idle line detected */ #define USART_SR_IDLE (1 << 4) -/* ORE: Overrun error */ +/** ORE: Overrun error */ #define USART_SR_ORE (1 << 3) -/* NE: Noise error flag */ +/** NE: Noise error flag */ #define USART_SR_NE (1 << 2) -/* FE: Framing error */ +/** FE: Framing error */ #define USART_SR_FE (1 << 1) -/* PE: Parity error */ +/** PE: Parity error */ #define USART_SR_PE (1 << 0) +/**@}*/ /* --- USART_DR values ----------------------------------------------------- */ @@ -269,27 +298,51 @@ /* --- Convenience defines ------------------------------------------------- */ /* CR1_PCE / CR1_PS combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_parity USART Parity Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_PARITY_NONE 0x00 #define USART_PARITY_EVEN USART_CR1_PCE #define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) +/**@}*/ #define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) /* CR1_TE/CR1_RE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_MODE_RX USART_CR1_RE #define USART_MODE_TX USART_CR1_TE #define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +/**@}*/ #define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) +/****************************************************************************/ +/** @defgroup usart_cr2_stopbits USART Stop Bit Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ #define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ #define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ #define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ +/**@}*/ /* CR3_CTSE/CR3_RTSE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_FLOWCONTROL_NONE 0x00 #define USART_FLOWCONTROL_RTS USART_CR3_RTSE #define USART_FLOWCONTROL_CTS USART_CR3_CTSE #define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +/**@}*/ #define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) /* --- Function prototypes ------------------------------------------------- */ @@ -318,3 +371,5 @@ void usart_disable_tx_dma(u32 usart); END_DECLS #endif +/**@}*/ + diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c index 1d0ea9b..2958d7c 100644 --- a/lib/stm32/usart.c +++ b/lib/stm32/usart.c @@ -1,3 +1,22 @@ +/** @defgroup STM32F1xx_usart_file USART + +@ingroup STM32F_files + +@brief libopencm3 STM32F USART + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 30 August 2012 + +This library supports the USART/UART in the STM32F series +of ARM Cortex Microcontrollers by ST Microelectronics. + +Devices can have up to 3 USARTs and 2 UARTs. + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,6 +36,8 @@ * along with this library. If not, see . */ +/**@{*/ + #include #if defined(STM32F1) @@ -29,6 +50,20 @@ # error "stm32 family not defined." #endif +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Baudrate. + +The baud rate is computed from the APB high-speed prescaler clock (for USART1) +or the APB low-speed prescaler clock (for other USARTs). These values must +be correctly set before calling this function (refer to the rcc_clock_setup-* +functions in RCC). + +@todo Add support for USART6 and oversampling in F2/F4 + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] baud unsigned 32 bit. Baud rate specified in Hz. +*/ + void usart_set_baudrate(u32 usart, u32 baud) { u32 clock = rcc_ppre1_frequency; @@ -59,6 +94,16 @@ void usart_set_baudrate(u32 usart, u32 baud) USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Word Length. + +The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit +if parity is enabled, in which case the data length will be 7 or 8 bits respectively. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] bits unsigned 32 bit. Word length in bits 8 or 9. +*/ + void usart_set_databits(u32 usart, u32 bits) { if (bits == 8) @@ -67,6 +112,15 @@ void usart_set_databits(u32 usart, u32 bits) USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Stop Bit(s). + +The stop bits are specified as 0.5, 1, 1.5 or 2. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits. +*/ + void usart_set_stopbits(u32 usart, u32 stopbits) { u32 reg32; @@ -76,6 +130,15 @@ void usart_set_stopbits(u32 usart, u32 stopbits) USART_CR2(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Parity. + +The parity bit can be selected as none, even or odd. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity. +*/ + void usart_set_parity(u32 usart, u32 parity) { u32 reg32; @@ -85,6 +148,15 @@ void usart_set_parity(u32 usart, u32 parity) USART_CR1(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Rx/Tx Mode. + +The mode can be selected as Rx only, Tx only or Rx+Tx. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode. +*/ + void usart_set_mode(u32 usart, u32 mode) { u32 reg32; @@ -94,6 +166,15 @@ void usart_set_mode(u32 usart, u32 mode) USART_CR1(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Hardware Flow Control. + +The flow control bit can be selected as none, RTS, CTS or RTS+CTS. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol. +*/ + void usart_set_flow_control(u32 usart, u32 flowcontrol) { u32 reg32; @@ -103,46 +184,112 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol) USART_CR3(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable(u32 usart) { USART_CR1(usart) |= USART_CR1_UE; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Disable. + +At the end of the current frame, the USART is disabled to reduce power. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable(u32 usart) { USART_CR1(usart) &= ~USART_CR1_UE; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Send a Data Word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] data unsigned 16 bit. +*/ + void usart_send(u32 usart, u16 data) { /* Send data. */ USART_DR(usart) = (data & USART_DR_MASK); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Read a Received Data Word. + +If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@returns unsigned 16 bit data word. +*/ + u16 usart_recv(u32 usart) { /* Receive data. */ return USART_DR(usart) & USART_DR_MASK; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Wait for Transmit Data Buffer Empty + +Blocks until the transmit data buffer becomes empty and is ready to accept the +next data word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_wait_send_ready(u32 usart) { /* Wait until the data has been transferred into the shift register. */ while ((USART_SR(usart) & USART_SR_TXE) == 0); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Wait for Received Data Available + +Blocks until the receive data buffer holds a valid received data word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_wait_recv_ready(u32 usart) { /* Wait until the data is ready to be received. */ while ((USART_SR(usart) & USART_SR_RXNE) == 0); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Send Data Word with Blocking + +Blocks until the transmit data buffer becomes empty then writes the next data word +for transmission. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] data unsigned 16 bit. +*/ + void usart_send_blocking(u32 usart, u16 data) { usart_wait_send_ready(usart); usart_send(usart, data); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Read a Received Data Word with Blocking. + +Wait until a data word has been received then return the word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@returns unsigned 16 bit data word. +*/ + u16 usart_recv_blocking(u32 usart) { usart_wait_recv_ready(usart); @@ -150,22 +297,62 @@ u16 usart_recv_blocking(u32 usart) return usart_recv(usart); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver DMA Enable. + +DMA is available on: +@li USART1 Rx DMA1 channel 5. +@li USART2 Rx DMA1 channel 6. +@li USART3 Rx DMA1 channel 3. +@li UART4 Rx DMA2 channel 3. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable_rx_dma(u32 usart) { USART_CR3(usart) |= USART_CR3_DMAR; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver DMA Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable_rx_dma(u32 usart) { USART_CR3(usart) &= ~USART_CR3_DMAR; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter DMA Enable. + +DMA is available on: +@li USART1 Tx DMA1 channel 4. +@li USART2 Tx DMA1 channel 7. +@li USART3 Tx DMA1 channel 2. +@li UART4 Tx DMA2 channel 5. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable_tx_dma(u32 usart) { USART_CR3(usart) |= USART_CR3_DMAT; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter DMA Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable_tx_dma(u32 usart) { USART_CR3(usart) &= ~USART_CR3_DMAT; } + + +/**@}*/ + -- cgit v1.2.3