From 34beeae925798dc49ad79f2f8c47aeaee7d8262a Mon Sep 17 00:00:00 2001 From: Jason Kotzin Date: Thu, 16 Aug 2012 18:50:38 -0700 Subject: USB core updated for reentrance based on Christian Cier-Zniewski's branch --- include/libopencm3/stm32/otg_fs.h | 105 +++++++++++++++++++++----------------- 1 file changed, 58 insertions(+), 47 deletions(-) (limited to 'include/libopencm3/stm32/otg_fs.h') diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h index 5680e43..d8ee393 100644 --- a/include/libopencm3/stm32/otg_fs.h +++ b/include/libopencm3/stm32/otg_fs.h @@ -24,7 +24,7 @@ #include /* Core Global Control and Status Registers */ -#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) +#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) #define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) #define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) #define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) @@ -42,40 +42,40 @@ #define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x-1)) /* Host-mode Control and Status Registers */ -#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) -#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) -#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) -#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) -#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) -#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) -#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) -#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) -#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) -#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) -#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) +#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) +#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) +#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) +#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) +#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) +#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) +#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) +#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) +#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) +#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) +#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) /* Device-mode Control and Status Registers */ -#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) -#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) -#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) -#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) -#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) -#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) -#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) -#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) -#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) -#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) -#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) -#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) -#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) -#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) -#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) -#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) -#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) -#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) -#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) -#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) -#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) +#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) +#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) +#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) +#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) +#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) +#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) +#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) +#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) +#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) +#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) +#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) +#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) +#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) +#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) +#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) +#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) +#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) +#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) +#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) +#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) +#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) /* Power and clock gating control and status register */ #define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) @@ -84,6 +84,18 @@ #define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) /* Global CSRs */ +/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */ +#define OTG_FS_GOTGCTL_BSVLD (1 << 19) +#define OTG_FS_GOTGCTL_ASVLD (1 << 18) +#define OTG_FS_GOTGCTL_DBCT (1 << 17) +#define OTG_FS_GOTGCTL_CIDSTS (1 << 16) +#define OTG_FS_GOTGCTL_DHNPEN (1 << 11) +#define OTG_FS_GOTGCTL_HSHNPEN (1 << 10) +#define OTG_FS_GOTGCTL_HNPRQ (1 << 9) +#define OTG_FS_GOTGCTL_HNGSCS (1 << 8) +#define OTG_FS_GOTGCTL_SRQ (1 << 1) +#define OTG_FS_GOTGCTL_SRQSCS (1 << 0) + /* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ #define OTG_FS_GAHBCFG_GINT 0x0001 #define OTG_FS_GAHBCFG_TXFELVL 0x0080 @@ -175,20 +187,20 @@ /* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ /* Bits 31:25 - Reserved */ -#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) -#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) -#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) #define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) -#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) -#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) -#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) -#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) +#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) /* OTG_FS general core configuration register (OTG_FS_GCCFG) */ /* Bits 31:21 - Reserved */ @@ -320,4 +332,3 @@ #define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) #endif - -- cgit v1.2.3