From 8318384cf1fec4d0b336e5d4deb1f126526584be Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 19 Jul 2012 22:41:52 +0000 Subject: More progress towards L1 support. Believe gpio is complete, but untested without finishing at least the RCC defines. RCC defines are a work in progress --- include/libopencm3/stm32/l1/gpio.h | 241 +++++++++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) create mode 100644 include/libopencm3/stm32/l1/gpio.h (limited to 'include/libopencm3/stm32/l1/gpio.h') diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h new file mode 100644 index 0000000..76325a9 --- /dev/null +++ b/include/libopencm3/stm32/l1/gpio.h @@ -0,0 +1,241 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOH GPIO_PORT_H_BASE + +/* GPIO number definitions (for convenience) */ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff + +/* --- GPIO registers ------------------------------------------------------ */ + +/* Port mode register (GPIOx_MODER) */ +#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIOA_MODER GPIO_MODER(GPIOA) +#define GPIOB_MODER GPIO_MODER(GPIOB) +#define GPIOC_MODER GPIO_MODER(GPIOC) +#define GPIOD_MODER GPIO_MODER(GPIOD) +#define GPIOE_MODER GPIO_MODER(GPIOE) +#define GPIOH_MODER GPIO_MODER(GPIOH) + +/* Port output type register (GPIOx_OTYPER) */ +#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) +#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) +#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) +#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) +#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) +#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) + +/* Port output speed register (GPIOx_OSPEEDR) */ +#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) +#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) +#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) +#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) +#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) +#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) + +/* Port pull-up/pull-down register (GPIOx_PUPDR) */ +#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) +#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) +#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) +#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) +#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) +#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOH_IDR GPIO_IDR(GPIOH) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOH_ODR GPIO_ODR(GPIOH) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOH_BSRR GPIO_BSRR(GPIOH) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x1C) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOH_LCKR GPIO_LCKR(GPIOH) + +/* Alternate function low register (GPIOx_AFRL) */ +#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIOA_AFRL GPIO_AFRL(GPIOA) +#define GPIOB_AFRL GPIO_AFRL(GPIOB) +#define GPIOC_AFRL GPIO_AFRL(GPIOC) +#define GPIOD_AFRL GPIO_AFRL(GPIOD) +#define GPIOE_AFRL GPIO_AFRL(GPIOE) +#define GPIOH_AFRL GPIO_AFRL(GPIOH) + +/* Alternate function high register (GPIOx_AFRH) */ +#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIOA_AFRH GPIO_AFRH(GPIOA) +#define GPIOB_AFRH GPIO_AFRH(GPIOB) +#define GPIOC_AFRH GPIO_AFRH(GPIOC) +#define GPIOD_AFRH GPIO_AFRH(GPIOD) +#define GPIOE_AFRH GPIO_AFRH(GPIOE) +#define GPIOH_AFRH GPIO_AFRH(GPIOH) + +/* --- GPIOx_MODER values-------------------------------------------- */ + +#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) +#define GPIO_MODE_INPUT 0x00 /* Default */ +#define GPIO_MODE_OUTPUT 0x01 +#define GPIO_MODE_ALTFN 0x02 +#define GPIO_MODE_ANALOG 0x03 + +/* --- GPIOx_OTYPER values -------------------------------------------- */ +/* Output type (OTx values) */ +#define GPIO_OTYPE_PP 0x0 +#define GPIO_OTYPE_OD 0x1 + +/* Output speed values */ +#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) +#define GPIO_OSPEED_400KHZ 0x0 +#define GPIO_OSPEED_2MHZ 0x1 +#define GPIO_OSPEED_10MHZ 0x2 +#define GPIO_OSPEED_40MHZ 0x3 + +/* --- GPIOx_PUPDR values ------------------------------------------- */ + +#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) +#define GPIO_PUPD_NONE 0x0 +#define GPIO_PUPD_PULLUP 0x1 +#define GPIO_PUPD_PULLDOWN 0x2 + +/* --- GPIO_IDR values ----------------------------------------------------- */ + +/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIO_ODR values ----------------------------------------------------- */ + +/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIO_BSRR values ---------------------------------------------------- */ + +/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIO_LCKR values ---------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- GPIOx_AFRL/H values ------------------------------------------------- */ + +/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ +/* See datasheet table 5, page 35 for the definitions */ + +#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) +#define GPIO_AF0 0x0 +#define GPIO_AF1 0x1 +#define GPIO_AF2 0x2 +#define GPIO_AF3 0x3 +#define GPIO_AF4 0x4 +#define GPIO_AF5 0x5 +#define GPIO_AF6 0x6 +#define GPIO_AF7 0x7 +#define GPIO_AF8 0x8 +#define GPIO_AF9 0x9 +#define GPIO_AF10 0xa +#define GPIO_AF11 0xb +#define GPIO_AF12 0xc +#define GPIO_AF13 0xd +#define GPIO_AF14 0xe +#define GPIO_AF15 0xf + +/* --- Function prototypes ------------------------------------------------- */ + +/* + * L1, like F2 and F4, has the "new" GPIO peripheral, so use that style + * TODO: this should all really be moved to a "common" gpio header + */ + +void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios); +void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios); +void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios); + +/* F1 compatible api */ +void gpio_set(u32 gpioport, u16 gpios); +void gpio_clear(u32 gpioport, u16 gpios); +u16 gpio_get(u32 gpioport, u16 gpios); +void gpio_toggle(u32 gpioport, u16 gpios); +u16 gpio_port_read(u32 gpioport); +void gpio_port_write(u32 gpioport, u16 data); +void gpio_port_config_lock(u32 gpioport, u16 gpios); + +#endif -- cgit v1.2.3 From 25acaa58783b4d046acbe961cb62efe0b39ec981 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 22 Oct 2012 21:29:42 +0000 Subject: Add usart support for L1. Only tested with basic tx blocking, ie, the same example code as on F2/F4, but the description of the block is almost identical. --- examples/stm32/l1/stm32l-discovery/usart/Makefile | 25 +++++++ examples/stm32/l1/stm32l-discovery/usart/README | 12 ++++ examples/stm32/l1/stm32l-discovery/usart/usart.c | 80 +++++++++++++++++++++++ include/libopencm3/stm32/l1/gpio.h | 2 +- lib/stm32/l1/Makefile | 2 +- lib/stm32/usart.c | 2 + 6 files changed, 121 insertions(+), 2 deletions(-) create mode 100644 examples/stm32/l1/stm32l-discovery/usart/Makefile create mode 100644 examples/stm32/l1/stm32l-discovery/usart/README create mode 100644 examples/stm32/l1/stm32l-discovery/usart/usart.c (limited to 'include/libopencm3/stm32/l1/gpio.h') diff --git a/examples/stm32/l1/stm32l-discovery/usart/Makefile b/examples/stm32/l1/stm32l-discovery/usart/Makefile new file mode 100644 index 0000000..ac088fe --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/usart/Makefile @@ -0,0 +1,25 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = usart + +LDSCRIPT = ../../../../../lib/stm32/l1/stm32l15xxb.ld + +include ../../Makefile.include + diff --git a/examples/stm32/l1/stm32l-discovery/usart/README b/examples/stm32/l1/stm32l-discovery/usart/README new file mode 100644 index 0000000..dcbc5d9 --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/usart/README @@ -0,0 +1,12 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program sends some characters on USART2 on the +ST STM32L DISCOVERY eval board. (USART2 TX on PA2) + +The terminal settings for the receiving device/PC are 38400 8n1. + +The sending is done in a blocking way in the code, see the usart_irq example +for a more elaborate USART example. + diff --git a/examples/stm32/l1/stm32l-discovery/usart/usart.c b/examples/stm32/l1/stm32l-discovery/usart/usart.c new file mode 100644 index 0000000..3335ca8 --- /dev/null +++ b/examples/stm32/l1/stm32l-discovery/usart/usart.c @@ -0,0 +1,80 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include + +void clock_setup(void) { + /* We are running on MSI after boot. */ + /* Enable GPIOD clock for LED & USARTs. */ + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOAEN); + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN); + + /* Enable clocks for USART2. */ + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN); +} + +void usart_setup(void) { + /* Setup USART2 parameters. */ + usart_set_baudrate(USART2, 38400); + usart_set_databits(USART2, 8); + usart_set_stopbits(USART2, USART_STOPBITS_1); + usart_set_mode(USART2, USART_MODE_TX); + usart_set_parity(USART2, USART_PARITY_NONE); + usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART2); +} + +void gpio_setup(void) { + /* Setup GPIO pin GPIO7 on GPIO port B for Green LED. */ + gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO7); + + /* Setup GPIO pins for USART2 transmit. */ + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2); + + /* Setup USART2 TX pin as alternate function. */ + gpio_set_af(GPIOA, GPIO_AF7, GPIO2); +} + +int main(void) { + int i, j = 0, c = 0; + + clock_setup(); + gpio_setup(); + usart_setup(); + + /* Blink the LED (PD12) on the board with every transmitted byte. */ + while (1) { + gpio_toggle(GPIOB, GPIO7); /* LED on/off */ + usart_send_blocking(USART2, c + '0'); /* USART2: Send byte. */ + c = (c == 9) ? 0 : c + 1; /* Increment c. */ + if ((j++ % 80) == 0) { /* Newline after line full. */ + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + } + for (i = 0; i < 100000; i++) /* Wait a bit. */ + __asm__("NOP"); + } + + return 0; +} diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h index 76325a9..a39c9f6 100644 --- a/include/libopencm3/stm32/l1/gpio.h +++ b/include/libopencm3/stm32/l1/gpio.h @@ -152,7 +152,7 @@ #define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) #define GPIO_MODE_INPUT 0x00 /* Default */ #define GPIO_MODE_OUTPUT 0x01 -#define GPIO_MODE_ALTFN 0x02 +#define GPIO_MODE_AF 0x02 #define GPIO_MODE_ANALOG 0x03 /* --- GPIOx_OTYPER values -------------------------------------------- */ diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index a009857..f852239 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o desig.o crc.o +OBJS = rcc.o gpio.o desig.o crc.o usart.o VPATH += ../../usb:../:../../cm3 diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c index 5cf861b..1faf486 100644 --- a/lib/stm32/usart.c +++ b/lib/stm32/usart.c @@ -46,6 +46,8 @@ LGPL License Terms @ref lgpl_license # include #elif defined(STM32F4) # include +#elif defined(STM32L1) +# include #else # error "stm32 family not defined." #endif -- cgit v1.2.3