From 1fea1df39abde97d1e84f5b99f9793701b1691b7 Mon Sep 17 00:00:00 2001 From: Stephen Caudle Date: Mon, 31 Oct 2011 11:11:03 -0400 Subject: Fix more STM32 whitespace issues --- include/libopencm3/stm32/f4/flash.h | 118 ++++++++++++------------- include/libopencm3/stm32/f4/gpio.h | 18 ++-- include/libopencm3/stm32/f4/nvic_f4.h | 162 +++++++++++++++++----------------- include/libopencm3/stm32/f4/rcc.h | 16 ++-- include/libopencm3/stm32/f4/scb.h | 34 +++---- include/libopencm3/stm32/f4/spi.h | 4 +- include/libopencm3/stm32/f4/syscfg.h | 2 +- include/libopencm3/stm32/f4/timer.h | 29 +++--- include/libopencm3/stm32/f4/usart.h | 2 +- 9 files changed, 189 insertions(+), 196 deletions(-) (limited to 'include/libopencm3/stm32/f4') diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h index 4ed86f1..a2a44e9 100644 --- a/include/libopencm3/stm32/f4/flash.h +++ b/include/libopencm3/stm32/f4/flash.h @@ -42,76 +42,76 @@ /* --- FLASH_ACR values ---------------------------------------------------- */ -#define FLASH_DCRST (1 << 12) -#define FLASH_ICRST (1 << 11) -#define FLASH_DCE (1 << 10) -#define FLASH_ICE (1 << 9) -#define FLASH_PRFTEN (1 << 8) -#define FLASH_LATENCY_0WS 0x00 -#define FLASH_LATENCY_1WS 0x01 -#define FLASH_LATENCY_2WS 0x02 -#define FLASH_LATENCY_3WS 0x03 -#define FLASH_LATENCY_4WS 0x04 -#define FLASH_LATENCY_5WS 0x05 -#define FLASH_LATENCY_6WS 0x06 -#define FLASH_LATENCY_7WS 0x07 +#define FLASH_DCRST (1 << 12) +#define FLASH_ICRST (1 << 11) +#define FLASH_DCE (1 << 10) +#define FLASH_ICE (1 << 9) +#define FLASH_PRFTEN (1 << 8) +#define FLASH_LATENCY_0WS 0x00 +#define FLASH_LATENCY_1WS 0x01 +#define FLASH_LATENCY_2WS 0x02 +#define FLASH_LATENCY_3WS 0x03 +#define FLASH_LATENCY_4WS 0x04 +#define FLASH_LATENCY_5WS 0x05 +#define FLASH_LATENCY_6WS 0x06 +#define FLASH_LATENCY_7WS 0x07 /* --- FLASH_SR values ----------------------------------------------------- */ -#define FLASH_BSY (1 << 16) -#define FLASH_PGSERR (1 << 7) -#define FLASH_PGPERR (1 << 6) -#define FLASH_PGAERR (1 << 5) -#define FLASH_WRPERR (1 << 4) -#define FLASH_OPERR (1 << 1) -#define FLASH_EOP (1 << 0) +#define FLASH_BSY (1 << 16) +#define FLASH_PGSERR (1 << 7) +#define FLASH_PGPERR (1 << 6) +#define FLASH_PGAERR (1 << 5) +#define FLASH_WRPERR (1 << 4) +#define FLASH_OPERR (1 << 1) +#define FLASH_EOP (1 << 0) /* --- FLASH_CR values ----------------------------------------------------- */ -#define FLASH_LOCK (1 << 31) -#define FLASH_ERRIE (1 << 25) -#define FLASH_EOPIE (1 << 24) -#define FLASH_STRT (1 << 16) -#define FLASH_MER (1 << 2) -#define FLASH_SER (1 << 1) -#define FLASH_PG (1 << 0) -#define FLASH_SECTOR_0 (0x00 << 3) -#define FLASH_SECTOR_1 (0x01 << 3) -#define FLASH_SECTOR_2 (0x02 << 3) -#define FLASH_SECTOR_3 (0x03 << 3) -#define FLASH_SECTOR_4 (0x04 << 3) -#define FLASH_SECTOR_5 (0x05 << 3) -#define FLASH_SECTOR_6 (0x06 << 3) -#define FLASH_SECTOR_7 (0x07 << 3) -#define FLASH_SECTOR_8 (0x08 << 3) -#define FLASH_SECTOR_9 (0x09 << 3) -#define FLASH_SECTOR_10 (0x0a << 3) -#define FLASH_SECTOR_11 (0x0b << 3) -#define FLASH_PROGRAM_X8 (0x00 << 8) -#define FLASH_PROGRAM_X16 (0x01 << 8) -#define FLASH_PROGRAM_X32 (0x02 << 8) -#define FLASH_PROGRAM_X64 (0x03 << 8) +#define FLASH_LOCK (1 << 31) +#define FLASH_ERRIE (1 << 25) +#define FLASH_EOPIE (1 << 24) +#define FLASH_STRT (1 << 16) +#define FLASH_MER (1 << 2) +#define FLASH_SER (1 << 1) +#define FLASH_PG (1 << 0) +#define FLASH_SECTOR_0 (0x00 << 3) +#define FLASH_SECTOR_1 (0x01 << 3) +#define FLASH_SECTOR_2 (0x02 << 3) +#define FLASH_SECTOR_3 (0x03 << 3) +#define FLASH_SECTOR_4 (0x04 << 3) +#define FLASH_SECTOR_5 (0x05 << 3) +#define FLASH_SECTOR_6 (0x06 << 3) +#define FLASH_SECTOR_7 (0x07 << 3) +#define FLASH_SECTOR_8 (0x08 << 3) +#define FLASH_SECTOR_9 (0x09 << 3) +#define FLASH_SECTOR_10 (0x0a << 3) +#define FLASH_SECTOR_11 (0x0b << 3) +#define FLASH_PROGRAM_X8 (0x00 << 8) +#define FLASH_PROGRAM_X16 (0x01 << 8) +#define FLASH_PROGRAM_X32 (0x02 << 8) +#define FLASH_PROGRAM_X64 (0x03 << 8) /* --- FLASH_OPTCR values -------------------------------------------------- */ /* FLASH_OPTCR[27:16]: nWRP */ /* FLASH_OBR[15:8]: RDP */ -#define FLASH_NRST_STDBY (1 << 7) -#define FLASH_NRST_STOP (1 << 6) -#define FLASH_WDG_SW (1 << 5) -#define FLASH_OPTSTRT (1 << 1) -#define FLASH_OPTLOCK (1 << 0) -#define FLASH_BOR_LEVEL_3 (0x00 << 2) -#define FLASH_BOR_LEVEL_2 (0x01 << 2) -#define FLASH_BOR_LEVEL_1 (0x02 << 2) -#define FLASH_BOR_OFF (0x03 << 2) +#define FLASH_NRST_STDBY (1 << 7) +#define FLASH_NRST_STOP (1 << 6) +#define FLASH_WDG_SW (1 << 5) +#define FLASH_OPTSTRT (1 << 1) +#define FLASH_OPTLOCK (1 << 0) +#define FLASH_BOR_LEVEL_3 (0x00 << 2) +#define FLASH_BOR_LEVEL_2 (0x01 << 2) +#define FLASH_BOR_LEVEL_1 (0x02 << 2) +#define FLASH_BOR_OFF (0x03 << 2) /* --- FLASH Keys -----------------------------------------------------------*/ -#define FLASH_KEY1 ((u32)0x45670123) -#define FLASH_KEY2 ((u32)0xcdef89ab) -#define FLASH_OPTKEY1 ((u32)0x08192a3b) -#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f) +#define FLASH_KEY1 ((u32)0x45670123) +#define FLASH_KEY2 ((u32)0xcdef89ab) +#define FLASH_OPTKEY1 ((u32)0x08192a3b) +#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f) /* --- Function prototypes ------------------------------------------------- */ @@ -144,10 +144,4 @@ void flash_program_byte(u32 address, u8 data, u32 program_size); void flash_wait_for_last_operation(void); void flash_program_option_bytes(u32 data); -#if 0 -// TODO: Implement support for option bytes -void flash_erase_option_bytes(void); -void flash_program_option_bytes(u32 address, u16 data); -#endif - #endif diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h index 7832075..5e0377d 100644 --- a/include/libopencm3/stm32/f4/gpio.h +++ b/include/libopencm3/stm32/f4/gpio.h @@ -179,8 +179,8 @@ /* --- GPIOx_MODER values -------------------------------------------------- */ -#define GPIO_MODE(n, mode) (mode << (2*(n))) -#define GPIO_MODE_MASK(n) (0x3 << (2*(n))) +#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) #define GPIO_MODE_INPUT 0x0 #define GPIO_MODE_OUTPUT 0x1 #define GPIO_MODE_AF 0x2 @@ -193,8 +193,8 @@ /* --- GPIOx_OSPEEDR values ------------------------------------------------ */ -#define GPIO_OSPEED(n, speed) (speed << (2*(n))) -#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n))) +#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) #define GPIO_OSPEED_2MHZ 0x0 #define GPIO_OSPEED_25MHZ 0x1 #define GPIO_OSPEED_50MHZ 0x2 @@ -202,8 +202,8 @@ /* --- GPIOx_PUPDR values -------------------------------------------------- */ -#define GPIO_PUPD(n, pupd) (pupd << (2*(n))) -#define GPIO_PUPD_MASK(n) (0x3 << (2*(n))) +#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) #define GPIO_PUPD_NONE 0x0 #define GPIO_PUPD_PULLUP 0x1 #define GPIO_PUPD_PULLDOWN 0x2 @@ -231,8 +231,8 @@ /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See Datasheet Table 6 (pg. 48) for alternate function mappings. */ -#define GPIO_AFR(n, af) (af << ((n)*4)) -#define GPIO_AFR_MASK(n) (0xf << ((n)*4)) +#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) #define GPIO_AF0 0x0 #define GPIO_AF1 0x1 #define GPIO_AF2 0x2 @@ -258,7 +258,7 @@ * Note: The F2 series has a completely new GPIO peripheral with different * configuration options. Here we implement a different API partly to more * closely match the peripheral capabilities and also to deliberately break - * compatibility with old F1 code so there is no confusion with similar + * compatibility with old F1 code so there is no confusion with similar * sounding functions that have very different functionality. */ diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h index 6375d41..f0cec96 100644 --- a/include/libopencm3/stm32/f4/nvic_f4.h +++ b/include/libopencm3/stm32/f4/nvic_f4.h @@ -27,86 +27,86 @@ */ /* User Interrupts */ -#define NVIC_NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMP_STAMP_IRQ 2 -#define NVIC_RTC_WKUP_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_STREAM0_IRQ 11 -#define NVIC_DMA1_STREAM1_IRQ 12 -#define NVIC_DMA1_STREAM2_IRQ 13 -#define NVIC_DMA1_STREAM3_IRQ 14 -#define NVIC_DMA1_STREAM4_IRQ 15 -#define NVIC_DMA1_STREAM5_IRQ 16 -#define NVIC_DMA1_STREAM6_IRQ 17 -#define NVIC_ADC_IRQ 18 -#define NVIC_CAN1_TX_IRQ 19 -#define NVIC_CAN1_RX0_IRQ 20 -#define NVIC_CAN1_RX1_IRQ 21 -#define NVIC_CAN1_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_TIM9_IRQ 24 -#define NVIC_TIM1_UP_TIM10_IRQ 25 -#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_FS_WKUP_IRQ 42 -#define NVIC_TIM8_BRK_TIM12_IRQ 43 -#define NVIC_TIM8_UP_TIM13_IRQ 44 -#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_DMA1_STREAM7_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_USART4_IRQ 52 -#define NVIC_USART5_IRQ 53 -#define NVIC_TIM6_DAC_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_STREAM0_IRQ 56 -#define NVIC_DMA2_STREAM1_IRQ 57 -#define NVIC_DMA2_STREAM2_IRQ 58 -#define NVIC_DMA2_STREAM3_IRQ 59 -#define NVIC_DMA2_STREAM4_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 -#define NVIC_DMA2_STREAM5_IRQ 68 -#define NVIC_DMA2_STREAM6_IRQ 69 -#define NVIC_DMA2_STREAM7_IRQ 70 -#define NVIC_USART6_IRQ 71 -#define NVIC_I2C3_EV_IRQ 72 -#define NVIC_I2C3_ER_IRQ 73 -#define NVIC_OTG_HS_EP1_OUT_IRQ 74 -#define NVIC_OTG_HS_EP1_IN_IRQ 75 -#define NVIC_OTG_HS_WKUP_IRQ 76 -#define NVIC_OTG_HS_IRQ 77 -#define NVIC_DCMI_IRQ 78 -#define NVIC_CRYP_IRQ 79 -#define NVIC_HASH_RNG_IRQ 80 +#define NVIC_NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMP_STAMP_IRQ 2 +#define NVIC_RTC_WKUP_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_STREAM0_IRQ 11 +#define NVIC_DMA1_STREAM1_IRQ 12 +#define NVIC_DMA1_STREAM2_IRQ 13 +#define NVIC_DMA1_STREAM3_IRQ 14 +#define NVIC_DMA1_STREAM4_IRQ 15 +#define NVIC_DMA1_STREAM5_IRQ 16 +#define NVIC_DMA1_STREAM6_IRQ 17 +#define NVIC_ADC_IRQ 18 +#define NVIC_CAN1_TX_IRQ 19 +#define NVIC_CAN1_RX0_IRQ 20 +#define NVIC_CAN1_RX1_IRQ 21 +#define NVIC_CAN1_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_TIM9_IRQ 24 +#define NVIC_TIM1_UP_TIM10_IRQ 25 +#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_FS_WKUP_IRQ 42 +#define NVIC_TIM8_BRK_TIM12_IRQ 43 +#define NVIC_TIM8_UP_TIM13_IRQ 44 +#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_DMA1_STREAM7_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_USART4_IRQ 52 +#define NVIC_USART5_IRQ 53 +#define NVIC_TIM6_DAC_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_STREAM0_IRQ 56 +#define NVIC_DMA2_STREAM1_IRQ 57 +#define NVIC_DMA2_STREAM2_IRQ 58 +#define NVIC_DMA2_STREAM3_IRQ 59 +#define NVIC_DMA2_STREAM4_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 +#define NVIC_DMA2_STREAM5_IRQ 68 +#define NVIC_DMA2_STREAM6_IRQ 69 +#define NVIC_DMA2_STREAM7_IRQ 70 +#define NVIC_USART6_IRQ 71 +#define NVIC_I2C3_EV_IRQ 72 +#define NVIC_I2C3_ER_IRQ 73 +#define NVIC_OTG_HS_EP1_OUT_IRQ 74 +#define NVIC_OTG_HS_EP1_IN_IRQ 75 +#define NVIC_OTG_HS_WKUP_IRQ 76 +#define NVIC_OTG_HS_IRQ 77 +#define NVIC_DCMI_IRQ 78 +#define NVIC_CRYP_IRQ 79 +#define NVIC_HASH_RNG_IRQ 80 #endif diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index debeeda..a01aaad 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -133,14 +133,14 @@ /* HPRE: AHB high-speed prescaler */ #define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 (0x8+0) -#define RCC_CFGR_HPRE_DIV_4 (0x8+1) -#define RCC_CFGR_HPRE_DIV_8 (0x8+2) -#define RCC_CFGR_HPRE_DIV_16 (0x8+3) -#define RCC_CFGR_HPRE_DIV_64 (0x8+4) -#define RCC_CFGR_HPRE_DIV_128 (0x8+5) -#define RCC_CFGR_HPRE_DIV_256 (0x8+6) -#define RCC_CFGR_HPRE_DIV_512 (0x8+7) +#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SHIFT 2 diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h index 9594cf1..b73ada3 100644 --- a/include/libopencm3/stm32/f4/scb.h +++ b/include/libopencm3/stm32/f4/scb.h @@ -27,50 +27,50 @@ /* --- SCB: Registers ------------------------------------------------------ */ /* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) +#define SCB_CPUID MMIO32(SCB_BASE + 0x00) /* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) +#define SCB_ICSR MMIO32(SCB_BASE + 0x04) /* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) +#define SCB_VTOR MMIO32(SCB_BASE + 0x08) /* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) +#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) /* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) +#define SCB_SCR MMIO32(SCB_BASE + 0x10) /* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) +#define SCB_CCR MMIO32(SCB_BASE + 0x14) /* SHP: System Handler Priority Registers */ /* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) +#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) +#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) +#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) +#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) /* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) +#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) /* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) +#define SCB_CFSR MMIO32(SCB_BASE + 0x28) /* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) +#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) /* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) +#define SCB_DFSR MMIO32(SCB_BASE + 0x30) /* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) +#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) /* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) +#define SCB_BFAR MMIO32(SCB_BASE + 0x38) /* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) +#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) /* --- SCB values ---------------------------------------------------------- */ diff --git a/include/libopencm3/stm32/f4/spi.h b/include/libopencm3/stm32/f4/spi.h index 23c9479..0d29e67 100644 --- a/include/libopencm3/stm32/f4/spi.h +++ b/include/libopencm3/stm32/f4/spi.h @@ -31,8 +31,8 @@ /* FRF: Frame format. */ #define SPI_CR2_FRF (1 << 4) -#define SPI_CR2_FRF_TI (1 << 4) -#define SPI_CR2_FRF_MOTOROLA (1 << 4) +#define SPI_CR2_FRF_TI (1 << 4) +#define SPI_CR2_FRF_MOTOROLA (1 << 4) /* --- SPI_SR values ------------------------------------------------------- */ diff --git a/include/libopencm3/stm32/f4/syscfg.h b/include/libopencm3/stm32/f4/syscfg.h index b0d93f9..fbe647f 100644 --- a/include/libopencm3/stm32/f4/syscfg.h +++ b/include/libopencm3/stm32/f4/syscfg.h @@ -40,7 +40,7 @@ /* External interrupt configuration register 4 (SYSCFG_EXTICR4) */ #define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14) -#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) +#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) #endif diff --git a/include/libopencm3/stm32/f4/timer.h b/include/libopencm3/stm32/f4/timer.h index a76c7ef..6fe9e6a 100644 --- a/include/libopencm3/stm32/f4/timer.h +++ b/include/libopencm3/stm32/f4/timer.h @@ -22,33 +22,32 @@ #include - -/* +/* * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: * CNT, ARR, CCR1, CCR2, CCR3, CCR4 */ /* Timer 2/5 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) -#define TIM2_OR TIM_OR(TIM2) -#define TIM5_OR TIM_OR(TIM5) +#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM2_OR TIM_OR(TIM2) +#define TIM5_OR TIM_OR(TIM5) /* --- TIM2_OR values ---------------------------------------------------- */ /* MOE: Main output enable */ -#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10) -#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) -#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) -#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) -#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) +#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10) +#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) +#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) +#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) +#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) /* --- TIM5_OR values ---------------------------------------------------- */ /* MOE: Main output enable */ -#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) -#define TIM5_OR_TI4_RMP_LSI (0x1 << 6) -#define TIM5_OR_TI4_RMP_LSE (0x2 << 6) -#define TIM5_OR_TI4_RMP_RTC (0x3 << 6) -#define TIM5_OR_TI4_RMP_MASK (0x3 << 6) +#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) +#define TIM5_OR_TI4_RMP_LSI (0x1 << 6) +#define TIM5_OR_TI4_RMP_LSE (0x2 << 6) +#define TIM5_OR_TI4_RMP_RTC (0x3 << 6) +#define TIM5_OR_TI4_RMP_MASK (0x3 << 6) #endif diff --git a/include/libopencm3/stm32/f4/usart.h b/include/libopencm3/stm32/f4/usart.h index 5c4f939..d59f906 100644 --- a/include/libopencm3/stm32/f4/usart.h +++ b/include/libopencm3/stm32/f4/usart.h @@ -30,6 +30,6 @@ /* --- USART_CR3 values ---------------------------------------------------- */ /* ONEBIT: One sample bit method enable */ -#define USART_CR3_ONEBIT (1 << 11) +#define USART_CR3_ONEBIT (1 << 11) #endif -- cgit v1.2.3