From ec904f176b014b611efa3c3fe81dce4a74378b5a Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Wed, 29 Feb 2012 16:02:51 -0800 Subject: Cleaned up and streamlined DMA support for f1. Definitely needs a bunch of testing! --- include/libopencm3/stm32/f1/dma.h | 803 ++++++++++---------------------------- 1 file changed, 207 insertions(+), 596 deletions(-) (limited to 'include/libopencm3/stm32/f1') diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h index 6fe316e..6e9d5e2 100644 --- a/include/libopencm3/stm32/f1/dma.h +++ b/include/libopencm3/stm32/f1/dma.h @@ -2,6 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Piotr Esden-Tempski * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -41,615 +42,225 @@ #define DMA1_IFCR DMA_IFCR(DMA1) #define DMA2_IFCR DMA_IFCR(DMA2) -/* DMA channel 1 configuration register (DMAx_CCR1) */ -#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0) -#define DMA1_CCR1 DMA_CCR1(DMA1) -#define DMA2_CCR1 DMA_CCR1(DMA2) - -/* DMA channel 2 configuration register (DMAx_CCR2) */ -#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1) -#define DMA1_CCR2 DMA_CCR2(DMA1) -#define DMA2_CCR2 DMA_CCR2(DMA2) - -/* DMA channel 3 configuration register (DMAx_CCR3) */ -#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2) -#define DMA1_CCR3 DMA_CCR3(DMA1) -#define DMA2_CCR3 DMA_CCR3(DMA2) - -/* DMA channel 4 configuration register (DMAx_CCR4) */ -#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3) -#define DMA1_CCR4 DMA_CCR4(DMA1) -#define DMA2_CCR4 DMA_CCR4(DMA2) - -/* DMA channel 5 configuration register (DMAx_CCR5) */ -#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4) -#define DMA1_CCR5 DMA_CCR5(DMA1) -#define DMA2_CCR5 DMA_CCR5(DMA2) - -/* DMA channel 6 configuration register (DMAx_CCR6) */ -#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5) -#define DMA1_CCR6 DMA_CCR6(DMA1) - -/* DMA channel 7 configuration register (DMAx_CCR7) */ -#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6) -#define DMA1_CCR7 DMA_CCR7(DMA1) - -/* DMA channel 1 number of data register (DMAx_CNDTR1) */ -#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0) -#define DMA1_CNDTR1 DMA_CNDTR1(DMA1) -#define DMA2_CNDTR1 DMA_CNDTR1(DMA2) - -/* DMA channel 2 number of data register (DMAx_CNDTR2) */ -#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1) -#define DMA1_CNDTR2 DMA_CNDTR2(DMA1) -#define DMA2_CNDTR2 DMA_CNDTR2(DMA2) - -/* DMA channel 3 number of data register (DMAx_CNDTR3) */ -#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2) -#define DMA1_CNDTR3 DMA_CNDTR3(DMA1) -#define DMA2_CNDTR3 DMA_CNDTR3(DMA2) - -/* DMA channel 4 number of data register (DMAx_CNDTR4) */ -#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3) -#define DMA1_CNDTR4 DMA_CNDTR4(DMA1) -#define DMA2_CNDTR4 DMA_CNDTR4(DMA2) - -/* DMA channel 5 number of data register (DMAx_CNDTR5) */ -#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4) -#define DMA1_CNDTR5 DMA_CNDTR5(DMA1) -#define DMA2_CNDTR5 DMA_CNDTR5(DMA2) - -/* DMA channel 6 number of data register (DMAx_CNDTR6) */ -#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5) -#define DMA1_CNDTR6 DMA_CNDTR6(DMA1) - -/* DMA channel 7 number of data register (DMAx_CNDTR7) */ -#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6) -#define DMA1_CNDTR7 DMA_CNDTR7(DMA1) - -/* DMA channel 1 peripheral address register (DMAx_CPAR1) */ -#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0) -#define DMA1_CPAR1 DMA_CPAR1(DMA1) -#define DMA2_CPAR1 DMA_CPAR1(DMA2) - -/* DMA channel 2 peripheral address register (DMAx_CPAR2) */ -#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1) -#define DMA1_CPAR2 DMA_CPAR2(DMA1) -#define DMA2_CPAR2 DMA_CPAR2(DMA2) - -/* DMA channel 3 peripheral address register (DMAx_CPAR3) */ -#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2) -#define DMA1_CPAR3 DMA_CPAR3(DMA1) -#define DMA2_CPAR3 DMA_CPAR3(DMA2) - -/* DMA channel 4 peripheral address register (DMAx_CPAR4) */ -#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3) -#define DMA1_CPAR4 DMA_CPAR4(DMA1) -#define DMA2_CPAR4 DMA_CPAR4(DMA2) - -/* DMA channel 5 peripheral address register (DMAx_CPAR5) */ -#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4) -#define DMA1_CPAR5 DMA_CPAR5(DMA1) -#define DMA2_CPAR5 DMA_CPAR5(DMA2) - -/* DMA channel 6 peripheral address register (DMAx_CPAR6) */ -#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5) -#define DMA1_CPAR6 DMA_CPAR6(DMA1) - -/* DMA channel 7 peripheral address register (DMAx_CPAR7) */ -#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6) -#define DMA1_CPAR7 DMA_CPAR7(DMA1) - -/* DMA channel 1 memory address register (DMAx_CMAR1) */ -#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0) -#define DMA1_CMAR1 DMA_CMAR1(DMA1) -#define DMA2_CMAR1 DMA_CMAR1(DMA2) - -/* DMA channel 2 memory address register (DMAx_CMAR2) */ -#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1) -#define DMA1_CMAR2 DMA_CMAR2(DMA1) -#define DMA2_CMAR2 DMA_CMAR2(DMA2) - -/* DMA channel 3 memory address register (DMAx_CMAR3) */ -#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2) -#define DMA1_CMAR3 DMA_CMAR3(DMA1) -#define DMA2_CMAR3 DMA_CMAR3(DMA2) - -/* DMA channel 4 memory address register (DMAx_CMAR4) */ -#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3) -#define DMA1_CMAR4 DMA_CMAR4(DMA1) -#define DMA2_CMAR4 DMA_CMAR4(DMA2) - -/* DMA channel 5 memory address register (DMAx_CMAR5) */ -#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4) -#define DMA1_CMAR5 DMA_CMAR5(DMA1) -#define DMA2_CMAR5 DMA_CMAR5(DMA2) - -/* DMA channel 6 memory address register (DMAx_CMAR6) */ -#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5) -#define DMA1_CMAR6 DMA_CMAR6(DMA1) - -/* DMA channel 7 memory address register (DMAx_CMAR7) */ -#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6) -#define DMA1_CMAR7 DMA_CMAR7(DMA1) +/* DMA channel configuration register (DMAx_CCRy) */ +#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CCR(channel) DMA_CCR(DMA1, channel) +#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1) +#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2) +#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3) +#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4) +#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5) +#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6) +#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7) + +#define DMA2_CCR(channel) DMA_CCR(DMA2, channel) +#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1) +#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2) +#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3) +#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4) +#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) + +/* DMA number of data register (DMAx_CNDTRy) */ +#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) +#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1) +#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2) +#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3) +#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4) +#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5) +#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6) +#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7) + +#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel) +#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1) +#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2) +#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3) +#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4) +#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) + +/* DMA peripheral address register (DMAx_CPARy) */ +#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) +#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1) +#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2) +#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3) +#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4) +#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5) +#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6) +#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7) + +#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel) +#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1) +#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2) +#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3) +#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4) +#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5) + +/* DMA memory address register (DMAx_CMARy) */ + +#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) +#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1) +#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2) +#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3) +#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4) +#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5) +#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6) +#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7) + +#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel) +#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1) +#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2) +#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3) +#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4) +#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5) /* --- DMA_ISR values ------------------------------------------------------ */ -/* TEIF7: Channel 7 transfer error flag */ -#define DMA_ISR_TEIF7 (1 << 27) -/* HTIF7: Channel 7 half transfer flag */ -#define DMA_ISR_HTIF7 (1 << 26) -/* TCIF7: Channel 7 transfer complete flag */ -#define DMA_ISR_TCIF7 (1 << 25) -/* GIF7: Channel 7 global interrupt flag */ -#define DMA_ISR_GIF7 (1 << 24) -/* TEIF6: Channel 6 transfer error flag */ -#define DMA_ISR_TEIF6 (1 << 23) -/* HTIF6: Channel 6 half transfer flag */ -#define DMA_ISR_HTIF6 (1 << 22) -/* TCIF6: Channel 6 transfer complete flag */ -#define DMA_ISR_TCIF6 (1 << 21) -/* GIF6: Channel 6 global interrupt flag */ -#define DMA_ISR_GIF6 (1 << 20) -/* TEIF5: Channel 5 transfer error flag */ -#define DMA_ISR_TEIF5 (1 << 19) -/* HTIF5: Channel 5 half transfer flag */ -#define DMA_ISR_HTIF5 (1 << 18) -/* TCIF5: Channel 5 transfer complete flag */ -#define DMA_ISR_TCIF5 (1 << 17) -/* GIF5: Channel 5 global interrupt flag */ -#define DMA_ISR_GIF5 (1 << 16) -/* TEIF4: Channel 4 transfer error flag */ -#define DMA_ISR_TEIF4 (1 << 15) -/* HTIF4: Channel 4 half transfer flag */ -#define DMA_ISR_HTIF4 (1 << 14) -/* TCIF4: Channel 4 transfer complete flag */ -#define DMA_ISR_TCIF4 (1 << 13) -/* GIF4: Channel 4 global interrupt flag */ -#define DMA_ISR_GIF4 (1 << 12) -/* TEIF3: Channel 3 transfer error flag */ -#define DMA_ISR_TEIF3 (1 << 11) -/* HTIF3: Channel 3 half transfer flag */ -#define DMA_ISR_HTIF3 (1 << 10) -/* TCIF3: Channel 3 transfer complete flag */ -#define DMA_ISR_TCIF3 (1 << 9) -/* GIF3: Channel 3 global interrupt flag */ -#define DMA_ISR_GIF3 (1 << 8) -/* TEIF2: Channel 2 transfer error flag */ -#define DMA_ISR_TEIF2 (1 << 7) -/* HTIF2: Channel 23 half transfer flag */ -#define DMA_ISR_HTIF2 (1 << 6) -/* TCIF2: Channel 2 transfer complete flag */ -#define DMA_ISR_TCIF2 (1 << 5) -/* GIF2: Channel 2 global interrupt flag */ -#define DMA_ISR_GIF2 (1 << 4) -/* TEIF1: Channel 1 transfer error flag */ -#define DMA_ISR_TEIF1 (1 << 3) -/* HTIF1: Channel 1 half transfer flag */ -#define DMA_ISR_HTIF1 (1 << 2) -/* TCIF1: Channel 1 transfer complete flag */ -#define DMA_ISR_TCIF1 (1 << 1) -/* GIF1: Channel 1 global interrupt flag */ -#define DMA_ISR_GIF1 (1 << 0) +/* TEIF: Transfer error interrupt flag */ +#define DMA_ISR_TEIF_BIT (1 << 3) +#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF << (4 * (channel) -1)) + +#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) +#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) +#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3) +#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4) +#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5) +#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6) +#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) + +/* HTIF: Half transfer interrupt flag */ +#define DMA_ISR_HTIF_BIT (1 << 2) +#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF << (4 * (channel) -1)) + +#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) +#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) +#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3) +#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4) +#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5) +#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6) +#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) + +/* TCIF: Transfer complete interrupt flag */ +#define DMA_ISR_TCIF_BIT (1 << 1) +#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF << (4 * (channel) -1)) + +#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) +#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) +#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3) +#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4) +#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5) +#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6) +#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7) + +/* GIF: Global interrupt flag */ +#define DMA_ISR_GIF_BIT (1 << 0) +#define DMA_ISR_GIF(channel) (DMA_ISR_GIF << (4 * (channel) -1)) + +#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) +#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) +#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3) +#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4) +#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5) +#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6) +#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7) /* --- DMA_IFCR values ----------------------------------------------------- */ -/* CTEIF7: Channel 7 transfer error clear */ -#define DMA_IFCR_CTEIF7 (1 << 27) -/* CHTIF7: Channel 7 half transfer clear */ -#define DMA_IFCR_CHTIF7 (1 << 26) -/* CTCIF7: Channel 7 transfer complete clear */ -#define DMA_IFCR_CTCIF7 (1 << 25) -/* CGIF7: Channel 7 global interrupt clear */ -#define DMA_IFCR_CGIF7 (1 << 24) -/* CTEIF6: Channel 6 transfer error clear */ -#define DMA_IFCR_CTEIF6 (1 << 23) -/* CHTIF6: Channel 6 half transfer clear */ -#define DMA_IFCR_CHTIF6 (1 << 22) -/* CTCIF6: Channel 6 transfer complete clear */ -#define DMA_IFCR_CTCIF6 (1 << 21) -/* CGIF6: Channel 6 global interrupt clear */ -#define DMA_IFCR_CGIF6 (1 << 20) -/* CTEIF5: Channel 5 transfer error clear */ -#define DMA_IFCR_CTEIF5 (1 << 19) -/* CHTIF5: Channel 5 half transfer clear */ -#define DMA_IFCR_CHTIF5 (1 << 18) -/* CTCIF5: Channel 5 transfer complete clear */ -#define DMA_IFCR_CTCIF5 (1 << 17) -/* CGIF5: Channel 5 global interrupt clear */ -#define DMA_IFCR_CGIF5 (1 << 16) -/* CTEIF4: Channel 4 transfer error clear */ -#define DMA_IFCR_CTEIF4 (1 << 15) -/* CHTIF4: Channel 4 half transfer clear */ -#define DMA_IFCR_CHTIF4 (1 << 14) -/* CTCIF4: Channel 4 transfer complete clear */ -#define DMA_IFCR_CTCIF4 (1 << 13) -/* CGIF4: Channel 4 global interrupt clear */ -#define DMA_IFCR_CGIF4 (1 << 12) -/* CTEIF3: Channel 3 transfer error clear */ -#define DMA_IFCR_CTEIF3 (1 << 11) -/* CHTIF3: Channel 3 half transfer clear */ -#define DMA_IFCR_CHTIF3 (1 << 10) -/* CTCIF3: Channel 3 transfer complete clear */ -#define DMA_IFCR_CTCIF3 (1 << 9) -/* CGIF3: Channel 3 global interrupt clear */ -#define DMA_IFCR_CGIF3 (1 << 8) -/* CTEIF2: Channel 2 transfer error clear */ -#define DMA_IFCR_CTEIF2 (1 << 7) -/* CHTIF2: Channel 2 half transfer clear */ -#define DMA_IFCR_CHTIF2 (1 << 6) -/* CTCIF2: Channel 2 transfer complete clear */ -#define DMA_IFCR_CTCIF2 (1 << 5) -/* CGIF2: Channel 2 global interrupt clear */ -#define DMA_IFCR_CGIF2 (1 << 4) -/* CTEIF1: Channel 1 transfer error clear */ -#define DMA_IFCR_CTEIF1 (1 << 3) -/* CHTIF1: Channel 1 half transfer clear */ -#define DMA_IFCR_CHTIF1 (1 << 2) -/* CTCIF1: Channel 1 transfer complete clear */ -#define DMA_IFCR_CTCIF1 (1 << 1) -/* CGIF1: Channel 1 global interrupt clear */ -#define DMA_IFCR_CGIF1 (1 << 0) - -/* --- DMA_CCR1 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR1_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR1_PL_LSB 12 -#define DMA_CCR1_PL_LOW 0x0 -#define DMA_CCR1_PL_MEDIUM 0x1 -#define DMA_CCR1_PL_HIGH 0x2 -#define DMA_CCR1_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR1_MSIZE_LSB 10 -#define DMA_CCR1_MSIZE_8BIT 0x0 -#define DMA_CCR1_MSIZE_16BIT 0x1 -#define DMA_CCR1_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR1_PSIZE_LSB 8 -#define DMA_CCR1_PSIZE_8BIT 0x0 -#define DMA_CCR1_PSIZE_16BIT 0x1 -#define DMA_CCR1_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR1_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR1_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR1_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR1_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR1_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR1_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR1_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR1_EN (1 << 0) - -/* --- DMA_CCR2 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR2_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR2_PL_LSB 12 -#define DMA_CCR2_PL_LOW 0x0 -#define DMA_CCR2_PL_MEDIUM 0x1 -#define DMA_CCR2_PL_HIGH 0x2 -#define DMA_CCR2_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR2_MSIZE_LSB 10 -#define DMA_CCR2_MSIZE_8BIT 0x0 -#define DMA_CCR2_MSIZE_16BIT 0x1 -#define DMA_CCR2_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR2_PSIZE_LSB 8 -#define DMA_CCR2_PSIZE_8BIT 0x0 -#define DMA_CCR2_PSIZE_16BIT 0x1 -#define DMA_CCR2_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR2_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR2_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR2_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR2_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR2_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR2_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR2_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR2_EN (1 << 0) - -/* --- DMA_CCR3 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR3_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR3_PL_LSB 12 -#define DMA_CCR3_PL_LOW 0x0 -#define DMA_CCR3_PL_MEDIUM 0x1 -#define DMA_CCR3_PL_HIGH 0x2 -#define DMA_CCR3_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR3_MSIZE_LSB 10 -#define DMA_CCR3_MSIZE_8BIT 0x0 -#define DMA_CCR31_MSIZE_16BIT 0x1 -#define DMA_CCR3_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR3_PSIZE_LSB 8 -#define DMA_CCR3_PSIZE_8BIT 0x0 -#define DMA_CCR3_PSIZE_16BIT 0x1 -#define DMA_CCR3_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR3_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR3_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR3_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR3_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR3_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR3_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR3_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR3_EN (1 << 0) - -/* --- DMA_CCR4 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR4_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR4_PL_LSB 12 -#define DMA_CCR4_PL_LOW 0x0 -#define DMA_CCR4_PL_MEDIUM 0x1 -#define DMA_CCR4_PL_HIGH 0x2 -#define DMA_CCR4_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR4_MSIZE_LSB 10 -#define DMA_CCR4_MSIZE_8BIT 0x0 -#define DMA_CCR4_MSIZE_16BIT 0x1 -#define DMA_CCR4_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR4_PSIZE_LSB 8 -#define DMA_CCR4_PSIZE_8BIT 0x0 -#define DMA_CCR4_PSIZE_16BIT 0x1 -#define DMA_CCR4_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR4_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR4_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR4_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR4_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR4_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR4_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR4_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR4_EN (1 << 0) - -/* --- DMA_CCR5 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR5_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR5_PL_LSB 12 -#define DMA_CCR5_PL_LOW 0x0 -#define DMA_CCR5_PL_MEDIUM 0x1 -#define DMA_CCR5_PL_HIGH 0x2 -#define DMA_CCR5_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR5_MSIZE_LSB 10 -#define DMA_CCR5_MSIZE_8BIT 0x0 -#define DMA_CCR5_MSIZE_16BIT 0x1 -#define DMA_CCR5_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR5_PSIZE_LSB 8 -#define DMA_CCR5_PSIZE_8BIT 0x0 -#define DMA_CCR5_PSIZE_16BIT 0x1 -#define DMA_CCR5_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR5_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR5_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR5_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR5_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR5_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR5_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR5_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR5_EN (1 << 0) - -/* --- DMA_CCR6 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR6_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR6_PL_LSB 12 -#define DMA_CCR6_PL_LOW 0x0 -#define DMA_CCR6_PL_MEDIUM 0x1 -#define DMA_CCR6_PL_HIGH 0x2 -#define DMA_CCR6_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR6_MSIZE_LSB 10 -#define DMA_CCR6_MSIZE_8BIT 0x0 -#define DMA_CCR6_MSIZE_16BIT 0x1 -#define DMA_CCR6_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR6_PSIZE_LSB 8 -#define DMA_CCR6_PSIZE_8BIT 0x0 -#define DMA_CCR6_PSIZE_16BIT 0x1 -#define DMA_CCR6_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR6_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR6_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR6_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR6_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR6_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR6_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR6_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR6_EN (1 << 0) - -/* --- DMA_CCR7 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR7_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR7_PL_LSB 12 -#define DMA_CCR7_PL_LOW 0x0 -#define DMA_CCR7_PL_MEDIUM 0x1 -#define DMA_CCR7_PL_HIGH 0x2 -#define DMA_CCR7_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR7_MSIZE_LSB 10 -#define DMA_CCR7_MSIZE_8BIT 0x0 -#define DMA_CCR7_MSIZE_16BIT 0x1 -#define DMA_CCR7_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR7_PSIZE_LSB 8 -#define DMA_CCR7_PSIZE_8BIT 0x0 -#define DMA_CCR7_PSIZE_16BIT 0x1 -#define DMA_CCR7_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR7_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR7_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR7_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR7_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR7_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR7_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR7_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR7_EN (1 << 0) +/* CTEIF: Transfer error clear */ +#define DMA_IFCR_CTEIF_BIT (1 << 3) +#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * (channel) -1)) + +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3) +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4) +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5) +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6) +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) + +/* CHTIF: Half transfer clear */ +#define DMA_IFCR_CHTIF_BIT (1 << 2) +#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * (channel) -1)) + +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3) +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4) +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5) +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6) +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) + +/* CTCIF: Transfer complete clear */ +#define DMA_IFCR_CTCIF_BIT (1 << 1) +#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * (channel) -1)) + +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3) +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4) +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5) +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6) +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) + +/* CGIF: Global interrupt clear */ +#define DMA_IFCR_CGIF_BIT (1 << 0) +#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * (channel) -1)) + +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3) +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4) +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5) +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6) +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7) + +/* Clear interrupts mask */ +#define DMA_IFCR_CIF_BIT 0xF +#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (4 * ((channel) - 1))) + +#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) +#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) +#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3) +#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4) +#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5) +#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6) +#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7) /* --- DMA_CCRx generic values --------------------------------------------- */ /* MEM2MEM: Memory to memory mode */ -#define DMA_CCR_MEM2MEM (1 << 14) +#define DMA_CCR_MEM2MEM (1 << 14) /* PL[13:12]: Channel priority level */ -#define DMA_CCR_PL_LSB 12 -#define DMA_CCR_PL_LOW 0x0 -#define DMA_CCR_PL_MEDIUM 0x1 -#define DMA_CCR_PL_HIGH 0x2 -#define DMA_CCR_PL_VERY_HIGH 0x3 +#define DMA_CCR_PL_LOW (0x0 << 12) +#define DMA_CCR_PL_MEDIUM (0x1 << 12) +#define DMA_CCR_PL_HIGH (0x2 << 12) +#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) +#define DMA_CCR_PL_MASK (0x3 << 12) +#define DMA_CCR_PL_SHIFT 12 /* MSIZE[11:10]: Memory size */ -#define DMA_CCR_MSIZE_LSB 10 -#define DMA_CCR_MSIZE_8BIT 0x0 -#define DMA_CCR_MSIZE_16BIT 0x1 -#define DMA_CCR_MSIZE_32BIT 0x2 +#define DMA_CCR_MSIZE_8BIT (0x0 << 10) +#define DMA_CCR_MSIZE_16BIT (0x1 << 10) +#define DMA_CCR_MSIZE_32BIT (0x2 << 10) +#define DMA_CCR_MSIZE_MASK (0x2 << 10) +#define DMA_CCR_MSIZE_SHIFT 10 /* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR_PSIZE_LSB 8 -#define DMA_CCR_PSIZE_8BIT 0x0 -#define DMA_CCR_PSIZE_16BIT 0x1 -#define DMA_CCR_PSIZE_32BIT 0x2 +#define DMA_CCR_PSIZE_8BIT (0x0 << 10) +#define DMA_CCR_PSIZE_16BIT (0x1 << 10) +#define DMA_CCR_PSIZE_32BIT (0x2 << 10) +#define DMA_CCR_PSIZE_MASK (0x2 << 10) +#define DMA_CCR_PSIZE_SHIFT 8 /* MINC: Memory increment mode */ #define DMA_CCR_MINC (1 << 7) @@ -700,9 +311,9 @@ /* --- function prototypes ------------------------------------------------- */ void dma_enable_mem2mem_mode(u32 dma, u8 channel); -void dma_set_priority(u32 dma, u8 channel, u8 prio); -void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size); -void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size); +void dma_set_priority(u32 dma, u8 channel, u32 prio); +void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size); +void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size); void dma_enable_memory_increment_mode(u32 dma, u8 channel); void dma_enable_peripheral_increment_mode(u32 dma, u8 channel); void dma_enable_circular_mode(u32 dma, u8 channel); -- cgit v1.2.3