From 416f633dbb5bdf8a7ef99e52f9de1142d126c8e5 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 5 Jun 2012 08:03:34 -0600 Subject: fixed some column alignment to conform with libopencm3 precedent --- include/libopencm3/lpc43xx/ssp.h | 102 +++++++++++++++++++-------------------- 1 file changed, 51 insertions(+), 51 deletions(-) (limited to 'include/libopencm3/lpc43xx/ssp.h') diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h index 6a1510c..338fd88 100644 --- a/include/libopencm3/lpc43xx/ssp.h +++ b/include/libopencm3/lpc43xx/ssp.h @@ -26,67 +26,67 @@ /* --- Convenience macros -------------------------------------------------- */ /* SSP port base addresses (for convenience) */ -#define SSP0 SSP0_BASE -#define SSP1 SSP1_BASE +#define SSP0 SSP0_BASE +#define SSP1 SSP1_BASE /* --- SSP registers ------------------------------------------------------- */ /* Control Register 0 */ -#define SSP_CR0(port) MMIO32(port + 0x000) -#define SSP0_CR0 SSP_CR0(SSP0) -#define SSP1_CR0 SSP_CR0(SSP1) +#define SSP_CR0(port) MMIO32(port + 0x000) +#define SSP0_CR0 SSP_CR0(SSP0) +#define SSP1_CR0 SSP_CR0(SSP1) /* Control Register 1 */ -#define SSP_CR1(port) MMIO32(port + 0x004) -#define SSP0_CR1 SSP_CR1(SSP0) -#define SSP1_CR1 SSP_CR1(SSP1) +#define SSP_CR1(port) MMIO32(port + 0x004) +#define SSP0_CR1 SSP_CR1(SSP0) +#define SSP1_CR1 SSP_CR1(SSP1) /* Data Register */ -#define SSP_DR(port) MMIO32(port + 0x008) -#define SSP0_DR SSP_DR(SSP0) -#define SSP1_DR SSP_DR(SSP1) +#define SSP_DR(port) MMIO32(port + 0x008) +#define SSP0_DR SSP_DR(SSP0) +#define SSP1_DR SSP_DR(SSP1) /* Status Register */ -#define SSP_SR(port) MMIO32(port + 0x00C) -#define SSP0_SR SSP_SR(SSP0) -#define SSP1_SR SSP_SR(SSP1) +#define SSP_SR(port) MMIO32(port + 0x00C) +#define SSP0_SR SSP_SR(SSP0) +#define SSP1_SR SSP_SR(SSP1) -#define SSP_SR_TFE BIT0 -#define SSP_SR_TNF BIT1 -#define SSP_SR_RNE BIT2 -#define SSP_SR_RFF BIT3 -#define SSP_SR_BSY BIT4 +#define SSP_SR_TFE BIT0 +#define SSP_SR_TNF BIT1 +#define SSP_SR_RNE BIT2 +#define SSP_SR_RFF BIT3 +#define SSP_SR_BSY BIT4 /* Clock Prescale Register */ -#define SSP_CPSR(port) MMIO32(port + 0x010) -#define SSP0_CPSR SSP_CPSR(SSP0) -#define SSP1_CPSR SSP_CPSR(SSP1) +#define SSP_CPSR(port) MMIO32(port + 0x010) +#define SSP0_CPSR SSP_CPSR(SSP0) +#define SSP1_CPSR SSP_CPSR(SSP1) /* Interrupt Mask Set and Clear Register */ -#define SSP_IMSC(port) MMIO32(port + 0x014) -#define SSP0_IMSC SSP_IMSC(SSP0) -#define SSP1_IMSC SSP_IMSC(SSP1) +#define SSP_IMSC(port) MMIO32(port + 0x014) +#define SSP0_IMSC SSP_IMSC(SSP0) +#define SSP1_IMSC SSP_IMSC(SSP1) /* Raw Interrupt Status Register */ -#define SSP_RIS(port) MMIO32(port + 0x018) -#define SSP0_RIS SSP_RIS(SSP0) -#define SSP1_RIS SSP_RIS(SSP1) +#define SSP_RIS(port) MMIO32(port + 0x018) +#define SSP0_RIS SSP_RIS(SSP0) +#define SSP1_RIS SSP_RIS(SSP1) /* Masked Interrupt Status Register */ -#define SSP_MIS(port) MMIO32(port + 0x01C) -#define SSP0_MIS SSP_MIS(SSP0) -#define SSP1_MIS SSP_MIS(SSP1) +#define SSP_MIS(port) MMIO32(port + 0x01C) +#define SSP0_MIS SSP_MIS(SSP0) +#define SSP1_MIS SSP_MIS(SSP1) /* SSPICR Interrupt Clear Register */ -#define SSP_ICR(port) MMIO32(port + 0x020) -#define SSP0_ICR SSP_ICR(SSP0) -#define SSP1_ICR SSP_ICR(SSP1) +#define SSP_ICR(port) MMIO32(port + 0x020) +#define SSP0_ICR SSP_ICR(SSP0) +#define SSP1_ICR SSP_ICR(SSP1) /* SSP1 DMA control register */ -#define SSP_DMACR(port) MMIO32(port + 0x024) -#define SSP0_DMACR SSP_DMACR(SSP0) -#define SSP1_DMACR SSP_DMACR(SSP1) +#define SSP_DMACR(port) MMIO32(port + 0x024) +#define SSP0_DMACR SSP_DMACR(SSP0) +#define SSP1_DMACR SSP_DMACR(SSP1) typedef enum { SSP0_NUM = 0x0, @@ -115,17 +115,17 @@ typedef enum { /* SSP Frame Format/Type Bits 4 & 5 */ typedef enum { - SSP_FRAME_SPI = 0x00, - SSP_FRAME_TI = BIT4, - SSP_FRAM_MICROWIRE = BIT5 + SSP_FRAME_SPI = 0x00, + SSP_FRAME_TI = BIT4, + SSP_FRAM_MICROWIRE = BIT5 } ssp_frame_format_t; /* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */ typedef enum { - SSP_CPOL_0_CPHA_0 = 0x0, - SSP_CPOL_1_CPHA_0 = BIT6, - SSP_CPOL_0_CPHA_1 = BIT7, - SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) + SSP_CPOL_0_CPHA_0 = 0x0, + SSP_CPOL_1_CPHA_0 = BIT6, + SSP_CPOL_0_CPHA_1 = BIT7, + SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) } ssp_cpol_cpha_t; /* @@ -133,8 +133,8 @@ typedef enum { */ /* SSP Mode Bit0 */ typedef enum { - SSP_MODE_NORMAL = 0x0, - SSP_MODE_LOOPBACK = BIT0 + SSP_MODE_NORMAL = 0x0, + SSP_MODE_LOOPBACK = BIT0 } ssp_mode_t; /* SSP Enable Bit1 */ @@ -142,8 +142,8 @@ typedef enum { /* SSP Master/Slave Mode Bit2 */ typedef enum { - SSP_MASTER = 0x0, - SSP_SLAVE = BIT2 + SSP_MASTER = 0x0, + SSP_SLAVE = BIT2 } ssp_master_slave_t; /* @@ -153,13 +153,13 @@ typedef enum { * transmit data line (MISO). */ typedef enum { - SSP_SLAVE_OUT_ENABLE = 0x0, - SSP_SLAVE_OUT_DISABLE = BIT3 + SSP_SLAVE_OUT_ENABLE = 0x0, + SSP_SLAVE_OUT_DISABLE = BIT3 } ssp_slave_option_t; /* This option is relevant only in slave mode */ void ssp_disable(ssp_num_t ssp_num); -void ssp_init( ssp_num_t ssp_num, +void ssp_init(ssp_num_t ssp_num, ssp_datasize_t data_size, ssp_frame_format_t frame_format, ssp_cpol_cpha_t cpol_cpha_format, -- cgit v1.2.3