From 98bb0b5c9115e7b12eee3c0f4a18fefcf2ebf515 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Mon, 28 May 2012 16:52:12 -0600 Subject: started nvic.h with some interrupt IDs --- include/libopencm3/lpc43xx/nvic.h | 94 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 include/libopencm3/lpc43xx/nvic.h (limited to 'include/libopencm3/lpc43xx/nvic.h') diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h new file mode 100644 index 0000000..336eab8 --- /dev/null +++ b/include/libopencm3/lpc43xx/nvic.h @@ -0,0 +1,94 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_NVIC_H +#define LPC43XX_NVIC_H + +#include +#include + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M4 System Interrupts */ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 + +/* LPC43xx M4 specific user interrupts */ +#define NVIC_M4_DAC_IRQ 0 +#define NVIC_M4_M0CORE_IRQ 1 +#define NVIC_M4_DMA_IRQ 2 +#define NVIC_M4_ETHERNET_IRQ 5 +#define NVIC_M4_SDIO_IRQ 6 +#define NVIC_M4_LCD_IRQ 7 +#define NVIC_M4_USB0_IRQ 8 +#define NVIC_M4_USB1_IRQ 9 +#define NVIC_M4_SCT_IRQ 10 +#define NVIC_M4_RITIMER_IRQ 11 +#define NVIC_M4_TIMER0_IRQ 12 +#define NVIC_M4_TIMER1_IRQ 13 +#define NVIC_M4_TIMER2_IRQ 14 +#define NVIC_M4_TIMER3_IRQ 15 +#define NVIC_M4_MCPWM_IRQ 16 +#define NVIC_M4_ADC0_IRQ 17 +#define NVIC_M4_I2C0_IRQ 18 +#define NVIC_M4_I2C1_IRQ 19 +#define NVIC_M4_SPI_IRQ 20 +#define NVIC_M4_ADC1_IRQ 21 +#define NVIC_M4_SSP0_IRQ 22 +#define NVIC_M4_SSP1_IRQ 23 +#define NVIC_M4_USART0_IRQ 24 +#define NVIC_M4_UART1_IRQ 25 +#define NVIC_M4_USART2_IRQ 26 +#define NVIC_M4_USART3_IRQ 27 +#define NVIC_M4_I2S0_IRQ 28 +#define NVIC_M4_I2S1_IRQ 29 +#define NVIC_M4_SPIFI_IRQ 30 +#define NVIC_M4_SGPIO_IRQ 31 +#define NVIC_M4_PIN_INT0_IRQ 32 +#define NVIC_M4_PIN_INT1_IRQ 33 +#define NVIC_M4_PIN_INT2_IRQ 34 +#define NVIC_M4_PIN_INT3_IRQ 35 +#define NVIC_M4_PIN_INT4_IRQ 36 +#define NVIC_M4_PIN_INT5_IRQ 37 +#define NVIC_M4_PIN_INT6_IRQ 38 +#define NVIC_M4_PIN_INT7_IRQ 39 +#define NVIC_M4_GINT0_IRQ 40 +#define NVIC_M4_GINT1_IRQ 41 +#define NVIC_M4_EVENTROUTER_IRQ 42 +#define NVIC_M4_C_CAN1_IRQ 43 +#define NVIC_M4_ATIMER_IRQ 46 +#define NVIC_M4_RTC_IRQ 47 +#define NVIC_M4_WWDT_IRQ 49 +#define NVIC_M4_C_CAN0_IRQ 51 +#define NVIC_M4_QEI_IRQ 52 + +/* LPC43xx M0 specific user interrupts */ +//TODO + +#endif -- cgit v1.2.3 From 8d97dbc7c31d814e521ad9792fcf1914543288bf Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Sat, 9 Jun 2012 18:27:42 +0200 Subject: Work on scs.h register and also nvic.h. ARM Interrupt API (see nvic.h). ARM SysTick API (see systick.h). Example using both Interrupt and SysTick and blink LED1/2/3 see systickdemo.c. --- examples/lpc43xx/hackrf-jellybean/systick/Makefile | 24 ++ examples/lpc43xx/hackrf-jellybean/systick/README | 8 + .../lpc43xx/hackrf-jellybean/systick/systickdemo.c | 184 ++++++++++++++++ include/libopencm3/cm3/scs.h | 242 +++++++++++++++++++++ include/libopencm3/lpc43xx/nvic.h | 53 +++++ include/libopencm3/lpc43xx/systick.h | 84 +++++++ lib/lpc43xx/Makefile | 2 +- lib/lpc43xx/nvic.c | 76 +++++++ lib/lpc43xx/systick.c | 69 ++++++ 9 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/README create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c create mode 100644 include/libopencm3/lpc43xx/systick.h create mode 100644 lib/lpc43xx/nvic.c create mode 100644 lib/lpc43xx/systick.c (limited to 'include/libopencm3/lpc43xx/nvic.h') diff --git a/examples/lpc43xx/hackrf-jellybean/systick/Makefile b/examples/lpc43xx/hackrf-jellybean/systick/Makefile new file mode 100644 index 0000000..93b471e --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2012 Benjamin Vernoux +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = systickdemo + +LDSCRIPT = ../jellybean-lpc4330.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/systick/README b/examples/lpc43xx/hackrf-jellybean/systick/README new file mode 100644 index 0000000..8c32cdc --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/README @@ -0,0 +1,8 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This program exercises the SysTick Interrupt of ARM CortexM4 on Jellybean's LPC43xx. +It also enable Cycle Counter to be used for accurate delay independant from Clock Frequency. +The Demo Use Cycle Counter and SysTick Interrupt to compute number of cycles executed per second. +The result is LED1/2 & 3 Blink with an accurate 1s Period (using SysTick) (Checked visualy and with Oscilloscope). diff --git a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c new file mode 100644 index 0000000..66c8e06 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c @@ -0,0 +1,184 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include "../jellybean_conf.h" + +/* Global counter incremented by SysTick Interrupt each millisecond */ +volatile u32 g_ulSysTickCount; +u32 g_NbCyclePerSecond; + +void gpio_setup(void) +{ + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ +} + +void systick_setup(void) +{ + u32 systick_reload_val; + g_ulSysTickCount = 0; + + /* Disable IRQ globally */ + asm volatile ("cpsid i"); + + /* Set processor Clock as Source Clock */ + systick_set_clocksource(STK_CTRL_CLKSOURCE); + + /* Get SysTick calibration value to obtain by default 1 tick = 10ms */ + systick_reload_val = systick_get_calib(); + /* + * Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*8=96MHz + * Fix the Calibration value bu multiplication by 8 + */ + systick_reload_val = (systick_reload_val*8); + + /* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */ + systick_reload_val = systick_reload_val/10; + systick_set_reload(systick_reload_val); + + systick_interrupt_enable(); + + /* Start counting. */ + systick_counter_enable(); + + /* Set SysTick Priority to maximum */ + nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF); + + /* Enable IRQ globally */ + asm volatile ("cpsie i"); +} + +void scs_dwt_cycle_counter_enabled(void) +{ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA; +} + +u32 sys_tick_get_time_ms(void) +{ + return g_ulSysTickCount; +} + +u32 sys_tick_delta_time_ms(u32 start, u32 end) +{ + #define MAX_T_U32 ((2^32)-1) + u32 diff; + + if(end > start) + { + diff=end-start; + }else + { + diff=MAX_T_U32-(start-end)+1; + } + + return diff; +} + +void sys_tick_wait_time_ms(u32 wait_ms) +{ + u32 start, end; + u32 tickms; + + start = sys_tick_get_time_ms(); + + do + { + end = sys_tick_get_time_ms(); + tickms = sys_tick_delta_time_ms(start, end); + }while(tickms < wait_ms); +} + +/* Called each 1ms/1000Hz by interrupt + 1) Count the number of cycle per second. + 2) Increment g_ulSysTickCount counter. +*/ +void sys_tick_handler(void) +{ + if(g_ulSysTickCount==0) + { + /* Clear Cycle Counter*/ + SCS_DWT_CYCCNT = 0; + }else if(g_ulSysTickCount==1000) + { + /* Capture number of cycle elapsed during 1 second */ + g_NbCyclePerSecond = SCS_DWT_CYCCNT; + } + + g_ulSysTickCount++; +} + +int main(void) +{ + systick_setup(); + + gpio_setup(); + + /* SCS & Cycle Counter enabled (used to count number of cycles executed per second see g_NbCyclePerSecond */ + scs_dwt_cycle_counter_enabled(); + + while (1) + { + gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ + + sys_tick_wait_time_ms(500); + + gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */ + + sys_tick_wait_time_ms(500); + } + + return 0; +} diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h index 033ec73..fff4a1b 100644 --- a/include/libopencm3/cm3/scs.h +++ b/include/libopencm3/cm3/scs.h @@ -2,6 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -20,9 +21,85 @@ #ifndef LIBOPENCM3_CM3_SCS_H #define LIBOPENCM3_CM3_SCS_H +/* + * All the definition hereafter are generic for CortexMx ARMv7-M + * See ARM document "ARMv7-M Architecture Reference Manual" for more details. + * See also ARM document "ARM Compiler toolchain Developing Software for ARM Processors" for details on System Timer/SysTick. + */ + +/* + * The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for + * configuration, status reporting and control. The SCS registers divide into the following groups: + * - system control and identification + * - the CPUID processor identification space + * - system configuration and status + * - fault reporting + * - a system timer, SysTick + * - a Nested Vectored Interrupt Controller (NVIC) + * - a Protected Memory System Architecture (PMSA) + * - system debug. + */ + +/* System Handler Priority 8 bits Registers, SHPR1/2/3 */ +/* Note: 12 8bit Registers */ +#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id) + +/* + * Debug Halting Control and Status Register (DHCSR). + * + * Purpose Controls halting debug. + * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when the system + * is running with halting debug enabled is UNPREDICTABLE. + * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running when S_HALT is set to 0. + * - When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this register. + * - For more information about the use of DHCSR see Debug stepping on + * page C1-824. + * Configurations Always implemented. + */ +/* SCS_DHCSR register */ #define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0) +/* + * Debug Core Register Selector Register (DCRSR). + * + * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core registers, + * special-purpose registers, and Floating-point extension registers. A write to DCRSR + * specifies the register to transfer, whether the transfer is a read or a write, and starts + * the transfer. + * Usage constraints: Only accessible in Debug state. + * Configurations Always implemented. + * + */ +/* SCS_DCRS register */ #define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4) +/* + * Debug Core Register Data Register (DCRDR) + * + * Purpose With the DCRSR, see Debug Core Register Selector Register, + * the DCRDR provides debug access to the ARM core registers, + * special-purpose registers, and Floating-point extension registers. The + * DCRDR is the data register for these accesses. + * - Used on its own, the DCRDR provides a message passing resource between + * an external debugger and a debug agent running on the processor. + * Note: + * The architecture does not define any handshaking mechanism for this use of DCRDR. + * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to + * particular transfers using the DCRSR and DCRDR. + * Configurations Always implemented. + * + */ +/* SCS_DCRDR register */ #define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8) +/* + * Debug Exception and Monitor Control Register (DEMCR). + * + * Purpose Manages vector catch behavior and DebugMonitor handling when debugging. + * Usage constraints: + * - Bits [23:16] provide DebugMonitor exception control. + * - Bits [15:0] provide Debug state, halting debug, control. + * Configurations Always implemented. + * + */ +/* SCS_DEMCR register */ #define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC) /* Debug Halting Control and Status Register (DHCSR) */ @@ -64,4 +141,169 @@ /* Bits 3:1 - Reserved */ #define SCS_DEMCR_VC_CORERESET (1 << 0) +/* + * System Control Space (SCS) => System timer register support in the SCS. + * To configure SysTick, load the interval required between SysTick events to the SysTick Reload + * Value register. The timer interrupt, or COUNTFLAG bit in the SysTick Control and Status + * register, is activated on the transition from 1 to 0, therefore it activates every n+1 clock ticks. + * If you require a period of 100, write 99 to the SysTick Reload Value register. The SysTick Reload + * Value register supports values between 0x1 and 0x00FFFFFF. + * + * If you want to use SysTick to generate an event at a timed interval, for example 1ms, you can + * use the SysTick Calibration Value Register to scale your value for the Reload register. The + * SysTick Calibration Value Register is a read-only register that contains the number of pulses for + * a period of 10ms, in the TENMS field, bits[23:0]. + * + * This register also has a SKEW bit. Bit[30] == 1 indicates that the calibration for 10ms in the + * TENMS section is not exactly 10ms due to clock frequency. Bit[31] == 1 indicates that the + * reference clock is not provided. + */ +/* + * SysTick Control and Status Register (CSR). + * Purpose Controls the system timer and provides status data. + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. +*/ +#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10) + +/* SysTick Reload Value Register (CVR). + * Purpose Reads or clears the current counter value. + * Usage constraints: + * - Any write to the register clears the register to zero. + * - The counter does not provide read-modify-write protection. + * - Unsupported bits are read as zero + * Configurations Always implemented. + */ +#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14) + +/* SysTick Current Value Register (RVR). + * Purpose Holds the reload value of the SYST_CVR. + * Usage constraints There are no usage constraints. + * Configurations Always implemented. + */ +#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18) + +/* + * SysTick Calibration value Register(Read Only) (CALIB) + * Purpose Reads the calibration value and parameters for SysTick. + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. + */ +#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C) + +/* --- SCS_SYST_CSR values ----------------------------------------------- */ +/* Counter is operating. */ +#define SCS_SYST_CSR_ENABLE (BIT0) +/* Count to 0 changes the SysTick exception status to pending. */ +#define SCS_SYST_CSR_TICKINT (BIT1) +/* SysTick uses the processor clock. */ +#define SCS_SYST_CSR_CLKSOURCE (BIT2) +/* + * Indicates whether the counter has counted to 0 since the last read of this register: + * 0 = Timer has not counted to 0 + * 1 = Timer has counted to 0. + */ +#define SCS_SYST_CSR_COUNTFLAG (BIT16) + +/* --- CM_SCS_SYST_RVR values ----------------------------------------------- */ +/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter reaches 0. */ +/* Bit 24 to 31 are Reserved */ + +/* --- CM_SCS_SYST_CVR values ----------------------------------------------- */ +/* Bit0 to 31 => Reads or clears the current counter value. */ + +/* --- CM_SCS_SYST_CALIB values ----------------------------------------------- */ +/* + * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock + * skew errors. If this field is zero, the calibration value is not known. + */ +#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1) + +/* + * Bit30 => SKEW Indicates whether the 10ms calibration value is exact: + * 0 = 10ms calibration value is exact. + * 1 = 10ms calibration value is inexact, because of the clock frequency + */ +#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30) +/* + * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented: + * 0 = The reference clock is implemented. + * 1 = The reference clock is not implemented. + * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot + * be cleared to 0. + */ +#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31) + +/* + * System Control Space (SCS) => Data Watchpoint and Trace (DWT). + * See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html (ARMv7-M Architecture Reference Manual) + * The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling + * for the processor. + */ +/* + * DWT Control register + * Purpose Provides configuration and status information for the DWT block, and used to control features of the block + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. + */ +#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00) +/* + * DWT_CYCCNT register + * Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT) + * When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero. + * + * Purpose Shows or sets the value of the processor cycle counter, CYCCNT. + * Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state. + * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL. + * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP. +*/ +#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04) + +/* DWT_CPICNT register + * Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls. + * Usage constraints: The counter initializes to 0 when software enables its counter overflow event by + * setting the DWT_CTRL.CPIEVTENA bit to 1. + * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL. + * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not + * include the profiling counters, this register is UNK/SBZP. + */ +#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08) + +/* DWT_EXCCNT register */ +#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C) + +/* DWT_EXCCNT register */ +#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10) + +/* DWT_EXCCNT register */ +#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14) + +/* DWT_EXCCNT register */ +#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18) + +/* DWT_PCSR register */ +#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18) + +/* --- SCS_DWT_CTRL values ----------------------------------------------- */ +/* + * Enables CYCCNT: + * 0 = Disabled, 1 = Enabled + * This bit is UNK/SBZP if the NOCYCCNT bit is RAO. + */ +#define SCS_DWT_CTRL_CYCCNTENA (BIT0) + +/* TODO bit definition values for other DWT_XXX register */ + +/* Macro to be called at startup to enable SCS & Cycle Counter */ +#define SCS_DWT_CYCLE_COUNTER_ENABLED() ( (SCS_DEMCR |= SCS_DEMCR_TRCENA)\ + (SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA) ) + +#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR=0) + +/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not enabled) */ +#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE)) + +/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */ +#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE | SCS_SYST_CSR_TICKINT)) + #endif diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index 336eab8..b996ab8 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -3,6 +3,7 @@ * * Copyright (C) 2010 Piotr Esden-Tempski * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -22,8 +23,48 @@ #define LPC43XX_NVIC_H #include +#include #include +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M4 System Interrupts */ @@ -91,4 +132,16 @@ /* LPC43xx M0 specific user interrupts */ //TODO +/* --- NVIC functions ------------------------------------------------------ */ + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u8 irqn); + #endif diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h new file mode 100644 index 0000000..9f8b38d --- /dev/null +++ b/include/libopencm3/lpc43xx/systick.h @@ -0,0 +1,84 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ +/* See also libopencm3\cm3\scs.h for details on SysTicks registers */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +u32 systick_get_calib(void); + +#endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 38d5bf7..e8bd8fc 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o i2c.o ssp.o +OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o # VPATH += ../usb diff --git a/lib/lpc43xx/nvic.c b/lib/lpc43xx/nvic.c new file mode 100644 index 0000000..4793312 --- /dev/null +++ b/lib/lpc43xx/nvic.c @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Fergus Noble + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +#include +#include + +void nvic_enable_irq(u8 irqn) +{ + NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); +} + +void nvic_disable_irq(u8 irqn) +{ + NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); +} + +u8 nvic_get_pending_irq(u8 irqn) +{ + return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +void nvic_set_pending_irq(u8 irqn) +{ + NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); +} + +void nvic_clear_pending_irq(u8 irqn) +{ + NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); +} + +u8 nvic_get_active_irq(u8 irqn) +{ + return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +u8 nvic_get_irq_enabled(u8 irqn) +{ + return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +void nvic_set_priority(u8 irqn, u8 priority) +{ + if(irqn>NVIC_M4_QEI_IRQ) + { + /* Cortex-M system interrupts */ + SCS_SHPR( (irqn&0xF)-4 ) = priority; + }else + { + /* Device specific interrupts */ + NVIC_IPR(irqn) = priority; + } +} + +void nvic_generate_software_interrupt(u8 irqn) +{ + if (irqn <= 239) + NVIC_STIR |= irqn; +} diff --git a/lib/lpc43xx/systick.c b/lib/lpc43xx/systick.c new file mode 100644 index 0000000..82345a9 --- /dev/null +++ b/lib/lpc43xx/systick.c @@ -0,0 +1,69 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +void systick_set_clocksource(u8 clocksource) +{ + STK_CTRL |= clocksource; +} + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} + +u32 systick_get_calib(void) +{ + return (STK_CALIB&0x00FFFFFF); +} -- cgit v1.2.3 From 3aab6220d83d5b9fcd318e9d87225ff405cad783 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Sun, 2 Sep 2012 17:12:58 +0200 Subject: Add C linkage declaration for C++ usage --- include/libopencm3/cm3/common.h | 10 ++++++++++ include/libopencm3/lm3s/gpio.h | 4 ++++ include/libopencm3/lpc17xx/gpio.h | 4 ++++ include/libopencm3/lpc43xx/gpio.h | 4 ++++ include/libopencm3/lpc43xx/i2c.h | 4 ++++ include/libopencm3/lpc43xx/nvic.h | 4 ++++ include/libopencm3/lpc43xx/scu.h | 4 ++++ include/libopencm3/lpc43xx/ssp.h | 4 ++++ include/libopencm3/lpc43xx/systick.h | 4 ++++ include/libopencm3/stm32/can.h | 4 ++++ include/libopencm3/stm32/crc.h | 4 ++++ include/libopencm3/stm32/dac.h | 4 ++++ include/libopencm3/stm32/exti.h | 4 ++++ include/libopencm3/stm32/f1/adc.h | 3 +++ include/libopencm3/stm32/f1/desig.h | 4 ++++ include/libopencm3/stm32/f1/dma.h | 4 ++++ include/libopencm3/stm32/f1/flash.h | 4 ++++ include/libopencm3/stm32/f1/gpio.h | 4 ++++ include/libopencm3/stm32/f1/rcc.h | 4 ++++ include/libopencm3/stm32/f1/rtc.h | 4 ++++ include/libopencm3/stm32/f1/scb.h | 5 +++++ include/libopencm3/stm32/f2/flash.h | 4 ++++ include/libopencm3/stm32/f2/gpio.h | 4 ++++ include/libopencm3/stm32/f2/rcc.h | 4 ++++ include/libopencm3/stm32/f2/scb.h | 5 +++++ include/libopencm3/stm32/f2/timer.h | 4 ++++ include/libopencm3/stm32/f4/flash.h | 4 ++++ include/libopencm3/stm32/f4/gpio.h | 4 ++++ include/libopencm3/stm32/f4/pwr.h | 4 ++++ include/libopencm3/stm32/f4/rcc.h | 4 ++++ include/libopencm3/stm32/f4/scb.h | 5 +++++ include/libopencm3/stm32/f4/timer.h | 4 ++++ include/libopencm3/stm32/i2c.h | 4 ++++ include/libopencm3/stm32/iwdg.h | 4 ++++ include/libopencm3/stm32/nvic.h | 4 ++++ include/libopencm3/stm32/pwr.h | 4 ++++ include/libopencm3/stm32/spi.h | 4 ++++ include/libopencm3/stm32/systick.h | 4 ++++ include/libopencm3/stm32/timer.h | 5 +++++ include/libopencm3/stm32/usart.h | 4 ++++ include/libopencm3/usb/usbd.h | 4 ++++ 41 files changed, 173 insertions(+) (limited to 'include/libopencm3/lpc43xx/nvic.h') diff --git a/include/libopencm3/cm3/common.h b/include/libopencm3/cm3/common.h index 54cd2e4..7ef18fe 100644 --- a/include/libopencm3/cm3/common.h +++ b/include/libopencm3/cm3/common.h @@ -32,6 +32,16 @@ typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; +/* This must be placed around external function declaration for C++ + * support. */ +#ifdef __cplusplus +# define BEGIN_DECLS extern "C" { +# define END_DECLS } +#else +# define BEGIN_DECLS +# define END_DECLS +#endif + /* Generic memory-mapped I/O accessor functions */ #define MMIO8(addr) (*(volatile u8 *)(addr)) #define MMIO16(addr) (*(volatile u16 *)(addr)) diff --git a/include/libopencm3/lm3s/gpio.h b/include/libopencm3/lm3s/gpio.h index 852609f..5296b74 100644 --- a/include/libopencm3/lm3s/gpio.h +++ b/include/libopencm3/lm3s/gpio.h @@ -69,7 +69,11 @@ #define GPIO_CR(port) MMIO32(port + 0x524) #define GPIO_AMSEL(port) MMIO32(port + 0x528) +BEGIN_DECLS + void gpio_set(u32 gpioport, u8 gpios); void gpio_clear(u32 gpioport, u8 gpios); +END_DECLS + #endif diff --git a/include/libopencm3/lpc17xx/gpio.h b/include/libopencm3/lpc17xx/gpio.h index 7b07ac5..15afd87 100644 --- a/include/libopencm3/lpc17xx/gpio.h +++ b/include/libopencm3/lpc17xx/gpio.h @@ -132,7 +132,11 @@ /* Overall interrupt status */ #define GPIO_IS MMIO32(GPIOINTERRPUT_BASE + 0x80) +BEGIN_DECLS + void gpio_set(u32 gpioport, u32 gpios); void gpio_clear(u32 gpioport, u32 gpios); +END_DECLS + #endif diff --git a/include/libopencm3/lpc43xx/gpio.h b/include/libopencm3/lpc43xx/gpio.h index 8abd546..daa21fd 100644 --- a/include/libopencm3/lpc43xx/gpio.h +++ b/include/libopencm3/lpc43xx/gpio.h @@ -153,8 +153,12 @@ //TODO interrupts +BEGIN_DECLS + void gpio_set(u32 gpioport, u32 gpios); void gpio_clear(u32 gpioport, u32 gpios); void gpio_toggle(u32 gpioport, u32 gpios); +END_DECLS + #endif diff --git a/include/libopencm3/lpc43xx/i2c.h b/include/libopencm3/lpc43xx/i2c.h index 249962c..b163af8 100644 --- a/include/libopencm3/lpc43xx/i2c.h +++ b/include/libopencm3/lpc43xx/i2c.h @@ -133,10 +133,14 @@ /* --- I2C funtion prototypes----------------------------------------------- */ +BEGIN_DECLS + void i2c0_init(void); void i2c0_tx_start(void); void i2c0_tx_byte(u8 byte); u8 i2c0_rx_byte(void); void i2c0_stop(void); +END_DECLS + #endif diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index b996ab8..cdbf070 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -134,6 +134,8 @@ /* --- NVIC functions ------------------------------------------------------ */ +BEGIN_DECLS + void nvic_enable_irq(u8 irqn); void nvic_disable_irq(u8 irqn); u8 nvic_get_pending_irq(u8 irqn); @@ -144,4 +146,6 @@ u8 nvic_get_irq_enabled(u8 irqn); void nvic_set_priority(u8 irqn, u8 priority); void nvic_generate_software_interrupt(u8 irqn); +END_DECLS + #endif diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index 6e1be7f..c1b9fc2 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -725,6 +725,10 @@ typedef enum { #define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) #define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +BEGIN_DECLS + void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf); +END_DECLS + #endif diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h index ed69668..b3d95db 100644 --- a/include/libopencm3/lpc43xx/ssp.h +++ b/include/libopencm3/lpc43xx/ssp.h @@ -157,6 +157,8 @@ typedef enum { SSP_SLAVE_OUT_DISABLE = BIT3 } ssp_slave_option_t; /* This option is relevant only in slave mode */ +BEGIN_DECLS + void ssp_disable(ssp_num_t ssp_num); /* @@ -178,4 +180,6 @@ u16 ssp_read(ssp_num_t ssp_num); void ssp_write(ssp_num_t ssp_num, u16 data); +END_DECLS + #endif diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h index 9f8b38d..2ae52c2 100644 --- a/include/libopencm3/lpc43xx/systick.h +++ b/include/libopencm3/lpc43xx/systick.h @@ -70,6 +70,8 @@ /* --- Function Prototypes ------------------------------------------------- */ +BEGIN_DECLS + void systick_set_reload(u32 value); u32 systick_get_value(void); void systick_set_clocksource(u8 clocksource); @@ -81,4 +83,6 @@ u8 systick_get_countflag(void); u32 systick_get_calib(void); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h index 0a05798..d6636d5 100644 --- a/include/libopencm3/stm32/can.h +++ b/include/libopencm3/stm32/can.h @@ -615,6 +615,8 @@ /* --- CAN functions -------------------------------------------------------- */ +BEGIN_DECLS + void can_reset(u32 canport); int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp); @@ -639,4 +641,6 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, void can_fifo_release(u32 canport, u8 fifo); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h index 7d80259..3848191 100644 --- a/include/libopencm3/stm32/crc.h +++ b/include/libopencm3/stm32/crc.h @@ -53,6 +53,8 @@ /* --- CRC function prototypes --------------------------------------------- */ +BEGIN_DECLS + /* TODO */ /** @@ -75,4 +77,6 @@ u32 crc_calculate(u32 data); */ u32 crc_calculate_block(u32 *datap, int size); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h index 3a57132..75d4edb 100644 --- a/include/libopencm3/stm32/dac.h +++ b/include/libopencm3/stm32/dac.h @@ -393,6 +393,8 @@ typedef enum { /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void dac_enable(data_channel dac_channel); void dac_disable(data_channel dac_channel); void dac_buffer_enable(data_channel dac_channel); @@ -409,6 +411,8 @@ void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_ void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format); void dac_software_trigger(data_channel dac_channel); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h index d1935ad..7645825 100644 --- a/include/libopencm3/stm32/exti.h +++ b/include/libopencm3/stm32/exti.h @@ -61,10 +61,14 @@ typedef enum trigger_e { EXTI_TRIGGER_BOTH, } exti_trigger_type; +BEGIN_DECLS + void exti_set_trigger(u32 extis, exti_trigger_type trig); void exti_enable_request(u32 extis); void exti_disable_request(u32 extis); void exti_reset_request(u32 extis); void exti_select_source(u32 exti, u32 gpioport); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index 563e75d..f13b7c7 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -485,6 +485,7 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS /* TODO */ void adc_enable_analog_watchdog_regular(u32 adc); @@ -532,4 +533,6 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/f1/desig.h index 743e946..74cfb35 100644 --- a/include/libopencm3/stm32/f1/desig.h +++ b/include/libopencm3/stm32/f1/desig.h @@ -36,6 +36,8 @@ #define DESIG_UID_63_32 MMIO32(DESIG_UNIQUE_ID_BASE + 0x04) #define DESIG_UID_95_64 MMIO32(DESIG_UNIQUE_ID_BASE + 0x08) +BEGIN_DECLS + /** * Read the onboard flash size * @return flash size in KB @@ -49,4 +51,6 @@ u16 desig_get_flash_size(void); */ void desig_get_unique_id(u32 result[]); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h index 64eafe0..b08803f 100644 --- a/include/libopencm3/stm32/f1/dma.h +++ b/include/libopencm3/stm32/f1/dma.h @@ -346,6 +346,8 @@ LGPL License Terms @ref lgpl_license /* --- function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void dma_channel_reset(u32 dma, u8 channel); void dma_enable_mem2mem_mode(u32 dma, u8 channel); void dma_set_priority(u32 dma, u8 channel, u32 prio); @@ -368,6 +370,8 @@ void dma_set_peripheral_address(u32 dma, u8 channel, u32 address); void dma_set_memory_address(u32 dma, u8 channel, u32 address); void dma_set_number_of_data(u32 dma, u8 channel, u16 number); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h index 2c026d6..919b4d4 100644 --- a/include/libopencm3/stm32/f1/flash.h +++ b/include/libopencm3/stm32/f1/flash.h @@ -89,6 +89,8 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void flash_prefetch_buffer_enable(void); void flash_prefetch_buffer_disable(void); void flash_halfcycle_enable(void); @@ -110,4 +112,6 @@ void flash_wait_for_last_operation(void); void flash_erase_option_bytes(void); void flash_program_option_bytes(u32 address, u16 data); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h index 2f4292a..a1e74cc 100644 --- a/include/libopencm3/stm32/f1/gpio.h +++ b/include/libopencm3/stm32/f1/gpio.h @@ -950,6 +950,8 @@ Line Devices only /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios); void gpio_set(u32 gpioport, u16 gpios); void gpio_clear(u32 gpioport, u16 gpios); @@ -962,6 +964,8 @@ void gpio_set_eventout(u8 evoutport, u8 evoutpin); void gpio_primary_remap(u8 swjenable, u32 maps); void gpio_secondary_remap(u32 maps); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h index 63f6770..855e43b 100644 --- a/include/libopencm3/stm32/f1/rcc.h +++ b/include/libopencm3/stm32/f1/rcc.h @@ -476,6 +476,8 @@ typedef enum { PLL, HSE, HSI, LSE, LSI } osc_t; +BEGIN_DECLS + void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); @@ -512,6 +514,8 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); void rcc_backupdomain_reset(void); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h index 5e203ab..04aea01 100644 --- a/include/libopencm3/stm32/f1/rtc.h +++ b/include/libopencm3/stm32/f1/rtc.h @@ -126,6 +126,8 @@ typedef enum { RTC_SEC, RTC_ALR, RTC_OW, } rtcflag_t; +BEGIN_DECLS + void rtc_awake_from_off(osc_t clock_source); void rtc_enter_config_mode(void); void rtc_exit_config_mode(void); @@ -144,4 +146,6 @@ u32 rtc_check_flag(rtcflag_t flag_val); void rtc_awake_from_standby(void); void rtc_auto_awake(osc_t clock_source, u32 prescale_val); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h index 12a74a2..181aa7a 100644 --- a/include/libopencm3/stm32/f1/scb.h +++ b/include/libopencm3/stm32/f1/scb.h @@ -293,10 +293,15 @@ /* BFAR [31:0]: Bus fault address */ /* --- SCB functions ------------------------------------------------------- */ + +BEGIN_DECLS + void scb_reset_core(void); void scb_reset_system(void); void scb_set_priority_grouping(u32 prigroup); /* TODO: */ +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f2/flash.h b/include/libopencm3/stm32/f2/flash.h index 5b4483f..2c78757 100644 --- a/include/libopencm3/stm32/f2/flash.h +++ b/include/libopencm3/stm32/f2/flash.h @@ -116,6 +116,8 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void flash_dcache_enable(void); void flash_dcache_disable(void); void flash_icache_enable(void); @@ -145,4 +147,6 @@ void flash_program_byte(u32 address, u8 data, u32 program_size); void flash_wait_for_last_operation(void); void flash_program_option_bytes(u32 data); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h index 1a9fd0f..6616769 100644 --- a/include/libopencm3/stm32/f2/gpio.h +++ b/include/libopencm3/stm32/f2/gpio.h @@ -254,6 +254,8 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + /* * Note: The F2 series has a completely new GPIO peripheral with different * configuration options. Here we implement a different API partly to more @@ -275,4 +277,6 @@ u16 gpio_port_read(u32 gpioport); void gpio_port_write(u32 gpioport, u16 data); void gpio_port_config_lock(u32 gpioport, u16 gpios); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h index dfce266..4ffa242 100644 --- a/include/libopencm3/stm32/f2/rcc.h +++ b/include/libopencm3/stm32/f2/rcc.h @@ -479,6 +479,8 @@ typedef enum { PLL, HSE, HSI, LSE, LSI } osc_t; +BEGIN_DECLS + void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); @@ -509,4 +511,6 @@ u32 rcc_get_system_clock_source(int i); void rcc_clock_setup_hse_3v3(const clock_scale_t *clock); void rcc_backupdomain_reset(void); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h index 12a74a2..181aa7a 100644 --- a/include/libopencm3/stm32/f2/scb.h +++ b/include/libopencm3/stm32/f2/scb.h @@ -293,10 +293,15 @@ /* BFAR [31:0]: Bus fault address */ /* --- SCB functions ------------------------------------------------------- */ + +BEGIN_DECLS + void scb_reset_core(void); void scb_reset_system(void); void scb_set_priority_grouping(u32 prigroup); /* TODO: */ +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f2/timer.h b/include/libopencm3/stm32/f2/timer.h index 3436bba..737d6f0 100644 --- a/include/libopencm3/stm32/f2/timer.h +++ b/include/libopencm3/stm32/f2/timer.h @@ -52,6 +52,10 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void timer_set_option(u32 timer_peripheral, u32 option); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h index f85d56f..2221333 100644 --- a/include/libopencm3/stm32/f4/flash.h +++ b/include/libopencm3/stm32/f4/flash.h @@ -115,6 +115,8 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void flash_dcache_enable(void); void flash_dcache_disable(void); void flash_icache_enable(void); @@ -144,4 +146,6 @@ void flash_program_byte(u32 address, u8 data, u32 program_size); void flash_wait_for_last_operation(void); void flash_program_option_bytes(u32 data); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h index a5b4361..b7da9c6 100644 --- a/include/libopencm3/stm32/f4/gpio.h +++ b/include/libopencm3/stm32/f4/gpio.h @@ -254,6 +254,8 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + /* * Note: The F4 series has a completely new GPIO peripheral with different * configuration options. Here we implement a different API partly to more @@ -275,4 +277,6 @@ u16 gpio_port_read(u32 gpioport); void gpio_port_write(u32 gpioport, u16 data); void gpio_port_config_lock(u32 gpioport, u16 gpios); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h index ede1ae7..25fb163 100644 --- a/include/libopencm3/stm32/f4/pwr.h +++ b/include/libopencm3/stm32/f4/pwr.h @@ -63,6 +63,10 @@ typedef enum { SCALE2, } vos_scale_t; +BEGIN_DECLS + void pwr_set_vos_scale(vos_scale_t scale); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index 648ccb0..1688584 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -482,6 +482,8 @@ typedef enum { PLL, HSE, HSI, LSE, LSI } osc_t; +BEGIN_DECLS + void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); @@ -512,4 +514,6 @@ u32 rcc_get_system_clock_source(int i); void rcc_clock_setup_hse_3v3(const clock_scale_t *clock); void rcc_backupdomain_reset(void); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h index 12a74a2..181aa7a 100644 --- a/include/libopencm3/stm32/f4/scb.h +++ b/include/libopencm3/stm32/f4/scb.h @@ -293,10 +293,15 @@ /* BFAR [31:0]: Bus fault address */ /* --- SCB functions ------------------------------------------------------- */ + +BEGIN_DECLS + void scb_reset_core(void); void scb_reset_system(void); void scb_set_priority_grouping(u32 prigroup); /* TODO: */ +END_DECLS + #endif diff --git a/include/libopencm3/stm32/f4/timer.h b/include/libopencm3/stm32/f4/timer.h index 6d19990..988d02c 100644 --- a/include/libopencm3/stm32/f4/timer.h +++ b/include/libopencm3/stm32/f4/timer.h @@ -52,6 +52,10 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void timer_set_option(u32 timer_peripheral, u32 option); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h index 1606b64..13257eb 100644 --- a/include/libopencm3/stm32/i2c.h +++ b/include/libopencm3/stm32/i2c.h @@ -316,6 +316,8 @@ /* --- I2C funtion prototypes----------------------------------------------- */ +BEGIN_DECLS + void i2c_reset(u32 i2c); void i2c_peripheral_enable(u32 i2c); void i2c_peripheral_disable(u32 i2c); @@ -331,4 +333,6 @@ void i2c_set_trise(u32 i2c, u16 trise); void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); void i2c_send_data(u32 i2c, u8 data); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h index a5f1ac1..4e44907 100644 --- a/include/libopencm3/stm32/iwdg.h +++ b/include/libopencm3/stm32/iwdg.h @@ -106,12 +106,16 @@ LGPL License Terms @ref lgpl_license /* --- IWDG function prototypes---------------------------------------------- */ +BEGIN_DECLS + void iwdg_start(void); void iwdg_set_period_ms(u32 period); bool iwdg_reload_busy(void); bool iwdg_prescaler_busy(void); void iwdg_reset(void); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h index 6a98737..d6dfa35 100644 --- a/include/libopencm3/stm32/nvic.h +++ b/include/libopencm3/stm32/nvic.h @@ -116,6 +116,8 @@ IRQ numbers -3 and -6 to -9 are reserved /* --- NVIC functions ------------------------------------------------------ */ +BEGIN_DECLS + void nvic_enable_irq(u8 irqn); void nvic_disable_irq(u8 irqn); u8 nvic_get_pending_irq(u8 irqn); @@ -126,6 +128,8 @@ u8 nvic_get_irq_enabled(u8 irqn); void nvic_set_priority(u8 irqn, u8 priority); void nvic_generate_software_interrupt(u16 irqn); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h index 7084382..e709f3d 100644 --- a/include/libopencm3/stm32/pwr.h +++ b/include/libopencm3/stm32/pwr.h @@ -106,6 +106,8 @@ LGPL License Terms @ref lgpl_license /* --- PWR function prototypes ------------------------------------------- */ +BEGIN_DECLS + void pwr_disable_backup_domain_write_protect(void); void pwr_enable_backup_domain_write_protect(void); void pwr_enable_power_voltage_detect(u32 pvd_level); @@ -122,6 +124,8 @@ bool pwr_voltage_high(void); bool pwr_get_standby_flag(void); bool pwr_get_wakeup_flag(void); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h index e64dd0f..11ba820 100644 --- a/include/libopencm3/stm32/spi.h +++ b/include/libopencm3/stm32/spi.h @@ -297,6 +297,8 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void spi_reset(u32 spi_peripheral); int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst); void spi_enable(u32 spi); @@ -343,4 +345,6 @@ void spi_disable_tx_dma(u32 spi); void spi_enable_rx_dma(u32 spi); void spi_disable_rx_dma(u32 spi); +END_DECLS + #endif diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h index aa6c287..e42c4e6 100644 --- a/include/libopencm3/stm32/systick.h +++ b/include/libopencm3/stm32/systick.h @@ -93,6 +93,8 @@ LGPL License Terms @ref lgpl_license /* --- Function Prototypes ------------------------------------------------- */ +BEGIN_DECLS + void systick_set_reload(u32 value); u32 systick_get_value(void); void systick_set_clocksource(u8 clocksource); @@ -102,6 +104,8 @@ void systick_counter_enable(void); void systick_counter_disable(void); u8 systick_get_countflag(void); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index b1e1064..b6f8949 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -1022,6 +1022,9 @@ enum tim_ic_pol { }; /* --- TIM function prototypes ------------------------------------------------------- */ + +BEGIN_DECLS + void timer_reset(u32 timer_peripheral); void timer_enable_irq(u32 timer_peripheral, u32 irq); void timer_disable_irq(u32 timer_peripheral, u32 irq); @@ -1101,6 +1104,8 @@ void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol); void timer_slave_set_mode(u32 timer, u8 mode); void timer_slave_set_trigger(u32 timer, u8 trigger); +END_DECLS + #endif /**@}*/ diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 5c7f285..9ec6c3d 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -294,6 +294,8 @@ /* --- Function prototypes ------------------------------------------------- */ +BEGIN_DECLS + void usart_set_baudrate(u32 usart, u32 baud); void usart_set_databits(u32 usart, u32 bits); void usart_set_stopbits(u32 usart, u32 stopbits); @@ -313,4 +315,6 @@ void usart_disable_rx_dma(u32 usart); void usart_enable_tx_dma(u32 usart); void usart_disable_tx_dma(u32 usart); +END_DECLS + #endif diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h index f453bc2..e4b3578 100644 --- a/include/libopencm3/usb/usbd.h +++ b/include/libopencm3/usb/usbd.h @@ -22,6 +22,8 @@ #include +BEGIN_DECLS + typedef struct _usbd_driver usbd_driver; extern const usbd_driver stm32f103_usb_driver; extern const usbd_driver stm32f107_usb_driver; @@ -73,4 +75,6 @@ extern void usbd_ep_nak_set(u8 addr, u8 nak); /* Optional */ extern void usbd_cable_connect(u8 on); +END_DECLS + #endif -- cgit v1.2.3