From a69d83d312396ee604426dce5341a54316c7c9b5 Mon Sep 17 00:00:00 2001 From: chrysn Date: Wed, 3 Oct 2012 18:15:20 +0200 Subject: unified vector table initialization the cortex generic interrupts get moved to lib/cm3/vector.c, the platorms' individual irq names, initialization and handler prototypes go to platoform specific irq.h files. as the vector.c file heavily depends on platoform specific headers, it can't be built once-and-for-all in lib/cm3/, so there are inclusion stubs in the various architecture dirs; this might be better solved with Makefile / include path handling. one particular file is lib/lpc43xx/vector.c; that platform's initialization code contains an additional section to copy everything from flash to ram (which probably performs better there). that code still resides in the inclusion stub, and gets mashed in using defines. would need a cleaner implementation together with the Makefile solution. this commit contains some files of the upcoming efm32 branch, from which it was cherry-picked. the .bin files produced from before and after this commit only differ in lpc43xx, where the startup sequence was subtly modified. --- include/libopencm3/cm3/vector.h | 65 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 include/libopencm3/cm3/vector.h (limited to 'include/libopencm3/cm3') diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h new file mode 100644 index 0000000..198992b --- /dev/null +++ b/include/libopencm3/cm3/vector.h @@ -0,0 +1,65 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions for handling vector tables. + * + * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2 + * (from the EFM32 documentation at + * http://www.energymicro.com/downloads/datasheets), and was seen analogously + * in other ARM implementations' libopencm3 files. + * + * The structure of the vector table is implemented independently of the system + * vector table starting at memory position 0x0, as it can be relocated to + * other memory locations too. + * + * The exact size of a vector interrupt table depends on the number of + * interrupts IRQ_COUNT, which is defined per family. + */ + +#ifndef LIBOPENCM3_VECTOR_H +#define LIBOPENCM3_VECTOR_H + +#include + +// #include "irq.h" /* we'll nede some definitions */ + +/** Type of an interrupt function. Only used to avoid hard-to-read function + * pointers in the efm32_vector_table_t struct. */ +typedef void (*vector_table_entry_t)(void); + +typedef struct { + unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ + vector_table_entry_t reset; + vector_table_entry_t nmi; + vector_table_entry_t hard_fault; + vector_table_entry_t memory_manage_fault; + vector_table_entry_t bus_fault; + vector_table_entry_t usage_fault; + vector_table_entry_t reserved_x001c[4]; + vector_table_entry_t sv_call; + vector_table_entry_t debug_monitor; + vector_table_entry_t reserved_x0034; + vector_table_entry_t pend_sv; + vector_table_entry_t systick; + vector_table_entry_t irq[IRQ_COUNT]; +} vector_table_t; + +#endif -- cgit v1.2.3 From 837de3ff9771ea03b5b54dda8ba7f77d404bdcdf Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 10:27:51 +0200 Subject: nvic.h factored out (incomplete) --- include/libopencm3/cm3/nvic.h | 123 +++++++++++++++++++++++++++++++++++++ include/libopencm3/lpc43xx/nvic.h | 85 -------------------------- include/libopencm3/stm32/nvic.h | 124 -------------------------------------- 3 files changed, 123 insertions(+), 209 deletions(-) create mode 100644 include/libopencm3/cm3/nvic.h (limited to 'include/libopencm3/cm3') diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h new file mode 100644 index 0000000..3a3aa2f --- /dev/null +++ b/include/libopencm3/cm3/nvic.h @@ -0,0 +1,123 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_nvic_defines NVIC Defines + +@brief libopencm3 Cortex Nested Vectored Interrupt Controller + +@ingroup CM3_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/**@{*/ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 and M4 System Interrupts */ +/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts +@ingroup CM3_nvic_defines + +IRQ numbers -3 and -6 to -9 are reserved +@{*/ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 +/**@}*/ + +/* Note: User interrupts are family specific and are defined in a family + * specific header file in the corresponding subfolder. + */ + +/* --- NVIC functions ------------------------------------------------------ */ + +BEGIN_DECLS + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u16 irqn); + +END_DECLS + +#endif diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index cdbf070..597e21a 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -1,70 +1,3 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_NVIC_H -#define LPC43XX_NVIC_H - -#include -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M4 System Interrupts */ @@ -131,21 +64,3 @@ /* LPC43xx M0 specific user interrupts */ //TODO - -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h index 694fab8..b8c22a2 100644 --- a/include/libopencm3/stm32/nvic.h +++ b/include/libopencm3/stm32/nvic.h @@ -1,108 +1,3 @@ -/** @defgroup STM32F_nvic_defines NVIC Defines - -@brief libopencm3 STM32F Nested Vectored Interrupt Controller - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -/** @defgroup nvic_sysint Cortex M3 System Interrupts -@ingroup STM32F_nvic_defines - -IRQ numbers -3 and -6 to -9 are reserved -@{*/ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 -/**@}*/ - - -/* Note: User interrupts are family specific and are defined in a family - * specific header file in the corresponding subfolder. - */ - #if defined(STM32F1) # include #elif defined(STM32F2) @@ -114,22 +9,3 @@ IRQ numbers -3 and -6 to -9 are reserved #endif -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u16 irqn); - -END_DECLS - -#endif -/**@}*/ - -- cgit v1.2.3 From f705d1cd6ec77f6610046c3d9a009c263b526f25 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 12:46:30 +0200 Subject: dispatch for chip specific nvic --- include/libopencm3/cm3/nvic.h | 2 ++ include/libopencm3/cm3/vector.h | 5 ++--- include/libopencm3/dispatch/nvic.h | 16 ++++++++++++++++ include/libopencm3/stm32/nvic.h | 11 ----------- 4 files changed, 20 insertions(+), 14 deletions(-) create mode 100644 include/libopencm3/dispatch/nvic.h delete mode 100644 include/libopencm3/stm32/nvic.h (limited to 'include/libopencm3/cm3') diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h index 3a3aa2f..3f83285 100644 --- a/include/libopencm3/cm3/nvic.h +++ b/include/libopencm3/cm3/nvic.h @@ -104,6 +104,8 @@ IRQ numbers -3 and -6 to -9 are reserved * specific header file in the corresponding subfolder. */ +#include + /* --- NVIC functions ------------------------------------------------------ */ BEGIN_DECLS diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h index 198992b..f78e9d8 100644 --- a/include/libopencm3/cm3/vector.h +++ b/include/libopencm3/cm3/vector.h @@ -38,8 +38,7 @@ #define LIBOPENCM3_VECTOR_H #include - -// #include "irq.h" /* we'll nede some definitions */ +#include /** Type of an interrupt function. Only used to avoid hard-to-read function * pointers in the efm32_vector_table_t struct. */ @@ -59,7 +58,7 @@ typedef struct { vector_table_entry_t reserved_x0034; vector_table_entry_t pend_sv; vector_table_entry_t systick; - vector_table_entry_t irq[IRQ_COUNT]; + vector_table_entry_t irq[NVIC_IRQ_COUNT]; } vector_table_t; #endif diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h new file mode 100644 index 0000000..322ec29 --- /dev/null +++ b/include/libopencm3/dispatch/nvic.h @@ -0,0 +1,16 @@ +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include + +#elif defined(TINYGECKO) +# include + +#elif defined(LPC43XX) +# include + +#else +# error "no chipset defined." +#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h deleted file mode 100644 index b8c22a2..0000000 --- a/include/libopencm3/stm32/nvic.h +++ /dev/null @@ -1,11 +0,0 @@ -#if defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#else -# error "stm32 family not defined." -#endif - - -- cgit v1.2.3 From e20f1c0d8fb6c75c434b93834a9d67262198d908 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 21:42:12 +0200 Subject: unify scb (system control block) these register definitions are common to all cortex mcus. some of the registers might not be implemented everywhere (especially the floating point registers), but defining them does no harm. this modification does not result in any changes in the example binaries. --- examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c | 2 +- examples/stm32/f1/other/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/other/usb_hid/usbhid.c | 2 +- examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c | 2 +- examples/stm32/f1/stm32-h103/usb_hid/usbhid.c | 2 +- examples/stm32/f1/stm32-h103/usb_iap/usbiap.c | 2 +- include/libopencm3/cm3/scb.h | 376 ++++++++++++++++++++++++++ include/libopencm3/stm32/f1/scb.h | 307 --------------------- include/libopencm3/stm32/f2/scb.h | 307 --------------------- include/libopencm3/stm32/f4/scb.h | 376 -------------------------- lib/cm3/scb.c | 35 +++ lib/stm32/f1/scb.c | 35 --- lib/stm32/f2/scb.c | 35 --- lib/stm32/f4/scb.c | 35 --- lib/stm32/f4/vector_chipset.c | 2 +- 16 files changed, 419 insertions(+), 1103 deletions(-) create mode 100644 include/libopencm3/cm3/scb.h delete mode 100644 include/libopencm3/stm32/f1/scb.h delete mode 100644 include/libopencm3/stm32/f2/scb.h delete mode 100644 include/libopencm3/stm32/f4/scb.h create mode 100644 lib/cm3/scb.c delete mode 100644 lib/stm32/f1/scb.c delete mode 100644 lib/stm32/f2/scb.c delete mode 100644 lib/stm32/f4/scb.c (limited to 'include/libopencm3/cm3') diff --git a/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c b/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c index 4ffc0a1..d8fcde4 100644 --- a/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c index 8d83896..a0a4d12 100644 --- a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c +++ b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c @@ -32,7 +32,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/other/usb_dfu/usbdfu.c b/examples/stm32/f1/other/usb_dfu/usbdfu.c index 0211a47..84e1b36 100644 --- a/examples/stm32/f1/other/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/other/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/other/usb_hid/usbhid.c b/examples/stm32/f1/other/usb_hid/usbhid.c index dd3c57a..6329f0e 100644 --- a/examples/stm32/f1/other/usb_hid/usbhid.c +++ b/examples/stm32/f1/other/usb_hid/usbhid.c @@ -28,7 +28,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c b/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c index 49f265b..9c0bab9 100644 --- a/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c +++ b/examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c index 9ed40d1..d0c2aff 100644 --- a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c +++ b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c @@ -28,7 +28,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c b/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c index c5cc8ba..9091f36 100644 --- a/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c +++ b/examples/stm32/f1/stm32-h103/usb_iap/usbiap.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/libopencm3/cm3/scb.h b/include/libopencm3/cm3/scb.h new file mode 100644 index 0000000..8e9c757 --- /dev/null +++ b/include/libopencm3/cm3/scb.h @@ -0,0 +1,376 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SCB_H +#define LIBOPENCM3_SCB_H + +#include +#include + +/* --- SCB: Registers ------------------------------------------------------ */ + +/* CPUID: CPUID base register */ +#define SCB_CPUID MMIO32(SCB_BASE + 0x00) + +/* ICSR: Interrupt Control State Register */ +#define SCB_ICSR MMIO32(SCB_BASE + 0x04) + +/* VTOR: Vector Table Offset Register */ +#define SCB_VTOR MMIO32(SCB_BASE + 0x08) + +/* AIRCR: Application Interrupt and Reset Control Register */ +#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) + +/* SCR: System Control Register */ +#define SCB_SCR MMIO32(SCB_BASE + 0x10) + +/* CCR: Configuration Control Register */ +#define SCB_CCR MMIO32(SCB_BASE + 0x14) + +/* SHP: System Handler Priority Registers */ +/* Note: 12 8bit registers */ +#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) +#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) +#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) +#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) + +/* SHCSR: System Handler Control and State Register */ +#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) + +/* CFSR: Configurable Fault Status Registers */ +#define SCB_CFSR MMIO32(SCB_BASE + 0x28) + +/* HFSR: Hard Fault Status Register */ +#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) + +/* DFSR: Debug Fault Status Register */ +#define SCB_DFSR MMIO32(SCB_BASE + 0x30) + +/* MMFAR: Memory Manage Fault Address Register */ +#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) + +/* BFAR: Bus Fault Address Register */ +#define SCB_BFAR MMIO32(SCB_BASE + 0x38) + +/* AFSR: Auxiliary Fault Status Register */ +#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) + +/* ID_PFR0: Processor Feature Register 0 */ +#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) + +/* ID_PFR1: Processor Feature Register 1 */ +#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) + +/* ID_DFR0: Debug Features Register 0 */ +#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) + +/* ID_AFR0: Auxiliary Features Register 0 */ +#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) + +/* ID_MMFR0: Memory Model Feature Register 0 */ +#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) + +/* ID_MMFR1: Memory Model Feature Register 1 */ +#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) + +/* ID_MMFR2: Memory Model Feature Register 2 */ +#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) + +/* ID_MMFR3: Memory Model Feature Register 3 */ +#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) + +/* ID_ISAR0: Instruction Set Attributes Register 0 */ +#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) + +/* ID_ISAR1: Instruction Set Attributes Register 1 */ +#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) + +/* ID_ISAR2: Instruction Set Attributes Register 2 */ +#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) + +/* ID_ISAR3: Instruction Set Attributes Register 3 */ +#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) + +/* ID_ISAR4: Instruction Set Attributes Register 4 */ +#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) + +/* CPACR: Coprocessor Access Control Register */ +#define SCB_CPACR MMIO32(SCB_BASE + 0x88) + +/* FPCCR: Floating-Point Context Control Register */ +#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) + +/* FPCAR: Floating-Point Context Address Register */ +#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) + +/* FPDSCR: Floating-Point Default Status Control Register */ +#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) + +/* MVFR0: Media and Floating-Point Feature Register 0 */ +#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) + +/* MVFR1: Media and Floating-Point Feature Register 1 */ +#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) + +/* --- SCB values ---------------------------------------------------------- */ + +/* --- SCB_CPUID values ---------------------------------------------------- */ + +/* Implementer[31:24]: Implementer code */ +#define SCP_CPUID_IMPLEMENTER_LSB 24 +/* Variant[23:20]: Variant number */ +#define SCP_CPUID_VARIANT_LSB 20 +/* Constant[19:16]: Reads as 0xF */ +#define SCP_CPUID_CONSTANT_LSB 16 +/* PartNo[15:4]: Part number of the processor */ +#define SCP_CPUID_PARTNO_LSB 4 +/* Revision[3:0]: Revision number */ +#define SCP_CPUID_REVISION_LSB 0 + +/* --- SCB_ICSR values ----------------------------------------------------- */ + +/* NMIPENDSET: NMI set-pending bit */ +#define SCB_ICSR_NMIPENDSET (1 << 31) +/* Bits [30:29]: reserved - must be kept cleared */ +/* PENDSVSET: PendSV set-pending bit */ +#define SCB_ICSR_PENDSVSET (1 << 28) +/* PENDSVCLR: PendSV clear-pending bit */ +#define SCB_ICSR_PENDSVCLR (1 << 27) +/* PENDSTSET: SysTick exception set-pending bit */ +#define SCB_ICSR_PENDSTSET (1 << 26) +/* PENDSTCLR: SysTick exception clear-pending bit */ +#define SCB_ICSR_PENDSTCLR (1 << 25) +/* Bit 24: reserved - must be kept cleared */ +/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ +/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ +#define SCB_ICSR_ISRPENDING (1 << 22) +/* VECTPENDING[21:12] Pending vector */ +#define SCB_ICSR_VECTPENDING_LSB 12 +/* RETOBASE: Return to base level */ +#define SCB_ICSR_RETOBASE (1 << 11) +/* Bits [10:9]: reserved - must be kept cleared */ +/* VECTACTIVE[8:0] Active vector */ +#define SCB_ICSR_VECTACTIVE_LSB 0 + +/* --- SCB_VTOR values ----------------------------------------------------- */ + +/* Bits [31:30]: reserved - must be kept cleared */ +/* TBLOFF[29:9]: Vector table base offset field */ +#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ + +/* --- SCB_AIRCR values ---------------------------------------------------- */ + +/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ +#define SCB_AIRCR_VECTKEYSTAT_LSB 16 +#define SCB_AIRCR_VECTKEY 0x05FA0000 +/* ENDIANESS Data endianness bit */ +#define SCB_AIRCR_ENDIANESS (1 << 15) +/* Bits [14:11]: reserved - must be kept cleared */ +/* PRIGROUP[10:8]: Interrupt priority grouping field */ +#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) +#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) +#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) +#define SCB_AIRCR_PRIGROUP_SHIFT 8 +/* Bits [7:3]: reserved - must be kept cleared */ +/* SYSRESETREQ System reset request */ +#define SCB_AIRCR_SYSRESETREQ (1 << 2) +/* VECTCLRACTIVE */ +#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) +/* VECTRESET */ +#define SCB_AIRCR_VECTRESET (1 << 0) + +/* --- SCB_SCR values ------------------------------------------------------ */ + +/* Bits [31:5]: reserved - must be kept cleared */ +/* SEVEONPEND Send Event on Pending bit */ +#define SCB_SCR_SEVEONPEND (1 << 4) +/* Bit 3: reserved - must be kept cleared */ +/* SLEEPDEEP */ +#define SCB_SCR_SLEEPDEEP (1 << 2) +/* SLEEPONEXIT */ +#define SCB_SCR_SLEEPONEXIT (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_CCR values ------------------------------------------------------ */ + +/* Bits [31:10]: reserved - must be kept cleared */ +/* STKALIGN */ +#define SCB_CCR_STKALIGN (1 << 9) +/* BFHFNMIGN */ +#define SCB_CCR_BFHFNMIGN (1 << 8) +/* Bits [7:5]: reserved - must be kept cleared */ +/* DIV_0_TRP */ +#define SCB_CCR_DIV_0_TRP (1 << 4) +/* UNALIGN_TRP */ +#define SCB_CCR_UNALIGN_TRP (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* USERSETMPEND */ +#define SCB_CCR_USERSETMPEND (1 << 1) +/* NONBASETHRDENA */ +#define SCB_CCR_NONBASETHRDENA (1 << 0) + +/* --- SCB_SHPR1 values ---------------------------------------------------- */ + +/* Bits [31:24]: reserved - must be kept cleared */ +/* PRI_6[23:16]: Priority of system handler 6, usage fault */ +#define SCB_SHPR1_PRI_6_LSB 16 +/* PRI_5[15:8]: Priority of system handler 5, bus fault */ +#define SCB_SHPR1_PRI_5_LSB 8 +/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ +#define SCB_SHPR1_PRI_4_LSB 0 + +/* --- SCB_SHPR2 values ---------------------------------------------------- */ + +/* PRI_11[31:24]: Priority of system handler 11, SVCall */ +#define SCB_SHPR2_PRI_11_LSB 24 +/* Bits [23:0]: reserved - must be kept cleared */ + +/* --- SCB_SHPR3 values ---------------------------------------------------- */ + +/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ +#define SCB_SHPR3_PRI_15_LSB 24 +/* PRI_14[23:16]: Priority of system handler 14, PendSV */ +#define SCB_SHPR3_PRI_14_LSB 16 +/* Bits [15:0]: reserved - must be kept cleared */ + +/* --- SCB_SHCSR values ---------------------------------------------------- */ + +/* Bits [31:19]: reserved - must be kept cleared */ +/* USGFAULTENA: Usage fault enable */ +#define SCB_SHCSR_USGFAULTENA (1 << 18) +/* BUSFAULTENA: Bus fault enable */ +#define SCB_SHCSR_BUSFAULTENA (1 << 17) +/* MEMFAULTENA: Memory management fault enable */ +#define SCB_SHCSR_MEMFAULTENA (1 << 16) +/* SVCALLPENDED: SVC call pending */ +#define SCB_SHCSR_SVCALLPENDED (1 << 15) +/* BUSFAULTPENDED: Bus fault exception pending */ +#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) +/* MEMFAULTPENDED: Memory management fault exception pending */ +#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) +/* USGFAULTPENDED: Usage fault exception pending */ +#define SCB_SHCSR_USGFAULTPENDED (1 << 12) +/* SYSTICKACT: SysTick exception active */ +#define SCB_SHCSR_SYSTICKACT (1 << 11) +/* PENDSVACT: PendSV exception active */ +#define SCB_SHCSR_PENDSVACT (1 << 10) +/* Bit 9: reserved - must be kept cleared */ +/* MONITORACT: Debug monitor active */ +#define SCB_SHCSR_MONITORACT (1 << 8) +/* SVCALLACT: SVC call active */ +#define SCB_SHCSR_SVCALLACT (1 << 7) +/* Bits [6:4]: reserved - must be kept cleared */ +/* USGFAULTACT: Usage fault exception active */ +#define SCB_SHCSR_USGFAULTACT (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* BUSFAULTACT: Bus fault exception active */ +#define SCB_SHCSR_BUSFAULTACT (1 << 1) +/* MEMFAULTACT: Memory management fault exception active */ +#define SCB_SHCSR_MEMFAULTACT (1 << 0) + +/* --- SCB_CFSR values ----------------------------------------------------- */ + +/* Bits [31:26]: reserved - must be kept cleared */ +/* DIVBYZERO: Divide by zero usage fault */ +#define SCB_CFSR_DIVBYZERO (1 << 25) +/* UNALIGNED: Unaligned access usage fault */ +#define SCB_CFSR_UNALIGNED (1 << 24) +/* Bits [23:20]: reserved - must be kept cleared */ +/* NOCP: No coprocessor usage fault */ +#define SCB_CFSR_NOCP (1 << 19) +/* INVPC: Invalid PC load usage fault */ +#define SCB_CFSR_INVPC (1 << 18) +/* INVSTATE: Invalid state usage fault */ +#define SCB_CFSR_INVSTATE (1 << 17) +/* UNDEFINSTR: Undefined instruction usage fault */ +#define SCB_CFSR_UNDEFINSTR (1 << 16) +/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ +#define SCB_CFSR_BFARVALID (1 << 15) +/* Bits [14:13]: reserved - must be kept cleared */ +/* STKERR: Bus fault on stacking for exception entry */ +#define SCB_CFSR_STKERR (1 << 12) +/* UNSTKERR: Bus fault on unstacking for a return from exception */ +#define SCB_CFSR_UNSTKERR (1 << 11) +/* IMPRECISERR: Imprecise data bus error */ +#define SCB_CFSR_IMPRECISERR (1 << 10) +/* PRECISERR: Precise data bus error */ +#define SCB_CFSR_PRECISERR (1 << 9) +/* IBUSERR: Instruction bus error */ +#define SCB_CFSR_IBUSERR (1 << 8) +/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ +#define SCB_CFSR_MMARVALID (1 << 7) +/* Bits [6:5]: reserved - must be kept cleared */ +/* MSTKERR: Memory manager fault on stacking for exception entry */ +#define SCB_CFSR_MSTKERR (1 << 4) +/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ +#define SCB_CFSR_MUNSTKERR (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* DACCVIOL: Data access violation flag */ +#define SCB_CFSR_DACCVIOL (1 << 1) +/* IACCVIOL: Instruction access violation flag */ +#define SCB_CFSR_IACCVIOL (1 << 0) + +/* --- SCB_HFSR values ----------------------------------------------------- */ + +/* DEBUG_VT: reserved for debug use */ +#define SCB_HFSR_DEBUG_VT (1 << 31) +/* FORCED: Forced hard fault */ +#define SCB_HFSR_FORCED (1 << 30) +/* Bits [29:2]: reserved - must be kept cleared */ +/* VECTTBL: Vector table hard fault */ +#define SCB_HFSR_VECTTBL (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_MMFAR values ---------------------------------------------------- */ + +/* MMFAR [31:0]: Memory management fault address */ + +/* --- SCB_BFAR values ----------------------------------------------------- */ + +/* BFAR [31:0]: Bus fault address */ + +/* --- SCB_CPACR values ---------------------------------------------------- */ + +/* CPACR CPn: Access privileges values */ +#define SCB_CPACR_NONE 0 /* Access denied */ +#define SCB_CPACR_PRIV 1 /* Privileged access only */ +#define SCB_CPACR_FULL 3 /* Full access */ + +/* CPACR [20:21]: Access privileges for coprocessor 10 */ +#define SCB_CPACR_CP10 (1 << 20) +/* CPACR [22:23]: Access privileges for coprocessor 11 */ +#define SCB_CPACR_CP11 (1 << 22) + +/* --- SCB functions ------------------------------------------------------- */ + +BEGIN_DECLS + +void scb_reset_core(void); +void scb_reset_system(void); +void scb_set_priority_grouping(u32 prigroup); + +/* TODO: */ + +END_DECLS + +#endif diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h deleted file mode 100644 index 181aa7a..0000000 --- a/include/libopencm3/stm32/f1/scb.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h deleted file mode 100644 index 181aa7a..0000000 --- a/include/libopencm3/stm32/f2/scb.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h deleted file mode 100644 index 7187ca9..0000000 --- a/include/libopencm3/stm32/f4/scb.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* ID_PFR0: Processor Feature Register 0 */ -#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) - -/* ID_PFR1: Processor Feature Register 1 */ -#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) - -/* ID_DFR0: Debug Features Register 0 */ -#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) - -/* ID_AFR0: Auxiliary Features Register 0 */ -#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) - -/* ID_MMFR0: Memory Model Feature Register 0 */ -#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) - -/* ID_MMFR1: Memory Model Feature Register 1 */ -#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) - -/* ID_MMFR2: Memory Model Feature Register 2 */ -#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) - -/* ID_MMFR3: Memory Model Feature Register 3 */ -#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) - -/* ID_ISAR0: Instruction Set Attributes Register 0 */ -#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) - -/* ID_ISAR1: Instruction Set Attributes Register 1 */ -#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) - -/* ID_ISAR2: Instruction Set Attributes Register 2 */ -#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) - -/* ID_ISAR3: Instruction Set Attributes Register 3 */ -#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) - -/* ID_ISAR4: Instruction Set Attributes Register 4 */ -#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) - -/* CPACR: Coprocessor Access Control Register */ -#define SCB_CPACR MMIO32(SCB_BASE + 0x88) - -/* FPCCR: Floating-Point Context Control Register */ -#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) - -/* FPCAR: Floating-Point Context Address Register */ -#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) - -/* FPDSCR: Floating-Point Default Status Control Register */ -#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) - -/* MVFR0: Media and Floating-Point Feature Register 0 */ -#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) - -/* MVFR1: Media and Floating-Point Feature Register 1 */ -#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB_CPACR values ---------------------------------------------------- */ - -/* CPACR CPn: Access privileges values */ -#define SCB_CPACR_NONE 0 /* Access denied */ -#define SCB_CPACR_PRIV 1 /* Privileged access only */ -#define SCB_CPACR_FULL 3 /* Full access */ - -/* CPACR [20:21]: Access privileges for coprocessor 10 */ -#define SCB_CPACR_CP10 (1 << 20) -/* CPACR [22:23]: Access privileges for coprocessor 11 */ -#define SCB_CPACR_CP11 (1 << 22) - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -void scb_reset_core(void); -void scb_reset_system(void); -void scb_set_priority_grouping(u32 prigroup); - -/* TODO: */ - -END_DECLS - -#endif diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c new file mode 100644 index 0000000..904bd7c --- /dev/null +++ b/lib/cm3/scb.c @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void scb_reset_core(void) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; +} + +void scb_reset_system(void) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; +} + +void scb_set_priority_grouping(u32 prigroup) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; +} diff --git a/lib/stm32/f1/scb.c b/lib/stm32/f1/scb.c deleted file mode 100644 index e59134e..0000000 --- a/lib/stm32/f1/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f2/scb.c b/lib/stm32/f2/scb.c deleted file mode 100644 index abb7b44..0000000 --- a/lib/stm32/f2/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f4/scb.c b/lib/stm32/f4/scb.c deleted file mode 100644 index cbf4d53..0000000 --- a/lib/stm32/f4/scb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} - -void scb_set_priority_grouping(u32 prigroup) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; -} diff --git a/lib/stm32/f4/vector_chipset.c b/lib/stm32/f4/vector_chipset.c index 5304299..145be05 100644 --- a/lib/stm32/f4/vector_chipset.c +++ b/lib/stm32/f4/vector_chipset.c @@ -18,7 +18,7 @@ * along with this library. If not, see . */ -#include +#include static void pre_main(void) { -- cgit v1.2.3 From bc5146b710c8be3dfa4a8601bd3ca29408ae6397 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 22:26:46 +0200 Subject: unified systick handling the only change this results in in the example binaries is in the hackrf-jellybean/systick example, where the the check in systick_set_clocksource for overflowing from the stm32 area gets used. --- .../lpc43xx/hackrf-jellybean/systick/systickdemo.c | 2 +- examples/stm32/f1/lisa-m-1/can/can.c | 2 +- examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c | 2 +- .../lisa-m-2/usart_irq_printf/usart_irq_printf.c | 2 +- examples/stm32/f1/obldc/can/can.c | 2 +- examples/stm32/f1/obldc/systick/systick.c | 2 +- examples/stm32/f1/other/systick/systick.c | 2 +- examples/stm32/f1/other/usb_hid/usbhid.c | 2 +- .../stm32-h103/usart_irq_printf/usart_irq_printf.c | 2 +- examples/stm32/f1/stm32-h103/usb_hid/usbhid.c | 2 +- include/libopencm3/cm3/systick.h | 113 ++++++++++++++++ include/libopencm3/lpc43xx/systick.h | 88 ------------ include/libopencm3/stm32/systick.h | 111 --------------- lib/cm3/systick.c | 149 +++++++++++++++++++++ lib/lpc43xx/systick.c | 69 ---------- lib/stm32/systick.c | 139 ------------------- 16 files changed, 272 insertions(+), 417 deletions(-) create mode 100644 include/libopencm3/cm3/systick.h delete mode 100644 include/libopencm3/lpc43xx/systick.h delete mode 100644 include/libopencm3/stm32/systick.h create mode 100644 lib/cm3/systick.c delete mode 100644 lib/lpc43xx/systick.c delete mode 100644 lib/stm32/systick.c (limited to 'include/libopencm3/cm3') diff --git a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c index 61792d1..d38b0bc 100644 --- a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include "../jellybean_conf.h" diff --git a/examples/stm32/f1/lisa-m-1/can/can.c b/examples/stm32/f1/lisa-m-1/can/can.c index 92ebd85..41432b6 100644 --- a/examples/stm32/f1/lisa-m-1/can/can.c +++ b/examples/stm32/f1/lisa-m-1/can/can.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include struct can_tx_msg { diff --git a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c index a0a4d12..f5f0146 100644 --- a/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c +++ b/examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c b/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c index e4e0127..dd2e221 100644 --- a/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/obldc/can/can.c b/examples/stm32/f1/obldc/can/can.c index a29d8d7..281ab1d 100644 --- a/examples/stm32/f1/obldc/can/can.c +++ b/examples/stm32/f1/obldc/can/can.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include struct can_tx_msg { diff --git a/examples/stm32/f1/obldc/systick/systick.c b/examples/stm32/f1/obldc/systick/systick.c index 7abdd54..1426793 100644 --- a/examples/stm32/f1/obldc/systick/systick.c +++ b/examples/stm32/f1/obldc/systick/systick.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include u32 temp32; diff --git a/examples/stm32/f1/other/systick/systick.c b/examples/stm32/f1/other/systick/systick.c index 9aa2e94..c04704d 100644 --- a/examples/stm32/f1/other/systick/systick.c +++ b/examples/stm32/f1/other/systick/systick.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include u32 temp32; diff --git a/examples/stm32/f1/other/usb_hid/usbhid.c b/examples/stm32/f1/other/usb_hid/usbhid.c index 6329f0e..a61d9ea 100644 --- a/examples/stm32/f1/other/usb_hid/usbhid.c +++ b/examples/stm32/f1/other/usb_hid/usbhid.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c b/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c index 5effb28..b052dc3 100644 --- a/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c index d0c2aff..1c27c2f 100644 --- a/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c +++ b/examples/stm32/f1/stm32-h103/usb_hid/usbhid.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/libopencm3/cm3/systick.h b/include/libopencm3/cm3/systick.h new file mode 100644 index 0000000..5e7715b --- /dev/null +++ b/include/libopencm3/cm3/systick.h @@ -0,0 +1,113 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_systick_defines SysTick Defines + +@brief libopencm3 Defined Constants and Types for the Cortex SysTick + +@ingroup CM3_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 19 August 2012 + +LGPL License Terms @ref lgpl_license + */ + +/**@{*/ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +#define STK_CTRL_CLKSOURCE_LSB 2 +/** @defgroup systick_clksource Clock source selection +@ingroup CM3_systick_defines + +@{*/ +#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 +#define STK_CTRL_CLKSOURCE_AHB 1 +/**@}*/ + +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +u32 systick_get_calib(void); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h deleted file mode 100644 index 2ae52c2..0000000 --- a/include/libopencm3/lpc43xx/systick.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ -/* See also libopencm3\cm3\scs.h for details on SysTicks registers */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -u32 systick_get_calib(void); - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h deleted file mode 100644 index e42c4e6..0000000 --- a/include/libopencm3/stm32/systick.h +++ /dev/null @@ -1,111 +0,0 @@ -/** @defgroup STM32F_systick_defines SysTick Defines - -@brief libopencm3 Defined Constants and Types for the STM32F SysTick - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 19 August 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -#define STK_CTRL_CLKSOURCE_LSB 2 -/** @defgroup systick_clksource Clock source selection -@ingroup STM32F_systick_defines - -@{*/ -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 -/**@}*/ - -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -END_DECLS - -#endif -/**@}*/ - diff --git a/lib/cm3/systick.c b/lib/cm3/systick.c new file mode 100644 index 0000000..325ffff --- /dev/null +++ b/lib/cm3/systick.c @@ -0,0 +1,149 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_systick_file SysTick + +@ingroup CM3_files + +@brief libopencm3 Cortex System Tick Timer + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 19 August 2012 + +This library supports the System Tick timer in ARM Cortex Microcontrollers. + +The System Tick timer is part of the ARM Cortex core. It is a 24 bit +down counter that can be configured with an automatical reload value. + +LGPL License Terms @ref lgpl_license + */ + +/**@{*/ +#include + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Set the Automatic Reload Value. + +The counter is set to the reload value when the counter starts and after it +reaches zero. + +@param[in] value u32. 24 bit reload value. +*/ + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Read the Automatic Reload Value. + +@returns 24 bit reload value as u32. +*/ + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Set the SysTick Clock Source. + +The clock source can be either the AHB clock or the same clock divided by 8. + +@param[in] clocksource u8. Clock source from @ref systick_clksource. +*/ + +void systick_set_clocksource(u8 clocksource) +{ + if (clocksource < 2) + STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Enable SysTick Interrupt. + +*/ + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Disable SysTick Interrupt. + +*/ + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Enable SysTick Counter. + +*/ + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Disable SysTick Counter. + +*/ + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Read the Counter Flag. + +The count flag is set when the timer count becomes zero, and is cleared when the +flag is read. + +@returns Boolean if flag set. +*/ + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief SysTick Get Calibration Value + +@returns Current calibration value +*/ +u32 systick_get_calib(void) +{ + return (STK_CALIB&0x00FFFFFF); +} +/**@}*/ + diff --git a/lib/lpc43xx/systick.c b/lib/lpc43xx/systick.c deleted file mode 100644 index 82345a9..0000000 --- a/lib/lpc43xx/systick.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -void systick_set_clocksource(u8 clocksource) -{ - STK_CTRL |= clocksource; -} - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} - -u32 systick_get_calib(void) -{ - return (STK_CALIB&0x00FFFFFF); -} diff --git a/lib/stm32/systick.c b/lib/stm32/systick.c deleted file mode 100644 index 36077cc..0000000 --- a/lib/stm32/systick.c +++ /dev/null @@ -1,139 +0,0 @@ -/** @defgroup STM32F_systick_file SysTick - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxx System Tick Timer - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 19 August 2012 - -This library supports the System Tick timer in the -STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. - -The System Tick timer is part of the ARM Cortex core. It is a 24 bit -down counter that can be configured with an automatical reload value. - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#include - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Set the Automatic Reload Value. - -The counter is set to the reload value when the counter starts and after it -reaches zero. - -@param[in] value u32. 24 bit reload value. -*/ - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Read the Automatic Reload Value. - -@returns 24 bit reload value as u32. -*/ - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Set the SysTick Clock Source. - -The clock source can be either the AHB clock or the same clock divided by 8. - -@param[in] clocksource u8. Clock source from @ref systick_clksource. -*/ - -void systick_set_clocksource(u8 clocksource) -{ - if (clocksource < 2) - STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Enable SysTick Interrupt. - -*/ - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Disable SysTick Interrupt. - -*/ - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Enable SysTick Counter. - -*/ - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Disable SysTick Counter. - -*/ - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief SysTick Read the Counter Flag. - -The count flag is set when the timer count becomes zero, and is cleared when the -flag is read. - -@returns Boolean if flag set. -*/ - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} -/**@}*/ - -- cgit v1.2.3